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OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / video / mb862xx / mb862xxfbdrv.c
blob11a7a333701d3abc7da2aa57573344dc0576645c
1 /*
2 * drivers/mb862xx/mb862xxfb.c
3 *
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
5 *
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #undef DEBUG
16
17 #include <linux/fb.h>
18 #include <linux/delay.h>
19 #include <linux/uaccess.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #if defined(CONFIG_OF)
25 #include <linux/of_platform.h>
26 #endif
27 #include "mb862xxfb.h"
28 #include "mb862xx_reg.h"
29
30 #define NR_PALETTE 256
31 #define MB862XX_MEM_SIZE 0x1000000
32 #define CORALP_MEM_SIZE 0x2000000
33 #define CARMINE_MEM_SIZE 0x8000000
34 #define DRV_NAME "mb862xxfb"
35
36 #if defined(CONFIG_SOCRATES)
37 static struct mb862xx_gc_mode socrates_gc_mode = {
38 /* Mode for Prime View PM070WL4 TFT LCD Panel */
39 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
40 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
41 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
42 };
43 #endif
44
45 /* Helpers */
46 static inline int h_total(struct fb_var_screeninfo *var)
47 {
48 return var->xres + var->left_margin +
49 var->right_margin + var->hsync_len;
50 }
51
52 static inline int v_total(struct fb_var_screeninfo *var)
53 {
54 return var->yres + var->upper_margin +
55 var->lower_margin + var->vsync_len;
56 }
57
58 static inline int hsp(struct fb_var_screeninfo *var)
59 {
60 return var->xres + var->right_margin - 1;
61 }
62
63 static inline int vsp(struct fb_var_screeninfo *var)
64 {
65 return var->yres + var->lower_margin - 1;
66 }
67
68 static inline int d_pitch(struct fb_var_screeninfo *var)
69 {
70 return var->xres * var->bits_per_pixel / 8;
71 }
72
73 static inline unsigned int chan_to_field(unsigned int chan,
74 struct fb_bitfield *bf)
75 {
76 chan &= 0xffff;
77 chan >>= 16 - bf->length;
78 return chan << bf->offset;
79 }
80
81 static int mb862xxfb_setcolreg(unsigned regno,
82 unsigned red, unsigned green, unsigned blue,
83 unsigned transp, struct fb_info *info)
84 {
85 struct mb862xxfb_par *par = info->par;
86 unsigned int val;
87
88 switch (info->fix.visual) {
89 case FB_VISUAL_TRUECOLOR:
90 if (regno < 16) {
91 val = chan_to_field(red, &info->var.red);
92 val |= chan_to_field(green, &info->var.green);
93 val |= chan_to_field(blue, &info->var.blue);
94 par->pseudo_palette[regno] = val;
95 }
96 break;
97 case FB_VISUAL_PSEUDOCOLOR:
98 if (regno < 256) {
99 val = (red >> 8) << 16;
100 val |= (green >> 8) << 8;
101 val |= blue >> 8;
102 outreg(disp, GC_L0PAL0 + (regno * 4), val);
103 }
104 break;
105 default:
106 return 1; /* unsupported type */
107 }
108 return 0;
109 }
110
111 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
112 struct fb_info *fbi)
113 {
114 unsigned long tmp;
115
116 if (fbi->dev)
117 dev_dbg(fbi->dev, "%s\n", __func__);
118
119 /* check if these values fit into the registers */
120 if (var->hsync_len > 255 || var->vsync_len > 255)
121 return -EINVAL;
122
123 if ((var->xres + var->right_margin) >= 4096)
124 return -EINVAL;
125
126 if ((var->yres + var->lower_margin) > 4096)
127 return -EINVAL;
128
129 if (h_total(var) > 4096 || v_total(var) > 4096)
130 return -EINVAL;
131
132 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
133 return -EINVAL;
134
135 if (var->bits_per_pixel <= 8)
136 var->bits_per_pixel = 8;
137 else if (var->bits_per_pixel <= 16)
138 var->bits_per_pixel = 16;
139 else if (var->bits_per_pixel <= 32)
140 var->bits_per_pixel = 32;
141
142 /*
143 * can cope with 8,16 or 24/32bpp if resulting
144 * pitch is divisible by 64 without remainder
145 */
146 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
147 int r;
148
149 var->bits_per_pixel = 0;
150 do {
151 var->bits_per_pixel += 8;
152 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
153 } while (r && var->bits_per_pixel <= 32);
154
155 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
156 return -EINVAL;
157 }
158
159 /* line length is going to be 128 bit aligned */
160 tmp = (var->xres * var->bits_per_pixel) / 8;
161 if ((tmp & 15) != 0)
162 return -EINVAL;
163
164 /* set r/g/b positions and validate bpp */
165 switch (var->bits_per_pixel) {
166 case 8:
167 var->red.length = var->bits_per_pixel;
168 var->green.length = var->bits_per_pixel;
169 var->blue.length = var->bits_per_pixel;
170 var->red.offset = 0;
171 var->green.offset = 0;
172 var->blue.offset = 0;
173 var->transp.length = 0;
174 break;
175 case 16:
176 var->red.length = 5;
177 var->green.length = 5;
178 var->blue.length = 5;
179 var->red.offset = 10;
180 var->green.offset = 5;
181 var->blue.offset = 0;
182 var->transp.length = 0;
183 break;
184 case 24:
185 case 32:
186 var->transp.length = 8;
187 var->red.length = 8;
188 var->green.length = 8;
189 var->blue.length = 8;
190 var->transp.offset = 24;
191 var->red.offset = 16;
192 var->green.offset = 8;
193 var->blue.offset = 0;
194 break;
195 default:
196 return -EINVAL;
197 }
198 return 0;
199 }
200
201 /*
202 * set display parameters
203 */
204 static int mb862xxfb_set_par(struct fb_info *fbi)
205 {
206 struct mb862xxfb_par *par = fbi->par;
207 unsigned long reg, sc;
208
209 dev_dbg(par->dev, "%s\n", __func__);
210 if (par->type == BT_CORALP)
211 mb862xxfb_init_accel(fbi, fbi->var.xres);
212
213 if (par->pre_init)
214 return 0;
215
216 /* disp off */
217 reg = inreg(disp, GC_DCM1);
218 reg &= ~GC_DCM01_DEN;
219 outreg(disp, GC_DCM1, reg);
220
221 /* set display reference clock div. */
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
223 reg = inreg(disp, GC_DCM1);
224 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
225 reg |= sc << 8;
226 outreg(disp, GC_DCM1, reg);
227 dev_dbg(par->dev, "SC 0x%lx\n", sc);
228
229 /* disp dimension, format */
230 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
231 (fbi->var.yres - 1));
232 if (fbi->var.bits_per_pixel == 16)
233 reg |= GC_L0M_L0C_16;
234 outreg(disp, GC_L0M, reg);
235
236 if (fbi->var.bits_per_pixel == 32) {
237 reg = inreg(disp, GC_L0EM);
238 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
239 }
240 outreg(disp, GC_WY_WX, 0);
241 reg = pack(fbi->var.yres - 1, fbi->var.xres);
242 outreg(disp, GC_WH_WW, reg);
243 outreg(disp, GC_L0OA0, 0);
244 outreg(disp, GC_L0DA0, 0);
245 outreg(disp, GC_L0DY_L0DX, 0);
246 outreg(disp, GC_L0WY_L0WX, 0);
247 outreg(disp, GC_L0WH_L0WW, reg);
248
249 /* both HW-cursors off */
250 reg = inreg(disp, GC_CPM_CUTC);
251 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
252 outreg(disp, GC_CPM_CUTC, reg);
253
254 /* timings */
255 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
256 outreg(disp, GC_HDB_HDP, reg);
257 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
258 outreg(disp, GC_VDP_VSP, reg);
259 reg = ((fbi->var.vsync_len - 1) << 24) |
260 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
261 outreg(disp, GC_VSW_HSW_HSP, reg);
262 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
263 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
264
265 /* display on */
266 reg = inreg(disp, GC_DCM1);
267 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
268 reg &= ~GC_DCM01_ESY;
269 outreg(disp, GC_DCM1, reg);
270 return 0;
271 }
272
273 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
274 struct fb_info *info)
275 {
276 struct mb862xxfb_par *par = info->par;
277 unsigned long reg;
278
279 reg = pack(var->yoffset, var->xoffset);
280 outreg(disp, GC_L0WY_L0WX, reg);
281
282 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
283 outreg(disp, GC_L0WH_L0WW, reg);
284 return 0;
285 }
286
287 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
288 {
289 struct mb862xxfb_par *par = fbi->par;
290 unsigned long reg;
291
292 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
293
294 switch (mode) {
295 case FB_BLANK_POWERDOWN:
296 reg = inreg(disp, GC_DCM1);
297 reg &= ~GC_DCM01_DEN;
298 outreg(disp, GC_DCM1, reg);
299 break;
300 case FB_BLANK_UNBLANK:
301 reg = inreg(disp, GC_DCM1);
302 reg |= GC_DCM01_DEN;
303 outreg(disp, GC_DCM1, reg);
304 break;
305 case FB_BLANK_NORMAL:
306 case FB_BLANK_VSYNC_SUSPEND:
307 case FB_BLANK_HSYNC_SUSPEND:
308 default:
309 return 1;
310 }
311 return 0;
312 }
313
314 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
315 unsigned long arg)
316 {
317 struct mb862xxfb_par *par = fbi->par;
318 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
319 void __user *argp = (void __user *)arg;
320 int *enable;
321 u32 l1em = 0;
322
323 switch (cmd) {
324 case MB862XX_L1_GET_CFG:
325 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
326 return -EFAULT;
327 break;
328 case MB862XX_L1_SET_CFG:
329 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
330 return -EFAULT;
331 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
332 /* downscaling */
333 outreg(cap, GC_CAP_CSC,
334 pack((l1_cfg->sh << 11) / l1_cfg->dh,
335 (l1_cfg->sw << 11) / l1_cfg->dw));
336 l1em = inreg(disp, GC_L1EM);
337 l1em &= ~GC_L1EM_DM;
338 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
339 (l1_cfg->sh <= l1_cfg->dh)) {
340 /* upscaling */
341 outreg(cap, GC_CAP_CSC,
342 pack((l1_cfg->sh << 11) / l1_cfg->dh,
343 (l1_cfg->sw << 11) / l1_cfg->dw));
344 outreg(cap, GC_CAP_CMSS,
345 pack(l1_cfg->sw >> 1, l1_cfg->sh));
346 outreg(cap, GC_CAP_CMDS,
347 pack(l1_cfg->dw >> 1, l1_cfg->dh));
348 l1em = inreg(disp, GC_L1EM);
349 l1em |= GC_L1EM_DM;
350 }
351
352 if (l1_cfg->mirror) {
353 outreg(cap, GC_CAP_CBM,
354 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
355 l1em |= l1_cfg->dw * 2 - 8;
356 } else {
357 outreg(cap, GC_CAP_CBM,
358 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
359 l1em &= 0xffff0000;
360 }
361 outreg(disp, GC_L1EM, l1em);
362 break;
363 case MB862XX_L1_ENABLE:
364 enable = (int *)arg;
365 if (*enable) {
366 outreg(disp, GC_L1DA, par->cap_buf);
367 outreg(cap, GC_CAP_IMG_START,
368 pack(l1_cfg->sy >> 1, l1_cfg->sx));
369 outreg(cap, GC_CAP_IMG_END,
370 pack(l1_cfg->sh, l1_cfg->sw));
371 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
372 (par->l1_stride << 16));
373 outreg(disp, GC_L1WY_L1WX,
374 pack(l1_cfg->dy, l1_cfg->dx));
375 outreg(disp, GC_L1WH_L1WW,
376 pack(l1_cfg->dh - 1, l1_cfg->dw));
377 outreg(disp, GC_DLS, 1);
378 outreg(cap, GC_CAP_VCM,
379 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
380 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
381 GC_DCM1_DEN | GC_DCM1_L1E);
382 } else {
383 outreg(cap, GC_CAP_VCM,
384 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
385 outreg(disp, GC_DCM1,
386 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
387 }
388 break;
389 case MB862XX_L1_CAP_CTL:
390 enable = (int *)arg;
391 if (*enable) {
392 outreg(cap, GC_CAP_VCM,
393 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
394 } else {
395 outreg(cap, GC_CAP_VCM,
396 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
397 }
398 break;
399 default:
400 return -EINVAL;
401 }
402 return 0;
403 }
404
405 /* framebuffer ops */
406 static struct fb_ops mb862xxfb_ops = {
407 .owner = THIS_MODULE,
408 .fb_check_var = mb862xxfb_check_var,
409 .fb_set_par = mb862xxfb_set_par,
410 .fb_setcolreg = mb862xxfb_setcolreg,
411 .fb_blank = mb862xxfb_blank,
412 .fb_pan_display = mb862xxfb_pan,
413 .fb_fillrect = cfb_fillrect,
414 .fb_copyarea = cfb_copyarea,
415 .fb_imageblit = cfb_imageblit,
416 .fb_ioctl = mb862xxfb_ioctl,
417 };
418
419 /* initialize fb_info data */
420 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
421 {
422 struct mb862xxfb_par *par = fbi->par;
423 struct mb862xx_gc_mode *mode = par->gc_mode;
424 unsigned long reg;
425 int stride;
426
427 fbi->fbops = &mb862xxfb_ops;
428 fbi->pseudo_palette = par->pseudo_palette;
429 fbi->screen_base = par->fb_base;
430 fbi->screen_size = par->mapped_vram;
431
432 strcpy(fbi->fix.id, DRV_NAME);
433 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
434 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
435 fbi->fix.mmio_len = par->mmio_len;
436 fbi->fix.accel = FB_ACCEL_NONE;
437 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
438 fbi->fix.type_aux = 0;
439 fbi->fix.xpanstep = 1;
440 fbi->fix.ypanstep = 1;
441 fbi->fix.ywrapstep = 0;
442
443 reg = inreg(disp, GC_DCM1);
444 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
445 /* get the disp mode from active display cfg */
446 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
447 unsigned long hsp, vsp, ht, vt;
448
449 dev_dbg(par->dev, "using bootloader's disp. mode\n");
450 fbi->var.pixclock = (sc * 1000000) / par->refclk;
451 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
452 reg = inreg(disp, GC_VDP_VSP);
453 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
454 vsp = (reg & 0x0fff) + 1;
455 fbi->var.xres_virtual = fbi->var.xres;
456 fbi->var.yres_virtual = fbi->var.yres;
457 reg = inreg(disp, GC_L0EM);
458 if (reg & GC_L0EM_L0EC_24) {
459 fbi->var.bits_per_pixel = 32;
460 } else {
461 reg = inreg(disp, GC_L0M);
462 if (reg & GC_L0M_L0C_16)
463 fbi->var.bits_per_pixel = 16;
464 else
465 fbi->var.bits_per_pixel = 8;
466 }
467 reg = inreg(disp, GC_VSW_HSW_HSP);
468 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
469 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
470 hsp = (reg & 0xffff) + 1;
471 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
472 fbi->var.right_margin = hsp - fbi->var.xres;
473 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
474 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
475 fbi->var.lower_margin = vsp - fbi->var.yres;
476 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
477 } else if (mode) {
478 dev_dbg(par->dev, "using supplied mode\n");
479 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
480 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
481 } else {
482 int ret;
483
484 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
485 NULL, 0, NULL, 16);
486 if (ret == 0 || ret == 4) {
487 dev_err(par->dev,
488 "failed to get initial mode\n");
489 return -EINVAL;
490 }
491 }
492
493 fbi->var.xoffset = 0;
494 fbi->var.yoffset = 0;
495 fbi->var.grayscale = 0;
496 fbi->var.nonstd = 0;
497 fbi->var.height = -1;
498 fbi->var.width = -1;
499 fbi->var.accel_flags = 0;
500 fbi->var.vmode = FB_VMODE_NONINTERLACED;
501 fbi->var.activate = FB_ACTIVATE_NOW;
502 fbi->flags = FBINFO_DEFAULT |
503 #ifdef __BIG_ENDIAN
504 FBINFO_FOREIGN_ENDIAN |
505 #endif
506 FBINFO_HWACCEL_XPAN |
507 FBINFO_HWACCEL_YPAN;
508
509 /* check and possibly fix bpp */
510 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
511 dev_err(par->dev, "check_var() failed on initial setup?\n");
512
513 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
514 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
515 fbi->fix.line_length = (fbi->var.xres_virtual *
516 fbi->var.bits_per_pixel) / 8;
517 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
518
519 /*
520 * reserve space for capture buffers and two cursors
521 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
522 */
523 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
524 par->cap_len = 0x1bd800;
525 par->l1_cfg.sx = 0;
526 par->l1_cfg.sy = 0;
527 par->l1_cfg.sw = 720;
528 par->l1_cfg.sh = 576;
529 par->l1_cfg.dx = 0;
530 par->l1_cfg.dy = 0;
531 par->l1_cfg.dw = 720;
532 par->l1_cfg.dh = 576;
533 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
534 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
535 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
536 (par->l1_stride << 16));
537 outreg(cap, GC_CAP_CBOA, par->cap_buf);
538 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
539 return 0;
540 }
541
542 /*
543 * show some display controller and cursor registers
544 */
545 static ssize_t mb862xxfb_show_dispregs(struct device *dev,
546 struct device_attribute *attr, char *buf)
547 {
548 struct fb_info *fbi = dev_get_drvdata(dev);
549 struct mb862xxfb_par *par = fbi->par;
550 char *ptr = buf;
551 unsigned int reg;
552
553 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
554 ptr += sprintf(ptr, "%08x = %08x\n",
555 reg, inreg(disp, reg));
556
557 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
558 ptr += sprintf(ptr, "%08x = %08x\n",
559 reg, inreg(disp, reg));
560
561 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
562 ptr += sprintf(ptr, "%08x = %08x\n",
563 reg, inreg(disp, reg));
564
565 for (reg = 0x400; reg <= 0x410; reg += 4)
566 ptr += sprintf(ptr, "geo %08x = %08x\n",
567 reg, inreg(geo, reg));
568
569 for (reg = 0x400; reg <= 0x410; reg += 4)
570 ptr += sprintf(ptr, "draw %08x = %08x\n",
571 reg, inreg(draw, reg));
572
573 for (reg = 0x440; reg <= 0x450; reg += 4)
574 ptr += sprintf(ptr, "draw %08x = %08x\n",
575 reg, inreg(draw, reg));
576
577 return ptr - buf;
578 }
579
580 static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
581
582 irqreturn_t mb862xx_intr(int irq, void *dev_id)
583 {
584 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
585 unsigned long reg_ist, mask;
586
587 if (!par)
588 return IRQ_NONE;
589
590 if (par->type == BT_CARMINE) {
591 /* Get Interrupt Status */
592 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
593 mask = inreg(ctrl, GC_CTRL_INT_MASK);
594 if (reg_ist == 0)
595 return IRQ_HANDLED;
596
597 reg_ist &= mask;
598 if (reg_ist == 0)
599 return IRQ_HANDLED;
600
601 /* Clear interrupt status */
602 outreg(ctrl, 0x0, reg_ist);
603 } else {
604 /* Get status */
605 reg_ist = inreg(host, GC_IST);
606 mask = inreg(host, GC_IMASK);
607
608 reg_ist &= mask;
609 if (reg_ist == 0)
610 return IRQ_HANDLED;
611
612 /* Clear status */
613 outreg(host, GC_IST, ~reg_ist);
614 }
615 return IRQ_HANDLED;
616 }
617
618 #if defined(CONFIG_FB_MB862XX_LIME)
619 /*
620 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
621 */
622 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
623 {
624 unsigned long ccf, mmr;
625 unsigned long ver, rev;
626
627 if (!par)
628 return -ENODEV;
629
630 #if defined(CONFIG_FB_PRE_INIT_FB)
631 par->pre_init = 1;
632 #endif
633 par->host = par->mmio_base;
634 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
635 par->disp = par->mmio_base + MB862XX_DISP_BASE;
636 par->cap = par->mmio_base + MB862XX_CAP_BASE;
637 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
638 par->geo = par->mmio_base + MB862XX_GEO_BASE;
639 par->pio = par->mmio_base + MB862XX_PIO_BASE;
640
641 par->refclk = GC_DISP_REFCLK_400;
642
643 ver = inreg(host, GC_CID);
644 rev = inreg(pio, GC_REVISION);
645 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
646 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
647 (int)rev & 0xff);
648 par->type = BT_LIME;
649 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
650 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
651 } else {
652 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
653 return -ENODEV;
654 }
655
656 if (!par->pre_init) {
657 outreg(host, GC_CCF, ccf);
658 udelay(200);
659 outreg(host, GC_MMR, mmr);
660 udelay(10);
661 }
662
663 /* interrupt status */
664 outreg(host, GC_IST, 0);
665 outreg(host, GC_IMASK, GC_INT_EN);
666 return 0;
667 }
668
669 static int __devinit of_platform_mb862xx_probe(struct platform_device *ofdev)
670 {
671 struct device_node *np = ofdev->dev.of_node;
672 struct device *dev = &ofdev->dev;
673 struct mb862xxfb_par *par;
674 struct fb_info *info;
675 struct resource res;
676 resource_size_t res_size;
677 unsigned long ret = -ENODEV;
678
679 if (of_address_to_resource(np, 0, &res)) {
680 dev_err(dev, "Invalid address\n");
681 return -ENXIO;
682 }
683
684 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
685 if (info == NULL) {
686 dev_err(dev, "cannot allocate framebuffer\n");
687 return -ENOMEM;
688 }
689
690 par = info->par;
691 par->info = info;
692 par->dev = dev;
693
694 par->irq = irq_of_parse_and_map(np, 0);
695 if (par->irq == NO_IRQ) {
696 dev_err(dev, "failed to map irq\n");
697 ret = -ENODEV;
698 goto fbrel;
699 }
700
701 res_size = resource_size(&res);
702 par->res = request_mem_region(res.start, res_size, DRV_NAME);
703 if (par->res == NULL) {
704 dev_err(dev, "Cannot claim framebuffer/mmio\n");
705 ret = -ENXIO;
706 goto irqdisp;
707 }
708
709 #if defined(CONFIG_SOCRATES)
710 par->gc_mode = &socrates_gc_mode;
711 #endif
712
713 par->fb_base_phys = res.start;
714 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
715 par->mmio_len = MB862XX_MMIO_SIZE;
716 if (par->gc_mode)
717 par->mapped_vram = par->gc_mode->max_vram;
718 else
719 par->mapped_vram = MB862XX_MEM_SIZE;
720
721 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
722 if (par->fb_base == NULL) {
723 dev_err(dev, "Cannot map framebuffer\n");
724 goto rel_reg;
725 }
726
727 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
728 if (par->mmio_base == NULL) {
729 dev_err(dev, "Cannot map registers\n");
730 goto fb_unmap;
731 }
732
733 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
734 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
735 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
736 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
737
738 if (mb862xx_gdc_init(par))
739 goto io_unmap;
740
741 if (request_irq(par->irq, mb862xx_intr, 0,
742 DRV_NAME, (void *)par)) {
743 dev_err(dev, "Cannot request irq\n");
744 goto io_unmap;
745 }
746
747 mb862xxfb_init_fbinfo(info);
748
749 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
750 dev_err(dev, "Could not allocate cmap for fb_info.\n");
751 goto free_irq;
752 }
753
754 if ((info->fbops->fb_set_par)(info))
755 dev_err(dev, "set_var() failed on initial setup?\n");
756
757 if (register_framebuffer(info)) {
758 dev_err(dev, "failed to register framebuffer\n");
759 goto rel_cmap;
760 }
761
762 dev_set_drvdata(dev, info);
763
764 if (device_create_file(dev, &dev_attr_dispregs))
765 dev_err(dev, "Can't create sysfs regdump file\n");
766 return 0;
767
768 rel_cmap:
769 fb_dealloc_cmap(&info->cmap);
770 free_irq:
771 outreg(host, GC_IMASK, 0);
772 free_irq(par->irq, (void *)par);
773 io_unmap:
774 iounmap(par->mmio_base);
775 fb_unmap:
776 iounmap(par->fb_base);
777 rel_reg:
778 release_mem_region(res.start, res_size);
779 irqdisp:
780 irq_dispose_mapping(par->irq);
781 fbrel:
782 dev_set_drvdata(dev, NULL);
783 framebuffer_release(info);
784 return ret;
785 }
786
787 static int __devexit of_platform_mb862xx_remove(struct platform_device *ofdev)
788 {
789 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
790 struct mb862xxfb_par *par = fbi->par;
791 resource_size_t res_size = resource_size(par->res);
792 unsigned long reg;
793
794 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
795
796 /* display off */
797 reg = inreg(disp, GC_DCM1);
798 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
799 outreg(disp, GC_DCM1, reg);
800
801 /* disable interrupts */
802 outreg(host, GC_IMASK, 0);
803
804 free_irq(par->irq, (void *)par);
805 irq_dispose_mapping(par->irq);
806
807 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
808
809 unregister_framebuffer(fbi);
810 fb_dealloc_cmap(&fbi->cmap);
811
812 iounmap(par->mmio_base);
813 iounmap(par->fb_base);
814
815 dev_set_drvdata(&ofdev->dev, NULL);
816 release_mem_region(par->res->start, res_size);
817 framebuffer_release(fbi);
818 return 0;
819 }
820
821 /*
822 * common types
823 */
824 static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
825 { .compatible = "fujitsu,MB86276", },
826 { .compatible = "fujitsu,lime", },
827 { .compatible = "fujitsu,MB86277", },
828 { .compatible = "fujitsu,mint", },
829 { .compatible = "fujitsu,MB86293", },
830 { .compatible = "fujitsu,MB86294", },
831 { .compatible = "fujitsu,coral", },
832 { /* end */ }
833 };
834
835 static struct platform_driver of_platform_mb862xxfb_driver = {
836 .driver = {
837 .name = DRV_NAME,
838 .owner = THIS_MODULE,
839 .of_match_table = of_platform_mb862xx_tbl,
840 },
841 .probe = of_platform_mb862xx_probe,
842 .remove = __devexit_p(of_platform_mb862xx_remove),
843 };
844 #endif
845
846 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
847 static int coralp_init(struct mb862xxfb_par *par)
848 {
849 int cn, ver;
850
851 par->host = par->mmio_base;
852 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
853 par->disp = par->mmio_base + MB862XX_DISP_BASE;
854 par->cap = par->mmio_base + MB862XX_CAP_BASE;
855 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
856 par->geo = par->mmio_base + MB862XX_GEO_BASE;
857 par->pio = par->mmio_base + MB862XX_PIO_BASE;
858
859 par->refclk = GC_DISP_REFCLK_400;
860
861 if (par->mapped_vram >= 0x2000000) {
862 /* relocate gdc registers space */
863 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
864 udelay(1); /* wait at least 20 bus cycles */
865 }
866
867 ver = inreg(host, GC_CID);
868 cn = (ver & GC_CID_CNAME_MSK) >> 8;
869 ver = ver & GC_CID_VERSION_MSK;
870 if (cn == 3) {
871 unsigned long reg;
872
873 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
874 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
875 par->pdev->revision);
876 reg = inreg(disp, GC_DCM1);
877 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
878 par->pre_init = 1;
879
880 if (!par->pre_init) {
881 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
882 udelay(200);
883 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
884 udelay(10);
885 }
886 /* Clear interrupt status */
887 outreg(host, GC_IST, 0);
888 } else {
889 return -ENODEV;
890 }
891
892 mb862xx_i2c_init(par);
893 return 0;
894 }
895
896 static int init_dram_ctrl(struct mb862xxfb_par *par)
897 {
898 unsigned long i = 0;
899
900 /*
901 * Set io mode first! Spec. says IC may be destroyed
902 * if not set to SSTL2/LVCMOS before init.
903 */
904 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
905
906 /* DRAM init */
907 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
908 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
909 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
910 GC_EVB_DCTL_REFRESH_SETTIME2);
911 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
912 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
913 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
914
915 /* DLL reset done? */
916 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
917 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
918 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
919 dev_err(par->dev, "VRAM init failed.\n");
920 return -EINVAL;
921 }
922 }
923 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
924 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
925 return 0;
926 }
927
928 static int carmine_init(struct mb862xxfb_par *par)
929 {
930 unsigned long reg;
931
932 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
933 par->i2c = par->mmio_base + MB86297_I2C_BASE;
934 par->disp = par->mmio_base + MB86297_DISP0_BASE;
935 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
936 par->cap = par->mmio_base + MB86297_CAP0_BASE;
937 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
938 par->draw = par->mmio_base + MB86297_DRAW_BASE;
939 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
940 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
941
942 par->refclk = GC_DISP_REFCLK_533;
943
944 /* warm up */
945 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
946 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
947
948 /* check for engine module revision */
949 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
950 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
951 par->pdev->revision);
952 else
953 goto err_init;
954
955 reg &= ~GC_CTRL_CLK_EN_2D3D;
956 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
957
958 /* set up vram */
959 if (init_dram_ctrl(par) < 0)
960 goto err_init;
961
962 outreg(ctrl, GC_CTRL_INT_MASK, 0);
963 return 0;
964
965 err_init:
966 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
967 return -EINVAL;
968 }
969
970 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
971 {
972 switch (par->type) {
973 case BT_CORALP:
974 return coralp_init(par);
975 case BT_CARMINE:
976 return carmine_init(par);
977 default:
978 return -ENODEV;
979 }
980 }
981
982 #define CHIP_ID(id) \
983 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
984
985 static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
986 /* MB86295/MB86296 */
987 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
988 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
989 /* MB86297 */
990 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
991 { 0, }
992 };
993
994 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
995
996 static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
997 const struct pci_device_id *ent)
998 {
999 struct mb862xxfb_par *par;
1000 struct fb_info *info;
1001 struct device *dev = &pdev->dev;
1002 int ret;
1003
1004 ret = pci_enable_device(pdev);
1005 if (ret < 0) {
1006 dev_err(dev, "Cannot enable PCI device\n");
1007 goto out;
1008 }
1009
1010 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1011 if (!info) {
1012 dev_err(dev, "framebuffer alloc failed\n");
1013 ret = -ENOMEM;
1014 goto dis_dev;
1015 }
1016
1017 par = info->par;
1018 par->info = info;
1019 par->dev = dev;
1020 par->pdev = pdev;
1021 par->irq = pdev->irq;
1022
1023 ret = pci_request_regions(pdev, DRV_NAME);
1024 if (ret < 0) {
1025 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1026 goto rel_fb;
1027 }
1028
1029 switch (pdev->device) {
1030 case PCI_DEVICE_ID_FUJITSU_CORALP:
1031 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1032 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1033 par->mapped_vram = CORALP_MEM_SIZE;
1034 if (par->mapped_vram >= 0x2000000) {
1035 par->mmio_base_phys = par->fb_base_phys +
1036 MB862XX_MMIO_HIGH_BASE;
1037 } else {
1038 par->mmio_base_phys = par->fb_base_phys +
1039 MB862XX_MMIO_BASE;
1040 }
1041 par->mmio_len = MB862XX_MMIO_SIZE;
1042 par->type = BT_CORALP;
1043 break;
1044 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1045 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1046 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1047 par->mmio_len = pci_resource_len(par->pdev, 3);
1048 par->mapped_vram = CARMINE_MEM_SIZE;
1049 par->type = BT_CARMINE;
1050 break;
1051 default:
1052 /* should never occur */
1053 goto rel_reg;
1054 }
1055
1056 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1057 if (par->fb_base == NULL) {
1058 dev_err(dev, "Cannot map framebuffer\n");
1059 goto rel_reg;
1060 }
1061
1062 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1063 if (par->mmio_base == NULL) {
1064 dev_err(dev, "Cannot map registers\n");
1065 ret = -EIO;
1066 goto fb_unmap;
1067 }
1068
1069 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1070 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1071 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1072 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1073
1074 if (mb862xx_pci_gdc_init(par))
1075 goto io_unmap;
1076
1077 if (request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1078 DRV_NAME, (void *)par)) {
1079 dev_err(dev, "Cannot request irq\n");
1080 goto io_unmap;
1081 }
1082
1083 mb862xxfb_init_fbinfo(info);
1084
1085 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1086 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1087 ret = -ENOMEM;
1088 goto free_irq;
1089 }
1090
1091 if ((info->fbops->fb_set_par)(info))
1092 dev_err(dev, "set_var() failed on initial setup?\n");
1093
1094 ret = register_framebuffer(info);
1095 if (ret < 0) {
1096 dev_err(dev, "failed to register framebuffer\n");
1097 goto rel_cmap;
1098 }
1099
1100 pci_set_drvdata(pdev, info);
1101
1102 if (device_create_file(dev, &dev_attr_dispregs))
1103 dev_err(dev, "Can't create sysfs regdump file\n");
1104
1105 if (par->type == BT_CARMINE)
1106 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1107 else
1108 outreg(host, GC_IMASK, GC_INT_EN);
1109
1110 return 0;
1111
1112 rel_cmap:
1113 fb_dealloc_cmap(&info->cmap);
1114 free_irq:
1115 free_irq(par->irq, (void *)par);
1116 io_unmap:
1117 iounmap(par->mmio_base);
1118 fb_unmap:
1119 iounmap(par->fb_base);
1120 rel_reg:
1121 pci_release_regions(pdev);
1122 rel_fb:
1123 framebuffer_release(info);
1124 dis_dev:
1125 pci_disable_device(pdev);
1126 out:
1127 return ret;
1128 }
1129
1130 static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
1131 {
1132 struct fb_info *fbi = pci_get_drvdata(pdev);
1133 struct mb862xxfb_par *par = fbi->par;
1134 unsigned long reg;
1135
1136 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1137
1138 /* display off */
1139 reg = inreg(disp, GC_DCM1);
1140 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1141 outreg(disp, GC_DCM1, reg);
1142
1143 if (par->type == BT_CARMINE) {
1144 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1145 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1146 } else {
1147 outreg(host, GC_IMASK, 0);
1148 }
1149
1150 mb862xx_i2c_exit(par);
1151
1152 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1153
1154 pci_set_drvdata(pdev, NULL);
1155 unregister_framebuffer(fbi);
1156 fb_dealloc_cmap(&fbi->cmap);
1157
1158 free_irq(par->irq, (void *)par);
1159 iounmap(par->mmio_base);
1160 iounmap(par->fb_base);
1161
1162 pci_release_regions(pdev);
1163 framebuffer_release(fbi);
1164 pci_disable_device(pdev);
1165 }
1166
1167 static struct pci_driver mb862xxfb_pci_driver = {
1168 .name = DRV_NAME,
1169 .id_table = mb862xx_pci_tbl,
1170 .probe = mb862xx_pci_probe,
1171 .remove = __devexit_p(mb862xx_pci_remove),
1172 };
1173 #endif
1174
1175 static int __devinit mb862xxfb_init(void)
1176 {
1177 int ret = -ENODEV;
1178
1179 #if defined(CONFIG_FB_MB862XX_LIME)
1180 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1181 #endif
1182 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1183 ret = pci_register_driver(&mb862xxfb_pci_driver);
1184 #endif
1185 return ret;
1186 }
1187
1188 static void __exit mb862xxfb_exit(void)
1189 {
1190 #if defined(CONFIG_FB_MB862XX_LIME)
1191 platform_driver_unregister(&of_platform_mb862xxfb_driver);
1192 #endif
1193 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1194 pci_unregister_driver(&mb862xxfb_pci_driver);
1195 #endif
1196 }
1197
1198 module_init(mb862xxfb_init);
1199 module_exit(mb862xxfb_exit);
1200
1201 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1202 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1203 MODULE_LICENSE("GPL v2");