drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/export.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <video/omapdss.h>
  36 #include <plat/clock.h>
  37 #include "dss.h"
  38 #include "dss_features.h"
  39
  40 #define DSS_SZ_REGS                     SZ_512
  41
  42 struct dss_reg {
  43         u16 idx;
  44 };
  45
  46 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  47
  48 #define DSS_REVISION                    DSS_REG(0x0000)
  49 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  50 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  51 #define DSS_CONTROL                     DSS_REG(0x0040)
  52 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  53 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  54 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  55
  56 #define REG_GET(idx, start, end) \
  57         FLD_GET(dss_read_reg(idx), start, end)
  58
  59 #define REG_FLD_MOD(idx, val, start, end) \
  60         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  61
  62 static struct {
  63         struct platform_device *pdev;
  64         void __iomem    *base;
  65
  66         struct clk      *dpll4_m4_ck;
  67         struct clk      *dss_clk;
  68
  69         unsigned long   cache_req_pck;
  70         unsigned long   cache_prate;
  71         struct dss_clock_info cache_dss_cinfo;
  72         struct dispc_clock_info cache_dispc_cinfo;
  73
  74         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  75         enum omap_dss_clk_source dispc_clk_source;
  76         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  77
  78         bool            ctx_valid;
  79         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  80 } dss;
  81
  82 static const char * const dss_generic_clk_source_names[] = {
  83         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  84         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  85         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
  86 };
  87
  88 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  89 {
  90         __raw_writel(val, dss.base + idx.idx);
  91 }
  92
  93 static inline u32 dss_read_reg(const struct dss_reg idx)
  94 {
  95         return __raw_readl(dss.base + idx.idx);
  96 }
  97
  98 #define SR(reg) \
  99         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 100 #define RR(reg) \
 101         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 102
 103 static void dss_save_context(void)
 104 {
 105         DSSDBG("dss_save_context\n");
 106
 107         SR(CONTROL);
 108
 109         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 110                         OMAP_DISPLAY_TYPE_SDI) {
 111                 SR(SDI_CONTROL);
 112                 SR(PLL_CONTROL);
 113         }
 114
 115         dss.ctx_valid = true;
 116
 117         DSSDBG("context saved\n");
 118 }
 119
 120 static void dss_restore_context(void)
 121 {
 122         DSSDBG("dss_restore_context\n");
 123
 124         if (!dss.ctx_valid)
 125                 return;
 126
 127         RR(CONTROL);
 128
 129         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 130                         OMAP_DISPLAY_TYPE_SDI) {
 131                 RR(SDI_CONTROL);
 132                 RR(PLL_CONTROL);
 133         }
 134
 135         DSSDBG("context restored\n");
 136 }
 137
 138 #undef SR
 139 #undef RR
 140
 141 void dss_sdi_init(u8 datapairs)
 142 {
 143         u32 l;
 144
 145         BUG_ON(datapairs > 3 || datapairs < 1);
 146
 147         l = dss_read_reg(DSS_SDI_CONTROL);
 148         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 149         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 150         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 151         dss_write_reg(DSS_SDI_CONTROL, l);
 152
 153         l = dss_read_reg(DSS_PLL_CONTROL);
 154         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 155         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 156         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 157         dss_write_reg(DSS_PLL_CONTROL, l);
 158 }
 159
 160 int dss_sdi_enable(void)
 161 {
 162         unsigned long timeout;
 163
 164         dispc_pck_free_enable(1);
 165
 166         /* Reset SDI PLL */
 167         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 168         udelay(1);      /* wait 2x PCLK */
 169
 170         /* Lock SDI PLL */
 171         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 172
 173         /* Waiting for PLL lock request to complete */
 174         timeout = jiffies + msecs_to_jiffies(500);
 175         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 176                 if (time_after_eq(jiffies, timeout)) {
 177                         DSSERR("PLL lock request timed out\n");
 178                         goto err1;
 179                 }
 180         }
 181
 182         /* Clearing PLL_GO bit */
 183         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 184
 185         /* Waiting for PLL to lock */
 186         timeout = jiffies + msecs_to_jiffies(500);
 187         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 188                 if (time_after_eq(jiffies, timeout)) {
 189                         DSSERR("PLL lock timed out\n");
 190                         goto err1;
 191                 }
 192         }
 193
 194         dispc_lcd_enable_signal(1);
 195
 196         /* Waiting for SDI reset to complete */
 197         timeout = jiffies + msecs_to_jiffies(500);
 198         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 199                 if (time_after_eq(jiffies, timeout)) {
 200                         DSSERR("SDI reset timed out\n");
 201                         goto err2;
 202                 }
 203         }
 204
 205         return 0;
 206
 207  err2:
 208         dispc_lcd_enable_signal(0);
 209  err1:
 210         /* Reset SDI PLL */
 211         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 212
 213         dispc_pck_free_enable(0);
 214
 215         return -ETIMEDOUT;
 216 }
 217
 218 void dss_sdi_disable(void)
 219 {
 220         dispc_lcd_enable_signal(0);
 221
 222         dispc_pck_free_enable(0);
 223
 224         /* Reset SDI PLL */
 225         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 226 }
 227
 228 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 229 {
 230         return dss_generic_clk_source_names[clk_src];
 231 }
 232
 233
 234 void dss_dump_clocks(struct seq_file *s)
 235 {
 236         unsigned long dpll4_ck_rate;
 237         unsigned long dpll4_m4_ck_rate;
 238         const char *fclk_name, *fclk_real_name;
 239         unsigned long fclk_rate;
 240
 241         if (dss_runtime_get())
 242                 return;
 243
 244         seq_printf(s, "- DSS -\n");
 245
 246         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 247         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 248         fclk_rate = clk_get_rate(dss.dss_clk);
 249
 250         if (dss.dpll4_m4_ck) {
 251                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 252                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 253
 254                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 255
 256                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 257                         seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
 258                                         fclk_name, fclk_real_name,
 259                                         dpll4_ck_rate,
 260                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 261                                         fclk_rate);
 262                 else
 263                         seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
 264                                         fclk_name, fclk_real_name,
 265                                         dpll4_ck_rate,
 266                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 267                                         fclk_rate);
 268         } else {
 269                 seq_printf(s, "%s (%s) = %lu\n",
 270                                 fclk_name, fclk_real_name,
 271                                 fclk_rate);
 272         }
 273
 274         dss_runtime_put();
 275 }
 276
 277 void dss_dump_regs(struct seq_file *s)
 278 {
 279 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 280
 281         if (dss_runtime_get())
 282                 return;
 283
 284         DUMPREG(DSS_REVISION);
 285         DUMPREG(DSS_SYSCONFIG);
 286         DUMPREG(DSS_SYSSTATUS);
 287         DUMPREG(DSS_CONTROL);
 288
 289         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 290                         OMAP_DISPLAY_TYPE_SDI) {
 291                 DUMPREG(DSS_SDI_CONTROL);
 292                 DUMPREG(DSS_PLL_CONTROL);
 293                 DUMPREG(DSS_SDI_STATUS);
 294         }
 295
 296         dss_runtime_put();
 297 #undef DUMPREG
 298 }
 299
 300 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 301 {
 302         struct platform_device *dsidev;
 303         int b;
 304         u8 start, end;
 305
 306         switch (clk_src) {
 307         case OMAP_DSS_CLK_SRC_FCK:
 308                 b = 0;
 309                 break;
 310         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 311                 b = 1;
 312                 dsidev = dsi_get_dsidev_from_id(0);
 313                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 314                 break;
 315         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 316                 b = 2;
 317                 dsidev = dsi_get_dsidev_from_id(1);
 318                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 319                 break;
 320         default:
 321                 BUG();
 322         }
 323
 324         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 325
 326         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 327
 328         dss.dispc_clk_source = clk_src;
 329 }
 330
 331 void dss_select_dsi_clk_source(int dsi_module,
 332                 enum omap_dss_clk_source clk_src)
 333 {
 334         struct platform_device *dsidev;
 335         int b;
 336
 337         switch (clk_src) {
 338         case OMAP_DSS_CLK_SRC_FCK:
 339                 b = 0;
 340                 break;
 341         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 342                 BUG_ON(dsi_module != 0);
 343                 b = 1;
 344                 dsidev = dsi_get_dsidev_from_id(0);
 345                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 346                 break;
 347         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 348                 BUG_ON(dsi_module != 1);
 349                 b = 1;
 350                 dsidev = dsi_get_dsidev_from_id(1);
 351                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 352                 break;
 353         default:
 354                 BUG();
 355         }
 356
 357         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 358
 359         dss.dsi_clk_source[dsi_module] = clk_src;
 360 }
 361
 362 void dss_select_lcd_clk_source(enum omap_channel channel,
 363                 enum omap_dss_clk_source clk_src)
 364 {
 365         struct platform_device *dsidev;
 366         int b, ix, pos;
 367
 368         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 369                 return;
 370
 371         switch (clk_src) {
 372         case OMAP_DSS_CLK_SRC_FCK:
 373                 b = 0;
 374                 break;
 375         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 376                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 377                 b = 1;
 378                 dsidev = dsi_get_dsidev_from_id(0);
 379                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 380                 break;
 381         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 382                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
 383                 b = 1;
 384                 dsidev = dsi_get_dsidev_from_id(1);
 385                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 386                 break;
 387         default:
 388                 BUG();
 389         }
 390
 391         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
 392         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 393
 394         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 395         dss.lcd_clk_source[ix] = clk_src;
 396 }
 397
 398 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 399 {
 400         return dss.dispc_clk_source;
 401 }
 402
 403 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 404 {
 405         return dss.dsi_clk_source[dsi_module];
 406 }
 407
 408 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 409 {
 410         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 411                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 412                 return dss.lcd_clk_source[ix];
 413         } else {
 414                 /* LCD_CLK source is the same as DISPC_FCLK source for
 415                  * OMAP2 and OMAP3 */
 416                 return dss.dispc_clk_source;
 417         }
 418 }
 419
 420 /* calculate clock rates using dividers in cinfo */
 421 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 422 {
 423         if (dss.dpll4_m4_ck) {
 424                 unsigned long prate;
 425                 u16 fck_div_max = 16;
 426
 427                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 428                         fck_div_max = 32;
 429
 430                 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
 431                         return -EINVAL;
 432
 433                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 434
 435                 cinfo->fck = prate / cinfo->fck_div;
 436         } else {
 437                 if (cinfo->fck_div != 0)
 438                         return -EINVAL;
 439                 cinfo->fck = clk_get_rate(dss.dss_clk);
 440         }
 441
 442         return 0;
 443 }
 444
 445 int dss_set_clock_div(struct dss_clock_info *cinfo)
 446 {
 447         if (dss.dpll4_m4_ck) {
 448                 unsigned long prate;
 449                 int r;
 450
 451                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 452                 DSSDBG("dpll4_m4 = %ld\n", prate);
 453
 454                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 455                 if (r)
 456                         return r;
 457         } else {
 458                 if (cinfo->fck_div != 0)
 459                         return -EINVAL;
 460         }
 461
 462         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 463
 464         return 0;
 465 }
 466
 467 int dss_get_clock_div(struct dss_clock_info *cinfo)
 468 {
 469         cinfo->fck = clk_get_rate(dss.dss_clk);
 470
 471         if (dss.dpll4_m4_ck) {
 472                 unsigned long prate;
 473
 474                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 475
 476                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 477                         cinfo->fck_div = prate / (cinfo->fck);
 478                 else
 479                         cinfo->fck_div = prate / (cinfo->fck / 2);
 480         } else {
 481                 cinfo->fck_div = 0;
 482         }
 483
 484         return 0;
 485 }
 486
 487 unsigned long dss_get_dpll4_rate(void)
 488 {
 489         if (dss.dpll4_m4_ck)
 490                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 491         else
 492                 return 0;
 493 }
 494
 495 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 496                 struct dss_clock_info *dss_cinfo,
 497                 struct dispc_clock_info *dispc_cinfo)
 498 {
 499         unsigned long prate;
 500         struct dss_clock_info best_dss;
 501         struct dispc_clock_info best_dispc;
 502
 503         unsigned long fck, max_dss_fck;
 504
 505         u16 fck_div, fck_div_max = 16;
 506
 507         int match = 0;
 508         int min_fck_per_pck;
 509
 510         prate = dss_get_dpll4_rate();
 511
 512         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 513
 514         fck = clk_get_rate(dss.dss_clk);
 515         if (req_pck == dss.cache_req_pck &&
 516                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 517                          dss.cache_dss_cinfo.fck == fck)) {
 518                 DSSDBG("dispc clock info found from cache.\n");
 519                 *dss_cinfo = dss.cache_dss_cinfo;
 520                 *dispc_cinfo = dss.cache_dispc_cinfo;
 521                 return 0;
 522         }
 523
 524         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 525
 526         if (min_fck_per_pck &&
 527                 req_pck * min_fck_per_pck > max_dss_fck) {
 528                 DSSERR("Requested pixel clock not possible with the current "
 529                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 530                                 "the constraint off.\n");
 531                 min_fck_per_pck = 0;
 532         }
 533
 534 retry:
 535         memset(&best_dss, 0, sizeof(best_dss));
 536         memset(&best_dispc, 0, sizeof(best_dispc));
 537
 538         if (dss.dpll4_m4_ck == NULL) {
 539                 struct dispc_clock_info cur_dispc;
 540                 /* XXX can we change the clock on omap2? */
 541                 fck = clk_get_rate(dss.dss_clk);
 542                 fck_div = 1;
 543
 544                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 545                 match = 1;
 546
 547                 best_dss.fck = fck;
 548                 best_dss.fck_div = fck_div;
 549
 550                 best_dispc = cur_dispc;
 551
 552                 goto found;
 553         } else {
 554                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 555                         fck_div_max = 32;
 556
 557                 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
 558                         struct dispc_clock_info cur_dispc;
 559
 560                         if (fck_div_max == 32)
 561                                 fck = prate / fck_div;
 562                         else
 563                                 fck = prate / fck_div * 2;
 564
 565                         if (fck > max_dss_fck)
 566                                 continue;
 567
 568                         if (min_fck_per_pck &&
 569                                         fck < req_pck * min_fck_per_pck)
 570                                 continue;
 571
 572                         match = 1;
 573
 574                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 575
 576                         if (abs(cur_dispc.pck - req_pck) <
 577                                         abs(best_dispc.pck - req_pck)) {
 578
 579                                 best_dss.fck = fck;
 580                                 best_dss.fck_div = fck_div;
 581
 582                                 best_dispc = cur_dispc;
 583
 584                                 if (cur_dispc.pck == req_pck)
 585                                         goto found;
 586                         }
 587                 }
 588         }
 589
 590 found:
 591         if (!match) {
 592                 if (min_fck_per_pck) {
 593                         DSSERR("Could not find suitable clock settings.\n"
 594                                         "Turning FCK/PCK constraint off and"
 595                                         "trying again.\n");
 596                         min_fck_per_pck = 0;
 597                         goto retry;
 598                 }
 599
 600                 DSSERR("Could not find suitable clock settings.\n");
 601
 602                 return -EINVAL;
 603         }
 604
 605         if (dss_cinfo)
 606                 *dss_cinfo = best_dss;
 607         if (dispc_cinfo)
 608                 *dispc_cinfo = best_dispc;
 609
 610         dss.cache_req_pck = req_pck;
 611         dss.cache_prate = prate;
 612         dss.cache_dss_cinfo = best_dss;
 613         dss.cache_dispc_cinfo = best_dispc;
 614
 615         return 0;
 616 }
 617
 618 void dss_set_venc_output(enum omap_dss_venc_type type)
 619 {
 620         int l = 0;
 621
 622         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 623                 l = 0;
 624         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 625                 l = 1;
 626         else
 627                 BUG();
 628
 629         /* venc out selection. 0 = comp, 1 = svideo */
 630         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 631 }
 632
 633 void dss_set_dac_pwrdn_bgz(bool enable)
 634 {
 635         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 636 }
 637
 638 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 639 {
 640         REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
 641 }
 642
 643 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 644 {
 645         enum omap_display_type displays;
 646
 647         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 648         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 649                 return DSS_VENC_TV_CLK;
 650
 651         return REG_GET(DSS_CONTROL, 15, 15);
 652 }
 653
 654 static int dss_get_clocks(void)
 655 {
 656         struct clk *clk;
 657         int r;
 658
 659         clk = clk_get(&dss.pdev->dev, "fck");
 660         if (IS_ERR(clk)) {
 661                 DSSERR("can't get clock fck\n");
 662                 r = PTR_ERR(clk);
 663                 goto err;
 664         }
 665
 666         dss.dss_clk = clk;
 667
 668         if (cpu_is_omap34xx()) {
 669                 clk = clk_get(NULL, "dpll4_m4_ck");
 670                 if (IS_ERR(clk)) {
 671                         DSSERR("Failed to get dpll4_m4_ck\n");
 672                         r = PTR_ERR(clk);
 673                         goto err;
 674                 }
 675         } else if (cpu_is_omap44xx()) {
 676                 clk = clk_get(NULL, "dpll_per_m5x2_ck");
 677                 if (IS_ERR(clk)) {
 678                         DSSERR("Failed to get dpll_per_m5x2_ck\n");
 679                         r = PTR_ERR(clk);
 680                         goto err;
 681                 }
 682         } else { /* omap24xx */
 683                 clk = NULL;
 684         }
 685
 686         dss.dpll4_m4_ck = clk;
 687
 688         return 0;
 689
 690 err:
 691         if (dss.dss_clk)
 692                 clk_put(dss.dss_clk);
 693         if (dss.dpll4_m4_ck)
 694                 clk_put(dss.dpll4_m4_ck);
 695
 696         return r;
 697 }
 698
 699 static void dss_put_clocks(void)
 700 {
 701         if (dss.dpll4_m4_ck)
 702                 clk_put(dss.dpll4_m4_ck);
 703         clk_put(dss.dss_clk);
 704 }
 705
 706 int dss_runtime_get(void)
 707 {
 708         int r;
 709
 710         DSSDBG("dss_runtime_get\n");
 711
 712         r = pm_runtime_get_sync(&dss.pdev->dev);
 713         WARN_ON(r < 0);
 714         return r < 0 ? r : 0;
 715 }
 716
 717 void dss_runtime_put(void)
 718 {
 719         int r;
 720
 721         DSSDBG("dss_runtime_put\n");
 722
 723         r = pm_runtime_put_sync(&dss.pdev->dev);
 724         WARN_ON(r < 0);
 725 }
 726
 727 /* DEBUGFS */
 728 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 729 void dss_debug_dump_clocks(struct seq_file *s)
 730 {
 731         dss_dump_clocks(s);
 732         dispc_dump_clocks(s);
 733 #ifdef CONFIG_OMAP2_DSS_DSI
 734         dsi_dump_clocks(s);
 735 #endif
 736 }
 737 #endif
 738
 739 /* DSS HW IP initialisation */
 740 static int omap_dsshw_probe(struct platform_device *pdev)
 741 {
 742         struct resource *dss_mem;
 743         u32 rev;
 744         int r;
 745
 746         dss.pdev = pdev;
 747
 748         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 749         if (!dss_mem) {
 750                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 751                 r = -EINVAL;
 752                 goto err_ioremap;
 753         }
 754         dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
 755         if (!dss.base) {
 756                 DSSERR("can't ioremap DSS\n");
 757                 r = -ENOMEM;
 758                 goto err_ioremap;
 759         }
 760
 761         r = dss_get_clocks();
 762         if (r)
 763                 goto err_clocks;
 764
 765         pm_runtime_enable(&pdev->dev);
 766
 767         r = dss_runtime_get();
 768         if (r)
 769                 goto err_runtime_get;
 770
 771         /* Select DPLL */
 772         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 773
 774 #ifdef CONFIG_OMAP2_DSS_VENC
 775         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 776         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 777         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 778 #endif
 779         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 780         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 781         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 782         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 783         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 784
 785         r = dpi_init();
 786         if (r) {
 787                 DSSERR("Failed to initialize DPI\n");
 788                 goto err_dpi;
 789         }
 790
 791         r = sdi_init();
 792         if (r) {
 793                 DSSERR("Failed to initialize SDI\n");
 794                 goto err_sdi;
 795         }
 796
 797         rev = dss_read_reg(DSS_REVISION);
 798         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 799                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 800
 801         dss_runtime_put();
 802
 803         return 0;
 804 err_sdi:
 805         dpi_exit();
 806 err_dpi:
 807         dss_runtime_put();
 808 err_runtime_get:
 809         pm_runtime_disable(&pdev->dev);
 810         dss_put_clocks();
 811 err_clocks:
 812         iounmap(dss.base);
 813 err_ioremap:
 814         return r;
 815 }
 816
 817 static int omap_dsshw_remove(struct platform_device *pdev)
 818 {
 819         dpi_exit();
 820         sdi_exit();
 821
 822         iounmap(dss.base);
 823
 824         pm_runtime_disable(&pdev->dev);
 825
 826         dss_put_clocks();
 827
 828         return 0;
 829 }
 830
 831 static int dss_runtime_suspend(struct device *dev)
 832 {
 833         dss_save_context();
 834         return 0;
 835 }
 836
 837 static int dss_runtime_resume(struct device *dev)
 838 {
 839         dss_restore_context();
 840         return 0;
 841 }
 842
 843 static const struct dev_pm_ops dss_pm_ops = {
 844         .runtime_suspend = dss_runtime_suspend,
 845         .runtime_resume = dss_runtime_resume,
 846 };
 847
 848 static struct platform_driver omap_dsshw_driver = {
 849         .probe          = omap_dsshw_probe,
 850         .remove         = omap_dsshw_remove,
 851         .driver         = {
 852                 .name   = "omapdss_dss",
 853                 .owner  = THIS_MODULE,
 854                 .pm     = &dss_pm_ops,
 855         },
 856 };
 857
 858 int dss_init_platform_driver(void)
 859 {
 860         return platform_driver_register(&omap_dsshw_driver);
 861 }
 862
 863 void dss_uninit_platform_driver(void)
 864 {
 865         return platform_driver_unregister(&omap_dsshw_driver);
 866 }