drivers/atm/he.h

   1 /*
   2
   3   he.h
   4
   5   ForeRunnerHE ATM Adapter driver for ATM on Linux
   6   Copyright (C) 1999-2001  Naval Research Laboratory
   7
   8   This library is free software; you can redistribute it and/or
   9   modify it under the terms of the GNU Lesser General Public
  10   License as published by the Free Software Foundation; either
  11   version 2.1 of the License, or (at your option) any later version.
  12
  13   This library is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16   Lesser General Public License for more details.
  17
  18   You should have received a copy of the GNU Lesser General Public
  19   License along with this library; if not, write to the Free Software
  20   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21
  22 */
  23
  24 /*
  25
  26   he.h
  27
  28   ForeRunnerHE ATM Adapter driver for ATM on Linux
  29   Copyright (C) 1999-2000  Naval Research Laboratory
  30
  31   Permission to use, copy, modify and distribute this software and its
  32   documentation is hereby granted, provided that both the copyright
  33   notice and this permission notice appear in all copies of the software,
  34   derivative works or modified versions, and any portions thereof, and
  35   that both notices appear in supporting documentation.
  36
  37   NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
  38   DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
  39   RESULTING FROM THE USE OF THIS SOFTWARE.
  40
  41  */
  42
  43 #ifndef _HE_H_
  44 #define _HE_H_
  45
  46 #define DEV_LABEL       "he"
  47
  48 #define CONFIG_DEFAULT_VCIBITS  12
  49 #define CONFIG_DEFAULT_VPIBITS  0
  50
  51 #define CONFIG_IRQ_SIZE         128
  52 #define CONFIG_IRQ_THRESH       (CONFIG_IRQ_SIZE/2)
  53
  54 #define CONFIG_TPDRQ_SIZE       512
  55 #define TPDRQ_MASK(x)           (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1))
  56
  57 #define CONFIG_RBRQ_SIZE        512
  58 #define CONFIG_RBRQ_THRESH      400
  59 #define RBRQ_MASK(x)            (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1))
  60
  61 #define CONFIG_TBRQ_SIZE        512
  62 #define CONFIG_TBRQ_THRESH      400
  63 #define TBRQ_MASK(x)            (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1))
  64
  65 #define CONFIG_RBPL_SIZE        512
  66 #define CONFIG_RBPL_THRESH      64
  67 #define CONFIG_RBPL_BUFSIZE     4096
  68 #define RBPL_MASK(x)            (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1))
  69
  70 #define CONFIG_RBPS_SIZE        1024
  71 #define CONFIG_RBPS_THRESH      64
  72 #define CONFIG_RBPS_BUFSIZE     128
  73 #define RBPS_MASK(x)            (((unsigned long)(x))&((CONFIG_RBPS_SIZE<<3)-1))
  74
  75 /* 5.1.3 initialize connection memory */
  76
  77 #define CONFIG_RSRA             0x00000
  78 #define CONFIG_RCMLBM           0x08000
  79 #define CONFIG_RCMABR           0x0d800
  80 #define CONFIG_RSRB             0x0e000
  81
  82 #define CONFIG_TSRA             0x00000
  83 #define CONFIG_TSRB             0x08000
  84 #define CONFIG_TSRC             0x0c000
  85 #define CONFIG_TSRD             0x0e000
  86 #define CONFIG_TMABR            0x0f000
  87 #define CONFIG_TPDBA            0x10000
  88
  89 #define HE_MAXCIDBITS           12
  90
  91 /* 2.9.3.3 interrupt encodings */
  92
  93 struct he_irq {
  94         volatile u32 isw;
  95 };
  96
  97 #define IRQ_ALIGNMENT           0x1000
  98
  99 #define NEXT_ENTRY(base, tail, mask) \
 100                                 (((unsigned long)base)|(((unsigned long)(tail+1))&mask))
 101
 102 #define ITYPE_INVALID           0xffffffff
 103 #define ITYPE_TBRQ_THRESH       (0<<3)
 104 #define ITYPE_TPD_COMPLETE      (1<<3)
 105 #define ITYPE_RBPS_THRESH       (2<<3)
 106 #define ITYPE_RBPL_THRESH       (3<<3)
 107 #define ITYPE_RBRQ_THRESH       (4<<3)
 108 #define ITYPE_RBRQ_TIMER        (5<<3)
 109 #define ITYPE_PHY               (6<<3)
 110 #define ITYPE_OTHER             0x80
 111 #define ITYPE_PARITY            0x81
 112 #define ITYPE_ABORT             0x82
 113
 114 #define ITYPE_GROUP(x)          (x & 0x7)
 115 #define ITYPE_TYPE(x)           (x & 0xf8)
 116
 117 #define HE_NUM_GROUPS 8
 118
 119 /* 2.1.4 transmit packet descriptor */
 120
 121 struct he_tpd {
 122
 123         /* read by the adapter */
 124
 125         volatile u32 status;
 126         volatile u32 reserved;
 127
 128 #define TPD_MAXIOV      3
 129         struct {
 130                 u32 addr, len;
 131         } iovec[TPD_MAXIOV];
 132
 133 #define address0 iovec[0].addr
 134 #define length0 iovec[0].len
 135
 136         /* linux-atm extensions */
 137
 138         struct sk_buff *skb;
 139         struct atm_vcc *vcc;
 140
 141         struct list_head entry;
 142 };
 143
 144 #define TPD_ALIGNMENT   64
 145 #define TPD_LEN_MASK    0xffff
 146
 147 #define TPD_ADDR_SHIFT  6
 148 #define TPD_MASK        0xffffffc0
 149 #define TPD_ADDR(x)     ((x) & TPD_MASK)
 150 #define TPD_INDEX(x)    (TPD_ADDR(x) >> TPD_ADDR_SHIFT)
 151
 152
 153 /* table 2.3 transmit buffer return elements */
 154
 155 struct he_tbrq {
 156         volatile u32 tbre;
 157 };
 158
 159 #define TBRQ_ALIGNMENT  CONFIG_TBRQ_SIZE
 160
 161 #define TBRQ_TPD(tbrq)          ((tbrq)->tbre & 0xffffffc0)
 162 #define TBRQ_EOS(tbrq)          ((tbrq)->tbre & (1<<3))
 163 #define TBRQ_MULTIPLE(tbrq)     ((tbrq)->tbre & (1))
 164
 165 /* table 2.21 receive buffer return queue element field organization */
 166
 167 struct he_rbrq {
 168         volatile u32 addr;
 169         volatile u32 cidlen;
 170 };
 171
 172 #define RBRQ_ALIGNMENT  CONFIG_RBRQ_SIZE
 173
 174 #define RBRQ_ADDR(rbrq)         ((rbrq)->addr & 0xffffffc0)
 175 #define RBRQ_CRC_ERR(rbrq)      ((rbrq)->addr & (1<<5))
 176 #define RBRQ_LEN_ERR(rbrq)      ((rbrq)->addr & (1<<4))
 177 #define RBRQ_END_PDU(rbrq)      ((rbrq)->addr & (1<<3))
 178 #define RBRQ_AAL5_PROT(rbrq)    ((rbrq)->addr & (1<<2))
 179 #define RBRQ_CON_CLOSED(rbrq)   ((rbrq)->addr & (1<<1))
 180 #define RBRQ_HBUF_ERR(rbrq)     ((rbrq)->addr & 1)
 181 #define RBRQ_CID(rbrq)          (((rbrq)->cidlen >> 16) & 0x1fff)
 182 #define RBRQ_BUFLEN(rbrq)       ((rbrq)->cidlen & 0xffff)
 183
 184 /* figure 2.3 transmit packet descriptor ready queue */
 185
 186 struct he_tpdrq {
 187         volatile u32 tpd;
 188         volatile u32 cid;
 189 };
 190
 191 #define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE
 192
 193 /* table 2.30 host status page detail */
 194
 195 #define HSP_ALIGNMENT   0x400           /* must align on 1k boundary */
 196
 197 struct he_hsp {
 198         struct he_hsp_entry {
 199                 volatile u32 tbrq_tail;
 200                 volatile u32 reserved1[15];
 201                 volatile u32 rbrq_tail;
 202                 volatile u32 reserved2[15];
 203         } group[HE_NUM_GROUPS];
 204 };
 205
 206 /* figure 2.9 receive buffer pools */
 207
 208 struct he_rbp {
 209         volatile u32 phys;
 210         volatile u32 status;
 211 };
 212
 213 /* NOTE: it is suggested that virt be the virtual address of the host
 214    buffer.  on a 64-bit machine, this would not work.  Instead, we
 215    store the real virtual address in another list, and store an index
 216    (and buffer status) in the virt member.
 217 */
 218
 219 #define RBP_INDEX_OFF   6
 220 #define RBP_INDEX(x)    (((long)(x) >> RBP_INDEX_OFF) & 0xffff)
 221 #define RBP_LOANED      0x80000000
 222 #define RBP_SMALLBUF    0x40000000
 223
 224 struct he_virt {
 225         void *virt;
 226 };
 227
 228 #define RBPL_ALIGNMENT CONFIG_RBPL_SIZE
 229 #define RBPS_ALIGNMENT CONFIG_RBPS_SIZE
 230
 231 #ifdef notyet
 232 struct he_group {
 233         u32 rpbs_size, rpbs_qsize;
 234         struct he_rbp rbps_ba;
 235
 236         u32 rpbl_size, rpbl_qsize;
 237         struct he_rpb_entry *rbpl_ba;
 238 };
 239 #endif
 240
 241 #define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc)
 242
 243 struct he_vcc_table
 244 {
 245         struct atm_vcc *vcc;
 246 };
 247
 248 struct he_cs_stper
 249 {
 250         long pcr;
 251         int inuse;
 252 };
 253
 254 #define HE_NUM_CS_STPER         16
 255
 256 struct he_dev {
 257         unsigned int number;
 258         unsigned int irq;
 259         void __iomem *membase;
 260
 261         char prod_id[30];
 262         char mac_addr[6];
 263         int media;
 264
 265         unsigned int vcibits, vpibits;
 266         unsigned int cells_per_row;
 267         unsigned int bytes_per_row;
 268         unsigned int cells_per_lbuf;
 269         unsigned int r0_numrows, r0_startrow, r0_numbuffs;
 270         unsigned int r1_numrows, r1_startrow, r1_numbuffs;
 271         unsigned int tx_numrows, tx_startrow, tx_numbuffs;
 272         unsigned int buffer_limit;
 273
 274         struct he_vcc_table *he_vcc_table;
 275
 276 #ifdef notyet
 277         struct he_group group[HE_NUM_GROUPS];
 278 #endif
 279         struct he_cs_stper cs_stper[HE_NUM_CS_STPER];
 280         unsigned total_bw;
 281
 282         dma_addr_t irq_phys;
 283         struct he_irq *irq_base, *irq_head, *irq_tail;
 284         volatile unsigned *irq_tailoffset;
 285         int irq_peak;
 286
 287         struct tasklet_struct tasklet;
 288         struct pci_pool *tpd_pool;
 289         struct list_head outstanding_tpds;
 290
 291         dma_addr_t tpdrq_phys;
 292         struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head;
 293
 294         spinlock_t global_lock;         /* 8.1.5 pci transaction ordering
 295                                           error problem */
 296         dma_addr_t rbrq_phys;
 297         struct he_rbrq *rbrq_base, *rbrq_head;
 298         int rbrq_peak;
 299
 300         struct pci_pool *rbpl_pool;
 301         dma_addr_t rbpl_phys;
 302         struct he_rbp *rbpl_base, *rbpl_tail;
 303         struct he_virt *rbpl_virt;
 304         int rbpl_peak;
 305
 306         struct pci_pool *rbps_pool;
 307         dma_addr_t rbps_phys;
 308         struct he_rbp *rbps_base, *rbps_tail;
 309         struct he_virt *rbps_virt;
 310         int rbps_peak;
 311
 312         dma_addr_t tbrq_phys;
 313         struct he_tbrq *tbrq_base, *tbrq_head;
 314         int tbrq_peak;
 315
 316         dma_addr_t hsp_phys;
 317         struct he_hsp *hsp;
 318
 319         struct pci_dev *pci_dev;
 320         struct atm_dev *atm_dev;
 321         struct he_dev *next;
 322 };
 323
 324 struct he_iovec
 325 {
 326         u32 iov_base;
 327         u32 iov_len;
 328 };
 329
 330 #define HE_MAXIOV 20
 331
 332 struct he_vcc
 333 {
 334         struct he_iovec iov_head[HE_MAXIOV];
 335         struct he_iovec *iov_tail;
 336         int pdu_len;
 337
 338         int rc_index;
 339
 340         wait_queue_head_t rx_waitq;
 341         wait_queue_head_t tx_waitq;
 342 };
 343
 344 #define HE_VCC(vcc)     ((struct he_vcc *)(vcc->dev_data))
 345
 346 #define PCI_VENDOR_ID_FORE      0x1127
 347 #define PCI_DEVICE_ID_FORE_HE   0x400
 348
 349 #define GEN_CNTL_0                              0x40
 350 #define  INT_PROC_ENBL          (1<<25)
 351 #define  SLAVE_ENDIAN_MODE      (1<<16)
 352 #define  MRL_ENB                (1<<5)
 353 #define  MRM_ENB                (1<<4)
 354 #define  INIT_ENB               (1<<2)
 355 #define  IGNORE_TIMEOUT         (1<<1)
 356 #define  ENBL_64                (1<<0)
 357
 358 #define MIN_PCI_LATENCY         32      /* errata 8.1.3 */
 359
 360 #define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data)
 361
 362 #define he_is622(dev)   ((dev)->media & 0x1)
 363 #define he_isMM(dev)    ((dev)->media & 0x20)
 364
 365 #define HE_REGMAP_SIZE  0x100000
 366
 367 #define RESET_CNTL      0x80000
 368 #define  BOARD_RST_STATUS       (1<<6)
 369
 370 #define HOST_CNTL       0x80004
 371 #define  PCI_BUS_SIZE64                 (1<<27)
 372 #define  DESC_RD_STATIC_64              (1<<26)
 373 #define  DATA_RD_STATIC_64              (1<<25)
 374 #define  DATA_WR_STATIC_64              (1<<24)
 375 #define  ID_CS                          (1<<12)
 376 #define  ID_WREN                        (1<<11)
 377 #define  ID_DOUT                        (1<<10)
 378 #define   ID_DOFFSET                    10
 379 #define  ID_DIN                         (1<<9)
 380 #define  ID_CLOCK                       (1<<8)
 381 #define  QUICK_RD_RETRY                 (1<<7)
 382 #define  QUICK_WR_RETRY                 (1<<6)
 383 #define  OUTFF_ENB                      (1<<5)
 384 #define  CMDFF_ENB                      (1<<4)
 385 #define  PERR_INT_ENB                   (1<<2)
 386 #define  IGNORE_INTR                    (1<<0)
 387
 388 #define LB_SWAP         0x80008
 389 #define  SWAP_RNUM_MAX(x)       (x<<27)
 390 #define  DATA_WR_SWAP           (1<<20)
 391 #define  DESC_RD_SWAP           (1<<19)
 392 #define  DATA_RD_SWAP           (1<<18)
 393 #define  INTR_SWAP              (1<<17)
 394 #define  DESC_WR_SWAP           (1<<16)
 395 #define  SDRAM_INIT             (1<<15)
 396 #define  BIG_ENDIAN_HOST        (1<<14)
 397 #define  XFER_SIZE              (1<<7)
 398
 399 #define LB_MEM_ADDR     0x8000c
 400 #define LB_MEM_DATA     0x80010
 401
 402 #define LB_MEM_ACCESS   0x80014
 403 #define  LB_MEM_HNDSHK          (1<<30)
 404 #define  LM_MEM_WRITE           (0x7)
 405 #define  LM_MEM_READ            (0x3)
 406
 407 #define SDRAM_CTL       0x80018
 408 #define  LB_64_ENB              (1<<3)
 409 #define  LB_TWR                 (1<<2)
 410 #define  LB_TRP                 (1<<1)
 411 #define  LB_TRAS                (1<<0)
 412
 413 #define INT_FIFO        0x8001c
 414 #define  INT_MASK_D             (1<<15)
 415 #define  INT_MASK_C             (1<<14)
 416 #define  INT_MASK_B             (1<<13)
 417 #define  INT_MASK_A             (1<<12)
 418 #define  INT_CLEAR_D            (1<<11)
 419 #define  INT_CLEAR_C            (1<<10)
 420 #define  INT_CLEAR_B            (1<<9)
 421 #define  INT_CLEAR_A            (1<<8)
 422
 423 #define ABORT_ADDR      0x80020
 424
 425 #define IRQ0_BASE       0x80080
 426 #define  IRQ_BASE(x)            (x<<12)
 427 #define  IRQ_MASK               ((CONFIG_IRQ_SIZE<<2)-1)        /* was 0x3ff */
 428 #define  IRQ_TAIL(x)            (((unsigned long)(x)) & IRQ_MASK)
 429 #define IRQ0_HEAD       0x80084
 430 #define  IRQ_SIZE(x)            (x<<22)
 431 #define  IRQ_THRESH(x)          (x<<12)
 432 #define  IRQ_HEAD(x)            (x<<2)
 433 /* #define  IRQ_PENDING         (1)             conflict with linux/irq.h */
 434 #define IRQ0_CNTL       0x80088
 435 #define  IRQ_ADDRSEL(x)         (x<<2)
 436 #define  IRQ_INT_A              (0<<2)
 437 #define  IRQ_INT_B              (1<<2)
 438 #define  IRQ_INT_C              (2<<2)
 439 #define  IRQ_INT_D              (3<<2)
 440 #define  IRQ_TYPE_ADDR          0x1
 441 #define  IRQ_TYPE_LINE          0x0
 442 #define IRQ0_DATA       0x8008c
 443
 444 #define IRQ1_BASE       0x80090
 445 #define IRQ1_HEAD       0x80094
 446 #define IRQ1_CNTL       0x80098
 447 #define IRQ1_DATA       0x8009c
 448
 449 #define IRQ2_BASE       0x800a0
 450 #define IRQ2_HEAD       0x800a4
 451 #define IRQ2_CNTL       0x800a8
 452 #define IRQ2_DATA       0x800ac
 453
 454 #define IRQ3_BASE       0x800b0
 455 #define IRQ3_HEAD       0x800b4
 456 #define IRQ3_CNTL       0x800b8
 457 #define IRQ3_DATA       0x800bc
 458
 459 #define GRP_10_MAP      0x800c0
 460 #define GRP_32_MAP      0x800c4
 461 #define GRP_54_MAP      0x800c8
 462 #define GRP_76_MAP      0x800cc
 463
 464 #define G0_RBPS_S       0x80400
 465 #define G0_RBPS_T       0x80404
 466 #define  RBP_TAIL(x)            ((x)<<3)
 467 #define  RBP_MASK(x)            ((x)|0x1fff)
 468 #define G0_RBPS_QI      0x80408
 469 #define  RBP_QSIZE(x)           ((x)<<14)
 470 #define  RBP_INT_ENB            (1<<13)
 471 #define  RBP_THRESH(x)          (x)
 472 #define G0_RBPS_BS      0x8040c
 473 #define G0_RBPL_S       0x80410
 474 #define G0_RBPL_T       0x80414
 475 #define G0_RBPL_QI      0x80418
 476 #define G0_RBPL_BS      0x8041c
 477
 478 #define G1_RBPS_S       0x80420
 479 #define G1_RBPS_T       0x80424
 480 #define G1_RBPS_QI      0x80428
 481 #define G1_RBPS_BS      0x8042c
 482 #define G1_RBPL_S       0x80430
 483 #define G1_RBPL_T       0x80434
 484 #define G1_RBPL_QI      0x80438
 485 #define G1_RBPL_BS      0x8043c
 486
 487 #define G2_RBPS_S       0x80440
 488 #define G2_RBPS_T       0x80444
 489 #define G2_RBPS_QI      0x80448
 490 #define G2_RBPS_BS      0x8044c
 491 #define G2_RBPL_S       0x80450
 492 #define G2_RBPL_T       0x80454
 493 #define G2_RBPL_QI      0x80458
 494 #define G2_RBPL_BS      0x8045c
 495
 496 #define G3_RBPS_S       0x80460
 497 #define G3_RBPS_T       0x80464
 498 #define G3_RBPS_QI      0x80468
 499 #define G3_RBPS_BS      0x8046c
 500 #define G3_RBPL_S       0x80470
 501 #define G3_RBPL_T       0x80474
 502 #define G3_RBPL_QI      0x80478
 503 #define G3_RBPL_BS      0x8047c
 504
 505 #define G4_RBPS_S       0x80480
 506 #define G4_RBPS_T       0x80484
 507 #define G4_RBPS_QI      0x80488
 508 #define G4_RBPS_BS      0x8048c
 509 #define G4_RBPL_S       0x80490
 510 #define G4_RBPL_T       0x80494
 511 #define G4_RBPL_QI      0x80498
 512 #define G4_RBPL_BS      0x8049c
 513
 514 #define G5_RBPS_S       0x804a0
 515 #define G5_RBPS_T       0x804a4
 516 #define G5_RBPS_QI      0x804a8
 517 #define G5_RBPS_BS      0x804ac
 518 #define G5_RBPL_S       0x804b0
 519 #define G5_RBPL_T       0x804b4
 520 #define G5_RBPL_QI      0x804b8
 521 #define G5_RBPL_BS      0x804bc
 522
 523 #define G6_RBPS_S       0x804c0
 524 #define G6_RBPS_T       0x804c4
 525 #define G6_RBPS_QI      0x804c8
 526 #define G6_RBPS_BS      0x804cc
 527 #define G6_RBPL_S       0x804d0
 528 #define G6_RBPL_T       0x804d4
 529 #define G6_RBPL_QI      0x804d8
 530 #define G6_RBPL_BS      0x804dc
 531
 532 #define G7_RBPS_S       0x804e0
 533 #define G7_RBPS_T       0x804e4
 534 #define G7_RBPS_QI      0x804e8
 535 #define G7_RBPS_BS      0x804ec
 536
 537 #define G7_RBPL_S       0x804f0
 538 #define G7_RBPL_T       0x804f4
 539 #define G7_RBPL_QI      0x804f8
 540 #define G7_RBPL_BS      0x804fc
 541
 542 #define G0_RBRQ_ST      0x80500
 543 #define G0_RBRQ_H       0x80504
 544 #define G0_RBRQ_Q       0x80508
 545 #define  RBRQ_THRESH(x)         ((x)<<13)
 546 #define  RBRQ_SIZE(x)           (x)
 547 #define G0_RBRQ_I       0x8050c
 548 #define  RBRQ_TIME(x)           ((x)<<8)
 549 #define  RBRQ_COUNT(x)          (x)
 550
 551 /* fill in 1 ... 7 later */
 552
 553 #define G0_TBRQ_B_T     0x80600
 554 #define G0_TBRQ_H       0x80604
 555 #define G0_TBRQ_S       0x80608
 556 #define G0_TBRQ_THRESH  0x8060c
 557 #define  TBRQ_THRESH(x)         (x)
 558
 559 /* fill in 1 ... 7 later */
 560
 561 #define RH_CONFIG       0x805c0
 562 #define  PHY_INT_ENB    (1<<10)
 563 #define  OAM_GID(x)     (x<<7)
 564 #define  PTMR_PRE(x)    (x)
 565
 566 #define G0_INMQ_S       0x80580
 567 #define G0_INMQ_L       0x80584
 568 #define G1_INMQ_S       0x80588
 569 #define G1_INMQ_L       0x8058c
 570 #define G2_INMQ_S       0x80590
 571 #define G2_INMQ_L       0x80594
 572 #define G3_INMQ_S       0x80598
 573 #define G3_INMQ_L       0x8059c
 574 #define G4_INMQ_S       0x805a0
 575 #define G4_INMQ_L       0x805a4
 576 #define G5_INMQ_S       0x805a8
 577 #define G5_INMQ_L       0x805ac
 578 #define G6_INMQ_S       0x805b0
 579 #define G6_INMQ_L       0x805b4
 580 #define G7_INMQ_S       0x805b8
 581 #define G7_INMQ_L       0x805bc
 582
 583 #define TPDRQ_B_H       0x80680
 584 #define TPDRQ_T         0x80684
 585 #define TPDRQ_S         0x80688
 586
 587 #define UBUFF_BA        0x8068c
 588
 589 #define RLBF0_H         0x806c0
 590 #define RLBF0_T         0x806c4
 591 #define RLBF1_H         0x806c8
 592 #define RLBF1_T         0x806cc
 593 #define RLBC_H          0x806d0
 594 #define RLBC_T          0x806d4
 595 #define RLBC_H2         0x806d8
 596 #define TLBF_H          0x806e0
 597 #define TLBF_T          0x806e4
 598 #define RLBF0_C         0x806e8
 599 #define RLBF1_C         0x806ec
 600 #define RXTHRSH         0x806f0
 601 #define LITHRSH         0x806f4
 602
 603 #define LBARB           0x80700
 604 #define  SLICE_X(x)              (x<<28)
 605 #define  ARB_RNUM_MAX(x)         (x<<23)
 606 #define  TH_PRTY(x)              (x<<21)
 607 #define  RH_PRTY(x)              (x<<19)
 608 #define  TL_PRTY(x)              (x<<17)
 609 #define  RL_PRTY(x)              (x<<15)
 610 #define  BUS_MULTI(x)            (x<<8)
 611 #define  NET_PREF(x)             (x)
 612
 613 #define SDRAMCON        0x80704
 614 #define  BANK_ON                (1<<14)
 615 #define  WIDE_DATA              (1<<13)
 616 #define  TWR_WAIT               (1<<12)
 617 #define  TRP_WAIT               (1<<11)
 618 #define  TRAS_WAIT              (1<<10)
 619 #define  REF_RATE(x)            (x)
 620
 621 #define LBSTAT          0x80708
 622
 623 #define RCC_STAT        0x8070c
 624 #define  RCC_BUSY               (1)
 625
 626 #define TCMCONFIG       0x80740
 627 #define  TM_DESL2               (1<<10)
 628 #define  TM_BANK_WAIT(x)        (x<<6)
 629 #define  TM_ADD_BANK4(x)        (x<<4)
 630 #define  TM_PAR_CHECK(x)        (x<<3)
 631 #define  TM_RW_WAIT(x)          (x<<2)
 632 #define  TM_SRAM_TYPE(x)        (x)
 633
 634 #define TSRB_BA         0x80744
 635 #define TSRC_BA         0x80748
 636 #define TMABR_BA        0x8074c
 637 #define TPD_BA          0x80750
 638 #define TSRD_BA         0x80758
 639
 640 #define TX_CONFIG       0x80760
 641 #define  DRF_THRESH(x)          (x<<22)
 642 #define  TX_UT_MODE(x)          (x<<21)
 643 #define  TX_VCI_MASK(x)         (x<<17)
 644 #define  LBFREE_CNT(x)          (x)
 645
 646 #define TXAAL5_PROTO    0x80764
 647 #define  CPCS_UU(x)             (x<<8)
 648 #define  CPI(x)                 (x)
 649
 650 #define RCMCONFIG       0x80780
 651 #define  RM_DESL2(x)            (x<<10)
 652 #define  RM_BANK_WAIT(x)        (x<<6)
 653 #define  RM_ADD_BANK(x)         (x<<4)
 654 #define  RM_PAR_CHECK(x)        (x<<3)
 655 #define  RM_RW_WAIT(x)          (x<<2)
 656 #define  RM_SRAM_TYPE(x)        (x)
 657
 658 #define RCMRSRB_BA      0x80784
 659 #define RCMLBM_BA       0x80788
 660 #define RCMABR_BA       0x8078c
 661
 662 #define RC_CONFIG       0x807c0
 663 #define  UT_RD_DELAY(x)         (x<<11)
 664 #define  WRAP_MODE(x)           (x<<10)
 665 #define  RC_UT_MODE(x)          (x<<9)
 666 #define  RX_ENABLE              (1<<8)
 667 #define  RX_VALVP(x)            (x<<4)
 668 #define  RX_VALVC(x)            (x)
 669
 670 #define MCC             0x807c4
 671 #define OEC             0x807c8
 672 #define DCC             0x807cc
 673 #define CEC             0x807d0
 674
 675 #define HSP_BA          0x807f0
 676
 677 #define LB_CONFIG       0x807f4
 678 #define  LB_SIZE(x)             (x)
 679
 680 #define CON_DAT         0x807f8
 681 #define CON_CTL         0x807fc
 682 #define  CON_CTL_MBOX           (2<<30)
 683 #define  CON_CTL_TCM            (1<<30)
 684 #define  CON_CTL_RCM            (0<<30)
 685 #define  CON_CTL_WRITE          (1<<29)
 686 #define  CON_CTL_READ           (0<<29)
 687 #define  CON_CTL_BUSY           (1<<28)
 688 #define  CON_BYTE_DISABLE_3     (1<<22)         /* 24..31 */
 689 #define  CON_BYTE_DISABLE_2     (1<<21)         /* 16..23 */
 690 #define  CON_BYTE_DISABLE_1     (1<<20)         /* 8..15 */
 691 #define  CON_BYTE_DISABLE_0     (1<<19)         /* 0..7 */
 692 #define  CON_CTL_ADDR(x)        (x)
 693
 694 #define FRAMER          0x80800         /* to 0x80bfc */
 695
 696 /* 3.3 network controller (internal) mailbox registers */
 697
 698 #define CS_STPER0       0x0
 699         /* ... */
 700 #define CS_STPER31      0x01f
 701
 702 #define CS_STTIM0       0x020
 703         /* ... */
 704 #define CS_STTIM31      0x03f
 705
 706 #define CS_TGRLD0       0x040
 707         /* ... */
 708 #define CS_TGRLD15      0x04f
 709
 710 #define CS_ERTHR0       0x050
 711 #define CS_ERTHR1       0x051
 712 #define CS_ERTHR2       0x052
 713 #define CS_ERTHR3       0x053
 714 #define CS_ERTHR4       0x054
 715 #define CS_ERCTL0       0x055
 716 #define  TX_ENABLE              (1<<28)
 717 #define  ER_ENABLE              (1<<27)
 718 #define CS_ERCTL1       0x056
 719 #define CS_ERCTL2       0x057
 720 #define CS_ERSTAT0      0x058
 721 #define CS_ERSTAT1      0x059
 722
 723 #define CS_RTCCT        0x060
 724 #define CS_RTFWC        0x061
 725 #define CS_RTFWR        0x062
 726 #define CS_RTFTC        0x063
 727 #define CS_RTATR        0x064
 728
 729 #define CS_TFBSET       0x070
 730 #define CS_TFBADD       0x071
 731 #define CS_TFBSUB       0x072
 732 #define CS_WCRMAX       0x073
 733 #define CS_WCRMIN       0x074
 734 #define CS_WCRINC       0x075
 735 #define CS_WCRDEC       0x076
 736 #define CS_WCRCEIL      0x077
 737 #define CS_BWDCNT       0x078
 738
 739 #define CS_OTPPER       0x080
 740 #define CS_OTWPER       0x081
 741 #define CS_OTTLIM       0x082
 742 #define CS_OTTCNT       0x083
 743
 744 #define CS_HGRRT0       0x090
 745         /* ... */
 746 #define CS_HGRRT7       0x097
 747
 748 #define CS_ORPTRS       0x0a0
 749
 750 #define RXCON_CLOSE     0x100
 751
 752
 753 #define RCM_MEM_SIZE    0x10000         /* 1M of 32-bit registers */
 754 #define TCM_MEM_SIZE    0x20000         /* 2M of 32-bit registers */
 755
 756 /* 2.5 transmit connection memory registers */
 757
 758 #define TSR0_CONN_STATE(x)      ((x>>28) & 0x7)
 759 #define TSR0_USE_WMIN           (1<<23)
 760 #define TSR0_GROUP(x)           ((x & 0x7)<<18)
 761 #define TSR0_ABR                (2<<16)
 762 #define TSR0_UBR                (1<<16)
 763 #define TSR0_CBR                (0<<16)
 764 #define TSR0_PROT               (1<<15)
 765 #define TSR0_AAL0_SDU           (2<<12)
 766 #define TSR0_AAL0               (1<<12)
 767 #define TSR0_AAL5               (0<<12)
 768 #define TSR0_HALT_ER            (1<<11)
 769 #define TSR0_MARK_CI            (1<<10)
 770 #define TSR0_MARK_ER            (1<<9)
 771 #define TSR0_UPDATE_GER         (1<<8)
 772 #define TSR0_RC_INDEX(x)        (x & 0x1F)
 773
 774 #define TSR1_PCR(x)             ((x & 0x7FFF)<<16)
 775 #define TSR1_MCR(x)             (x & 0x7FFF)
 776
 777 #define TSR2_ACR(x)             ((x & 0x7FFF)<<16)
 778
 779 #define TSR3_NRM_CNT(x)         ((x & 0xFF)<<24)
 780 #define TSR3_CRM_CNT(x)         (x & 0xFFFF)
 781
 782 #define TSR4_FLUSH_CONN         (1<<31)
 783 #define TSR4_SESSION_ENDED      (1<<30)
 784 #define TSR4_CRC10              (1<<28)
 785 #define TSR4_NULL_CRC10         (1<<27)
 786 #define TSR4_PROT               (1<<26)
 787 #define TSR4_AAL0_SDU           (2<<23)
 788 #define TSR4_AAL0               (1<<23)
 789 #define TSR4_AAL5               (0<<23)
 790
 791 #define TSR9_OPEN_CONN          (1<<20)
 792
 793 #define TSR11_ICR(x)            ((x & 0x7FFF)<<16)
 794 #define TSR11_TRM(x)            ((x & 0x7)<<13)
 795 #define TSR11_NRM(x)            ((x & 0x7)<<10)
 796 #define TSR11_ADTF(x)           (x & 0x3FF)
 797
 798 #define TSR13_RDF(x)            ((x & 0xF)<<23)
 799 #define TSR13_RIF(x)            ((x & 0xF)<<19)
 800 #define TSR13_CDF(x)            ((x & 0x7)<<16)
 801 #define TSR13_CRM(x)            (x & 0xFFFF)
 802
 803 #define TSR14_DELETE            (1<<31)
 804 #define TSR14_ABR_CLOSE         (1<<16)
 805
 806 /* 2.7.1 per connection receieve state registers */
 807
 808 #define RSR0_START_PDU  (1<<10)
 809 #define RSR0_OPEN_CONN  (1<<6)
 810 #define RSR0_CLOSE_CONN (0<<6)
 811 #define RSR0_PPD_ENABLE (1<<5)
 812 #define RSR0_EPD_ENABLE (1<<4)
 813 #define RSR0_TCP_CKSUM  (1<<3)
 814 #define RSR0_AAL5               (0)
 815 #define RSR0_AAL0               (1)
 816 #define RSR0_AAL0_SDU           (2)
 817 #define RSR0_RAWCELL            (3)
 818 #define RSR0_RAWCELL_CRC10      (4)
 819
 820 #define RSR1_AQI_ENABLE (1<<20)
 821 #define RSR1_RBPL_ONLY  (1<<19)
 822 #define RSR1_GROUP(x)   ((x)<<16)
 823
 824 #define RSR4_AQI_ENABLE (1<<30)
 825 #define RSR4_GROUP(x)   ((x)<<27)
 826 #define RSR4_RBPL_ONLY  (1<<26)
 827
 828 /* 2.1.4 transmit packet descriptor */
 829
 830 #define TPD_USERCELL            0x0
 831 #define TPD_SEGMENT_OAMF5       0x4
 832 #define TPD_END2END_OAMF5       0x5
 833 #define TPD_RMCELL              0x6
 834 #define TPD_CELLTYPE(x)         (x<<3)
 835 #define TPD_EOS                 (1<<2)
 836 #define TPD_CLP                 (1<<1)
 837 #define TPD_INT                 (1<<0)
 838 #define TPD_LST         (1<<31)
 839
 840 /* table 4.3 serial eeprom information */
 841
 842 #define PROD_ID         0x08    /* char[] */
 843 #define  PROD_ID_LEN    30
 844 #define HW_REV          0x26    /* char[] */
 845 #define M_SN            0x3a    /* integer */
 846 #define MEDIA           0x3e    /* integer */
 847 #define  HE155MM        0x26
 848 #define  HE622MM        0x27
 849 #define  HE155SM        0x46
 850 #define  HE622SM        0x47
 851 #define MAC_ADDR        0x42    /* char[] */
 852
 853 #define CS_LOW          0x0
 854 #define CS_HIGH         ID_CS /* HOST_CNTL_ID_PROM_SEL */
 855 #define CLK_LOW         0x0
 856 #define CLK_HIGH        ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */
 857 #define SI_HIGH         ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */
 858 #define EEPROM_DELAY    400 /* microseconds */
 859
 860 #endif /* _HE_H_ */