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staging: et131x: Fix issues when USE_FBR0 is not defined
[zen-stable.git] / drivers / staging / et131x / et131x.c
blob0fbb77d35c9c382b05bbbbf7b988701e0b4ac145
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
10 *
11 *------------------------------------------------------------------------------
12 *
13 * SOFTWARE LICENSE
14 *
15 * This software is provided subject to the following terms and conditions,
16 * which you should read carefully before using the software. Using this
17 * software indicates your acceptance of these terms and conditions. If you do
18 * not agree with these terms and conditions, do not use the software.
19 *
20 * Copyright © 2005 Agere Systems Inc.
21 * All rights reserved.
22 *
23 * Redistribution and use in source or binary forms, with or without
24 * modifications, are permitted provided that the following conditions are met:
25 *
26 * . Redistributions of source code must retain the above copyright notice, this
27 * list of conditions and the following Disclaimer as comments in the code as
28 * well as in the documentation and/or other materials provided with the
29 * distribution.
30 *
31 * . Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following Disclaimer in the documentation
33 * and/or other materials provided with the distribution.
34 *
35 * . Neither the name of Agere Systems Inc. nor the names of the contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
38 *
39 * Disclaimer
40 *
41 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
42 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
44 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
45 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
49 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
52 * DAMAGE.
53 *
54 */
55
56 #include <linux/pci.h>
57 #include <linux/init.h>
58 #include <linux/module.h>
59 #include <linux/types.h>
60 #include <linux/kernel.h>
61
62 #include <linux/sched.h>
63 #include <linux/ptrace.h>
64 #include <linux/slab.h>
65 #include <linux/ctype.h>
66 #include <linux/string.h>
67 #include <linux/timer.h>
68 #include <linux/interrupt.h>
69 #include <linux/in.h>
70 #include <linux/delay.h>
71 #include <linux/bitops.h>
72 #include <linux/io.h>
73 #include <asm/system.h>
74
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_arp.h>
79 #include <linux/ioport.h>
80 #include <linux/crc32.h>
81 #include <linux/random.h>
82 #include <linux/phy.h>
83
84 #include "et131x.h"
85
86 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
87 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
88 MODULE_LICENSE("Dual BSD/GPL");
89 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
90 "for the ET1310 by Agere Systems");
91
92 /* EEPROM defines */
93 #define MAX_NUM_REGISTER_POLLS 1000
94 #define MAX_NUM_WRITE_RETRIES 2
95
96 /* MAC defines */
97 #define COUNTER_WRAP_16_BIT 0x10000
98 #define COUNTER_WRAP_12_BIT 0x1000
99
100 /* PCI defines */
101 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
102 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
103
104 /* ISR defines */
105 /*
106 * For interrupts, normal running is:
107 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
108 * watchdog_interrupt & txdma_xfer_done
109 *
110 * In both cases, when flow control is enabled for either Tx or bi-direction,
111 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
112 * buffer rings are running low.
113 */
114 #define INT_MASK_DISABLE 0xffffffff
115
116 /* NOTE: Masking out MAC_STAT Interrupt for now...
117 * #define INT_MASK_ENABLE 0xfff6bf17
118 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
119 */
120 #define INT_MASK_ENABLE 0xfffebf17
121 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
122
123 /* General defines */
124 /* Packet and header sizes */
125 #define NIC_MIN_PACKET_SIZE 60
126
127 /* Multicast list size */
128 #define NIC_MAX_MCAST_LIST 128
129
130 /* Supported Filters */
131 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
132 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
133 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
134 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
135 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
136
137 /* Tx Timeout */
138 #define ET131X_TX_TIMEOUT (1 * HZ)
139 #define NIC_SEND_HANG_THRESHOLD 0
140
141 /* MP_TCB flags */
142 #define fMP_DEST_MULTI 0x00000001
143 #define fMP_DEST_BROAD 0x00000002
144
145 /* MP_ADAPTER flags */
146 #define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
147 #define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
148 #define fMP_ADAPTER_SECONDARY 0x00000010
149
150 /* MP_SHARED flags */
151 #define fMP_ADAPTER_SHUTDOWN 0x00100000
152 #define fMP_ADAPTER_LOWER_POWER 0x00200000
153
154 #define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
155 #define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000
156 #define fMP_ADAPTER_NO_CABLE 0x02000000
157 #define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
158 #define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000
159 #define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000
160
161 #define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
162 #define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
163
164 /* Some offsets in PCI config space that are actually used. */
165 #define ET1310_PCI_MAX_PYLD 0x4C
166 #define ET1310_PCI_MAC_ADDRESS 0xA4
167 #define ET1310_PCI_EEPROM_STATUS 0xB2
168 #define ET1310_PCI_ACK_NACK 0xC0
169 #define ET1310_PCI_REPLAY 0xC2
170 #define ET1310_PCI_L0L1LATENCY 0xCF
171
172 /* PCI Vendor/Product IDs */
173 #define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
174 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
175 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
176
177 /* Define order of magnitude converter */
178 #define NANO_IN_A_MICRO 1000
179
180 #define PARM_RX_NUM_BUFS_DEF 4
181 #define PARM_RX_TIME_INT_DEF 10
182 #define PARM_RX_MEM_END_DEF 0x2bc
183 #define PARM_TX_TIME_INT_DEF 40
184 #define PARM_TX_NUM_BUFS_DEF 4
185 #define PARM_DMA_CACHE_DEF 0
186
187 /* RX defines */
188 #define USE_FBR0 1
189
190 #define FBR_CHUNKS 32
191
192 #define MAX_DESC_PER_RING_RX 1024
193
194 /* number of RFDs - default and min */
195 #ifdef USE_FBR0
196 #define RFD_LOW_WATER_MARK 40
197 #define NIC_DEFAULT_NUM_RFD 1024
198 #define NUM_FBRS 2
199 #else
200 #define RFD_LOW_WATER_MARK 20
201 #define NIC_DEFAULT_NUM_RFD 256
202 #define NUM_FBRS 1
203 #endif
204
205 #define NIC_MIN_NUM_RFD 64
206
207 #define NUM_PACKETS_HANDLED 256
208
209 #define ALCATEL_BAD_STATUS 0xe47f0000
210 #define ALCATEL_MULTICAST_PKT 0x01000000
211 #define ALCATEL_BROADCAST_PKT 0x02000000
212
213 /* typedefs for Free Buffer Descriptors */
214 struct fbr_desc {
215 u32 addr_lo;
216 u32 addr_hi;
217 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
218 };
219
220 /* Packet Status Ring Descriptors
221 *
222 * Word 0:
223 *
224 * top 16 bits are from the Alcatel Status Word as enumerated in
225 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
226 *
227 * 0: hp hash pass
228 * 1: ipa IP checksum assist
229 * 2: ipp IP checksum pass
230 * 3: tcpa TCP checksum assist
231 * 4: tcpp TCP checksum pass
232 * 5: wol WOL Event
233 * 6: rxmac_error RXMAC Error Indicator
234 * 7: drop Drop packet
235 * 8: ft Frame Truncated
236 * 9: jp Jumbo Packet
237 * 10: vp VLAN Packet
238 * 11-15: unused
239 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
240 * 17: asw_RX_DV_event short receive event detected
241 * 18: asw_false_carrier_event bad carrier since last good packet
242 * 19: asw_code_err one or more nibbles signalled as errors
243 * 20: asw_CRC_err CRC error
244 * 21: asw_len_chk_err frame length field incorrect
245 * 22: asw_too_long frame length > 1518 bytes
246 * 23: asw_OK valid CRC + no code error
247 * 24: asw_multicast has a multicast address
248 * 25: asw_broadcast has a broadcast address
249 * 26: asw_dribble_nibble spurious bits after EOP
250 * 27: asw_control_frame is a control frame
251 * 28: asw_pause_frame is a pause frame
252 * 29: asw_unsupported_op unsupported OP code
253 * 30: asw_VLAN_tag VLAN tag detected
254 * 31: asw_long_evt Rx long event
255 *
256 * Word 1:
257 * 0-15: length length in bytes
258 * 16-25: bi Buffer Index
259 * 26-27: ri Ring Index
260 * 28-31: reserved
261 */
262
263 struct pkt_stat_desc {
264 u32 word0;
265 u32 word1;
266 };
267
268 /* Typedefs for the RX DMA status word */
269
270 /*
271 * rx status word 0 holds part of the status bits of the Rx DMA engine
272 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
273 * which contains the Free Buffer ring 0 and 1 available offset.
274 *
275 * bit 0-9 FBR1 offset
276 * bit 10 Wrap flag for FBR1
277 * bit 16-25 FBR0 offset
278 * bit 26 Wrap flag for FBR0
279 */
280
281 /*
282 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
283 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
284 * which contains the Packet Status Ring available offset.
285 *
286 * bit 0-15 reserved
287 * bit 16-27 PSRoffset
288 * bit 28 PSRwrap
289 * bit 29-31 unused
290 */
291
292 /*
293 * struct rx_status_block is a structure representing the status of the Rx
294 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
295 */
296 struct rx_status_block {
297 u32 word0;
298 u32 word1;
299 };
300
301 /*
302 * Structure for look-up table holding free buffer ring pointers, addresses
303 * and state.
304 */
305 struct fbr_lookup {
306 void *virt[MAX_DESC_PER_RING_RX];
307 void *buffer1[MAX_DESC_PER_RING_RX];
308 void *buffer2[MAX_DESC_PER_RING_RX];
309 u32 bus_high[MAX_DESC_PER_RING_RX];
310 u32 bus_low[MAX_DESC_PER_RING_RX];
311 void *ring_virtaddr;
312 dma_addr_t ring_physaddr;
313 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
314 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
315 uint64_t real_physaddr;
316 uint64_t offset;
317 u32 local_full;
318 u32 num_entries;
319 u32 buffsize;
320 };
321
322 /*
323 * struct rx_ring is the sructure representing the adaptor's local
324 * reference(s) to the rings
325 *
326 ******************************************************************************
327 * IMPORTANT NOTE :- fbr_lookup *fbr[NUM_FBRS] uses index 0 to refer to FBR1
328 * and index 1 to refer to FRB0
329 ******************************************************************************
330 */
331 struct rx_ring {
332 struct fbr_lookup *fbr[NUM_FBRS];
333 void *ps_ring_virtaddr;
334 dma_addr_t ps_ring_physaddr;
335 u32 local_psr_full;
336 u32 psr_num_entries;
337
338 struct rx_status_block *rx_status_block;
339 dma_addr_t rx_status_bus;
340
341 struct list_head recv_buff_pool;
342
343 /* RECV */
344 struct list_head recv_list;
345 u32 num_ready_recv;
346
347 u32 num_rfd;
348
349 bool unfinished_receives;
350
351 struct list_head recv_packet_pool;
352
353 /* lookaside lists */
354 struct kmem_cache *recv_lookaside;
355 };
356
357 /* TX defines */
358 /*
359 * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
360 *
361 * 0-15: length of packet
362 * 16-27: VLAN tag
363 * 28: VLAN CFI
364 * 29-31: VLAN priority
365 *
366 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
367 *
368 * 0: last packet in the sequence
369 * 1: first packet in the sequence
370 * 2: interrupt the processor when this pkt sent
371 * 3: Control word - no packet data
372 * 4: Issue half-duplex backpressure : XON/XOFF
373 * 5: send pause frame
374 * 6: Tx frame has error
375 * 7: append CRC
376 * 8: MAC override
377 * 9: pad packet
378 * 10: Packet is a Huge packet
379 * 11: append VLAN tag
380 * 12: IP checksum assist
381 * 13: TCP checksum assist
382 * 14: UDP checksum assist
383 */
384
385 /* struct tx_desc represents each descriptor on the ring */
386 struct tx_desc {
387 u32 addr_hi;
388 u32 addr_lo;
389 u32 len_vlan; /* control words how to xmit the */
390 u32 flags; /* data (detailed above) */
391 };
392
393 /*
394 * The status of the Tx DMA engine it sits in free memory, and is pointed to
395 * by 0x101c / 0x1020. This is a DMA10 type
396 */
397
398 /* TCB (Transmit Control Block: Host Side) */
399 struct tcb {
400 struct tcb *next; /* Next entry in ring */
401 u32 flags; /* Our flags for the packet */
402 u32 count; /* Used to spot stuck/lost packets */
403 u32 stale; /* Used to spot stuck/lost packets */
404 struct sk_buff *skb; /* Network skb we are tied to */
405 u32 index; /* Ring indexes */
406 u32 index_start;
407 };
408
409 /* Structure representing our local reference(s) to the ring */
410 struct tx_ring {
411 /* TCB (Transmit Control Block) memory and lists */
412 struct tcb *tcb_ring;
413
414 /* List of TCBs that are ready to be used */
415 struct tcb *tcb_qhead;
416 struct tcb *tcb_qtail;
417
418 /* list of TCBs that are currently being sent. NOTE that access to all
419 * three of these (including used) are controlled via the
420 * TCBSendQLock. This lock should be secured prior to incementing /
421 * decrementing used, or any queue manipulation on send_head /
422 * tail
423 */
424 struct tcb *send_head;
425 struct tcb *send_tail;
426 int used;
427
428 /* The actual descriptor ring */
429 struct tx_desc *tx_desc_ring;
430 dma_addr_t tx_desc_ring_pa;
431
432 /* send_idx indicates where we last wrote to in the descriptor ring. */
433 u32 send_idx;
434
435 /* The location of the write-back status block */
436 u32 *tx_status;
437 dma_addr_t tx_status_pa;
438
439 /* Packets since the last IRQ: used for interrupt coalescing */
440 int since_irq;
441 };
442
443 /* ADAPTER defines */
444 /*
445 * Do not change these values: if changed, then change also in respective
446 * TXdma and Rxdma engines
447 */
448 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
449 #define NUM_TCB 64
450
451 /*
452 * These values are all superseded by registry entries to facilitate tuning.
453 * Once the desired performance has been achieved, the optimal registry values
454 * should be re-populated to these #defines:
455 */
456 #define NUM_TRAFFIC_CLASSES 1
457
458 #define TX_ERROR_PERIOD 1000
459
460 #define LO_MARK_PERCENT_FOR_PSR 15
461 #define LO_MARK_PERCENT_FOR_RX 15
462
463 /* RFD (Receive Frame Descriptor) */
464 struct rfd {
465 struct list_head list_node;
466 struct sk_buff *skb;
467 u32 len; /* total size of receive frame */
468 u16 bufferindex;
469 u8 ringindex;
470 };
471
472 /* Flow Control */
473 #define FLOW_BOTH 0
474 #define FLOW_TXONLY 1
475 #define FLOW_RXONLY 2
476 #define FLOW_NONE 3
477
478 /* Struct to define some device statistics */
479 struct ce_stats {
480 /* MIB II variables
481 *
482 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
483 * MUST have 32, then we'll need another way to perform atomic
484 * operations
485 */
486 u32 unicast_pkts_rcvd;
487 atomic_t unicast_pkts_xmtd;
488 u32 multicast_pkts_rcvd;
489 atomic_t multicast_pkts_xmtd;
490 u32 broadcast_pkts_rcvd;
491 atomic_t broadcast_pkts_xmtd;
492 u32 rcvd_pkts_dropped;
493
494 /* Tx Statistics. */
495 u32 tx_underflows;
496
497 u32 tx_collisions;
498 u32 tx_excessive_collisions;
499 u32 tx_first_collisions;
500 u32 tx_late_collisions;
501 u32 tx_max_pkt_errs;
502 u32 tx_deferred;
503
504 /* Rx Statistics. */
505 u32 rx_overflows;
506
507 u32 rx_length_errs;
508 u32 rx_align_errs;
509 u32 rx_crc_errs;
510 u32 rx_code_violations;
511 u32 rx_other_errs;
512
513 u32 synchronous_iterations;
514 u32 interrupt_status;
515 };
516
517 /* The private adapter structure */
518 struct et131x_adapter {
519 struct net_device *netdev;
520 struct pci_dev *pdev;
521 struct mii_bus *mii_bus;
522 struct phy_device *phydev;
523 struct work_struct task;
524
525 /* Flags that indicate current state of the adapter */
526 u32 flags;
527
528 /* local link state, to determine if a state change has occurred */
529 int link;
530
531 /* Configuration */
532 u8 rom_addr[ETH_ALEN];
533 u8 addr[ETH_ALEN];
534 bool has_eeprom;
535 u8 eeprom_data[2];
536
537 /* Spinlocks */
538 spinlock_t lock;
539
540 spinlock_t tcb_send_qlock;
541 spinlock_t tcb_ready_qlock;
542 spinlock_t send_hw_lock;
543
544 spinlock_t rcv_lock;
545 spinlock_t rcv_pend_lock;
546 spinlock_t fbr_lock;
547
548 spinlock_t phy_lock;
549
550 /* Packet Filter and look ahead size */
551 u32 packet_filter;
552
553 /* multicast list */
554 u32 multicast_addr_count;
555 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
556
557 /* Pointer to the device's PCI register space */
558 struct address_map __iomem *regs;
559
560 /* Registry parameters */
561 u8 wanted_flow; /* Flow we want for 802.3x flow control */
562 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
563
564 /* Derived from the registry: */
565 u8 flowcontrol; /* flow control validated by the far-end */
566
567 /* Minimize init-time */
568 struct timer_list error_timer;
569
570 /* variable putting the phy into coma mode when boot up with no cable
571 * plugged in after 5 seconds
572 */
573 u8 boot_coma;
574
575 /* Next two used to save power information at power down. This
576 * information will be used during power up to set up parts of Power
577 * Management in JAGCore
578 */
579 u16 pdown_speed;
580 u8 pdown_duplex;
581
582 /* Tx Memory Variables */
583 struct tx_ring tx_ring;
584
585 /* Rx Memory Variables */
586 struct rx_ring rx_ring;
587
588 /* Stats */
589 struct ce_stats stats;
590
591 struct net_device_stats net_stats;
592 };
593
594 void et131x_error_timer_handler(unsigned long data);
595 void et131x_enable_interrupts(struct et131x_adapter *adapter);
596 void et131x_disable_interrupts(struct et131x_adapter *adapter);
597 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
598 u64 *phys_addr,
599 u64 *offset, u64 mask);
600 void et131x_adapter_setup(struct et131x_adapter *adapter);
601 void et131x_soft_reset(struct et131x_adapter *adapter);
602 void et131x_isr_handler(struct work_struct *work);
603 void et1310_setup_device_for_multicast(struct et131x_adapter *adapter);
604 void et1310_setup_device_for_unicast(struct et131x_adapter *adapter);
605 void et131x_up(struct net_device *netdev);
606 void et131x_down(struct net_device *netdev);
607 struct net_device *et131x_device_alloc(void);
608 void et131x_enable_txrx(struct net_device *netdev);
609 void et131x_disable_txrx(struct net_device *netdev);
610 int et1310_in_phy_coma(struct et131x_adapter *adapter);
611 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
612 u16 action,
613 u16 regnum, u16 bitnum, u8 *value);
614 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
615 u8 reg, u16 *value);
616 int32_t et131x_mii_write(struct et131x_adapter *adapter,
617 u8 reg, u16 value);
618 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
619 void et131x_rx_dma_disable(struct et131x_adapter *adapter);
620 void et131x_rx_dma_enable(struct et131x_adapter *adapter);
621 void et131x_reset_recv(struct et131x_adapter *adapter);
622 void et131x_init_send(struct et131x_adapter *adapter);
623 void et131x_tx_dma_enable(struct et131x_adapter *adapter);
624
625 /* EEPROM functions */
626
627 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
628 {
629 u32 reg;
630 int i;
631
632 /*
633 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
634 * bits 7,1:0 both equal to 1, at least once after reset.
635 * Subsequent operations need only to check that bits 1:0 are equal
636 * to 1 prior to starting a single byte read/write
637 */
638
639 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
640 /* Read registers grouped in DWORD1 */
641 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
642 return -EIO;
643
644 /* I2C idle and Phy Queue Avail both true */
645 if ((reg & 0x3000) == 0x3000) {
646 if (status)
647 *status = reg;
648 return reg & 0xFF;
649 }
650 }
651 return -ETIMEDOUT;
652 }
653
654
655 /**
656 * eeprom_write - Write a byte to the ET1310's EEPROM
657 * @adapter: pointer to our private adapter structure
658 * @addr: the address to write
659 * @data: the value to write
660 *
661 * Returns 1 for a successful write.
662 */
663 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
664 {
665 struct pci_dev *pdev = adapter->pdev;
666 int index = 0;
667 int retries;
668 int err = 0;
669 int i2c_wack = 0;
670 int writeok = 0;
671 u32 status;
672 u32 val = 0;
673
674 /*
675 * For an EEPROM, an I2C single byte write is defined as a START
676 * condition followed by the device address, EEPROM address, one byte
677 * of data and a STOP condition. The STOP condition will trigger the
678 * EEPROM's internally timed write cycle to the nonvolatile memory.
679 * All inputs are disabled during this write cycle and the EEPROM will
680 * not respond to any access until the internal write is complete.
681 */
682
683 err = eeprom_wait_ready(pdev, NULL);
684 if (err)
685 return err;
686
687 /*
688 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
689 * and bits 1:0 both =0. Bit 5 should be set according to the
690 * type of EEPROM being accessed (1=two byte addressing, 0=one
691 * byte addressing).
692 */
693 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
694 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
695 return -EIO;
696
697 i2c_wack = 1;
698
699 /* Prepare EEPROM address for Step 3 */
700
701 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
702 /* Write the address to the LBCIF Address Register */
703 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
704 break;
705 /*
706 * Write the data to the LBCIF Data Register (the I2C write
707 * will begin).
708 */
709 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
710 break;
711 /*
712 * Monitor bit 1:0 of the LBCIF Status Register. When bits
713 * 1:0 are both equal to 1, the I2C write has completed and the
714 * internal write cycle of the EEPROM is about to start.
715 * (bits 1:0 = 01 is a legal state while waiting from both
716 * equal to 1, but bits 1:0 = 10 is invalid and implies that
717 * something is broken).
718 */
719 err = eeprom_wait_ready(pdev, &status);
720 if (err < 0)
721 return 0;
722
723 /*
724 * Check bit 3 of the LBCIF Status Register. If equal to 1,
725 * an error has occurred.Don't break here if we are revision
726 * 1, this is so we do a blind write for load bug.
727 */
728 if ((status & LBCIF_STATUS_GENERAL_ERROR)
729 && adapter->pdev->revision == 0)
730 break;
731
732 /*
733 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
734 * ACK error has occurred on the address phase of the write.
735 * This could be due to an actual hardware failure or the
736 * EEPROM may still be in its internal write cycle from a
737 * previous write. This write operation was ignored and must be
738 *repeated later.
739 */
740 if (status & LBCIF_STATUS_ACK_ERROR) {
741 /*
742 * This could be due to an actual hardware failure
743 * or the EEPROM may still be in its internal write
744 * cycle from a previous write. This write operation
745 * was ignored and must be repeated later.
746 */
747 udelay(10);
748 continue;
749 }
750
751 writeok = 1;
752 break;
753 }
754
755 /*
756 * Set bit 6 of the LBCIF Control Register = 0.
757 */
758 udelay(10);
759
760 while (i2c_wack) {
761 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
762 LBCIF_CONTROL_LBCIF_ENABLE))
763 writeok = 0;
764
765 /* Do read until internal ACK_ERROR goes away meaning write
766 * completed
767 */
768 do {
769 pci_write_config_dword(pdev,
770 LBCIF_ADDRESS_REGISTER,
771 addr);
772 do {
773 pci_read_config_dword(pdev,
774 LBCIF_DATA_REGISTER, &val);
775 } while ((val & 0x00010000) == 0);
776 } while (val & 0x00040000);
777
778 if ((val & 0xFF00) != 0xC000 || index == 10000)
779 break;
780 index++;
781 }
782 return writeok ? 0 : -EIO;
783 }
784
785 /**
786 * eeprom_read - Read a byte from the ET1310's EEPROM
787 * @adapter: pointer to our private adapter structure
788 * @addr: the address from which to read
789 * @pdata: a pointer to a byte in which to store the value of the read
790 * @eeprom_id: the ID of the EEPROM
791 * @addrmode: how the EEPROM is to be accessed
792 *
793 * Returns 1 for a successful read
794 */
795 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
796 {
797 struct pci_dev *pdev = adapter->pdev;
798 int err;
799 u32 status;
800
801 /*
802 * A single byte read is similar to the single byte write, with the
803 * exception of the data flow:
804 */
805
806 err = eeprom_wait_ready(pdev, NULL);
807 if (err)
808 return err;
809 /*
810 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
811 * and bits 1:0 both =0. Bit 5 should be set according to the type
812 * of EEPROM being accessed (1=two byte addressing, 0=one byte
813 * addressing).
814 */
815 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
816 LBCIF_CONTROL_LBCIF_ENABLE))
817 return -EIO;
818 /*
819 * Write the address to the LBCIF Address Register (I2C read will
820 * begin).
821 */
822 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
823 return -EIO;
824 /*
825 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
826 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
827 * has occurred).
828 */
829 err = eeprom_wait_ready(pdev, &status);
830 if (err < 0)
831 return err;
832 /*
833 * Regardless of error status, read data byte from LBCIF Data
834 * Register.
835 */
836 *pdata = err;
837 /*
838 * Check bit 2 of the LBCIF Status Register. If = 1,
839 * then an error has occurred.
840 */
841 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
842 }
843
844 int et131x_init_eeprom(struct et131x_adapter *adapter)
845 {
846 struct pci_dev *pdev = adapter->pdev;
847 u8 eestatus;
848
849 /* We first need to check the EEPROM Status code located at offset
850 * 0xB2 of config space
851 */
852 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
853 &eestatus);
854
855 /* THIS IS A WORKAROUND:
856 * I need to call this function twice to get my card in a
857 * LG M1 Express Dual running. I tried also a msleep before this
858 * function, because I thougth there could be some time condidions
859 * but it didn't work. Call the whole function twice also work.
860 */
861 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
862 dev_err(&pdev->dev,
863 "Could not read PCI config space for EEPROM Status\n");
864 return -EIO;
865 }
866
867 /* Determine if the error(s) we care about are present. If they are
868 * present we need to fail.
869 */
870 if (eestatus & 0x4C) {
871 int write_failed = 0;
872 if (pdev->revision == 0x01) {
873 int i;
874 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
875
876 /* Re-write the first 4 bytes if we have an eeprom
877 * present and the revision id is 1, this fixes the
878 * corruption seen with 1310 B Silicon
879 */
880 for (i = 0; i < 3; i++)
881 if (eeprom_write(adapter, i, eedata[i]) < 0)
882 write_failed = 1;
883 }
884 if (pdev->revision != 0x01 || write_failed) {
885 dev_err(&pdev->dev,
886 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
887
888 /* This error could mean that there was an error
889 * reading the eeprom or that the eeprom doesn't exist.
890 * We will treat each case the same and not try to
891 * gather additional information that normally would
892 * come from the eeprom, like MAC Address
893 */
894 adapter->has_eeprom = 0;
895 return -EIO;
896 }
897 }
898 adapter->has_eeprom = 1;
899
900 /* Read the EEPROM for information regarding LED behavior. Refer to
901 * ET1310_phy.c, et131x_xcvr_init(), for its use.
902 */
903 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
904 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
905
906 if (adapter->eeprom_data[0] != 0xcd)
907 /* Disable all optional features */
908 adapter->eeprom_data[1] = 0x00;
909
910 return 0;
911 }
912
913 /* MAC functions */
914
915 /**
916 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
917 * @adapter: pointer to our adapter structure
918 */
919 void et1310_config_mac_regs1(struct et131x_adapter *adapter)
920 {
921 struct mac_regs __iomem *macregs = &adapter->regs->mac;
922 u32 station1;
923 u32 station2;
924 u32 ipg;
925
926 /* First we need to reset everything. Write to MAC configuration
927 * register 1 to perform reset.
928 */
929 writel(0xC00F0000, &macregs->cfg1);
930
931 /* Next lets configure the MAC Inter-packet gap register */
932 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
933 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
934 writel(ipg, &macregs->ipg);
935
936 /* Next lets configure the MAC Half Duplex register */
937 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
938 writel(0x00A1F037, &macregs->hfdp);
939
940 /* Next lets configure the MAC Interface Control register */
941 writel(0, &macregs->if_ctrl);
942
943 /* Let's move on to setting up the mii management configuration */
944 writel(0x07, &macregs->mii_mgmt_cfg); /* Clock reset 0x7 */
945
946 /* Next lets configure the MAC Station Address register. These
947 * values are read from the EEPROM during initialization and stored
948 * in the adapter structure. We write what is stored in the adapter
949 * structure to the MAC Station Address registers high and low. This
950 * station address is used for generating and checking pause control
951 * packets.
952 */
953 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
954 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
955 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
956 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
957 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
958 adapter->addr[2];
959 writel(station1, &macregs->station_addr_1);
960 writel(station2, &macregs->station_addr_2);
961
962 /* Max ethernet packet in bytes that will passed by the mac without
963 * being truncated. Allow the MAC to pass 4 more than our max packet
964 * size. This is 4 for the Ethernet CRC.
965 *
966 * Packets larger than (registry_jumbo_packet) that do not contain a
967 * VLAN ID will be dropped by the Rx function.
968 */
969 writel(adapter->registry_jumbo_packet + 4, &macregs->max_fm_len);
970
971 /* clear out MAC config reset */
972 writel(0, &macregs->cfg1);
973 }
974
975 /**
976 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
977 * @adapter: pointer to our adapter structure
978 */
979 void et1310_config_mac_regs2(struct et131x_adapter *adapter)
980 {
981 int32_t delay = 0;
982 struct mac_regs __iomem *mac = &adapter->regs->mac;
983 struct phy_device *phydev = adapter->phydev;
984 u32 cfg1;
985 u32 cfg2;
986 u32 ifctrl;
987 u32 ctl;
988
989 ctl = readl(&adapter->regs->txmac.ctl);
990 cfg1 = readl(&mac->cfg1);
991 cfg2 = readl(&mac->cfg2);
992 ifctrl = readl(&mac->if_ctrl);
993
994 /* Set up the if mode bits */
995 cfg2 &= ~0x300;
996 if (phydev && phydev->speed == SPEED_1000) {
997 cfg2 |= 0x200;
998 /* Phy mode bit */
999 ifctrl &= ~(1 << 24);
1000 } else {
1001 cfg2 |= 0x100;
1002 ifctrl |= (1 << 24);
1003 }
1004
1005 /* We need to enable Rx/Tx */
1006 cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
1007 /* Initialize loop back to off */
1008 cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
1009 if (adapter->flowcontrol == FLOW_RXONLY ||
1010 adapter->flowcontrol == FLOW_BOTH)
1011 cfg1 |= CFG1_RX_FLOW;
1012 writel(cfg1, &mac->cfg1);
1013
1014 /* Now we need to initialize the MAC Configuration 2 register */
1015 /* preamble 7, check length, huge frame off, pad crc, crc enable
1016 full duplex off */
1017 cfg2 |= 0x7016;
1018 cfg2 &= ~0x0021;
1019
1020 /* Turn on duplex if needed */
1021 if (phydev && phydev->duplex == DUPLEX_FULL)
1022 cfg2 |= 0x01;
1023
1024 ifctrl &= ~(1 << 26);
1025 if (phydev && phydev->duplex == DUPLEX_HALF)
1026 ifctrl |= (1<<26); /* Enable ghd */
1027
1028 writel(ifctrl, &mac->if_ctrl);
1029 writel(cfg2, &mac->cfg2);
1030
1031 do {
1032 udelay(10);
1033 delay++;
1034 cfg1 = readl(&mac->cfg1);
1035 } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
1036
1037 if (delay == 100) {
1038 dev_warn(&adapter->pdev->dev,
1039 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1040 cfg1);
1041 }
1042
1043 /* Enable txmac */
1044 ctl |= 0x09; /* TX mac enable, FC disable */
1045 writel(ctl, &adapter->regs->txmac.ctl);
1046
1047 /* Ready to start the RXDMA/TXDMA engine */
1048 if (adapter->flags & fMP_ADAPTER_LOWER_POWER) {
1049 et131x_rx_dma_enable(adapter);
1050 et131x_tx_dma_enable(adapter);
1051 }
1052 }
1053
1054 void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1055 {
1056 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1057 struct phy_device *phydev = adapter->phydev;
1058 u32 sa_lo;
1059 u32 sa_hi = 0;
1060 u32 pf_ctrl = 0;
1061
1062 /* Disable the MAC while it is being configured (also disable WOL) */
1063 writel(0x8, &rxmac->ctrl);
1064
1065 /* Initialize WOL to disabled. */
1066 writel(0, &rxmac->crc0);
1067 writel(0, &rxmac->crc12);
1068 writel(0, &rxmac->crc34);
1069
1070 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1071 * its default Values of 0x00000000 because there are not WOL masks
1072 * as of this time.
1073 */
1074 writel(0, &rxmac->mask0_word0);
1075 writel(0, &rxmac->mask0_word1);
1076 writel(0, &rxmac->mask0_word2);
1077 writel(0, &rxmac->mask0_word3);
1078
1079 writel(0, &rxmac->mask1_word0);
1080 writel(0, &rxmac->mask1_word1);
1081 writel(0, &rxmac->mask1_word2);
1082 writel(0, &rxmac->mask1_word3);
1083
1084 writel(0, &rxmac->mask2_word0);
1085 writel(0, &rxmac->mask2_word1);
1086 writel(0, &rxmac->mask2_word2);
1087 writel(0, &rxmac->mask2_word3);
1088
1089 writel(0, &rxmac->mask3_word0);
1090 writel(0, &rxmac->mask3_word1);
1091 writel(0, &rxmac->mask3_word2);
1092 writel(0, &rxmac->mask3_word3);
1093
1094 writel(0, &rxmac->mask4_word0);
1095 writel(0, &rxmac->mask4_word1);
1096 writel(0, &rxmac->mask4_word2);
1097 writel(0, &rxmac->mask4_word3);
1098
1099 /* Lets setup the WOL Source Address */
1100 sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) |
1101 (adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) |
1102 (adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) |
1103 adapter->addr[5];
1104 writel(sa_lo, &rxmac->sa_lo);
1105
1106 sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) |
1107 adapter->addr[1];
1108 writel(sa_hi, &rxmac->sa_hi);
1109
1110 /* Disable all Packet Filtering */
1111 writel(0, &rxmac->pf_ctrl);
1112
1113 /* Let's initialize the Unicast Packet filtering address */
1114 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1115 et1310_setup_device_for_unicast(adapter);
1116 pf_ctrl |= 4; /* Unicast filter */
1117 } else {
1118 writel(0, &rxmac->uni_pf_addr1);
1119 writel(0, &rxmac->uni_pf_addr2);
1120 writel(0, &rxmac->uni_pf_addr3);
1121 }
1122
1123 /* Let's initialize the Multicast hash */
1124 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1125 pf_ctrl |= 2; /* Multicast filter */
1126 et1310_setup_device_for_multicast(adapter);
1127 }
1128
1129 /* Runt packet filtering. Didn't work in version A silicon. */
1130 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
1131 pf_ctrl |= 8; /* Fragment filter */
1132
1133 if (adapter->registry_jumbo_packet > 8192)
1134 /* In order to transmit jumbo packets greater than 8k, the
1135 * FIFO between RxMAC and RxDMA needs to be reduced in size
1136 * to (16k - Jumbo packet size). In order to implement this,
1137 * we must use "cut through" mode in the RxMAC, which chops
1138 * packets down into segments which are (max_size * 16). In
1139 * this case we selected 256 bytes, since this is the size of
1140 * the PCI-Express TLP's that the 1310 uses.
1141 *
1142 * seg_en on, fc_en off, size 0x10
1143 */
1144 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1145 else
1146 writel(0, &rxmac->mcif_ctrl_max_seg);
1147
1148 /* Initialize the MCIF water marks */
1149 writel(0, &rxmac->mcif_water_mark);
1150
1151 /* Initialize the MIF control */
1152 writel(0, &rxmac->mif_ctrl);
1153
1154 /* Initialize the Space Available Register */
1155 writel(0, &rxmac->space_avail);
1156
1157 /* Initialize the the mif_ctrl register
1158 * bit 3: Receive code error. One or more nibbles were signaled as
1159 * errors during the reception of the packet. Clear this
1160 * bit in Gigabit, set it in 100Mbit. This was derived
1161 * experimentally at UNH.
1162 * bit 4: Receive CRC error. The packet's CRC did not match the
1163 * internally generated CRC.
1164 * bit 5: Receive length check error. Indicates that frame length
1165 * field value in the packet does not match the actual data
1166 * byte length and is not a type field.
1167 * bit 16: Receive frame truncated.
1168 * bit 17: Drop packet enable
1169 */
1170 if (phydev && phydev->speed == SPEED_100)
1171 writel(0x30038, &rxmac->mif_ctrl);
1172 else
1173 writel(0x30030, &rxmac->mif_ctrl);
1174
1175 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1176 * filter is always enabled since it is where the runt packets are
1177 * supposed to be dropped. For version A silicon, runt packet
1178 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1179 * but we still leave the packet filter on.
1180 */
1181 writel(pf_ctrl, &rxmac->pf_ctrl);
1182 writel(0x9, &rxmac->ctrl);
1183 }
1184
1185 void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1186 {
1187 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1188
1189 /* We need to update the Control Frame Parameters
1190 * cfpt - control frame pause timer set to 64 (0x40)
1191 * cfep - control frame extended pause timer set to 0x0
1192 */
1193 if (adapter->flowcontrol == FLOW_NONE)
1194 writel(0, &txmac->cf_param);
1195 else
1196 writel(0x40, &txmac->cf_param);
1197 }
1198
1199 void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1200 {
1201 struct macstat_regs __iomem *macstat =
1202 &adapter->regs->macstat;
1203
1204 /* Next we need to initialize all the macstat registers to zero on
1205 * the device.
1206 */
1207 writel(0, &macstat->txrx_0_64_byte_frames);
1208 writel(0, &macstat->txrx_65_127_byte_frames);
1209 writel(0, &macstat->txrx_128_255_byte_frames);
1210 writel(0, &macstat->txrx_256_511_byte_frames);
1211 writel(0, &macstat->txrx_512_1023_byte_frames);
1212 writel(0, &macstat->txrx_1024_1518_byte_frames);
1213 writel(0, &macstat->txrx_1519_1522_gvln_frames);
1214
1215 writel(0, &macstat->rx_bytes);
1216 writel(0, &macstat->rx_packets);
1217 writel(0, &macstat->rx_fcs_errs);
1218 writel(0, &macstat->rx_multicast_packets);
1219 writel(0, &macstat->rx_broadcast_packets);
1220 writel(0, &macstat->rx_control_frames);
1221 writel(0, &macstat->rx_pause_frames);
1222 writel(0, &macstat->rx_unknown_opcodes);
1223 writel(0, &macstat->rx_align_errs);
1224 writel(0, &macstat->rx_frame_len_errs);
1225 writel(0, &macstat->rx_code_errs);
1226 writel(0, &macstat->rx_carrier_sense_errs);
1227 writel(0, &macstat->rx_undersize_packets);
1228 writel(0, &macstat->rx_oversize_packets);
1229 writel(0, &macstat->rx_fragment_packets);
1230 writel(0, &macstat->rx_jabbers);
1231 writel(0, &macstat->rx_drops);
1232
1233 writel(0, &macstat->tx_bytes);
1234 writel(0, &macstat->tx_packets);
1235 writel(0, &macstat->tx_multicast_packets);
1236 writel(0, &macstat->tx_broadcast_packets);
1237 writel(0, &macstat->tx_pause_frames);
1238 writel(0, &macstat->tx_deferred);
1239 writel(0, &macstat->tx_excessive_deferred);
1240 writel(0, &macstat->tx_single_collisions);
1241 writel(0, &macstat->tx_multiple_collisions);
1242 writel(0, &macstat->tx_late_collisions);
1243 writel(0, &macstat->tx_excessive_collisions);
1244 writel(0, &macstat->tx_total_collisions);
1245 writel(0, &macstat->tx_pause_honored_frames);
1246 writel(0, &macstat->tx_drops);
1247 writel(0, &macstat->tx_jabbers);
1248 writel(0, &macstat->tx_fcs_errs);
1249 writel(0, &macstat->tx_control_frames);
1250 writel(0, &macstat->tx_oversize_frames);
1251 writel(0, &macstat->tx_undersize_frames);
1252 writel(0, &macstat->tx_fragments);
1253 writel(0, &macstat->carry_reg1);
1254 writel(0, &macstat->carry_reg2);
1255
1256 /* Unmask any counters that we want to track the overflow of.
1257 * Initially this will be all counters. It may become clear later
1258 * that we do not need to track all counters.
1259 */
1260 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1261 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1262 }
1263
1264 void et1310_config_flow_control(struct et131x_adapter *adapter)
1265 {
1266 struct phy_device *phydev = adapter->phydev;
1267
1268 if (phydev->duplex == DUPLEX_HALF) {
1269 adapter->flowcontrol = FLOW_NONE;
1270 } else {
1271 char remote_pause, remote_async_pause;
1272
1273 et1310_phy_access_mii_bit(adapter,
1274 TRUEPHY_BIT_READ, 5, 10, &remote_pause);
1275 et1310_phy_access_mii_bit(adapter,
1276 TRUEPHY_BIT_READ, 5, 11,
1277 &remote_async_pause);
1278
1279 if ((remote_pause == TRUEPHY_BIT_SET) &&
1280 (remote_async_pause == TRUEPHY_BIT_SET)) {
1281 adapter->flowcontrol = adapter->wanted_flow;
1282 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
1283 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1284 if (adapter->wanted_flow == FLOW_BOTH)
1285 adapter->flowcontrol = FLOW_BOTH;
1286 else
1287 adapter->flowcontrol = FLOW_NONE;
1288 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
1289 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1290 adapter->flowcontrol = FLOW_NONE;
1291 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
1292 remote_async_pause == TRUEPHY_SET_BIT) */
1293 if (adapter->wanted_flow == FLOW_BOTH)
1294 adapter->flowcontrol = FLOW_RXONLY;
1295 else
1296 adapter->flowcontrol = FLOW_NONE;
1297 }
1298 }
1299 }
1300
1301 /**
1302 * et1310_update_macstat_host_counters - Update the local copy of the statistics
1303 * @adapter: pointer to the adapter structure
1304 */
1305 void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1306 {
1307 struct ce_stats *stats = &adapter->stats;
1308 struct macstat_regs __iomem *macstat =
1309 &adapter->regs->macstat;
1310
1311 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1312 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1313 stats->tx_deferred += readl(&macstat->tx_deferred);
1314 stats->tx_excessive_collisions +=
1315 readl(&macstat->tx_multiple_collisions);
1316 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1317 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1318 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1319
1320 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1321 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1322 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1323 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1324 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1325 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1326 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1327 }
1328
1329 /**
1330 * et1310_handle_macstat_interrupt
1331 * @adapter: pointer to the adapter structure
1332 *
1333 * One of the MACSTAT counters has wrapped. Update the local copy of
1334 * the statistics held in the adapter structure, checking the "wrap"
1335 * bit for each counter.
1336 */
1337 void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1338 {
1339 u32 carry_reg1;
1340 u32 carry_reg2;
1341
1342 /* Read the interrupt bits from the register(s). These are Clear On
1343 * Write.
1344 */
1345 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1346 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1347
1348 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1349 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1350
1351 /* We need to do update the host copy of all the MAC_STAT counters.
1352 * For each counter, check it's overflow bit. If the overflow bit is
1353 * set, then increment the host version of the count by one complete
1354 * revolution of the counter. This routine is called when the counter
1355 * block indicates that one of the counters has wrapped.
1356 */
1357 if (carry_reg1 & (1 << 14))
1358 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1359 if (carry_reg1 & (1 << 8))
1360 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1361 if (carry_reg1 & (1 << 7))
1362 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1363 if (carry_reg1 & (1 << 2))
1364 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1365 if (carry_reg1 & (1 << 6))
1366 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1367 if (carry_reg1 & (1 << 3))
1368 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1369 if (carry_reg1 & (1 << 0))
1370 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1371 if (carry_reg2 & (1 << 16))
1372 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1373 if (carry_reg2 & (1 << 15))
1374 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1375 if (carry_reg2 & (1 << 6))
1376 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1377 if (carry_reg2 & (1 << 8))
1378 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1379 if (carry_reg2 & (1 << 5))
1380 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1381 if (carry_reg2 & (1 << 4))
1382 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1383 if (carry_reg2 & (1 << 2))
1384 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1385 }
1386
1387 void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1388 {
1389 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1390 uint32_t nIndex;
1391 uint32_t result;
1392 uint32_t hash1 = 0;
1393 uint32_t hash2 = 0;
1394 uint32_t hash3 = 0;
1395 uint32_t hash4 = 0;
1396 u32 pm_csr;
1397
1398 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1399 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1400 * specified) then we should pass NO multi-cast addresses to the
1401 * driver.
1402 */
1403 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1404 /* Loop through our multicast array and set up the device */
1405 for (nIndex = 0; nIndex < adapter->multicast_addr_count;
1406 nIndex++) {
1407 result = ether_crc(6, adapter->multicast_list[nIndex]);
1408
1409 result = (result & 0x3F800000) >> 23;
1410
1411 if (result < 32) {
1412 hash1 |= (1 << result);
1413 } else if ((31 < result) && (result < 64)) {
1414 result -= 32;
1415 hash2 |= (1 << result);
1416 } else if ((63 < result) && (result < 96)) {
1417 result -= 64;
1418 hash3 |= (1 << result);
1419 } else {
1420 result -= 96;
1421 hash4 |= (1 << result);
1422 }
1423 }
1424 }
1425
1426 /* Write out the new hash to the device */
1427 pm_csr = readl(&adapter->regs->global.pm_csr);
1428 if (!et1310_in_phy_coma(adapter)) {
1429 writel(hash1, &rxmac->multi_hash1);
1430 writel(hash2, &rxmac->multi_hash2);
1431 writel(hash3, &rxmac->multi_hash3);
1432 writel(hash4, &rxmac->multi_hash4);
1433 }
1434 }
1435
1436 void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1437 {
1438 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1439 u32 uni_pf1;
1440 u32 uni_pf2;
1441 u32 uni_pf3;
1442 u32 pm_csr;
1443
1444 /* Set up unicast packet filter reg 3 to be the first two octets of
1445 * the MAC address for both address
1446 *
1447 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1448 * MAC address for second address
1449 *
1450 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1451 * MAC address for first address
1452 */
1453 uni_pf3 = (adapter->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
1454 (adapter->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
1455 (adapter->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
1456 adapter->addr[1];
1457
1458 uni_pf2 = (adapter->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
1459 (adapter->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
1460 (adapter->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
1461 adapter->addr[5];
1462
1463 uni_pf1 = (adapter->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
1464 (adapter->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
1465 (adapter->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
1466 adapter->addr[5];
1467
1468 pm_csr = readl(&adapter->regs->global.pm_csr);
1469 if (!et1310_in_phy_coma(adapter)) {
1470 writel(uni_pf1, &rxmac->uni_pf_addr1);
1471 writel(uni_pf2, &rxmac->uni_pf_addr2);
1472 writel(uni_pf3, &rxmac->uni_pf_addr3);
1473 }
1474 }
1475
1476 /* PHY functions */
1477
1478 int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1479 {
1480 struct net_device *netdev = bus->priv;
1481 struct et131x_adapter *adapter = netdev_priv(netdev);
1482 u16 value;
1483 int ret;
1484
1485 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1486
1487 if (ret < 0)
1488 return ret;
1489 else
1490 return value;
1491 }
1492
1493 int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value)
1494 {
1495 struct net_device *netdev = bus->priv;
1496 struct et131x_adapter *adapter = netdev_priv(netdev);
1497
1498 return et131x_mii_write(adapter, reg, value);
1499 }
1500
1501 int et131x_mdio_reset(struct mii_bus *bus)
1502 {
1503 struct net_device *netdev = bus->priv;
1504 struct et131x_adapter *adapter = netdev_priv(netdev);
1505
1506 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
1507
1508 return 0;
1509 }
1510
1511 int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1512 {
1513 struct phy_device *phydev = adapter->phydev;
1514
1515 if (!phydev)
1516 return -EIO;
1517
1518 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1519 }
1520
1521 /**
1522 * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1523 * @adapter: pointer to our private adapter structure
1524 * @addr: the address of the transceiver
1525 * @reg: the register to read
1526 * @value: pointer to a 16-bit value in which the value will be stored
1527 *
1528 * Returns 0 on success, errno on failure (as defined in errno.h)
1529 */
1530 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1531 u8 reg, u16 *value)
1532 {
1533 struct mac_regs __iomem *mac = &adapter->regs->mac;
1534 int status = 0;
1535 u32 delay = 0;
1536 u32 mii_addr;
1537 u32 mii_cmd;
1538 u32 mii_indicator;
1539
1540 /* Save a local copy of the registers we are dealing with so we can
1541 * set them back
1542 */
1543 mii_addr = readl(&mac->mii_mgmt_addr);
1544 mii_cmd = readl(&mac->mii_mgmt_cmd);
1545
1546 /* Stop the current operation */
1547 writel(0, &mac->mii_mgmt_cmd);
1548
1549 /* Set up the register we need to read from on the correct PHY */
1550 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1551
1552 writel(0x1, &mac->mii_mgmt_cmd);
1553
1554 do {
1555 udelay(50);
1556 delay++;
1557 mii_indicator = readl(&mac->mii_mgmt_indicator);
1558 } while ((mii_indicator & MGMT_WAIT) && delay < 50);
1559
1560 /* If we hit the max delay, we could not read the register */
1561 if (delay == 50) {
1562 dev_warn(&adapter->pdev->dev,
1563 "reg 0x%08x could not be read\n", reg);
1564 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1565 mii_indicator);
1566
1567 status = -EIO;
1568 }
1569
1570 /* If we hit here we were able to read the register and we need to
1571 * return the value to the caller */
1572 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
1573
1574 /* Stop the read operation */
1575 writel(0, &mac->mii_mgmt_cmd);
1576
1577 /* set the registers we touched back to the state at which we entered
1578 * this function
1579 */
1580 writel(mii_addr, &mac->mii_mgmt_addr);
1581 writel(mii_cmd, &mac->mii_mgmt_cmd);
1582
1583 return status;
1584 }
1585
1586 /**
1587 * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
1588 * @adapter: pointer to our private adapter structure
1589 * @reg: the register to read
1590 * @value: 16-bit value to write
1591 *
1592 * FIXME: one caller in netdev still
1593 *
1594 * Return 0 on success, errno on failure (as defined in errno.h)
1595 */
1596 int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1597 {
1598 struct mac_regs __iomem *mac = &adapter->regs->mac;
1599 struct phy_device *phydev = adapter->phydev;
1600 int status = 0;
1601 u8 addr;
1602 u32 delay = 0;
1603 u32 mii_addr;
1604 u32 mii_cmd;
1605 u32 mii_indicator;
1606
1607 if (!phydev)
1608 return -EIO;
1609
1610 addr = phydev->addr;
1611
1612 /* Save a local copy of the registers we are dealing with so we can
1613 * set them back
1614 */
1615 mii_addr = readl(&mac->mii_mgmt_addr);
1616 mii_cmd = readl(&mac->mii_mgmt_cmd);
1617
1618 /* Stop the current operation */
1619 writel(0, &mac->mii_mgmt_cmd);
1620
1621 /* Set up the register we need to write to on the correct PHY */
1622 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1623
1624 /* Add the value to write to the registers to the mac */
1625 writel(value, &mac->mii_mgmt_ctrl);
1626
1627 do {
1628 udelay(50);
1629 delay++;
1630 mii_indicator = readl(&mac->mii_mgmt_indicator);
1631 } while ((mii_indicator & MGMT_BUSY) && delay < 100);
1632
1633 /* If we hit the max delay, we could not write the register */
1634 if (delay == 100) {
1635 u16 tmp;
1636
1637 dev_warn(&adapter->pdev->dev,
1638 "reg 0x%08x could not be written", reg);
1639 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1640 mii_indicator);
1641 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1642 readl(&mac->mii_mgmt_cmd));
1643
1644 et131x_mii_read(adapter, reg, &tmp);
1645
1646 status = -EIO;
1647 }
1648 /* Stop the write operation */
1649 writel(0, &mac->mii_mgmt_cmd);
1650
1651 /*
1652 * set the registers we touched back to the state at which we entered
1653 * this function
1654 */
1655 writel(mii_addr, &mac->mii_mgmt_addr);
1656 writel(mii_cmd, &mac->mii_mgmt_cmd);
1657
1658 return status;
1659 }
1660
1661 /**
1662 * et1310_phy_power_down - PHY power control
1663 * @adapter: device to control
1664 * @down: true for off/false for back on
1665 *
1666 * one hundred, ten, one thousand megs
1667 * How would you like to have your LAN accessed
1668 * Can't you see that this code processed
1669 * Phy power, phy power..
1670 */
1671 void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
1672 {
1673 u16 data;
1674
1675 et131x_mii_read(adapter, MII_BMCR, &data);
1676 data &= ~BMCR_PDOWN;
1677 if (down)
1678 data |= BMCR_PDOWN;
1679 et131x_mii_write(adapter, MII_BMCR, data);
1680 }
1681
1682 /* Still used from _mac for BIT_READ */
1683 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
1684 u16 regnum, u16 bitnum, u8 *value)
1685 {
1686 u16 reg;
1687 u16 mask = 0x0001 << bitnum;
1688
1689 /* Read the requested register */
1690 et131x_mii_read(adapter, regnum, &reg);
1691
1692 switch (action) {
1693 case TRUEPHY_BIT_READ:
1694 *value = (reg & mask) >> bitnum;
1695 break;
1696
1697 case TRUEPHY_BIT_SET:
1698 et131x_mii_write(adapter, regnum, reg | mask);
1699 break;
1700
1701 case TRUEPHY_BIT_CLEAR:
1702 et131x_mii_write(adapter, regnum, reg & ~mask);
1703 break;
1704
1705 default:
1706 break;
1707 }
1708 }
1709
1710 /**
1711 * et131x_xcvr_init - Init the phy if we are setting it into force mode
1712 * @adapter: pointer to our private adapter structure
1713 *
1714 */
1715 void et131x_xcvr_init(struct et131x_adapter *adapter)
1716 {
1717 u16 imr;
1718 u16 isr;
1719 u16 lcr2;
1720
1721 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
1722 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
1723
1724 /* Set the link status interrupt only. Bad behavior when link status
1725 * and auto neg are set, we run into a nested interrupt problem
1726 */
1727 imr |= (ET_PHY_INT_MASK_AUTONEGSTAT &
1728 ET_PHY_INT_MASK_LINKSTAT &
1729 ET_PHY_INT_MASK_ENABLE);
1730
1731 et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
1732
1733 /* Set the LED behavior such that LED 1 indicates speed (off =
1734 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1735 * link and activity (on for link, blink off for activity).
1736 *
1737 * NOTE: Some customizations have been added here for specific
1738 * vendors; The LED behavior is now determined by vendor data in the
1739 * EEPROM. However, the above description is the default.
1740 */
1741 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1742 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1743
1744 lcr2 &= (ET_LED2_LED_100TX & ET_LED2_LED_1000T);
1745 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1746
1747 if ((adapter->eeprom_data[1] & 0x8) == 0)
1748 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1749 else
1750 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1751
1752 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1753 }
1754 }
1755
1756 /* PM functions */
1757
1758 /**
1759 * et1310_in_phy_coma - check if the device is in phy coma
1760 * @adapter: pointer to our adapter structure
1761 *
1762 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1763 */
1764 int et1310_in_phy_coma(struct et131x_adapter *adapter)
1765 {
1766 u32 pmcsr;
1767
1768 pmcsr = readl(&adapter->regs->global.pm_csr);
1769
1770 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1771 }
1772
1773 /**
1774 * et1310_enable_phy_coma - called when network cable is unplugged
1775 * @adapter: pointer to our adapter structure
1776 *
1777 * driver receive an phy status change interrupt while in D0 and check that
1778 * phy_status is down.
1779 *
1780 * -- gate off JAGCore;
1781 * -- set gigE PHY in Coma mode
1782 * -- wake on phy_interrupt; Perform software reset JAGCore,
1783 * re-initialize jagcore and gigE PHY
1784 *
1785 * Add D0-ASPM-PhyLinkDown Support:
1786 * -- while in D0, when there is a phy_interrupt indicating phy link
1787 * down status, call the MPSetPhyComa routine to enter this active
1788 * state power saving mode
1789 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
1790 * indicating linkup status, call the MPDisablePhyComa routine to
1791 * restore JAGCore and gigE PHY
1792 */
1793 void et1310_enable_phy_coma(struct et131x_adapter *adapter)
1794 {
1795 unsigned long flags;
1796 u32 pmcsr;
1797
1798 pmcsr = readl(&adapter->regs->global.pm_csr);
1799
1800 /* Save the GbE PHY speed and duplex modes. Need to restore this
1801 * when cable is plugged back in
1802 */
1803 /*
1804 * TODO - when PM is re-enabled, check if we need to
1805 * perform a similar task as this -
1806 * adapter->pdown_speed = adapter->ai_force_speed;
1807 * adapter->pdown_duplex = adapter->ai_force_duplex;
1808 */
1809
1810 /* Stop sending packets. */
1811 spin_lock_irqsave(&adapter->send_hw_lock, flags);
1812 adapter->flags |= fMP_ADAPTER_LOWER_POWER;
1813 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
1814
1815 /* Wait for outstanding Receive packets */
1816
1817 et131x_disable_txrx(adapter->netdev);
1818
1819 /* Gate off JAGCore 3 clock domains */
1820 pmcsr &= ~ET_PMCSR_INIT;
1821 writel(pmcsr, &adapter->regs->global.pm_csr);
1822
1823 /* Program gigE PHY in to Coma mode */
1824 pmcsr |= ET_PM_PHY_SW_COMA;
1825 writel(pmcsr, &adapter->regs->global.pm_csr);
1826 }
1827
1828 /**
1829 * et1310_disable_phy_coma - Disable the Phy Coma Mode
1830 * @adapter: pointer to our adapter structure
1831 */
1832 void et1310_disable_phy_coma(struct et131x_adapter *adapter)
1833 {
1834 u32 pmcsr;
1835
1836 pmcsr = readl(&adapter->regs->global.pm_csr);
1837
1838 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
1839 pmcsr |= ET_PMCSR_INIT;
1840 pmcsr &= ~ET_PM_PHY_SW_COMA;
1841 writel(pmcsr, &adapter->regs->global.pm_csr);
1842
1843 /* Restore the GbE PHY speed and duplex modes;
1844 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
1845 */
1846 /* TODO - when PM is re-enabled, check if we need to
1847 * perform a similar task as this -
1848 * adapter->ai_force_speed = adapter->pdown_speed;
1849 * adapter->ai_force_duplex = adapter->pdown_duplex;
1850 */
1851
1852 /* Re-initialize the send structures */
1853 et131x_init_send(adapter);
1854
1855 /* Reset the RFD list and re-start RU */
1856 et131x_reset_recv(adapter);
1857
1858 /* Bring the device back to the state it was during init prior to
1859 * autonegotiation being complete. This way, when we get the auto-neg
1860 * complete interrupt, we can complete init by calling ConfigMacREGS2.
1861 */
1862 et131x_soft_reset(adapter);
1863
1864 /* setup et1310 as per the documentation ?? */
1865 et131x_adapter_setup(adapter);
1866
1867 /* Allow Tx to restart */
1868 adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
1869
1870 et131x_enable_txrx(adapter->netdev);
1871 }
1872
1873 /* RX functions */
1874
1875 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
1876 {
1877 u32 tmp_free_buff_ring = *free_buff_ring;
1878 tmp_free_buff_ring++;
1879 /* This works for all cases where limit < 1024. The 1023 case
1880 works because 1023++ is 1024 which means the if condition is not
1881 taken but the carry of the bit into the wrap bit toggles the wrap
1882 value correctly */
1883 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
1884 tmp_free_buff_ring &= ~ET_DMA10_MASK;
1885 tmp_free_buff_ring ^= ET_DMA10_WRAP;
1886 }
1887 /* For the 1023 case */
1888 tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP);
1889 *free_buff_ring = tmp_free_buff_ring;
1890 return tmp_free_buff_ring;
1891 }
1892
1893 /**
1894 * et131x_rx_dma_memory_alloc
1895 * @adapter: pointer to our private adapter structure
1896 *
1897 * Returns 0 on success and errno on failure (as defined in errno.h)
1898 *
1899 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
1900 * and the Packet Status Ring.
1901 */
1902 int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
1903 {
1904 u32 i, j;
1905 u32 bufsize;
1906 u32 pktstat_ringsize, fbr_chunksize;
1907 struct rx_ring *rx_ring;
1908
1909 /* Setup some convenience pointers */
1910 rx_ring = &adapter->rx_ring;
1911
1912 /* Alloc memory for the lookup table */
1913 #ifdef USE_FBR0
1914 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
1915 #endif
1916 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
1917
1918 /* The first thing we will do is configure the sizes of the buffer
1919 * rings. These will change based on jumbo packet support. Larger
1920 * jumbo packets increases the size of each entry in FBR0, and the
1921 * number of entries in FBR0, while at the same time decreasing the
1922 * number of entries in FBR1.
1923 *
1924 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
1925 * entries are huge in order to accommodate a "jumbo" frame, then it
1926 * will have less entries. Conversely, FBR1 will now be relied upon
1927 * to carry more "normal" frames, thus it's entry size also increases
1928 * and the number of entries goes up too (since it now carries
1929 * "small" + "regular" packets.
1930 *
1931 * In this scheme, we try to maintain 512 entries between the two
1932 * rings. Also, FBR1 remains a constant size - when it's size doubles
1933 * the number of entries halves. FBR0 increases in size, however.
1934 */
1935
1936 if (adapter->registry_jumbo_packet < 2048) {
1937 #ifdef USE_FBR0
1938 rx_ring->fbr[1]->buffsize = 256;
1939 rx_ring->fbr[1]->num_entries = 512;
1940 #endif
1941 rx_ring->fbr[0]->buffsize = 2048;
1942 rx_ring->fbr[0]->num_entries = 512;
1943 } else if (adapter->registry_jumbo_packet < 4096) {
1944 #ifdef USE_FBR0
1945 rx_ring->fbr[1]->buffsize = 512;
1946 rx_ring->fbr[1]->num_entries = 1024;
1947 #endif
1948 rx_ring->fbr[0]->buffsize = 4096;
1949 rx_ring->fbr[0]->num_entries = 512;
1950 } else {
1951 #ifdef USE_FBR0
1952 rx_ring->fbr[1]->buffsize = 1024;
1953 rx_ring->fbr[1]->num_entries = 768;
1954 #endif
1955 rx_ring->fbr[0]->buffsize = 16384;
1956 rx_ring->fbr[0]->num_entries = 128;
1957 }
1958
1959 #ifdef USE_FBR0
1960 adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries +
1961 adapter->rx_ring.fbr[0]->num_entries;
1962 #else
1963 adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries;
1964 #endif
1965
1966 /* Allocate an area of memory for Free Buffer Ring 1 */
1967 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
1968 rx_ring->fbr[0]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
1969 bufsize,
1970 &rx_ring->fbr[0]->ring_physaddr);
1971 if (!rx_ring->fbr[0]->ring_virtaddr) {
1972 dev_err(&adapter->pdev->dev,
1973 "Cannot alloc memory for Free Buffer Ring 1\n");
1974 return -ENOMEM;
1975 }
1976
1977 /* Save physical address
1978 *
1979 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
1980 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
1981 * are ever returned, make sure the high part is retrieved here
1982 * before storing the adjusted address.
1983 */
1984 rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr;
1985
1986 /* Align Free Buffer Ring 1 on a 4K boundary */
1987 et131x_align_allocated_memory(adapter,
1988 &rx_ring->fbr[0]->real_physaddr,
1989 &rx_ring->fbr[0]->offset, 0x0FFF);
1990
1991 rx_ring->fbr[0]->ring_virtaddr =
1992 (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
1993 rx_ring->fbr[0]->offset);
1994
1995 #ifdef USE_FBR0
1996 /* Allocate an area of memory for Free Buffer Ring 0 */
1997 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
1998 rx_ring->fbr[1]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
1999 bufsize,
2000 &rx_ring->fbr[1]->ring_physaddr);
2001 if (!rx_ring->fbr[1]->ring_virtaddr) {
2002 dev_err(&adapter->pdev->dev,
2003 "Cannot alloc memory for Free Buffer Ring 0\n");
2004 return -ENOMEM;
2005 }
2006
2007 /* Save physical address
2008 *
2009 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
2010 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2011 * are ever returned, make sure the high part is retrieved here before
2012 * storing the adjusted address.
2013 */
2014 rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr;
2015
2016 /* Align Free Buffer Ring 0 on a 4K boundary */
2017 et131x_align_allocated_memory(adapter,
2018 &rx_ring->fbr[1]->real_physaddr,
2019 &rx_ring->fbr[1]->offset, 0x0FFF);
2020
2021 rx_ring->fbr[1]->ring_virtaddr =
2022 (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
2023 rx_ring->fbr[1]->offset);
2024 #endif
2025 for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
2026 u64 fbr1_offset;
2027 u64 fbr1_tmp_physaddr;
2028 u32 fbr1_align;
2029
2030 /* This code allocates an area of memory big enough for N
2031 * free buffers + (buffer_size - 1) so that the buffers can
2032 * be aligned on 4k boundaries. If each buffer were aligned
2033 * to a buffer_size boundary, the effect would be to double
2034 * the size of FBR0. By allocating N buffers at once, we
2035 * reduce this overhead.
2036 */
2037 if (rx_ring->fbr[0]->buffsize > 4096)
2038 fbr1_align = 4096;
2039 else
2040 fbr1_align = rx_ring->fbr[0]->buffsize;
2041
2042 fbr_chunksize =
2043 (FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1;
2044 rx_ring->fbr[0]->mem_virtaddrs[i] =
2045 pci_alloc_consistent(adapter->pdev, fbr_chunksize,
2046 &rx_ring->fbr[0]->mem_physaddrs[i]);
2047
2048 if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
2049 dev_err(&adapter->pdev->dev,
2050 "Could not alloc memory\n");
2051 return -ENOMEM;
2052 }
2053
2054 /* See NOTE in "Save Physical Address" comment above */
2055 fbr1_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
2056
2057 et131x_align_allocated_memory(adapter,
2058 &fbr1_tmp_physaddr,
2059 &fbr1_offset, (fbr1_align - 1));
2060
2061 for (j = 0; j < FBR_CHUNKS; j++) {
2062 u32 index = (i * FBR_CHUNKS) + j;
2063
2064 /* Save the Virtual address of this index for quick
2065 * access later
2066 */
2067 rx_ring->fbr[0]->virt[index] =
2068 (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
2069 (j * rx_ring->fbr[0]->buffsize) + fbr1_offset;
2070
2071 /* now store the physical address in the descriptor
2072 * so the device can access it
2073 */
2074 rx_ring->fbr[0]->bus_high[index] =
2075 (u32) (fbr1_tmp_physaddr >> 32);
2076 rx_ring->fbr[0]->bus_low[index] =
2077 (u32) fbr1_tmp_physaddr;
2078
2079 fbr1_tmp_physaddr += rx_ring->fbr[0]->buffsize;
2080
2081 rx_ring->fbr[0]->buffer1[index] =
2082 rx_ring->fbr[0]->virt[index];
2083 rx_ring->fbr[0]->buffer2[index] =
2084 rx_ring->fbr[0]->virt[index] - 4;
2085 }
2086 }
2087
2088 #ifdef USE_FBR0
2089 /* Same for FBR0 (if in use) */
2090 for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
2091 u64 fbr0_offset;
2092 u64 fbr0_tmp_physaddr;
2093
2094 fbr_chunksize =
2095 ((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1;
2096 rx_ring->fbr[1]->mem_virtaddrs[i] =
2097 pci_alloc_consistent(adapter->pdev, fbr_chunksize,
2098 &rx_ring->fbr[1]->mem_physaddrs[i]);
2099
2100 if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
2101 dev_err(&adapter->pdev->dev,
2102 "Could not alloc memory\n");
2103 return -ENOMEM;
2104 }
2105
2106 /* See NOTE in "Save Physical Address" comment above */
2107 fbr0_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
2108
2109 et131x_align_allocated_memory(adapter,
2110 &fbr0_tmp_physaddr,
2111 &fbr0_offset,
2112 rx_ring->fbr[1]->buffsize - 1);
2113
2114 for (j = 0; j < FBR_CHUNKS; j++) {
2115 u32 index = (i * FBR_CHUNKS) + j;
2116
2117 rx_ring->fbr[1]->virt[index] =
2118 (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
2119 (j * rx_ring->fbr[1]->buffsize) + fbr0_offset;
2120
2121 rx_ring->fbr[1]->bus_high[index] =
2122 (u32) (fbr0_tmp_physaddr >> 32);
2123 rx_ring->fbr[1]->bus_low[index] =
2124 (u32) fbr0_tmp_physaddr;
2125
2126 fbr0_tmp_physaddr += rx_ring->fbr[1]->buffsize;
2127
2128 rx_ring->fbr[1]->buffer1[index] =
2129 rx_ring->fbr[1]->virt[index];
2130 rx_ring->fbr[1]->buffer2[index] =
2131 rx_ring->fbr[1]->virt[index] - 4;
2132 }
2133 }
2134 #endif
2135
2136 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2137 pktstat_ringsize =
2138 sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries;
2139
2140 rx_ring->ps_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
2141 pktstat_ringsize,
2142 &rx_ring->ps_ring_physaddr);
2143
2144 if (!rx_ring->ps_ring_virtaddr) {
2145 dev_err(&adapter->pdev->dev,
2146 "Cannot alloc memory for Packet Status Ring\n");
2147 return -ENOMEM;
2148 }
2149 printk(KERN_INFO "Packet Status Ring %lx\n",
2150 (unsigned long) rx_ring->ps_ring_physaddr);
2151
2152 /*
2153 * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
2154 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2155 * are ever returned, make sure the high part is retrieved here before
2156 * storing the adjusted address.
2157 */
2158
2159 /* Allocate an area of memory for writeback of status information */
2160 rx_ring->rx_status_block = pci_alloc_consistent(adapter->pdev,
2161 sizeof(struct rx_status_block),
2162 &rx_ring->rx_status_bus);
2163 if (!rx_ring->rx_status_block) {
2164 dev_err(&adapter->pdev->dev,
2165 "Cannot alloc memory for Status Block\n");
2166 return -ENOMEM;
2167 }
2168 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2169 printk(KERN_INFO "PRS %lx\n", (unsigned long)rx_ring->rx_status_bus);
2170
2171 /* Recv
2172 * pci_pool_create initializes a lookaside list. After successful
2173 * creation, nonpaged fixed-size blocks can be allocated from and
2174 * freed to the lookaside list.
2175 * RFDs will be allocated from this pool.
2176 */
2177 rx_ring->recv_lookaside = kmem_cache_create(adapter->netdev->name,
2178 sizeof(struct rfd),
2179 0,
2180 SLAB_CACHE_DMA |
2181 SLAB_HWCACHE_ALIGN,
2182 NULL);
2183
2184 adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE;
2185
2186 /* The RFDs are going to be put on lists later on, so initialize the
2187 * lists now.
2188 */
2189 INIT_LIST_HEAD(&rx_ring->recv_list);
2190 return 0;
2191 }
2192
2193 /**
2194 * et131x_rx_dma_memory_free - Free all memory allocated within this module.
2195 * @adapter: pointer to our private adapter structure
2196 */
2197 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2198 {
2199 u32 index;
2200 u32 bufsize;
2201 u32 pktstat_ringsize;
2202 struct rfd *rfd;
2203 struct rx_ring *rx_ring;
2204
2205 /* Setup some convenience pointers */
2206 rx_ring = &adapter->rx_ring;
2207
2208 /* Free RFDs and associated packet descriptors */
2209 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2210
2211 while (!list_empty(&rx_ring->recv_list)) {
2212 rfd = (struct rfd *) list_entry(rx_ring->recv_list.next,
2213 struct rfd, list_node);
2214
2215 list_del(&rfd->list_node);
2216 rfd->skb = NULL;
2217 kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd);
2218 }
2219
2220 /* Free Free Buffer Ring 1 */
2221 if (rx_ring->fbr[0]->ring_virtaddr) {
2222 /* First the packet memory */
2223 for (index = 0; index <
2224 (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
2225 if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
2226 u32 fbr1_align;
2227
2228 if (rx_ring->fbr[0]->buffsize > 4096)
2229 fbr1_align = 4096;
2230 else
2231 fbr1_align = rx_ring->fbr[0]->buffsize;
2232
2233 bufsize =
2234 (rx_ring->fbr[0]->buffsize * FBR_CHUNKS) +
2235 fbr1_align - 1;
2236
2237 pci_free_consistent(adapter->pdev,
2238 bufsize,
2239 rx_ring->fbr[0]->mem_virtaddrs[index],
2240 rx_ring->fbr[0]->mem_physaddrs[index]);
2241
2242 rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
2243 }
2244 }
2245
2246 /* Now the FIFO itself */
2247 rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
2248 rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
2249
2250 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
2251 + 0xfff;
2252
2253 pci_free_consistent(adapter->pdev, bufsize,
2254 rx_ring->fbr[0]->ring_virtaddr,
2255 rx_ring->fbr[0]->ring_physaddr);
2256
2257 rx_ring->fbr[0]->ring_virtaddr = NULL;
2258 }
2259
2260 #ifdef USE_FBR0
2261 /* Now the same for Free Buffer Ring 0 */
2262 if (rx_ring->fbr[1]->ring_virtaddr) {
2263 /* First the packet memory */
2264 for (index = 0; index <
2265 (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
2266 if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
2267 bufsize =
2268 (rx_ring->fbr[1]->buffsize *
2269 (FBR_CHUNKS + 1)) - 1;
2270
2271 pci_free_consistent(adapter->pdev,
2272 bufsize,
2273 rx_ring->fbr[1]->mem_virtaddrs[index],
2274 rx_ring->fbr[1]->mem_physaddrs[index]);
2275
2276 rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
2277 }
2278 }
2279
2280 /* Now the FIFO itself */
2281 rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
2282 rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
2283
2284 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
2285 + 0xfff;
2286
2287 pci_free_consistent(adapter->pdev,
2288 bufsize,
2289 rx_ring->fbr[1]->ring_virtaddr,
2290 rx_ring->fbr[1]->ring_physaddr);
2291
2292 rx_ring->fbr[1]->ring_virtaddr = NULL;
2293 }
2294 #endif
2295
2296 /* Free Packet Status Ring */
2297 if (rx_ring->ps_ring_virtaddr) {
2298 pktstat_ringsize =
2299 sizeof(struct pkt_stat_desc) *
2300 adapter->rx_ring.psr_num_entries;
2301
2302 pci_free_consistent(adapter->pdev, pktstat_ringsize,
2303 rx_ring->ps_ring_virtaddr,
2304 rx_ring->ps_ring_physaddr);
2305
2306 rx_ring->ps_ring_virtaddr = NULL;
2307 }
2308
2309 /* Free area of memory for the writeback of status information */
2310 if (rx_ring->rx_status_block) {
2311 pci_free_consistent(adapter->pdev,
2312 sizeof(struct rx_status_block),
2313 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2314 rx_ring->rx_status_block = NULL;
2315 }
2316
2317 /* Free receive buffer pool */
2318
2319 /* Free receive packet pool */
2320
2321 /* Destroy the lookaside (RFD) pool */
2322 if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) {
2323 kmem_cache_destroy(rx_ring->recv_lookaside);
2324 adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
2325 }
2326
2327 /* Free the FBR Lookup Table */
2328 #ifdef USE_FBR0
2329 kfree(rx_ring->fbr[1]);
2330 #endif
2331
2332 kfree(rx_ring->fbr[0]);
2333
2334 /* Reset Counters */
2335 rx_ring->num_ready_recv = 0;
2336 }
2337
2338 /**
2339 * et131x_init_recv - Initialize receive data structures.
2340 * @adapter: pointer to our private adapter structure
2341 *
2342 * Returns 0 on success and errno on failure (as defined in errno.h)
2343 */
2344 int et131x_init_recv(struct et131x_adapter *adapter)
2345 {
2346 int status = -ENOMEM;
2347 struct rfd *rfd = NULL;
2348 u32 rfdct;
2349 u32 numrfd = 0;
2350 struct rx_ring *rx_ring;
2351
2352 /* Setup some convenience pointers */
2353 rx_ring = &adapter->rx_ring;
2354
2355 /* Setup each RFD */
2356 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2357 rfd = kmem_cache_alloc(rx_ring->recv_lookaside,
2358 GFP_ATOMIC | GFP_DMA);
2359
2360 if (!rfd) {
2361 dev_err(&adapter->pdev->dev,
2362 "Couldn't alloc RFD out of kmem_cache\n");
2363 status = -ENOMEM;
2364 continue;
2365 }
2366
2367 rfd->skb = NULL;
2368
2369 /* Add this RFD to the recv_list */
2370 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2371
2372 /* Increment both the available RFD's, and the total RFD's. */
2373 rx_ring->num_ready_recv++;
2374 numrfd++;
2375 }
2376
2377 if (numrfd > NIC_MIN_NUM_RFD)
2378 status = 0;
2379
2380 rx_ring->num_rfd = numrfd;
2381
2382 if (status != 0) {
2383 kmem_cache_free(rx_ring->recv_lookaside, rfd);
2384 dev_err(&adapter->pdev->dev,
2385 "Allocation problems in et131x_init_recv\n");
2386 }
2387 return status;
2388 }
2389
2390 /**
2391 * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
2392 * @adapter: pointer to our adapter structure
2393 */
2394 void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
2395 {
2396 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2397 struct rx_ring *rx_local = &adapter->rx_ring;
2398 struct fbr_desc *fbr_entry;
2399 u32 entry;
2400 u32 psr_num_des;
2401 unsigned long flags;
2402
2403 /* Halt RXDMA to perform the reconfigure. */
2404 et131x_rx_dma_disable(adapter);
2405
2406 /* Load the completion writeback physical address
2407 *
2408 * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
2409 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2410 * are ever returned, make sure the high part is retrieved here
2411 * before storing the adjusted address.
2412 */
2413 writel((u32) ((u64)rx_local->rx_status_bus >> 32),
2414 &rx_dma->dma_wb_base_hi);
2415 writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo);
2416
2417 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
2418
2419 /* Set the address and parameters of the packet status ring into the
2420 * 1310's registers
2421 */
2422 writel((u32) ((u64)rx_local->ps_ring_physaddr >> 32),
2423 &rx_dma->psr_base_hi);
2424 writel((u32) rx_local->ps_ring_physaddr, &rx_dma->psr_base_lo);
2425 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
2426 writel(0, &rx_dma->psr_full_offset);
2427
2428 psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
2429 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
2430 &rx_dma->psr_min_des);
2431
2432 spin_lock_irqsave(&adapter->rcv_lock, flags);
2433
2434 /* These local variables track the PSR in the adapter structure */
2435 rx_local->local_psr_full = 0;
2436
2437 /* Now's the best time to initialize FBR1 contents */
2438 fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
2439 for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
2440 fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
2441 fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
2442 fbr_entry->word2 = entry;
2443 fbr_entry++;
2444 }
2445
2446 /* Set the address and parameters of Free buffer ring 1 (and 0 if
2447 * required) into the 1310's registers
2448 */
2449 writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
2450 &rx_dma->fbr1_base_hi);
2451 writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr1_base_lo);
2452 writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
2453 writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
2454
2455 /* This variable tracks the free buffer ring 1 full position, so it
2456 * has to match the above.
2457 */
2458 rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
2459 writel(
2460 ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
2461 &rx_dma->fbr1_min_des);
2462
2463 #ifdef USE_FBR0
2464 /* Now's the best time to initialize FBR0 contents */
2465 fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
2466 for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
2467 fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
2468 fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
2469 fbr_entry->word2 = entry;
2470 fbr_entry++;
2471 }
2472
2473 writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
2474 &rx_dma->fbr0_base_hi);
2475 writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr0_base_lo);
2476 writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
2477 writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
2478
2479 /* This variable tracks the free buffer ring 0 full position, so it
2480 * has to match the above.
2481 */
2482 rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
2483 writel(
2484 ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
2485 &rx_dma->fbr0_min_des);
2486 #endif
2487
2488 /* Program the number of packets we will receive before generating an
2489 * interrupt.
2490 * For version B silicon, this value gets updated once autoneg is
2491 *complete.
2492 */
2493 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
2494
2495 /* The "time_done" is not working correctly to coalesce interrupts
2496 * after a given time period, but rather is giving us an interrupt
2497 * regardless of whether we have received packets.
2498 * This value gets updated once autoneg is complete.
2499 */
2500 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
2501
2502 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2503 }
2504
2505 /**
2506 * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate.
2507 * @adapter: pointer to our adapter structure
2508 */
2509 void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2510 {
2511 struct phy_device *phydev = adapter->phydev;
2512
2513 if (!phydev)
2514 return;
2515
2516 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2517 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2518 */
2519 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2520 writel(0, &adapter->regs->rxdma.max_pkt_time);
2521 writel(1, &adapter->regs->rxdma.num_pkt_done);
2522 }
2523 }
2524
2525 /**
2526 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
2527 * @adapter: pointer to our adapter
2528 * @rfd: pointer to the RFD
2529 */
2530 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2531 {
2532 struct rx_ring *rx_local = &adapter->rx_ring;
2533 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2534 u16 buff_index = rfd->bufferindex;
2535 u8 ring_index = rfd->ringindex;
2536 unsigned long flags;
2537
2538 /* We don't use any of the OOB data besides status. Otherwise, we
2539 * need to clean up OOB data
2540 */
2541 if (
2542 #ifdef USE_FBR0
2543 (ring_index == 0 && buff_index < rx_local->fbr[1]->num_entries) ||
2544 #endif
2545 (ring_index == 1 && buff_index < rx_local->fbr[0]->num_entries)) {
2546 spin_lock_irqsave(&adapter->fbr_lock, flags);
2547
2548 if (ring_index == 1) {
2549 struct fbr_desc *next =
2550 (struct fbr_desc *) (rx_local->fbr[0]->ring_virtaddr) +
2551 INDEX10(rx_local->fbr[0]->local_full);
2552
2553 /* Handle the Free Buffer Ring advancement here. Write
2554 * the PA / Buffer Index for the returned buffer into
2555 * the oldest (next to be freed)FBR entry
2556 */
2557 next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
2558 next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
2559 next->word2 = buff_index;
2560
2561 writel(bump_free_buff_ring(&rx_local->fbr[0]->local_full,
2562 rx_local->fbr[0]->num_entries - 1),
2563 &rx_dma->fbr1_full_offset);
2564 }
2565 #ifdef USE_FBR0
2566 else {
2567 struct fbr_desc *next = (struct fbr_desc *)
2568 rx_local->fbr[1]->ring_virtaddr +
2569 INDEX10(rx_local->fbr[1]->local_full);
2570
2571 /* Handle the Free Buffer Ring advancement here. Write
2572 * the PA / Buffer Index for the returned buffer into
2573 * the oldest (next to be freed) FBR entry
2574 */
2575 next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
2576 next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
2577 next->word2 = buff_index;
2578
2579 writel(bump_free_buff_ring(
2580 &rx_local->fbr[1]->local_full,
2581 rx_local->fbr[1]->num_entries - 1),
2582 &rx_dma->fbr0_full_offset);
2583 }
2584 #endif
2585 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2586 } else {
2587 dev_err(&adapter->pdev->dev,
2588 "%s illegal Buffer Index returned\n", __func__);
2589 }
2590
2591 /* The processing on this RFD is done, so put it back on the tail of
2592 * our list
2593 */
2594 spin_lock_irqsave(&adapter->rcv_lock, flags);
2595 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2596 rx_local->num_ready_recv++;
2597 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2598
2599 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2600 }
2601
2602 /**
2603 * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
2604 * @adapter: pointer to our adapter structure
2605 */
2606 void et131x_rx_dma_disable(struct et131x_adapter *adapter)
2607 {
2608 u32 csr;
2609 /* Setup the receive dma configuration register */
2610 writel(0x00002001, &adapter->regs->rxdma.csr);
2611 csr = readl(&adapter->regs->rxdma.csr);
2612 if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */
2613 udelay(5);
2614 csr = readl(&adapter->regs->rxdma.csr);
2615 if ((csr & 0x00020000) == 0)
2616 dev_err(&adapter->pdev->dev,
2617 "RX Dma failed to enter halt state. CSR 0x%08x\n",
2618 csr);
2619 }
2620 }
2621
2622 /**
2623 * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
2624 * @adapter: pointer to our adapter structure
2625 */
2626 void et131x_rx_dma_enable(struct et131x_adapter *adapter)
2627 {
2628 /* Setup the receive dma configuration register for normal operation */
2629 u32 csr = 0x2000; /* FBR1 enable */
2630
2631 if (adapter->rx_ring.fbr[0]->buffsize == 4096)
2632 csr |= 0x0800;
2633 else if (adapter->rx_ring.fbr[0]->buffsize == 8192)
2634 csr |= 0x1000;
2635 else if (adapter->rx_ring.fbr[0]->buffsize == 16384)
2636 csr |= 0x1800;
2637 #ifdef USE_FBR0
2638 csr |= 0x0400; /* FBR0 enable */
2639 if (adapter->rx_ring.fbr[1]->buffsize == 256)
2640 csr |= 0x0100;
2641 else if (adapter->rx_ring.fbr[1]->buffsize == 512)
2642 csr |= 0x0200;
2643 else if (adapter->rx_ring.fbr[1]->buffsize == 1024)
2644 csr |= 0x0300;
2645 #endif
2646 writel(csr, &adapter->regs->rxdma.csr);
2647
2648 csr = readl(&adapter->regs->rxdma.csr);
2649 if ((csr & 0x00020000) != 0) {
2650 udelay(5);
2651 csr = readl(&adapter->regs->rxdma.csr);
2652 if ((csr & 0x00020000) != 0) {
2653 dev_err(&adapter->pdev->dev,
2654 "RX Dma failed to exit halt state. CSR 0x%08x\n",
2655 csr);
2656 }
2657 }
2658 }
2659
2660
2661 static inline void add_10bit(u32 *v, int n)
2662 {
2663 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
2664 }
2665
2666 static inline void add_12bit(u32 *v, int n)
2667 {
2668 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
2669 }
2670
2671 /**
2672 * nic_rx_pkts - Checks the hardware for available packets
2673 * @adapter: pointer to our adapter
2674 *
2675 * Returns rfd, a pointer to our MPRFD.
2676 *
2677 * Checks the hardware for available packets, using completion ring
2678 * If packets are available, it gets an RFD from the recv_list, attaches
2679 * the packet to it, puts the RFD in the RecvPendList, and also returns
2680 * the pointer to the RFD.
2681 */
2682 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2683 {
2684 struct rx_ring *rx_local = &adapter->rx_ring;
2685 struct rx_status_block *status;
2686 struct pkt_stat_desc *psr;
2687 struct rfd *rfd;
2688 u32 i;
2689 u8 *buf;
2690 unsigned long flags;
2691 struct list_head *element;
2692 u8 ring_index;
2693 u16 buff_index;
2694 u32 len;
2695 u32 word0;
2696 u32 word1;
2697
2698 /* RX Status block is written by the DMA engine prior to every
2699 * interrupt. It contains the next to be used entry in the Packet
2700 * Status Ring, and also the two Free Buffer rings.
2701 */
2702 status = rx_local->rx_status_block;
2703 word1 = status->word1 >> 16; /* Get the useful bits */
2704
2705 /* Check the PSR and wrap bits do not match */
2706 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2707 /* Looks like this ring is not updated yet */
2708 return NULL;
2709
2710 /* The packet status ring indicates that data is available. */
2711 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2712 (rx_local->local_psr_full & 0xFFF);
2713
2714 /* Grab any information that is required once the PSR is
2715 * advanced, since we can no longer rely on the memory being
2716 * accurate
2717 */
2718 len = psr->word1 & 0xFFFF;
2719 ring_index = (psr->word1 >> 26) & 0x03;
2720 buff_index = (psr->word1 >> 16) & 0x3FF;
2721 word0 = psr->word0;
2722
2723 /* Indicate that we have used this PSR entry. */
2724 /* FIXME wrap 12 */
2725 add_12bit(&rx_local->local_psr_full, 1);
2726 if (
2727 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2728 /* Clear psr full and toggle the wrap bit */
2729 rx_local->local_psr_full &= ~0xFFF;
2730 rx_local->local_psr_full ^= 0x1000;
2731 }
2732
2733 writel(rx_local->local_psr_full,
2734 &adapter->regs->rxdma.psr_full_offset);
2735
2736 #ifndef USE_FBR0
2737 if (ring_index != 1)
2738 return NULL;
2739 #endif
2740
2741 #ifdef USE_FBR0
2742 if (ring_index > 1 ||
2743 (ring_index == 0 &&
2744 buff_index > rx_local->fbr[1]->num_entries - 1) ||
2745 (ring_index == 1 &&
2746 buff_index > rx_local->fbr[0]->num_entries - 1))
2747 #else
2748 if (ring_index != 1 || buff_index > rx_local->fbr[0]->num_entries - 1)
2749 #endif
2750 {
2751 /* Illegal buffer or ring index cannot be used by S/W*/
2752 dev_err(&adapter->pdev->dev,
2753 "NICRxPkts PSR Entry %d indicates "
2754 "length of %d and/or bad bi(%d)\n",
2755 rx_local->local_psr_full & 0xFFF,
2756 len, buff_index);
2757 return NULL;
2758 }
2759
2760 /* Get and fill the RFD. */
2761 spin_lock_irqsave(&adapter->rcv_lock, flags);
2762
2763 rfd = NULL;
2764 element = rx_local->recv_list.next;
2765 rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
2766
2767 if (rfd == NULL) {
2768 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2769 return NULL;
2770 }
2771
2772 list_del(&rfd->list_node);
2773 rx_local->num_ready_recv--;
2774
2775 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2776
2777 rfd->bufferindex = buff_index;
2778 rfd->ringindex = ring_index;
2779
2780 /* In V1 silicon, there is a bug which screws up filtering of
2781 * runt packets. Therefore runt packet filtering is disabled
2782 * in the MAC and the packets are dropped here. They are
2783 * also counted here.
2784 */
2785 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2786 adapter->stats.rx_other_errs++;
2787 len = 0;
2788 }
2789
2790 if (len) {
2791 /* Determine if this is a multicast packet coming in */
2792 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2793 !(word0 & ALCATEL_BROADCAST_PKT)) {
2794 /* Promiscuous mode and Multicast mode are
2795 * not mutually exclusive as was first
2796 * thought. I guess Promiscuous is just
2797 * considered a super-set of the other
2798 * filters. Generally filter is 0x2b when in
2799 * promiscuous mode.
2800 */
2801 if ((adapter->packet_filter &
2802 ET131X_PACKET_TYPE_MULTICAST)
2803 && !(adapter->packet_filter &
2804 ET131X_PACKET_TYPE_PROMISCUOUS)
2805 && !(adapter->packet_filter &
2806 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2807 /*
2808 * Note - ring_index for fbr[] array is reversed
2809 * 1 for FBR0 etc
2810 */
2811 buf = rx_local->fbr[(ring_index == 0 ? 1 : 0)]->
2812 virt[buff_index];
2813
2814 /* Loop through our list to see if the
2815 * destination address of this packet
2816 * matches one in our list.
2817 */
2818 for (i = 0; i < adapter->multicast_addr_count;
2819 i++) {
2820 if (buf[0] ==
2821 adapter->multicast_list[i][0]
2822 && buf[1] ==
2823 adapter->multicast_list[i][1]
2824 && buf[2] ==
2825 adapter->multicast_list[i][2]
2826 && buf[3] ==
2827 adapter->multicast_list[i][3]
2828 && buf[4] ==
2829 adapter->multicast_list[i][4]
2830 && buf[5] ==
2831 adapter->multicast_list[i][5]) {
2832 break;
2833 }
2834 }
2835
2836 /* If our index is equal to the number
2837 * of Multicast address we have, then
2838 * this means we did not find this
2839 * packet's matching address in our
2840 * list. Set the len to zero,
2841 * so we free our RFD when we return
2842 * from this function.
2843 */
2844 if (i == adapter->multicast_addr_count)
2845 len = 0;
2846 }
2847
2848 if (len > 0)
2849 adapter->stats.multicast_pkts_rcvd++;
2850 } else if (word0 & ALCATEL_BROADCAST_PKT)
2851 adapter->stats.broadcast_pkts_rcvd++;
2852 else
2853 /* Not sure what this counter measures in
2854 * promiscuous mode. Perhaps we should check
2855 * the MAC address to see if it is directed
2856 * to us in promiscuous mode.
2857 */
2858 adapter->stats.unicast_pkts_rcvd++;
2859 }
2860
2861 if (len > 0) {
2862 struct sk_buff *skb = NULL;
2863
2864 /*rfd->len = len - 4; */
2865 rfd->len = len;
2866
2867 skb = dev_alloc_skb(rfd->len + 2);
2868 if (!skb) {
2869 dev_err(&adapter->pdev->dev,
2870 "Couldn't alloc an SKB for Rx\n");
2871 return NULL;
2872 }
2873
2874 adapter->net_stats.rx_bytes += rfd->len;
2875
2876 /*
2877 * Note - ring_index for fbr[] array is reversed,
2878 * 1 for FBR0 etc
2879 */
2880 memcpy(skb_put(skb, rfd->len),
2881 rx_local->fbr[(ring_index == 0 ? 1 : 0)]->virt[buff_index],
2882 rfd->len);
2883
2884 skb->dev = adapter->netdev;
2885 skb->protocol = eth_type_trans(skb, adapter->netdev);
2886 skb->ip_summed = CHECKSUM_NONE;
2887
2888 netif_rx(skb);
2889 } else {
2890 rfd->len = 0;
2891 }
2892
2893 nic_return_rfd(adapter, rfd);
2894 return rfd;
2895 }
2896
2897 /**
2898 * et131x_reset_recv - Reset the receive list
2899 * @adapter: pointer to our adapter
2900 *
2901 * Assumption, Rcv spinlock has been acquired.
2902 */
2903 void et131x_reset_recv(struct et131x_adapter *adapter)
2904 {
2905 WARN_ON(list_empty(&adapter->rx_ring.recv_list));
2906 }
2907
2908 /**
2909 * et131x_handle_recv_interrupt - Interrupt handler for receive processing
2910 * @adapter: pointer to our adapter
2911 *
2912 * Assumption, Rcv spinlock has been acquired.
2913 */
2914 void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
2915 {
2916 struct rfd *rfd = NULL;
2917 u32 count = 0;
2918 bool done = true;
2919
2920 /* Process up to available RFD's */
2921 while (count < NUM_PACKETS_HANDLED) {
2922 if (list_empty(&adapter->rx_ring.recv_list)) {
2923 WARN_ON(adapter->rx_ring.num_ready_recv != 0);
2924 done = false;
2925 break;
2926 }
2927
2928 rfd = nic_rx_pkts(adapter);
2929
2930 if (rfd == NULL)
2931 break;
2932
2933 /* Do not receive any packets until a filter has been set.
2934 * Do not receive any packets until we have link.
2935 * If length is zero, return the RFD in order to advance the
2936 * Free buffer ring.
2937 */
2938 if (!adapter->packet_filter ||
2939 !netif_carrier_ok(adapter->netdev) ||
2940 rfd->len == 0)
2941 continue;
2942
2943 /* Increment the number of packets we received */
2944 adapter->net_stats.rx_packets++;
2945
2946 /* Set the status on the packet, either resources or success */
2947 if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) {
2948 dev_warn(&adapter->pdev->dev,
2949 "RFD's are running out\n");
2950 }
2951 count++;
2952 }
2953
2954 if (count == NUM_PACKETS_HANDLED || !done) {
2955 adapter->rx_ring.unfinished_receives = true;
2956 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2957 &adapter->regs->global.watchdog_timer);
2958 } else
2959 /* Watchdog timer will disable itself if appropriate. */
2960 adapter->rx_ring.unfinished_receives = false;
2961 }
2962
2963 /* TX functions */
2964
2965 /**
2966 * et131x_tx_dma_memory_alloc
2967 * @adapter: pointer to our private adapter structure
2968 *
2969 * Returns 0 on success and errno on failure (as defined in errno.h).
2970 *
2971 * Allocates memory that will be visible both to the device and to the CPU.
2972 * The OS will pass us packets, pointers to which we will insert in the Tx
2973 * Descriptor queue. The device will read this queue to find the packets in
2974 * memory. The device will update the "status" in memory each time it xmits a
2975 * packet.
2976 */
2977 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2978 {
2979 int desc_size = 0;
2980 struct tx_ring *tx_ring = &adapter->tx_ring;
2981
2982 /* Allocate memory for the TCB's (Transmit Control Block) */
2983 adapter->tx_ring.tcb_ring =
2984 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
2985 if (!adapter->tx_ring.tcb_ring) {
2986 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
2987 return -ENOMEM;
2988 }
2989
2990 /* Allocate enough memory for the Tx descriptor ring, and allocate
2991 * some extra so that the ring can be aligned on a 4k boundary.
2992 */
2993 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
2994 tx_ring->tx_desc_ring =
2995 (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
2996 &tx_ring->tx_desc_ring_pa);
2997 if (!adapter->tx_ring.tx_desc_ring) {
2998 dev_err(&adapter->pdev->dev,
2999 "Cannot alloc memory for Tx Ring\n");
3000 return -ENOMEM;
3001 }
3002
3003 /* Save physical address
3004 *
3005 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
3006 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
3007 * are ever returned, make sure the high part is retrieved here before
3008 * storing the adjusted address.
3009 */
3010 /* Allocate memory for the Tx status block */
3011 tx_ring->tx_status = pci_alloc_consistent(adapter->pdev,
3012 sizeof(u32),
3013 &tx_ring->tx_status_pa);
3014 if (!adapter->tx_ring.tx_status_pa) {
3015 dev_err(&adapter->pdev->dev,
3016 "Cannot alloc memory for Tx status block\n");
3017 return -ENOMEM;
3018 }
3019 return 0;
3020 }
3021
3022 /**
3023 * et131x_tx_dma_memory_free - Free all memory allocated within this module
3024 * @adapter: pointer to our private adapter structure
3025 *
3026 * Returns 0 on success and errno on failure (as defined in errno.h).
3027 */
3028 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
3029 {
3030 int desc_size = 0;
3031
3032 if (adapter->tx_ring.tx_desc_ring) {
3033 /* Free memory relating to Tx rings here */
3034 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
3035 + 4096 - 1;
3036 pci_free_consistent(adapter->pdev,
3037 desc_size,
3038 adapter->tx_ring.tx_desc_ring,
3039 adapter->tx_ring.tx_desc_ring_pa);
3040 adapter->tx_ring.tx_desc_ring = NULL;
3041 }
3042
3043 /* Free memory for the Tx status block */
3044 if (adapter->tx_ring.tx_status) {
3045 pci_free_consistent(adapter->pdev,
3046 sizeof(u32),
3047 adapter->tx_ring.tx_status,
3048 adapter->tx_ring.tx_status_pa);
3049
3050 adapter->tx_ring.tx_status = NULL;
3051 }
3052 /* Free the memory for the tcb structures */
3053 kfree(adapter->tx_ring.tcb_ring);
3054 }
3055
3056 /**
3057 * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
3058 * @adapter: pointer to our private adapter structure
3059 *
3060 * Configure the transmit engine with the ring buffers we have created
3061 * and prepare it for use.
3062 */
3063 void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
3064 {
3065 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
3066
3067 /* Load the hardware with the start of the transmit descriptor ring. */
3068 writel((u32) ((u64)adapter->tx_ring.tx_desc_ring_pa >> 32),
3069 &txdma->pr_base_hi);
3070 writel((u32) adapter->tx_ring.tx_desc_ring_pa,
3071 &txdma->pr_base_lo);
3072
3073 /* Initialise the transmit DMA engine */
3074 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
3075
3076 /* Load the completion writeback physical address */
3077 writel((u32)((u64)adapter->tx_ring.tx_status_pa >> 32),
3078 &txdma->dma_wb_base_hi);
3079 writel((u32)adapter->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
3080
3081 *adapter->tx_ring.tx_status = 0;
3082
3083 writel(0, &txdma->service_request);
3084 adapter->tx_ring.send_idx = 0;
3085 }
3086
3087 /**
3088 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
3089 * @adapter: pointer to our adapter structure
3090 */
3091 void et131x_tx_dma_disable(struct et131x_adapter *adapter)
3092 {
3093 /* Setup the tramsmit dma configuration register */
3094 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
3095 &adapter->regs->txdma.csr);
3096 }
3097
3098 /**
3099 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
3100 * @adapter: pointer to our adapter structure
3101 *
3102 * Mainly used after a return to the D0 (full-power) state from a lower state.
3103 */
3104 void et131x_tx_dma_enable(struct et131x_adapter *adapter)
3105 {
3106 /* Setup the transmit dma configuration register for normal
3107 * operation
3108 */
3109 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
3110 &adapter->regs->txdma.csr);
3111 }
3112
3113 /**
3114 * et131x_init_send - Initialize send data structures
3115 * @adapter: pointer to our private adapter structure
3116 */
3117 void et131x_init_send(struct et131x_adapter *adapter)
3118 {
3119 struct tcb *tcb;
3120 u32 ct;
3121 struct tx_ring *tx_ring;
3122
3123 /* Setup some convenience pointers */
3124 tx_ring = &adapter->tx_ring;
3125 tcb = adapter->tx_ring.tcb_ring;
3126
3127 tx_ring->tcb_qhead = tcb;
3128
3129 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
3130
3131 /* Go through and set up each TCB */
3132 for (ct = 0; ct++ < NUM_TCB; tcb++)
3133 /* Set the link pointer in HW TCB to the next TCB in the
3134 * chain
3135 */
3136 tcb->next = tcb + 1;
3137
3138 /* Set the tail pointer */
3139 tcb--;
3140 tx_ring->tcb_qtail = tcb;
3141 tcb->next = NULL;
3142 /* Curr send queue should now be empty */
3143 tx_ring->send_head = NULL;
3144 tx_ring->send_tail = NULL;
3145 }
3146
3147 /**
3148 * nic_send_packet - NIC specific send handler for version B silicon.
3149 * @adapter: pointer to our adapter
3150 * @tcb: pointer to struct tcb
3151 *
3152 * Returns 0 or errno.
3153 */
3154 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
3155 {
3156 u32 i;
3157 struct tx_desc desc[24]; /* 24 x 16 byte */
3158 u32 frag = 0;
3159 u32 thiscopy, remainder;
3160 struct sk_buff *skb = tcb->skb;
3161 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
3162 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
3163 unsigned long flags;
3164 struct phy_device *phydev = adapter->phydev;
3165
3166 /* Part of the optimizations of this send routine restrict us to
3167 * sending 24 fragments at a pass. In practice we should never see
3168 * more than 5 fragments.
3169 *
3170 * NOTE: The older version of this function (below) can handle any
3171 * number of fragments. If needed, we can call this function,
3172 * although it is less efficient.
3173 */
3174 if (nr_frags > 23)
3175 return -EIO;
3176
3177 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
3178
3179 for (i = 0; i < nr_frags; i++) {
3180 /* If there is something in this element, lets get a
3181 * descriptor from the ring and get the necessary data
3182 */
3183 if (i == 0) {
3184 /* If the fragments are smaller than a standard MTU,
3185 * then map them to a single descriptor in the Tx
3186 * Desc ring. However, if they're larger, as is
3187 * possible with support for jumbo packets, then
3188 * split them each across 2 descriptors.
3189 *
3190 * This will work until we determine why the hardware
3191 * doesn't seem to like large fragments.
3192 */
3193 if ((skb->len - skb->data_len) <= 1514) {
3194 desc[frag].addr_hi = 0;
3195 /* Low 16bits are length, high is vlan and
3196 unused currently so zero */
3197 desc[frag].len_vlan =
3198 skb->len - skb->data_len;
3199
3200 /* NOTE: Here, the dma_addr_t returned from
3201 * pci_map_single() is implicitly cast as a
3202 * u32. Although dma_addr_t can be
3203 * 64-bit, the address returned by
3204 * pci_map_single() is always 32-bit
3205 * addressable (as defined by the pci/dma
3206 * subsystem)
3207 */
3208 desc[frag++].addr_lo =
3209 pci_map_single(adapter->pdev,
3210 skb->data,
3211 skb->len -
3212 skb->data_len,
3213 PCI_DMA_TODEVICE);
3214 } else {
3215 desc[frag].addr_hi = 0;
3216 desc[frag].len_vlan =
3217 (skb->len - skb->data_len) / 2;
3218
3219 /* NOTE: Here, the dma_addr_t returned from
3220 * pci_map_single() is implicitly cast as a
3221 * u32. Although dma_addr_t can be
3222 * 64-bit, the address returned by
3223 * pci_map_single() is always 32-bit
3224 * addressable (as defined by the pci/dma
3225 * subsystem)
3226 */
3227 desc[frag++].addr_lo =
3228 pci_map_single(adapter->pdev,
3229 skb->data,
3230 ((skb->len -
3231 skb->data_len) / 2),
3232 PCI_DMA_TODEVICE);
3233 desc[frag].addr_hi = 0;
3234
3235 desc[frag].len_vlan =
3236 (skb->len - skb->data_len) / 2;
3237
3238 /* NOTE: Here, the dma_addr_t returned from
3239 * pci_map_single() is implicitly cast as a
3240 * u32. Although dma_addr_t can be
3241 * 64-bit, the address returned by
3242 * pci_map_single() is always 32-bit
3243 * addressable (as defined by the pci/dma
3244 * subsystem)
3245 */
3246 desc[frag++].addr_lo =
3247 pci_map_single(adapter->pdev,
3248 skb->data +
3249 ((skb->len -
3250 skb->data_len) / 2),
3251 ((skb->len -
3252 skb->data_len) / 2),
3253 PCI_DMA_TODEVICE);
3254 }
3255 } else {
3256 desc[frag].addr_hi = 0;
3257 desc[frag].len_vlan =
3258 frags[i - 1].size;
3259
3260 /* NOTE: Here, the dma_addr_t returned from
3261 * pci_map_page() is implicitly cast as a u32.
3262 * Although dma_addr_t can be 64-bit, the address
3263 * returned by pci_map_page() is always 32-bit
3264 * addressable (as defined by the pci/dma subsystem)
3265 */
3266 desc[frag++].addr_lo =
3267 pci_map_page(adapter->pdev,
3268 frags[i - 1].page,
3269 frags[i - 1].page_offset,
3270 frags[i - 1].size,
3271 PCI_DMA_TODEVICE);
3272 }
3273 }
3274
3275 if (frag == 0)
3276 return -EIO;
3277
3278 if (phydev && phydev->speed == SPEED_1000) {
3279 if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
3280 /* Last element & Interrupt flag */
3281 desc[frag - 1].flags = 0x5;
3282 adapter->tx_ring.since_irq = 0;
3283 } else { /* Last element */
3284 desc[frag - 1].flags = 0x1;
3285 }
3286 } else
3287 desc[frag - 1].flags = 0x5;
3288
3289 desc[0].flags |= 2; /* First element flag */
3290
3291 tcb->index_start = adapter->tx_ring.send_idx;
3292 tcb->stale = 0;
3293
3294 spin_lock_irqsave(&adapter->send_hw_lock, flags);
3295
3296 thiscopy = NUM_DESC_PER_RING_TX -
3297 INDEX10(adapter->tx_ring.send_idx);
3298
3299 if (thiscopy >= frag) {
3300 remainder = 0;
3301 thiscopy = frag;
3302 } else {
3303 remainder = frag - thiscopy;
3304 }
3305
3306 memcpy(adapter->tx_ring.tx_desc_ring +
3307 INDEX10(adapter->tx_ring.send_idx), desc,
3308 sizeof(struct tx_desc) * thiscopy);
3309
3310 add_10bit(&adapter->tx_ring.send_idx, thiscopy);
3311
3312 if (INDEX10(adapter->tx_ring.send_idx) == 0 ||
3313 INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
3314 adapter->tx_ring.send_idx &= ~ET_DMA10_MASK;
3315 adapter->tx_ring.send_idx ^= ET_DMA10_WRAP;
3316 }
3317
3318 if (remainder) {
3319 memcpy(adapter->tx_ring.tx_desc_ring,
3320 desc + thiscopy,
3321 sizeof(struct tx_desc) * remainder);
3322
3323 add_10bit(&adapter->tx_ring.send_idx, remainder);
3324 }
3325
3326 if (INDEX10(adapter->tx_ring.send_idx) == 0) {
3327 if (adapter->tx_ring.send_idx)
3328 tcb->index = NUM_DESC_PER_RING_TX - 1;
3329 else
3330 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
3331 } else
3332 tcb->index = adapter->tx_ring.send_idx - 1;
3333
3334 spin_lock(&adapter->tcb_send_qlock);
3335
3336 if (adapter->tx_ring.send_tail)
3337 adapter->tx_ring.send_tail->next = tcb;
3338 else
3339 adapter->tx_ring.send_head = tcb;
3340
3341 adapter->tx_ring.send_tail = tcb;
3342
3343 WARN_ON(tcb->next != NULL);
3344
3345 adapter->tx_ring.used++;
3346
3347 spin_unlock(&adapter->tcb_send_qlock);
3348
3349 /* Write the new write pointer back to the device. */
3350 writel(adapter->tx_ring.send_idx,
3351 &adapter->regs->txdma.service_request);
3352
3353 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
3354 * timer to wake us up if this packet isn't followed by N more.
3355 */
3356 if (phydev && phydev->speed == SPEED_1000) {
3357 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
3358 &adapter->regs->global.watchdog_timer);
3359 }
3360 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
3361
3362 return 0;
3363 }
3364
3365 /**
3366 * send_packet - Do the work to send a packet
3367 * @skb: the packet(s) to send
3368 * @adapter: a pointer to the device's private adapter structure
3369 *
3370 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
3371 *
3372 * Assumption: Send spinlock has been acquired
3373 */
3374 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
3375 {
3376 int status;
3377 struct tcb *tcb = NULL;
3378 u16 *shbufva;
3379 unsigned long flags;
3380
3381 /* All packets must have at least a MAC address and a protocol type */
3382 if (skb->len < ETH_HLEN)
3383 return -EIO;
3384
3385 /* Get a TCB for this packet */
3386 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3387
3388 tcb = adapter->tx_ring.tcb_qhead;
3389
3390 if (tcb == NULL) {
3391 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3392 return -ENOMEM;
3393 }
3394
3395 adapter->tx_ring.tcb_qhead = tcb->next;
3396
3397 if (adapter->tx_ring.tcb_qhead == NULL)
3398 adapter->tx_ring.tcb_qtail = NULL;
3399
3400 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3401
3402 tcb->skb = skb;
3403
3404 if (skb->data != NULL && skb->len - skb->data_len >= 6) {
3405 shbufva = (u16 *) skb->data;
3406
3407 if ((shbufva[0] == 0xffff) &&
3408 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
3409 tcb->flags |= fMP_DEST_BROAD;
3410 } else if ((shbufva[0] & 0x3) == 0x0001) {
3411 tcb->flags |= fMP_DEST_MULTI;
3412 }
3413 }
3414
3415 tcb->next = NULL;
3416
3417 /* Call the NIC specific send handler. */
3418 status = nic_send_packet(adapter, tcb);
3419
3420 if (status != 0) {
3421 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3422
3423 if (adapter->tx_ring.tcb_qtail)
3424 adapter->tx_ring.tcb_qtail->next = tcb;
3425 else
3426 /* Apparently ready Q is empty. */
3427 adapter->tx_ring.tcb_qhead = tcb;
3428
3429 adapter->tx_ring.tcb_qtail = tcb;
3430 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3431 return status;
3432 }
3433 WARN_ON(adapter->tx_ring.used > NUM_TCB);
3434 return 0;
3435 }
3436
3437 /**
3438 * et131x_send_packets - This function is called by the OS to send packets
3439 * @skb: the packet(s) to send
3440 * @netdev:device on which to TX the above packet(s)
3441 *
3442 * Return 0 in almost all cases; non-zero value in extreme hard failure only
3443 */
3444 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
3445 {
3446 int status = 0;
3447 struct et131x_adapter *adapter = NULL;
3448
3449 adapter = netdev_priv(netdev);
3450
3451 /* Send these packets
3452 *
3453 * NOTE: The Linux Tx entry point is only given one packet at a time
3454 * to Tx, so the PacketCount and it's array used makes no sense here
3455 */
3456
3457 /* TCB is not available */
3458 if (adapter->tx_ring.used >= NUM_TCB) {
3459 /* NOTE: If there's an error on send, no need to queue the
3460 * packet under Linux; if we just send an error up to the
3461 * netif layer, it will resend the skb to us.
3462 */
3463 status = -ENOMEM;
3464 } else {
3465 /* We need to see if the link is up; if it's not, make the
3466 * netif layer think we're good and drop the packet
3467 */
3468 if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
3469 !netif_carrier_ok(netdev)) {
3470 dev_kfree_skb_any(skb);
3471 skb = NULL;
3472
3473 adapter->net_stats.tx_dropped++;
3474 } else {
3475 status = send_packet(skb, adapter);
3476 if (status != 0 && status != -ENOMEM) {
3477 /* On any other error, make netif think we're
3478 * OK and drop the packet
3479 */
3480 dev_kfree_skb_any(skb);
3481 skb = NULL;
3482 adapter->net_stats.tx_dropped++;
3483 }
3484 }
3485 }
3486 return status;
3487 }
3488
3489 /**
3490 * free_send_packet - Recycle a struct tcb
3491 * @adapter: pointer to our adapter
3492 * @tcb: pointer to struct tcb
3493 *
3494 * Complete the packet if necessary
3495 * Assumption - Send spinlock has been acquired
3496 */
3497 static inline void free_send_packet(struct et131x_adapter *adapter,
3498 struct tcb *tcb)
3499 {
3500 unsigned long flags;
3501 struct tx_desc *desc = NULL;
3502 struct net_device_stats *stats = &adapter->net_stats;
3503
3504 if (tcb->flags & fMP_DEST_BROAD)
3505 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3506 else if (tcb->flags & fMP_DEST_MULTI)
3507 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3508 else
3509 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3510
3511 if (tcb->skb) {
3512 stats->tx_bytes += tcb->skb->len;
3513
3514 /* Iterate through the TX descriptors on the ring
3515 * corresponding to this packet and umap the fragments
3516 * they point to
3517 */
3518 do {
3519 desc = (struct tx_desc *)
3520 (adapter->tx_ring.tx_desc_ring +
3521 INDEX10(tcb->index_start));
3522
3523 pci_unmap_single(adapter->pdev,
3524 desc->addr_lo,
3525 desc->len_vlan, PCI_DMA_TODEVICE);
3526
3527 add_10bit(&tcb->index_start, 1);
3528 if (INDEX10(tcb->index_start) >=
3529 NUM_DESC_PER_RING_TX) {
3530 tcb->index_start &= ~ET_DMA10_MASK;
3531 tcb->index_start ^= ET_DMA10_WRAP;
3532 }
3533 } while (desc != (adapter->tx_ring.tx_desc_ring +
3534 INDEX10(tcb->index)));
3535
3536 dev_kfree_skb_any(tcb->skb);
3537 }
3538
3539 memset(tcb, 0, sizeof(struct tcb));
3540
3541 /* Add the TCB to the Ready Q */
3542 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3543
3544 adapter->net_stats.tx_packets++;
3545
3546 if (adapter->tx_ring.tcb_qtail)
3547 adapter->tx_ring.tcb_qtail->next = tcb;
3548 else
3549 /* Apparently ready Q is empty. */
3550 adapter->tx_ring.tcb_qhead = tcb;
3551
3552 adapter->tx_ring.tcb_qtail = tcb;
3553
3554 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3555 WARN_ON(adapter->tx_ring.used < 0);
3556 }
3557
3558 /**
3559 * et131x_free_busy_send_packets - Free and complete the stopped active sends
3560 * @adapter: pointer to our adapter
3561 *
3562 * Assumption - Send spinlock has been acquired
3563 */
3564 void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3565 {
3566 struct tcb *tcb;
3567 unsigned long flags;
3568 u32 freed = 0;
3569
3570 /* Any packets being sent? Check the first TCB on the send list */
3571 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3572
3573 tcb = adapter->tx_ring.send_head;
3574
3575 while (tcb != NULL && freed < NUM_TCB) {
3576 struct tcb *next = tcb->next;
3577
3578 adapter->tx_ring.send_head = next;
3579
3580 if (next == NULL)
3581 adapter->tx_ring.send_tail = NULL;
3582
3583 adapter->tx_ring.used--;
3584
3585 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3586
3587 freed++;
3588 free_send_packet(adapter, tcb);
3589
3590 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3591
3592 tcb = adapter->tx_ring.send_head;
3593 }
3594
3595 WARN_ON(freed == NUM_TCB);
3596
3597 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3598
3599 adapter->tx_ring.used = 0;
3600 }
3601
3602 /**
3603 * et131x_handle_send_interrupt - Interrupt handler for sending processing
3604 * @adapter: pointer to our adapter
3605 *
3606 * Re-claim the send resources, complete sends and get more to send from
3607 * the send wait queue.
3608 *
3609 * Assumption - Send spinlock has been acquired
3610 */
3611 void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3612 {
3613 unsigned long flags;
3614 u32 serviced;
3615 struct tcb *tcb;
3616 u32 index;
3617
3618 serviced = readl(&adapter->regs->txdma.new_service_complete);
3619 index = INDEX10(serviced);
3620
3621 /* Has the ring wrapped? Process any descriptors that do not have
3622 * the same "wrap" indicator as the current completion indicator
3623 */
3624 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3625
3626 tcb = adapter->tx_ring.send_head;
3627
3628 while (tcb &&
3629 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3630 index < INDEX10(tcb->index)) {
3631 adapter->tx_ring.used--;
3632 adapter->tx_ring.send_head = tcb->next;
3633 if (tcb->next == NULL)
3634 adapter->tx_ring.send_tail = NULL;
3635
3636 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3637 free_send_packet(adapter, tcb);
3638 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3639
3640 /* Goto the next packet */
3641 tcb = adapter->tx_ring.send_head;
3642 }
3643 while (tcb &&
3644 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3645 && index > (tcb->index & ET_DMA10_MASK)) {
3646 adapter->tx_ring.used--;
3647 adapter->tx_ring.send_head = tcb->next;
3648 if (tcb->next == NULL)
3649 adapter->tx_ring.send_tail = NULL;
3650
3651 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3652 free_send_packet(adapter, tcb);
3653 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3654
3655 /* Goto the next packet */
3656 tcb = adapter->tx_ring.send_head;
3657 }
3658
3659 /* Wake up the queue when we hit a low-water mark */
3660 if (adapter->tx_ring.used <= NUM_TCB / 3)
3661 netif_wake_queue(adapter->netdev);
3662
3663 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3664 }
3665
3666 /* ETHTOOL functions */
3667
3668 static int et131x_get_settings(struct net_device *netdev,
3669 struct ethtool_cmd *cmd)
3670 {
3671 struct et131x_adapter *adapter = netdev_priv(netdev);
3672
3673 return phy_ethtool_gset(adapter->phydev, cmd);
3674 }
3675
3676 static int et131x_set_settings(struct net_device *netdev,
3677 struct ethtool_cmd *cmd)
3678 {
3679 struct et131x_adapter *adapter = netdev_priv(netdev);
3680
3681 return phy_ethtool_sset(adapter->phydev, cmd);
3682 }
3683
3684 static int et131x_get_regs_len(struct net_device *netdev)
3685 {
3686 #define ET131X_REGS_LEN 256
3687 return ET131X_REGS_LEN * sizeof(u32);
3688 }
3689
3690 static void et131x_get_regs(struct net_device *netdev,
3691 struct ethtool_regs *regs, void *regs_data)
3692 {
3693 struct et131x_adapter *adapter = netdev_priv(netdev);
3694 struct address_map __iomem *aregs = adapter->regs;
3695 u32 *regs_buff = regs_data;
3696 u32 num = 0;
3697
3698 memset(regs_data, 0, et131x_get_regs_len(netdev));
3699
3700 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3701 adapter->pdev->device;
3702
3703 /* PHY regs */
3704 et131x_mii_read(adapter, MII_BMCR, (u16 *)&regs_buff[num++]);
3705 et131x_mii_read(adapter, MII_BMSR, (u16 *)&regs_buff[num++]);
3706 et131x_mii_read(adapter, MII_PHYSID1, (u16 *)&regs_buff[num++]);
3707 et131x_mii_read(adapter, MII_PHYSID2, (u16 *)&regs_buff[num++]);
3708 et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)&regs_buff[num++]);
3709 et131x_mii_read(adapter, MII_LPA, (u16 *)&regs_buff[num++]);
3710 et131x_mii_read(adapter, MII_EXPANSION, (u16 *)&regs_buff[num++]);
3711 /* Autoneg next page transmit reg */
3712 et131x_mii_read(adapter, 0x07, (u16 *)&regs_buff[num++]);
3713 /* Link partner next page reg */
3714 et131x_mii_read(adapter, 0x08, (u16 *)&regs_buff[num++]);
3715 et131x_mii_read(adapter, MII_CTRL1000, (u16 *)&regs_buff[num++]);
3716 et131x_mii_read(adapter, MII_STAT1000, (u16 *)&regs_buff[num++]);
3717 et131x_mii_read(adapter, MII_ESTATUS, (u16 *)&regs_buff[num++]);
3718 et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)&regs_buff[num++]);
3719 et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)&regs_buff[num++]);
3720 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3721 (u16 *)&regs_buff[num++]);
3722 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
3723 (u16 *)&regs_buff[num++]);
3724 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
3725 (u16 *)&regs_buff[num++]);
3726 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
3727 (u16 *)&regs_buff[num++]);
3728 et131x_mii_read(adapter, PHY_CONFIG, (u16 *)&regs_buff[num++]);
3729 et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)&regs_buff[num++]);
3730 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)&regs_buff[num++]);
3731 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
3732 (u16 *)&regs_buff[num++]);
3733 et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)&regs_buff[num++]);
3734 et131x_mii_read(adapter, PHY_LED_1, (u16 *)&regs_buff[num++]);
3735 et131x_mii_read(adapter, PHY_LED_2, (u16 *)&regs_buff[num++]);
3736
3737 /* Global regs */
3738 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3739 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3740 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3741 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3742 regs_buff[num++] = readl(&aregs->global.pm_csr);
3743 regs_buff[num++] = adapter->stats.interrupt_status;
3744 regs_buff[num++] = readl(&aregs->global.int_mask);
3745 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3746 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3747 regs_buff[num++] = readl(&aregs->global.sw_reset);
3748 regs_buff[num++] = readl(&aregs->global.slv_timer);
3749 regs_buff[num++] = readl(&aregs->global.msi_config);
3750 regs_buff[num++] = readl(&aregs->global.loopback);
3751 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3752
3753 /* TXDMA regs */
3754 regs_buff[num++] = readl(&aregs->txdma.csr);
3755 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3756 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3757 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3758 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3759 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3760 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3761 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3762 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3763 regs_buff[num++] = readl(&aregs->txdma.service_request);
3764 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3765 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3766 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3767 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3768 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3769 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3770 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3771 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3772 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3773 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3774 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3775 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3776 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3777 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3778 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3779 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3780
3781 /* RXDMA regs */
3782 regs_buff[num++] = readl(&aregs->rxdma.csr);
3783 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3784 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3785 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3786 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3787 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3788 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3789 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3790 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3791 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3792 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3793 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3794 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3795 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3796 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3797 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3798 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3799 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3800 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3801 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3802 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3803 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3804 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3805 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3806 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3807 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3808 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3809 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3810 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3811 }
3812
3813 #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
3814 static void et131x_get_drvinfo(struct net_device *netdev,
3815 struct ethtool_drvinfo *info)
3816 {
3817 struct et131x_adapter *adapter = netdev_priv(netdev);
3818
3819 strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
3820 strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
3821 strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
3822 }
3823
3824 static struct ethtool_ops et131x_ethtool_ops = {
3825 .get_settings = et131x_get_settings,
3826 .set_settings = et131x_set_settings,
3827 .get_drvinfo = et131x_get_drvinfo,
3828 .get_regs_len = et131x_get_regs_len,
3829 .get_regs = et131x_get_regs,
3830 .get_link = ethtool_op_get_link,
3831 };
3832
3833 void et131x_set_ethtool_ops(struct net_device *netdev)
3834 {
3835 SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
3836 }
3837
3838 /* PCI functions */
3839
3840 /**
3841 * et131x_hwaddr_init - set up the MAC Address on the ET1310
3842 * @adapter: pointer to our private adapter structure
3843 */
3844 void et131x_hwaddr_init(struct et131x_adapter *adapter)
3845 {
3846 /* If have our default mac from init and no mac address from
3847 * EEPROM then we need to generate the last octet and set it on the
3848 * device
3849 */
3850 if (adapter->rom_addr[0] == 0x00 &&
3851 adapter->rom_addr[1] == 0x00 &&
3852 adapter->rom_addr[2] == 0x00 &&
3853 adapter->rom_addr[3] == 0x00 &&
3854 adapter->rom_addr[4] == 0x00 &&
3855 adapter->rom_addr[5] == 0x00) {
3856 /*
3857 * We need to randomly generate the last octet so we
3858 * decrease our chances of setting the mac address to
3859 * same as another one of our cards in the system
3860 */
3861 get_random_bytes(&adapter->addr[5], 1);
3862 /*
3863 * We have the default value in the register we are
3864 * working with so we need to copy the current
3865 * address into the permanent address
3866 */
3867 memcpy(adapter->rom_addr,
3868 adapter->addr, ETH_ALEN);
3869 } else {
3870 /* We do not have an override address, so set the
3871 * current address to the permanent address and add
3872 * it to the device
3873 */
3874 memcpy(adapter->addr,
3875 adapter->rom_addr, ETH_ALEN);
3876 }
3877 }
3878
3879 /**
3880 * et131x_pci_init - initial PCI setup
3881 * @adapter: pointer to our private adapter structure
3882 * @pdev: our PCI device
3883 *
3884 * Perform the initial setup of PCI registers and if possible initialise
3885 * the MAC address. At this point the I/O registers have yet to be mapped
3886 */
3887 static int et131x_pci_init(struct et131x_adapter *adapter,
3888 struct pci_dev *pdev)
3889 {
3890 int i;
3891 u8 max_payload;
3892 u8 read_size_reg;
3893
3894 if (et131x_init_eeprom(adapter) < 0)
3895 return -EIO;
3896
3897 /* Let's set up the PORT LOGIC Register. First we need to know what
3898 * the max_payload_size is
3899 */
3900 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
3901 dev_err(&pdev->dev,
3902 "Could not read PCI config space for Max Payload Size\n");
3903 return -EIO;
3904 }
3905
3906 /* Program the Ack/Nak latency and replay timers */
3907 max_payload &= 0x07; /* Only the lower 3 bits are valid */
3908
3909 if (max_payload < 2) {
3910 static const u16 acknak[2] = { 0x76, 0xD0 };
3911 static const u16 replay[2] = { 0x1E0, 0x2ED };
3912
3913 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3914 acknak[max_payload])) {
3915 dev_err(&pdev->dev,
3916 "Could not write PCI config space for ACK/NAK\n");
3917 return -EIO;
3918 }
3919 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3920 replay[max_payload])) {
3921 dev_err(&pdev->dev,
3922 "Could not write PCI config space for Replay Timer\n");
3923 return -EIO;
3924 }
3925 }
3926
3927 /* l0s and l1 latency timers. We are using default values.
3928 * Representing 001 for L0s and 010 for L1
3929 */
3930 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3931 dev_err(&pdev->dev,
3932 "Could not write PCI config space for Latency Timers\n");
3933 return -EIO;
3934 }
3935
3936 /* Change the max read size to 2k */
3937 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
3938 dev_err(&pdev->dev,
3939 "Could not read PCI config space for Max read size\n");
3940 return -EIO;
3941 }
3942
3943 read_size_reg &= 0x8f;
3944 read_size_reg |= 0x40;
3945
3946 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
3947 dev_err(&pdev->dev,
3948 "Could not write PCI config space for Max read size\n");
3949 return -EIO;
3950 }
3951
3952 /* Get MAC address from config space if an eeprom exists, otherwise
3953 * the MAC address there will not be valid
3954 */
3955 if (!adapter->has_eeprom) {
3956 et131x_hwaddr_init(adapter);
3957 return 0;
3958 }
3959
3960 for (i = 0; i < ETH_ALEN; i++) {
3961 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3962 adapter->rom_addr + i)) {
3963 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3964 return -EIO;
3965 }
3966 }
3967 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
3968 return 0;
3969 }
3970
3971 /**
3972 * et131x_error_timer_handler
3973 * @data: timer-specific variable; here a pointer to our adapter structure
3974 *
3975 * The routine called when the error timer expires, to track the number of
3976 * recurring errors.
3977 */
3978 void et131x_error_timer_handler(unsigned long data)
3979 {
3980 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3981 struct phy_device *phydev = adapter->phydev;
3982
3983 if (et1310_in_phy_coma(adapter)) {
3984 /* Bring the device immediately out of coma, to
3985 * prevent it from sleeping indefinitely, this
3986 * mechanism could be improved! */
3987 et1310_disable_phy_coma(adapter);
3988 adapter->boot_coma = 20;
3989 } else {
3990 et1310_update_macstat_host_counters(adapter);
3991 }
3992
3993 if (!phydev->link && adapter->boot_coma < 11)
3994 adapter->boot_coma++;
3995
3996 if (adapter->boot_coma == 10) {
3997 if (!phydev->link) {
3998 if (!et1310_in_phy_coma(adapter)) {
3999 /* NOTE - This was originally a 'sync with
4000 * interrupt'. How to do that under Linux?
4001 */
4002 et131x_enable_interrupts(adapter);
4003 et1310_enable_phy_coma(adapter);
4004 }
4005 }
4006 }
4007
4008 /* This is a periodic timer, so reschedule */
4009 mod_timer(&adapter->error_timer, jiffies +
4010 TX_ERROR_PERIOD * HZ / 1000);
4011 }
4012
4013 /**
4014 * et131x_configure_global_regs - configure JAGCore global regs
4015 * @adapter: pointer to our adapter structure
4016 *
4017 * Used to configure the global registers on the JAGCore
4018 */
4019 void et131x_configure_global_regs(struct et131x_adapter *adapter)
4020 {
4021 struct global_regs __iomem *regs = &adapter->regs->global;
4022
4023 writel(0, &regs->rxq_start_addr);
4024 writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
4025
4026 if (adapter->registry_jumbo_packet < 2048) {
4027 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
4028 * block of RAM that the driver can split between Tx
4029 * and Rx as it desires. Our default is to split it
4030 * 50/50:
4031 */
4032 writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
4033 writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
4034 } else if (adapter->registry_jumbo_packet < 8192) {
4035 /* For jumbo packets > 2k but < 8k, split 50-50. */
4036 writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
4037 writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
4038 } else {
4039 /* 9216 is the only packet size greater than 8k that
4040 * is available. The Tx buffer has to be big enough
4041 * for one whole packet on the Tx side. We'll make
4042 * the Tx 9408, and give the rest to Rx
4043 */
4044 writel(0x01b3, &regs->rxq_end_addr);
4045 writel(0x01b4, &regs->txq_start_addr);
4046 }
4047
4048 /* Initialize the loopback register. Disable all loopbacks. */
4049 writel(0, &regs->loopback);
4050
4051 /* MSI Register */
4052 writel(0, &regs->msi_config);
4053
4054 /* By default, disable the watchdog timer. It will be enabled when
4055 * a packet is queued.
4056 */
4057 writel(0, &regs->watchdog_timer);
4058 }
4059
4060 /**
4061 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
4062 * @adapter: pointer to our private adapter structure
4063 *
4064 * Returns 0 on success, errno on failure (as defined in errno.h)
4065 */
4066 void et131x_adapter_setup(struct et131x_adapter *adapter)
4067 {
4068 /* Configure the JAGCore */
4069 et131x_configure_global_regs(adapter);
4070
4071 et1310_config_mac_regs1(adapter);
4072
4073 /* Configure the MMC registers */
4074 /* All we need to do is initialize the Memory Control Register */
4075 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
4076
4077 et1310_config_rxmac_regs(adapter);
4078 et1310_config_txmac_regs(adapter);
4079
4080 et131x_config_rx_dma_regs(adapter);
4081 et131x_config_tx_dma_regs(adapter);
4082
4083 et1310_config_macstat_regs(adapter);
4084
4085 et1310_phy_power_down(adapter, 0);
4086 et131x_xcvr_init(adapter);
4087 }
4088
4089 /**
4090 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
4091 * @adapter: pointer to our private adapter structure
4092 */
4093 void et131x_soft_reset(struct et131x_adapter *adapter)
4094 {
4095 /* Disable MAC Core */
4096 writel(0xc00f0000, &adapter->regs->mac.cfg1);
4097
4098 /* Set everything to a reset value */
4099 writel(0x7F, &adapter->regs->global.sw_reset);
4100 writel(0x000f0000, &adapter->regs->mac.cfg1);
4101 writel(0x00000000, &adapter->regs->mac.cfg1);
4102 }
4103
4104 /**
4105 * et131x_align_allocated_memory - Align allocated memory on a given boundary
4106 * @adapter: pointer to our adapter structure
4107 * @phys_addr: pointer to Physical address
4108 * @offset: pointer to the offset variable
4109 * @mask: correct mask
4110 */
4111 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
4112 uint64_t *phys_addr,
4113 uint64_t *offset, uint64_t mask)
4114 {
4115 uint64_t new_addr;
4116
4117 *offset = 0;
4118
4119 new_addr = *phys_addr & ~mask;
4120
4121 if (new_addr != *phys_addr) {
4122 /* Move to next aligned block */
4123 new_addr += mask + 1;
4124 /* Return offset for adjusting virt addr */
4125 *offset = new_addr - *phys_addr;
4126 /* Return new physical address */
4127 *phys_addr = new_addr;
4128 }
4129 }
4130
4131 /**
4132 * et131x_adapter_memory_alloc
4133 * @adapter: pointer to our private adapter structure
4134 *
4135 * Returns 0 on success, errno on failure (as defined in errno.h).
4136 *
4137 * Allocate all the memory blocks for send, receive and others.
4138 */
4139 int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
4140 {
4141 int status;
4142
4143 /* Allocate memory for the Tx Ring */
4144 status = et131x_tx_dma_memory_alloc(adapter);
4145 if (status != 0) {
4146 dev_err(&adapter->pdev->dev,
4147 "et131x_tx_dma_memory_alloc FAILED\n");
4148 return status;
4149 }
4150 /* Receive buffer memory allocation */
4151 status = et131x_rx_dma_memory_alloc(adapter);
4152 if (status != 0) {
4153 dev_err(&adapter->pdev->dev,
4154 "et131x_rx_dma_memory_alloc FAILED\n");
4155 et131x_tx_dma_memory_free(adapter);
4156 return status;
4157 }
4158
4159 /* Init receive data structures */
4160 status = et131x_init_recv(adapter);
4161 if (status != 0) {
4162 dev_err(&adapter->pdev->dev,
4163 "et131x_init_recv FAILED\n");
4164 et131x_tx_dma_memory_free(adapter);
4165 et131x_rx_dma_memory_free(adapter);
4166 }
4167 return status;
4168 }
4169
4170 /**
4171 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
4172 * @adapter: pointer to our private adapter structure
4173 */
4174 void et131x_adapter_memory_free(struct et131x_adapter *adapter)
4175 {
4176 /* Free DMA memory */
4177 et131x_tx_dma_memory_free(adapter);
4178 et131x_rx_dma_memory_free(adapter);
4179 }
4180
4181 static void et131x_adjust_link(struct net_device *netdev)
4182 {
4183 struct et131x_adapter *adapter = netdev_priv(netdev);
4184 struct phy_device *phydev = adapter->phydev;
4185
4186 if (netif_carrier_ok(netdev)) {
4187 adapter->boot_coma = 20;
4188
4189 if (phydev && phydev->speed == SPEED_10) {
4190 /*
4191 * NOTE - Is there a way to query this without
4192 * TruePHY?
4193 * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
4194 * EMI_TRUEPHY_A13O) {
4195 */
4196 u16 register18;
4197
4198 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
4199 &register18);
4200 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4201 register18 | 0x4);
4202 et131x_mii_write(adapter, PHY_INDEX_REG,
4203 register18 | 0x8402);
4204 et131x_mii_write(adapter, PHY_DATA_REG,
4205 register18 | 511);
4206 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4207 register18);
4208 }
4209
4210 et1310_config_flow_control(adapter);
4211
4212 if (phydev && phydev->speed == SPEED_1000 &&
4213 adapter->registry_jumbo_packet > 2048) {
4214 u16 reg;
4215
4216 et131x_mii_read(adapter, PHY_CONFIG, &reg);
4217 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
4218 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
4219 et131x_mii_write(adapter, PHY_CONFIG, reg);
4220 }
4221
4222 et131x_set_rx_dma_timer(adapter);
4223 et1310_config_mac_regs2(adapter);
4224 }
4225
4226 if (phydev && phydev->link != adapter->link) {
4227 /*
4228 * Check to see if we are in coma mode and if
4229 * so, disable it because we will not be able
4230 * to read PHY values until we are out.
4231 */
4232 if (et1310_in_phy_coma(adapter))
4233 et1310_disable_phy_coma(adapter);
4234
4235 if (phydev->link) {
4236 adapter->boot_coma = 20;
4237 } else {
4238 dev_warn(&adapter->pdev->dev,
4239 "Link down - cable problem ?\n");
4240 adapter->boot_coma = 0;
4241
4242 if (phydev->speed == SPEED_10) {
4243 /* NOTE - Is there a way to query this without
4244 * TruePHY?
4245 * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
4246 * EMI_TRUEPHY_A13O)
4247 */
4248 u16 register18;
4249
4250 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
4251 &register18);
4252 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4253 register18 | 0x4);
4254 et131x_mii_write(adapter, PHY_INDEX_REG,
4255 register18 | 0x8402);
4256 et131x_mii_write(adapter, PHY_DATA_REG,
4257 register18 | 511);
4258 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4259 register18);
4260 }
4261
4262 /* Free the packets being actively sent & stopped */
4263 et131x_free_busy_send_packets(adapter);
4264
4265 /* Re-initialize the send structures */
4266 et131x_init_send(adapter);
4267
4268 /* Reset the RFD list and re-start RU */
4269 et131x_reset_recv(adapter);
4270
4271 /*
4272 * Bring the device back to the state it was during
4273 * init prior to autonegotiation being complete. This
4274 * way, when we get the auto-neg complete interrupt,
4275 * we can complete init by calling config_mac_regs2.
4276 */
4277 et131x_soft_reset(adapter);
4278
4279 /* Setup ET1310 as per the documentation */
4280 et131x_adapter_setup(adapter);
4281
4282 /* perform reset of tx/rx */
4283 et131x_disable_txrx(netdev);
4284 et131x_enable_txrx(netdev);
4285 }
4286
4287 adapter->link = phydev->link;
4288
4289 phy_print_status(phydev);
4290 }
4291 }
4292
4293 static int et131x_mii_probe(struct net_device *netdev)
4294 {
4295 struct et131x_adapter *adapter = netdev_priv(netdev);
4296 struct phy_device *phydev = NULL;
4297
4298 phydev = phy_find_first(adapter->mii_bus);
4299 if (!phydev) {
4300 dev_err(&adapter->pdev->dev, "no PHY found\n");
4301 return -ENODEV;
4302 }
4303
4304 phydev = phy_connect(netdev, dev_name(&phydev->dev),
4305 &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII);
4306
4307 if (IS_ERR(phydev)) {
4308 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
4309 return PTR_ERR(phydev);
4310 }
4311
4312 phydev->supported &= (SUPPORTED_10baseT_Half
4313 | SUPPORTED_10baseT_Full
4314 | SUPPORTED_100baseT_Half
4315 | SUPPORTED_100baseT_Full
4316 | SUPPORTED_Autoneg
4317 | SUPPORTED_MII
4318 | SUPPORTED_TP);
4319
4320 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
4321 phydev->supported |= SUPPORTED_1000baseT_Full;
4322
4323 phydev->advertising = phydev->supported;
4324 adapter->phydev = phydev;
4325
4326 dev_info(&adapter->pdev->dev, "attached PHY driver [%s] "
4327 "(mii_bus:phy_addr=%s)\n",
4328 phydev->drv->name, dev_name(&phydev->dev));
4329
4330 return 0;
4331 }
4332
4333 /**
4334 * et131x_adapter_init
4335 * @adapter: pointer to the private adapter struct
4336 * @pdev: pointer to the PCI device
4337 *
4338 * Initialize the data structures for the et131x_adapter object and link
4339 * them together with the platform provided device structures.
4340 */
4341 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
4342 struct pci_dev *pdev)
4343 {
4344 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
4345
4346 struct et131x_adapter *adapter;
4347
4348 /* Allocate private adapter struct and copy in relevant information */
4349 adapter = netdev_priv(netdev);
4350 adapter->pdev = pci_dev_get(pdev);
4351 adapter->netdev = netdev;
4352
4353 /* Do the same for the netdev struct */
4354 netdev->irq = pdev->irq;
4355 netdev->base_addr = pci_resource_start(pdev, 0);
4356
4357 /* Initialize spinlocks here */
4358 spin_lock_init(&adapter->lock);
4359 spin_lock_init(&adapter->tcb_send_qlock);
4360 spin_lock_init(&adapter->tcb_ready_qlock);
4361 spin_lock_init(&adapter->send_hw_lock);
4362 spin_lock_init(&adapter->rcv_lock);
4363 spin_lock_init(&adapter->rcv_pend_lock);
4364 spin_lock_init(&adapter->fbr_lock);
4365 spin_lock_init(&adapter->phy_lock);
4366
4367 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
4368
4369 /* Set the MAC address to a default */
4370 memcpy(adapter->addr, default_mac, ETH_ALEN);
4371
4372 return adapter;
4373 }
4374
4375 /**
4376 * et131x_pci_setup - Perform device initialization
4377 * @pdev: a pointer to the device's pci_dev structure
4378 * @ent: this device's entry in the pci_device_id table
4379 *
4380 * Returns 0 on success, errno on failure (as defined in errno.h)
4381 *
4382 * Registered in the pci_driver structure, this function is called when the
4383 * PCI subsystem finds a new PCI device which matches the information
4384 * contained in the pci_device_id table. This routine is the equivalent to
4385 * a device insertion routine.
4386 */
4387 static int __devinit et131x_pci_setup(struct pci_dev *pdev,
4388 const struct pci_device_id *ent)
4389 {
4390 int result;
4391 int pm_cap;
4392 struct net_device *netdev;
4393 struct et131x_adapter *adapter;
4394 int ii;
4395
4396 result = pci_enable_device(pdev);
4397 if (result) {
4398 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4399 goto err_out;
4400 }
4401
4402 /* Perform some basic PCI checks */
4403 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4404 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4405 goto err_disable;
4406 }
4407
4408 if (pci_request_regions(pdev, DRIVER_NAME)) {
4409 dev_err(&pdev->dev, "Can't get PCI resources\n");
4410 goto err_disable;
4411 }
4412
4413 pci_set_master(pdev);
4414
4415 /* Query PCI for Power Mgmt Capabilities
4416 *
4417 * NOTE: Now reading PowerMgmt in another location; is this still
4418 * needed?
4419 */
4420 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
4421 if (!pm_cap) {
4422 dev_err(&pdev->dev,
4423 "Cannot find Power Management capabilities\n");
4424 result = -EIO;
4425 goto err_release_res;
4426 }
4427
4428 /* Check the DMA addressing support of this device */
4429 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4430 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4431 if (result) {
4432 dev_err(&pdev->dev,
4433 "Unable to obtain 64 bit DMA for consistent allocations\n");
4434 goto err_release_res;
4435 }
4436 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
4437 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4438 if (result) {
4439 dev_err(&pdev->dev,
4440 "Unable to obtain 32 bit DMA for consistent allocations\n");
4441 goto err_release_res;
4442 }
4443 } else {
4444 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4445 result = -EIO;
4446 goto err_release_res;
4447 }
4448
4449 /* Allocate netdev and private adapter structs */
4450 netdev = et131x_device_alloc();
4451 if (!netdev) {
4452 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4453 result = -ENOMEM;
4454 goto err_release_res;
4455 }
4456
4457 SET_NETDEV_DEV(netdev, &pdev->dev);
4458 et131x_set_ethtool_ops(netdev);
4459
4460 adapter = et131x_adapter_init(netdev, pdev);
4461
4462 /* Initialise the PCI setup for the device */
4463 et131x_pci_init(adapter, pdev);
4464
4465 /* Map the bus-relative registers to system virtual memory */
4466 adapter->regs = pci_ioremap_bar(pdev, 0);
4467 if (!adapter->regs) {
4468 dev_err(&pdev->dev, "Cannot map device registers\n");
4469 result = -ENOMEM;
4470 goto err_free_dev;
4471 }
4472
4473 /* If Phy COMA mode was enabled when we went down, disable it here. */
4474 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
4475
4476 /* Issue a global reset to the et1310 */
4477 et131x_soft_reset(adapter);
4478
4479 /* Disable all interrupts (paranoid) */
4480 et131x_disable_interrupts(adapter);
4481
4482 /* Allocate DMA memory */
4483 result = et131x_adapter_memory_alloc(adapter);
4484 if (result) {
4485 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
4486 goto err_iounmap;
4487 }
4488
4489 /* Init send data structures */
4490 et131x_init_send(adapter);
4491
4492 /* Set up the task structure for the ISR's deferred handler */
4493 INIT_WORK(&adapter->task, et131x_isr_handler);
4494
4495 /* Copy address into the net_device struct */
4496 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4497
4498 /* Init variable for counting how long we do not have link status */
4499 adapter->boot_coma = 0;
4500 et1310_disable_phy_coma(adapter);
4501
4502 /* Setup the mii_bus struct */
4503 adapter->mii_bus = mdiobus_alloc();
4504 if (!adapter->mii_bus) {
4505 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4506 goto err_mem_free;
4507 }
4508
4509 adapter->mii_bus->name = "et131x_eth_mii";
4510 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4511 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4512 adapter->mii_bus->priv = netdev;
4513 adapter->mii_bus->read = et131x_mdio_read;
4514 adapter->mii_bus->write = et131x_mdio_write;
4515 adapter->mii_bus->reset = et131x_mdio_reset;
4516 adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
4517 if (!adapter->mii_bus->irq) {
4518 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
4519 goto err_mdio_free;
4520 }
4521
4522 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
4523 adapter->mii_bus->irq[ii] = PHY_POLL;
4524
4525 if (mdiobus_register(adapter->mii_bus)) {
4526 dev_err(&pdev->dev, "failed to register MII bus\n");
4527 mdiobus_free(adapter->mii_bus);
4528 goto err_mdio_free_irq;
4529 }
4530
4531 if (et131x_mii_probe(netdev)) {
4532 dev_err(&pdev->dev, "failed to probe MII bus\n");
4533 goto err_mdio_unregister;
4534 }
4535
4536 /* Setup et1310 as per the documentation */
4537 et131x_adapter_setup(adapter);
4538
4539 /* We can enable interrupts now
4540 *
4541 * NOTE - Because registration of interrupt handler is done in the
4542 * device's open(), defer enabling device interrupts to that
4543 * point
4544 */
4545
4546 /* Register the net_device struct with the Linux network layer */
4547 result = register_netdev(netdev);
4548 if (result != 0) {
4549 dev_err(&pdev->dev, "register_netdev() failed\n");
4550 goto err_mdio_unregister;
4551 }
4552
4553 /* Register the net_device struct with the PCI subsystem. Save a copy
4554 * of the PCI config space for this device now that the device has
4555 * been initialized, just in case it needs to be quickly restored.
4556 */
4557 pci_set_drvdata(pdev, netdev);
4558 pci_save_state(adapter->pdev);
4559
4560 return result;
4561
4562 err_mdio_unregister:
4563 mdiobus_unregister(adapter->mii_bus);
4564 err_mdio_free_irq:
4565 kfree(adapter->mii_bus->irq);
4566 err_mdio_free:
4567 mdiobus_free(adapter->mii_bus);
4568 err_mem_free:
4569 et131x_adapter_memory_free(adapter);
4570 err_iounmap:
4571 iounmap(adapter->regs);
4572 err_free_dev:
4573 pci_dev_put(pdev);
4574 free_netdev(netdev);
4575 err_release_res:
4576 pci_release_regions(pdev);
4577 err_disable:
4578 pci_disable_device(pdev);
4579 err_out:
4580 return result;
4581 }
4582
4583 /**
4584 * et131x_pci_remove
4585 * @pdev: a pointer to the device's pci_dev structure
4586 *
4587 * Registered in the pci_driver structure, this function is called when the
4588 * PCI subsystem detects that a PCI device which matches the information
4589 * contained in the pci_device_id table has been removed.
4590 */
4591 static void __devexit et131x_pci_remove(struct pci_dev *pdev)
4592 {
4593 struct net_device *netdev = pci_get_drvdata(pdev);
4594 struct et131x_adapter *adapter = netdev_priv(netdev);
4595
4596 unregister_netdev(netdev);
4597 mdiobus_unregister(adapter->mii_bus);
4598 kfree(adapter->mii_bus->irq);
4599 mdiobus_free(adapter->mii_bus);
4600
4601 et131x_adapter_memory_free(adapter);
4602 iounmap(adapter->regs);
4603 pci_dev_put(pdev);
4604
4605 free_netdev(netdev);
4606 pci_release_regions(pdev);
4607 pci_disable_device(pdev);
4608 }
4609
4610 #ifdef CONFIG_PM_SLEEP
4611 static int et131x_suspend(struct device *dev)
4612 {
4613 struct pci_dev *pdev = to_pci_dev(dev);
4614 struct net_device *netdev = pci_get_drvdata(pdev);
4615
4616 if (netif_running(netdev)) {
4617 netif_device_detach(netdev);
4618 et131x_down(netdev);
4619 pci_save_state(pdev);
4620 }
4621
4622 return 0;
4623 }
4624
4625 static int et131x_resume(struct device *dev)
4626 {
4627 struct pci_dev *pdev = to_pci_dev(dev);
4628 struct net_device *netdev = pci_get_drvdata(pdev);
4629
4630 if (netif_running(netdev)) {
4631 pci_restore_state(pdev);
4632 et131x_up(netdev);
4633 netif_device_attach(netdev);
4634 }
4635
4636 return 0;
4637 }
4638
4639 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
4640 #define ET131X_PM_OPS (&et131x_pm_ops)
4641 #else
4642 #define ET131X_PM_OPS NULL
4643 #endif
4644
4645 static struct pci_device_id et131x_pci_table[] __devinitdata = {
4646 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
4647 PCI_ANY_ID, 0, 0, 0UL},
4648 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
4649 PCI_ANY_ID, 0, 0, 0UL},
4650 {0,}
4651 };
4652
4653 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4654
4655 static struct pci_driver et131x_driver = {
4656 .name = DRIVER_NAME,
4657 .id_table = et131x_pci_table,
4658 .probe = et131x_pci_setup,
4659 .remove = __devexit_p(et131x_pci_remove),
4660 .driver.pm = ET131X_PM_OPS,
4661 };
4662
4663 /**
4664 * et131x_init_module - The "main" entry point called on driver initialization
4665 *
4666 * Returns 0 on success, errno on failure (as defined in errno.h)
4667 */
4668 static int __init et131x_init_module(void)
4669 {
4670 return pci_register_driver(&et131x_driver);
4671 }
4672
4673 /**
4674 * et131x_cleanup_module - The entry point called on driver cleanup
4675 */
4676 static void __exit et131x_cleanup_module(void)
4677 {
4678 pci_unregister_driver(&et131x_driver);
4679 }
4680
4681 module_init(et131x_init_module);
4682 module_exit(et131x_cleanup_module);
4683
4684 /* ISR functions */
4685
4686 /**
4687 * et131x_enable_interrupts - enable interrupt
4688 * @adapter: et131x device
4689 *
4690 * Enable the appropriate interrupts on the ET131x according to our
4691 * configuration
4692 */
4693 void et131x_enable_interrupts(struct et131x_adapter *adapter)
4694 {
4695 u32 mask;
4696
4697 /* Enable all global interrupts */
4698 if (adapter->flowcontrol == FLOW_TXONLY ||
4699 adapter->flowcontrol == FLOW_BOTH)
4700 mask = INT_MASK_ENABLE;
4701 else
4702 mask = INT_MASK_ENABLE_NO_FLOW;
4703
4704 writel(mask, &adapter->regs->global.int_mask);
4705 }
4706
4707 /**
4708 * et131x_disable_interrupts - interrupt disable
4709 * @adapter: et131x device
4710 *
4711 * Block all interrupts from the et131x device at the device itself
4712 */
4713 void et131x_disable_interrupts(struct et131x_adapter *adapter)
4714 {
4715 /* Disable all global interrupts */
4716 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
4717 }
4718
4719
4720 /**
4721 * et131x_isr - The Interrupt Service Routine for the driver.
4722 * @irq: the IRQ on which the interrupt was received.
4723 * @dev_id: device-specific info (here a pointer to a net_device struct)
4724 *
4725 * Returns a value indicating if the interrupt was handled.
4726 */
4727 irqreturn_t et131x_isr(int irq, void *dev_id)
4728 {
4729 bool handled = true;
4730 struct net_device *netdev = (struct net_device *)dev_id;
4731 struct et131x_adapter *adapter = NULL;
4732 u32 status;
4733
4734 if (!netif_device_present(netdev)) {
4735 handled = false;
4736 goto out;
4737 }
4738
4739 adapter = netdev_priv(netdev);
4740
4741 /* If the adapter is in low power state, then it should not
4742 * recognize any interrupt
4743 */
4744
4745 /* Disable Device Interrupts */
4746 et131x_disable_interrupts(adapter);
4747
4748 /* Get a copy of the value in the interrupt status register
4749 * so we can process the interrupting section
4750 */
4751 status = readl(&adapter->regs->global.int_status);
4752
4753 if (adapter->flowcontrol == FLOW_TXONLY ||
4754 adapter->flowcontrol == FLOW_BOTH) {
4755 status &= ~INT_MASK_ENABLE;
4756 } else {
4757 status &= ~INT_MASK_ENABLE_NO_FLOW;
4758 }
4759
4760 /* Make sure this is our interrupt */
4761 if (!status) {
4762 handled = false;
4763 et131x_enable_interrupts(adapter);
4764 goto out;
4765 }
4766
4767 /* This is our interrupt, so process accordingly */
4768
4769 if (status & ET_INTR_WATCHDOG) {
4770 struct tcb *tcb = adapter->tx_ring.send_head;
4771
4772 if (tcb)
4773 if (++tcb->stale > 1)
4774 status |= ET_INTR_TXDMA_ISR;
4775
4776 if (adapter->rx_ring.unfinished_receives)
4777 status |= ET_INTR_RXDMA_XFR_DONE;
4778 else if (tcb == NULL)
4779 writel(0, &adapter->regs->global.watchdog_timer);
4780
4781 status &= ~ET_INTR_WATCHDOG;
4782 }
4783
4784 if (status == 0) {
4785 /* This interrupt has in some way been "handled" by
4786 * the ISR. Either it was a spurious Rx interrupt, or
4787 * it was a Tx interrupt that has been filtered by
4788 * the ISR.
4789 */
4790 et131x_enable_interrupts(adapter);
4791 goto out;
4792 }
4793
4794 /* We need to save the interrupt status value for use in our
4795 * DPC. We will clear the software copy of that in that
4796 * routine.
4797 */
4798 adapter->stats.interrupt_status = status;
4799
4800 /* Schedule the ISR handler as a bottom-half task in the
4801 * kernel's tq_immediate queue, and mark the queue for
4802 * execution
4803 */
4804 schedule_work(&adapter->task);
4805 out:
4806 return IRQ_RETVAL(handled);
4807 }
4808
4809 /**
4810 * et131x_isr_handler - The ISR handler
4811 * @p_adapter, a pointer to the device's private adapter structure
4812 *
4813 * scheduled to run in a deferred context by the ISR. This is where the ISR's
4814 * work actually gets done.
4815 */
4816 void et131x_isr_handler(struct work_struct *work)
4817 {
4818 struct et131x_adapter *adapter =
4819 container_of(work, struct et131x_adapter, task);
4820 u32 status = adapter->stats.interrupt_status;
4821 struct address_map __iomem *iomem = adapter->regs;
4822
4823 /*
4824 * These first two are by far the most common. Once handled, we clear
4825 * their two bits in the status word. If the word is now zero, we
4826 * exit.
4827 */
4828 /* Handle all the completed Transmit interrupts */
4829 if (status & ET_INTR_TXDMA_ISR)
4830 et131x_handle_send_interrupt(adapter);
4831
4832 /* Handle all the completed Receives interrupts */
4833 if (status & ET_INTR_RXDMA_XFR_DONE)
4834 et131x_handle_recv_interrupt(adapter);
4835
4836 status &= 0xffffffd7;
4837
4838 if (status) {
4839 /* Handle the TXDMA Error interrupt */
4840 if (status & ET_INTR_TXDMA_ERR) {
4841 u32 txdma_err;
4842
4843 /* Following read also clears the register (COR) */
4844 txdma_err = readl(&iomem->txdma.tx_dma_error);
4845
4846 dev_warn(&adapter->pdev->dev,
4847 "TXDMA_ERR interrupt, error = %d\n",
4848 txdma_err);
4849 }
4850
4851 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
4852 if (status &
4853 (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
4854 /*
4855 * This indicates the number of unused buffers in
4856 * RXDMA free buffer ring 0 is <= the limit you
4857 * programmed. Free buffer resources need to be
4858 * returned. Free buffers are consumed as packets
4859 * are passed from the network to the host. The host
4860 * becomes aware of the packets from the contents of
4861 * the packet status ring. This ring is queried when
4862 * the packet done interrupt occurs. Packets are then
4863 * passed to the OS. When the OS is done with the
4864 * packets the resources can be returned to the
4865 * ET1310 for re-use. This interrupt is one method of
4866 * returning resources.
4867 */
4868
4869 /* If the user has flow control on, then we will
4870 * send a pause packet, otherwise just exit
4871 */
4872 if (adapter->flowcontrol == FLOW_TXONLY ||
4873 adapter->flowcontrol == FLOW_BOTH) {
4874 u32 pm_csr;
4875
4876 /* Tell the device to send a pause packet via
4877 * the back pressure register (bp req and
4878 * bp xon/xoff)
4879 */
4880 pm_csr = readl(&iomem->global.pm_csr);
4881 if (!et1310_in_phy_coma(adapter))
4882 writel(3, &iomem->txmac.bp_ctrl);
4883 }
4884 }
4885
4886 /* Handle Packet Status Ring Low Interrupt */
4887 if (status & ET_INTR_RXDMA_STAT_LOW) {
4888
4889 /*
4890 * Same idea as with the two Free Buffer Rings.
4891 * Packets going from the network to the host each
4892 * consume a free buffer resource and a packet status
4893 * resource. These resoures are passed to the OS.
4894 * When the OS is done with the resources, they need
4895 * to be returned to the ET1310. This is one method
4896 * of returning the resources.
4897 */
4898 }
4899
4900 /* Handle RXDMA Error Interrupt */
4901 if (status & ET_INTR_RXDMA_ERR) {
4902 /*
4903 * The rxdma_error interrupt is sent when a time-out
4904 * on a request issued by the JAGCore has occurred or
4905 * a completion is returned with an un-successful
4906 * status. In both cases the request is considered
4907 * complete. The JAGCore will automatically re-try the
4908 * request in question. Normally information on events
4909 * like these are sent to the host using the "Advanced
4910 * Error Reporting" capability. This interrupt is
4911 * another way of getting similar information. The
4912 * only thing required is to clear the interrupt by
4913 * reading the ISR in the global resources. The
4914 * JAGCore will do a re-try on the request. Normally
4915 * you should never see this interrupt. If you start
4916 * to see this interrupt occurring frequently then
4917 * something bad has occurred. A reset might be the
4918 * thing to do.
4919 */
4920 /* TRAP();*/
4921
4922 dev_warn(&adapter->pdev->dev,
4923 "RxDMA_ERR interrupt, error %x\n",
4924 readl(&iomem->txmac.tx_test));
4925 }
4926
4927 /* Handle the Wake on LAN Event */
4928 if (status & ET_INTR_WOL) {
4929 /*
4930 * This is a secondary interrupt for wake on LAN.
4931 * The driver should never see this, if it does,
4932 * something serious is wrong. We will TRAP the
4933 * message when we are in DBG mode, otherwise we
4934 * will ignore it.
4935 */
4936 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4937 }
4938
4939 /* Let's move on to the TxMac */
4940 if (status & ET_INTR_TXMAC) {
4941 u32 err = readl(&iomem->txmac.err);
4942
4943 /*
4944 * When any of the errors occur and TXMAC generates
4945 * an interrupt to report these errors, it usually
4946 * means that TXMAC has detected an error in the data
4947 * stream retrieved from the on-chip Tx Q. All of
4948 * these errors are catastrophic and TXMAC won't be
4949 * able to recover data when these errors occur. In
4950 * a nutshell, the whole Tx path will have to be reset
4951 * and re-configured afterwards.
4952 */
4953 dev_warn(&adapter->pdev->dev,
4954 "TXMAC interrupt, error 0x%08x\n",
4955 err);
4956
4957 /* If we are debugging, we want to see this error,
4958 * otherwise we just want the device to be reset and
4959 * continue
4960 */
4961 }
4962
4963 /* Handle RXMAC Interrupt */
4964 if (status & ET_INTR_RXMAC) {
4965 /*
4966 * These interrupts are catastrophic to the device,
4967 * what we need to do is disable the interrupts and
4968 * set the flag to cause us to reset so we can solve
4969 * this issue.
4970 */
4971 /* MP_SET_FLAG( adapter,
4972 fMP_ADAPTER_HARDWARE_ERROR); */
4973
4974 dev_warn(&adapter->pdev->dev,
4975 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4976 readl(&iomem->rxmac.err_reg));
4977
4978 dev_warn(&adapter->pdev->dev,
4979 "Enable 0x%08x, Diag 0x%08x\n",
4980 readl(&iomem->rxmac.ctrl),
4981 readl(&iomem->rxmac.rxq_diag));
4982
4983 /*
4984 * If we are debugging, we want to see this error,
4985 * otherwise we just want the device to be reset and
4986 * continue
4987 */
4988 }
4989
4990 /* Handle MAC_STAT Interrupt */
4991 if (status & ET_INTR_MAC_STAT) {
4992 /*
4993 * This means at least one of the un-masked counters
4994 * in the MAC_STAT block has rolled over. Use this
4995 * to maintain the top, software managed bits of the
4996 * counter(s).
4997 */
4998 et1310_handle_macstat_interrupt(adapter);
4999 }
5000
5001 /* Handle SLV Timeout Interrupt */
5002 if (status & ET_INTR_SLV_TIMEOUT) {
5003 /*
5004 * This means a timeout has occurred on a read or
5005 * write request to one of the JAGCore registers. The
5006 * Global Resources block has terminated the request
5007 * and on a read request, returned a "fake" value.
5008 * The most likely reasons are: Bad Address or the
5009 * addressed module is in a power-down state and
5010 * can't respond.
5011 */
5012 }
5013 }
5014 et131x_enable_interrupts(adapter);
5015 }
5016
5017 /* NETDEV functions */
5018
5019 /**
5020 * et131x_stats - Return the current device statistics.
5021 * @netdev: device whose stats are being queried
5022 *
5023 * Returns 0 on success, errno on failure (as defined in errno.h)
5024 */
5025 static struct net_device_stats *et131x_stats(struct net_device *netdev)
5026 {
5027 struct et131x_adapter *adapter = netdev_priv(netdev);
5028 struct net_device_stats *stats = &adapter->net_stats;
5029 struct ce_stats *devstat = &adapter->stats;
5030
5031 stats->rx_errors = devstat->rx_length_errs +
5032 devstat->rx_align_errs +
5033 devstat->rx_crc_errs +
5034 devstat->rx_code_violations +
5035 devstat->rx_other_errs;
5036 stats->tx_errors = devstat->tx_max_pkt_errs;
5037 stats->multicast = devstat->multicast_pkts_rcvd;
5038 stats->collisions = devstat->tx_collisions;
5039
5040 stats->rx_length_errors = devstat->rx_length_errs;
5041 stats->rx_over_errors = devstat->rx_overflows;
5042 stats->rx_crc_errors = devstat->rx_crc_errs;
5043
5044 /* NOTE: These stats don't have corresponding values in CE_STATS,
5045 * so we're going to have to update these directly from within the
5046 * TX/RX code
5047 */
5048 /* stats->rx_bytes = 20; devstat->; */
5049 /* stats->tx_bytes = 20; devstat->; */
5050 /* stats->rx_dropped = devstat->; */
5051 /* stats->tx_dropped = devstat->; */
5052
5053 /* NOTE: Not used, can't find analogous statistics */
5054 /* stats->rx_frame_errors = devstat->; */
5055 /* stats->rx_fifo_errors = devstat->; */
5056 /* stats->rx_missed_errors = devstat->; */
5057
5058 /* stats->tx_aborted_errors = devstat->; */
5059 /* stats->tx_carrier_errors = devstat->; */
5060 /* stats->tx_fifo_errors = devstat->; */
5061 /* stats->tx_heartbeat_errors = devstat->; */
5062 /* stats->tx_window_errors = devstat->; */
5063 return stats;
5064 }
5065
5066 /**
5067 * et131x_enable_txrx - Enable tx/rx queues
5068 * @netdev: device to be enabled
5069 */
5070 void et131x_enable_txrx(struct net_device *netdev)
5071 {
5072 struct et131x_adapter *adapter = netdev_priv(netdev);
5073
5074 /* Enable the Tx and Rx DMA engines (if not already enabled) */
5075 et131x_rx_dma_enable(adapter);
5076 et131x_tx_dma_enable(adapter);
5077
5078 /* Enable device interrupts */
5079 if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
5080 et131x_enable_interrupts(adapter);
5081
5082 /* We're ready to move some data, so start the queue */
5083 netif_start_queue(netdev);
5084 }
5085
5086 /**
5087 * et131x_disable_txrx - Disable tx/rx queues
5088 * @netdev: device to be disabled
5089 */
5090 void et131x_disable_txrx(struct net_device *netdev)
5091 {
5092 struct et131x_adapter *adapter = netdev_priv(netdev);
5093
5094 /* First thing is to stop the queue */
5095 netif_stop_queue(netdev);
5096
5097 /* Stop the Tx and Rx DMA engines */
5098 et131x_rx_dma_disable(adapter);
5099 et131x_tx_dma_disable(adapter);
5100
5101 /* Disable device interrupts */
5102 et131x_disable_interrupts(adapter);
5103 }
5104
5105 /**
5106 * et131x_up - Bring up a device for use.
5107 * @netdev: device to be opened
5108 */
5109 void et131x_up(struct net_device *netdev)
5110 {
5111 struct et131x_adapter *adapter = netdev_priv(netdev);
5112
5113 et131x_enable_txrx(netdev);
5114 phy_start(adapter->phydev);
5115 }
5116
5117 /**
5118 * et131x_open - Open the device for use.
5119 * @netdev: device to be opened
5120 *
5121 * Returns 0 on success, errno on failure (as defined in errno.h)
5122 */
5123 int et131x_open(struct net_device *netdev)
5124 {
5125 int result = 0;
5126 struct et131x_adapter *adapter = netdev_priv(netdev);
5127
5128 /* Start the timer to track NIC errors */
5129 init_timer(&adapter->error_timer);
5130 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
5131 adapter->error_timer.function = et131x_error_timer_handler;
5132 adapter->error_timer.data = (unsigned long)adapter;
5133 add_timer(&adapter->error_timer);
5134
5135 /* Register our IRQ */
5136 result = request_irq(netdev->irq, et131x_isr, IRQF_SHARED,
5137 netdev->name, netdev);
5138 if (result) {
5139 dev_err(&adapter->pdev->dev, "could not register IRQ %d\n",
5140 netdev->irq);
5141 return result;
5142 }
5143
5144 adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE;
5145
5146 et131x_up(netdev);
5147
5148 return result;
5149 }
5150
5151 /**
5152 * et131x_down - Bring down the device
5153 * @netdev: device to be broght down
5154 */
5155 void et131x_down(struct net_device *netdev)
5156 {
5157 struct et131x_adapter *adapter = netdev_priv(netdev);
5158
5159 /* Save the timestamp for the TX watchdog, prevent a timeout */
5160 netdev->trans_start = jiffies;
5161
5162 phy_stop(adapter->phydev);
5163 et131x_disable_txrx(netdev);
5164 }
5165
5166 /**
5167 * et131x_close - Close the device
5168 * @netdev: device to be closed
5169 *
5170 * Returns 0 on success, errno on failure (as defined in errno.h)
5171 */
5172 int et131x_close(struct net_device *netdev)
5173 {
5174 struct et131x_adapter *adapter = netdev_priv(netdev);
5175
5176 et131x_down(netdev);
5177
5178 adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE;
5179 free_irq(netdev->irq, netdev);
5180
5181 /* Stop the error timer */
5182 return del_timer_sync(&adapter->error_timer);
5183 }
5184
5185 /**
5186 * et131x_ioctl - The I/O Control handler for the driver
5187 * @netdev: device on which the control request is being made
5188 * @reqbuf: a pointer to the IOCTL request buffer
5189 * @cmd: the IOCTL command code
5190 *
5191 * Returns 0 on success, errno on failure (as defined in errno.h)
5192 */
5193 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
5194 {
5195 struct et131x_adapter *adapter = netdev_priv(netdev);
5196
5197 if (!adapter->phydev)
5198 return -EINVAL;
5199
5200 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
5201 }
5202
5203 /**
5204 * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
5205 * @adapter: pointer to our private adapter structure
5206 *
5207 * FIXME: lot of dups with MAC code
5208 *
5209 * Returns 0 on success, errno on failure
5210 */
5211 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
5212 {
5213 int status = 0;
5214 uint32_t filter = adapter->packet_filter;
5215 u32 ctrl;
5216 u32 pf_ctrl;
5217
5218 ctrl = readl(&adapter->regs->rxmac.ctrl);
5219 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
5220
5221 /* Default to disabled packet filtering. Enable it in the individual
5222 * case statements that require the device to filter something
5223 */
5224 ctrl |= 0x04;
5225
5226 /* Set us to be in promiscuous mode so we receive everything, this
5227 * is also true when we get a packet filter of 0
5228 */
5229 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
5230 pf_ctrl &= ~7; /* Clear filter bits */
5231 else {
5232 /*
5233 * Set us up with Multicast packet filtering. Three cases are
5234 * possible - (1) we have a multi-cast list, (2) we receive ALL
5235 * multicast entries or (3) we receive none.
5236 */
5237 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
5238 pf_ctrl &= ~2; /* Multicast filter bit */
5239 else {
5240 et1310_setup_device_for_multicast(adapter);
5241 pf_ctrl |= 2;
5242 ctrl &= ~0x04;
5243 }
5244
5245 /* Set us up with Unicast packet filtering */
5246 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
5247 et1310_setup_device_for_unicast(adapter);
5248 pf_ctrl |= 4;
5249 ctrl &= ~0x04;
5250 }
5251
5252 /* Set us up with Broadcast packet filtering */
5253 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
5254 pf_ctrl |= 1; /* Broadcast filter bit */
5255 ctrl &= ~0x04;
5256 } else
5257 pf_ctrl &= ~1;
5258
5259 /* Setup the receive mac configuration registers - Packet
5260 * Filter control + the enable / disable for packet filter
5261 * in the control reg.
5262 */
5263 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
5264 writel(ctrl, &adapter->regs->rxmac.ctrl);
5265 }
5266 return status;
5267 }
5268
5269 /**
5270 * et131x_multicast - The handler to configure multicasting on the interface
5271 * @netdev: a pointer to a net_device struct representing the device
5272 */
5273 static void et131x_multicast(struct net_device *netdev)
5274 {
5275 struct et131x_adapter *adapter = netdev_priv(netdev);
5276 uint32_t packet_filter = 0;
5277 unsigned long flags;
5278 struct netdev_hw_addr *ha;
5279 int i;
5280
5281 spin_lock_irqsave(&adapter->lock, flags);
5282
5283 /* Before we modify the platform-independent filter flags, store them
5284 * locally. This allows us to determine if anything's changed and if
5285 * we even need to bother the hardware
5286 */
5287 packet_filter = adapter->packet_filter;
5288
5289 /* Clear the 'multicast' flag locally; because we only have a single
5290 * flag to check multicast, and multiple multicast addresses can be
5291 * set, this is the easiest way to determine if more than one
5292 * multicast address is being set.
5293 */
5294 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
5295
5296 /* Check the net_device flags and set the device independent flags
5297 * accordingly
5298 */
5299
5300 if (netdev->flags & IFF_PROMISC)
5301 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
5302 else
5303 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
5304
5305 if (netdev->flags & IFF_ALLMULTI)
5306 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
5307
5308 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
5309 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
5310
5311 if (netdev_mc_count(netdev) < 1) {
5312 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
5313 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
5314 } else
5315 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
5316
5317 /* Set values in the private adapter struct */
5318 i = 0;
5319 netdev_for_each_mc_addr(ha, netdev) {
5320 if (i == NIC_MAX_MCAST_LIST)
5321 break;
5322 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
5323 }
5324 adapter->multicast_addr_count = i;
5325
5326 /* Are the new flags different from the previous ones? If not, then no
5327 * action is required
5328 *
5329 * NOTE - This block will always update the multicast_list with the
5330 * hardware, even if the addresses aren't the same.
5331 */
5332 if (packet_filter != adapter->packet_filter) {
5333 /* Call the device's filter function */
5334 et131x_set_packet_filter(adapter);
5335 }
5336 spin_unlock_irqrestore(&adapter->lock, flags);
5337 }
5338
5339 /**
5340 * et131x_tx - The handler to tx a packet on the device
5341 * @skb: data to be Tx'd
5342 * @netdev: device on which data is to be Tx'd
5343 *
5344 * Returns 0 on success, errno on failure (as defined in errno.h)
5345 */
5346 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
5347 {
5348 int status = 0;
5349
5350 /* Save the timestamp for the TX timeout watchdog */
5351 netdev->trans_start = jiffies;
5352
5353 /* Call the device-specific data Tx routine */
5354 status = et131x_send_packets(skb, netdev);
5355
5356 /* Check status and manage the netif queue if necessary */
5357 if (status != 0) {
5358 if (status == -ENOMEM) {
5359 /* Put the queue to sleep until resources are
5360 * available
5361 */
5362 netif_stop_queue(netdev);
5363 status = NETDEV_TX_BUSY;
5364 } else {
5365 status = NETDEV_TX_OK;
5366 }
5367 }
5368 return status;
5369 }
5370
5371 /**
5372 * et131x_tx_timeout - Timeout handler
5373 * @netdev: a pointer to a net_device struct representing the device
5374 *
5375 * The handler called when a Tx request times out. The timeout period is
5376 * specified by the 'tx_timeo" element in the net_device structure (see
5377 * et131x_alloc_device() to see how this value is set).
5378 */
5379 static void et131x_tx_timeout(struct net_device *netdev)
5380 {
5381 struct et131x_adapter *adapter = netdev_priv(netdev);
5382 struct tcb *tcb;
5383 unsigned long flags;
5384
5385 /* If the device is closed, ignore the timeout */
5386 if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE))
5387 return;
5388
5389 /* Any nonrecoverable hardware error?
5390 * Checks adapter->flags for any failure in phy reading
5391 */
5392 if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR)
5393 return;
5394
5395 /* Hardware failure? */
5396 if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) {
5397 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
5398 return;
5399 }
5400
5401 /* Is send stuck? */
5402 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
5403
5404 tcb = adapter->tx_ring.send_head;
5405
5406 if (tcb != NULL) {
5407 tcb->count++;
5408
5409 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
5410 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
5411 flags);
5412
5413 dev_warn(&adapter->pdev->dev,
5414 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
5415 tcb->index,
5416 tcb->flags);
5417
5418 adapter->net_stats.tx_errors++;
5419
5420 /* perform reset of tx/rx */
5421 et131x_disable_txrx(netdev);
5422 et131x_enable_txrx(netdev);
5423 return;
5424 }
5425 }
5426
5427 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
5428 }
5429
5430 /**
5431 * et131x_change_mtu - The handler called to change the MTU for the device
5432 * @netdev: device whose MTU is to be changed
5433 * @new_mtu: the desired MTU
5434 *
5435 * Returns 0 on success, errno on failure (as defined in errno.h)
5436 */
5437 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
5438 {
5439 int result = 0;
5440 struct et131x_adapter *adapter = netdev_priv(netdev);
5441
5442 /* Make sure the requested MTU is valid */
5443 if (new_mtu < 64 || new_mtu > 9216)
5444 return -EINVAL;
5445
5446 et131x_disable_txrx(netdev);
5447 et131x_handle_send_interrupt(adapter);
5448 et131x_handle_recv_interrupt(adapter);
5449
5450 /* Set the new MTU */
5451 netdev->mtu = new_mtu;
5452
5453 /* Free Rx DMA memory */
5454 et131x_adapter_memory_free(adapter);
5455
5456 /* Set the config parameter for Jumbo Packet support */
5457 adapter->registry_jumbo_packet = new_mtu + 14;
5458 et131x_soft_reset(adapter);
5459
5460 /* Alloc and init Rx DMA memory */
5461 result = et131x_adapter_memory_alloc(adapter);
5462 if (result != 0) {
5463 dev_warn(&adapter->pdev->dev,
5464 "Change MTU failed; couldn't re-alloc DMA memory\n");
5465 return result;
5466 }
5467
5468 et131x_init_send(adapter);
5469
5470 et131x_hwaddr_init(adapter);
5471 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
5472
5473 /* Init the device with the new settings */
5474 et131x_adapter_setup(adapter);
5475
5476 et131x_enable_txrx(netdev);
5477
5478 return result;
5479 }
5480
5481 /**
5482 * et131x_set_mac_addr - handler to change the MAC address for the device
5483 * @netdev: device whose MAC is to be changed
5484 * @new_mac: the desired MAC address
5485 *
5486 * Returns 0 on success, errno on failure (as defined in errno.h)
5487 *
5488 * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
5489 */
5490 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
5491 {
5492 int result = 0;
5493 struct et131x_adapter *adapter = netdev_priv(netdev);
5494 struct sockaddr *address = new_mac;
5495
5496 /* begin blux */
5497
5498 if (adapter == NULL)
5499 return -ENODEV;
5500
5501 /* Make sure the requested MAC is valid */
5502 if (!is_valid_ether_addr(address->sa_data))
5503 return -EINVAL;
5504
5505 et131x_disable_txrx(netdev);
5506 et131x_handle_send_interrupt(adapter);
5507 et131x_handle_recv_interrupt(adapter);
5508
5509 /* Set the new MAC */
5510 /* netdev->set_mac_address = &new_mac; */
5511
5512 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
5513
5514 printk(KERN_INFO "%s: Setting MAC address to %pM\n",
5515 netdev->name, netdev->dev_addr);
5516
5517 /* Free Rx DMA memory */
5518 et131x_adapter_memory_free(adapter);
5519
5520 et131x_soft_reset(adapter);
5521
5522 /* Alloc and init Rx DMA memory */
5523 result = et131x_adapter_memory_alloc(adapter);
5524 if (result != 0) {
5525 dev_err(&adapter->pdev->dev,
5526 "Change MAC failed; couldn't re-alloc DMA memory\n");
5527 return result;
5528 }
5529
5530 et131x_init_send(adapter);
5531
5532 et131x_hwaddr_init(adapter);
5533
5534 /* Init the device with the new settings */
5535 et131x_adapter_setup(adapter);
5536
5537 et131x_enable_txrx(netdev);
5538
5539 return result;
5540 }
5541
5542 static const struct net_device_ops et131x_netdev_ops = {
5543 .ndo_open = et131x_open,
5544 .ndo_stop = et131x_close,
5545 .ndo_start_xmit = et131x_tx,
5546 .ndo_set_multicast_list = et131x_multicast,
5547 .ndo_tx_timeout = et131x_tx_timeout,
5548 .ndo_change_mtu = et131x_change_mtu,
5549 .ndo_set_mac_address = et131x_set_mac_addr,
5550 .ndo_validate_addr = eth_validate_addr,
5551 .ndo_get_stats = et131x_stats,
5552 .ndo_do_ioctl = et131x_ioctl,
5553 };
5554
5555 /**
5556 * et131x_device_alloc
5557 *
5558 * Returns pointer to the allocated and initialized net_device struct for
5559 * this device.
5560 *
5561 * Create instances of net_device and wl_private for the new adapter and
5562 * register the device's entry points in the net_device structure.
5563 */
5564 struct net_device *et131x_device_alloc(void)
5565 {
5566 struct net_device *netdev;
5567
5568 /* Alloc net_device and adapter structs */
5569 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
5570
5571 if (!netdev) {
5572 printk(KERN_ERR "et131x: Alloc of net_device struct failed\n");
5573 return NULL;
5574 }
5575
5576 /*
5577 * Setup the function registration table (and other data) for a
5578 * net_device
5579 */
5580 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
5581 netdev->netdev_ops = &et131x_netdev_ops;
5582
5583 /* Poll? */
5584 /* netdev->poll = &et131x_poll; */
5585 /* netdev->poll_controller = &et131x_poll_controller; */
5586 return netdev;
5587 }
5588