arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <mach/hardware.h>
  18 #include <plat/mmc.h>
  19 #include <plat/omap-pm.h>
  20 #include <plat/mux.h>
  21 #include <plat/omap_device.h>
  22
  23 #include "mux.h"
  24 #include "hsmmc.h"
  25 #include "control.h"
  26
  27 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  28
  29 static u16 control_pbias_offset;
  30 static u16 control_devconf1_offset;
  31 static u16 control_mmc1;
  32
  33 #define HSMMC_NAME_LEN  9
  34
  35 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  36
  37 static int hsmmc_get_context_loss(struct device *dev)
  38 {
  39         return omap_pm_get_dev_context_loss_count(dev);
  40 }
  41
  42 #else
  43 #define hsmmc_get_context_loss NULL
  44 #endif
  45
  46 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  47                                   int power_on, int vdd)
  48 {
  49         u32 reg, prog_io;
  50         struct omap_mmc_platform_data *mmc = dev->platform_data;
  51
  52         if (mmc->slots[0].remux)
  53                 mmc->slots[0].remux(dev, slot, power_on);
  54
  55         /*
  56          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  57          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  58          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  59          *
  60          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  61          * is most naturally TWL VSIM; those pins also use PBIAS.
  62          *
  63          * FIXME handle VMMC1A as needed ...
  64          */
  65         if (power_on) {
  66                 if (cpu_is_omap2430()) {
  67                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  68                         if ((1 << vdd) >= MMC_VDD_30_31)
  69                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  70                         else
  71                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  72                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  73                 }
  74
  75                 if (mmc->slots[0].internal_clock) {
  76                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  77                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  78                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  79                 }
  80
  81                 reg = omap_ctrl_readl(control_pbias_offset);
  82                 if (cpu_is_omap3630()) {
  83                         /* Set MMC I/O to 52Mhz */
  84                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  85                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  86                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  87                 } else {
  88                         reg |= OMAP2_PBIASSPEEDCTRL0;
  89                 }
  90                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  91                 omap_ctrl_writel(reg, control_pbias_offset);
  92         } else {
  93                 reg = omap_ctrl_readl(control_pbias_offset);
  94                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  95                 omap_ctrl_writel(reg, control_pbias_offset);
  96         }
  97 }
  98
  99 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
 100                                  int power_on, int vdd)
 101 {
 102         u32 reg;
 103
 104         /* 100ms delay required for PBIAS configuration */
 105         msleep(100);
 106
 107         if (power_on) {
 108                 reg = omap_ctrl_readl(control_pbias_offset);
 109                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 110                 if ((1 << vdd) <= MMC_VDD_165_195)
 111                         reg &= ~OMAP2_PBIASLITEVMODE0;
 112                 else
 113                         reg |= OMAP2_PBIASLITEVMODE0;
 114                 omap_ctrl_writel(reg, control_pbias_offset);
 115         } else {
 116                 reg = omap_ctrl_readl(control_pbias_offset);
 117                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 118                         OMAP2_PBIASLITEVMODE0);
 119                 omap_ctrl_writel(reg, control_pbias_offset);
 120         }
 121 }
 122
 123 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 124                                   int power_on, int vdd)
 125 {
 126         u32 reg;
 127
 128         /*
 129          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 130          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 131          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 132          */
 133         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 134         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 135                 OMAP4_MMC1_PWRDNZ_MASK |
 136                 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
 137         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 138 }
 139
 140 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 141                                  int power_on, int vdd)
 142 {
 143         u32 reg;
 144         unsigned long timeout;
 145
 146         if (power_on) {
 147                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 148                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 149                 if ((1 << vdd) <= MMC_VDD_165_195)
 150                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 151                 else
 152                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 153                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 154                         OMAP4_MMC1_PWRDNZ_MASK);
 155                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 156
 157                 timeout = jiffies + msecs_to_jiffies(5);
 158                 do {
 159                         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 160                         if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
 161                                 break;
 162                         usleep_range(100, 200);
 163                 } while (!time_after(jiffies, timeout));
 164
 165                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 166                         pr_err("Pbias Voltage is not same as LDO\n");
 167                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 168                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
 169                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 170                 }
 171         }
 172 }
 173
 174 static void hsmmc23_before_set_reg(struct device *dev, int slot,
 175                                    int power_on, int vdd)
 176 {
 177         struct omap_mmc_platform_data *mmc = dev->platform_data;
 178
 179         if (mmc->slots[0].remux)
 180                 mmc->slots[0].remux(dev, slot, power_on);
 181
 182         if (power_on) {
 183                 /* Only MMC2 supports a CLKIN */
 184                 if (mmc->slots[0].internal_clock) {
 185                         u32 reg;
 186
 187                         reg = omap_ctrl_readl(control_devconf1_offset);
 188                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 189                         omap_ctrl_writel(reg, control_devconf1_offset);
 190                 }
 191         }
 192 }
 193
 194 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 195                                                         int vdd)
 196 {
 197         return 0;
 198 }
 199
 200 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 201                         int controller_nr)
 202 {
 203         if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
 204                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 205                                         OMAP_PIN_INPUT_PULLUP);
 206         if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
 207                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 208                                         OMAP_PIN_INPUT_PULLUP);
 209         if (cpu_is_omap34xx()) {
 210                 if (controller_nr == 0) {
 211                         omap_mux_init_signal("sdmmc1_clk",
 212                                 OMAP_PIN_INPUT_PULLUP);
 213                         omap_mux_init_signal("sdmmc1_cmd",
 214                                 OMAP_PIN_INPUT_PULLUP);
 215                         omap_mux_init_signal("sdmmc1_dat0",
 216                                 OMAP_PIN_INPUT_PULLUP);
 217                         if (mmc_controller->slots[0].caps &
 218                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 219                                 omap_mux_init_signal("sdmmc1_dat1",
 220                                         OMAP_PIN_INPUT_PULLUP);
 221                                 omap_mux_init_signal("sdmmc1_dat2",
 222                                         OMAP_PIN_INPUT_PULLUP);
 223                                 omap_mux_init_signal("sdmmc1_dat3",
 224                                         OMAP_PIN_INPUT_PULLUP);
 225                         }
 226                         if (mmc_controller->slots[0].caps &
 227                                                 MMC_CAP_8_BIT_DATA) {
 228                                 omap_mux_init_signal("sdmmc1_dat4",
 229                                         OMAP_PIN_INPUT_PULLUP);
 230                                 omap_mux_init_signal("sdmmc1_dat5",
 231                                         OMAP_PIN_INPUT_PULLUP);
 232                                 omap_mux_init_signal("sdmmc1_dat6",
 233                                         OMAP_PIN_INPUT_PULLUP);
 234                                 omap_mux_init_signal("sdmmc1_dat7",
 235                                         OMAP_PIN_INPUT_PULLUP);
 236                         }
 237                 }
 238                 if (controller_nr == 1) {
 239                         /* MMC2 */
 240                         omap_mux_init_signal("sdmmc2_clk",
 241                                 OMAP_PIN_INPUT_PULLUP);
 242                         omap_mux_init_signal("sdmmc2_cmd",
 243                                 OMAP_PIN_INPUT_PULLUP);
 244                         omap_mux_init_signal("sdmmc2_dat0",
 245                                 OMAP_PIN_INPUT_PULLUP);
 246
 247                         /*
 248                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 249                          * need to be muxed in the board-*.c files
 250                          */
 251                         if (mmc_controller->slots[0].caps &
 252                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 253                                 omap_mux_init_signal("sdmmc2_dat1",
 254                                         OMAP_PIN_INPUT_PULLUP);
 255                                 omap_mux_init_signal("sdmmc2_dat2",
 256                                         OMAP_PIN_INPUT_PULLUP);
 257                                 omap_mux_init_signal("sdmmc2_dat3",
 258                                         OMAP_PIN_INPUT_PULLUP);
 259                         }
 260                         if (mmc_controller->slots[0].caps &
 261                                                         MMC_CAP_8_BIT_DATA) {
 262                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 263                                         OMAP_PIN_INPUT_PULLUP);
 264                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 265                                         OMAP_PIN_INPUT_PULLUP);
 266                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 267                                         OMAP_PIN_INPUT_PULLUP);
 268                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 269                                         OMAP_PIN_INPUT_PULLUP);
 270                         }
 271                 }
 272
 273                 /*
 274                  * For MMC3 the pins need to be muxed in the board-*.c files
 275                  */
 276         }
 277 }
 278
 279 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 280                                         struct omap_mmc_platform_data *mmc)
 281 {
 282         char *hc_name;
 283
 284         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 285         if (!hc_name) {
 286                 pr_err("Cannot allocate memory for controller slot name\n");
 287                 kfree(hc_name);
 288                 return -ENOMEM;
 289         }
 290
 291         if (c->name)
 292                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 293         else
 294                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 295                                                                 c->mmc, 1);
 296         mmc->slots[0].name = hc_name;
 297         mmc->nr_slots = 1;
 298         mmc->slots[0].caps = c->caps;
 299         mmc->slots[0].internal_clock = !c->ext_clock;
 300         mmc->dma_mask = 0xffffffff;
 301         if (cpu_is_omap44xx())
 302                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 303         else
 304                 mmc->reg_offset = 0;
 305
 306         mmc->get_context_loss_count = hsmmc_get_context_loss;
 307
 308         mmc->slots[0].switch_pin = c->gpio_cd;
 309         mmc->slots[0].gpio_wp = c->gpio_wp;
 310
 311         mmc->slots[0].remux = c->remux;
 312         mmc->slots[0].init_card = c->init_card;
 313
 314         if (c->cover_only)
 315                 mmc->slots[0].cover = 1;
 316
 317         if (c->nonremovable)
 318                 mmc->slots[0].nonremovable = 1;
 319
 320         if (c->power_saving)
 321                 mmc->slots[0].power_saving = 1;
 322
 323         if (c->no_off)
 324                 mmc->slots[0].no_off = 1;
 325
 326         if (c->no_off_init)
 327                 mmc->slots[0].no_regulator_off_init = c->no_off_init;
 328
 329         if (c->vcc_aux_disable_is_sleep)
 330                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 331
 332         /*
 333          * NOTE:  MMC slots should have a Vcc regulator set up.
 334          * This may be from a TWL4030-family chip, another
 335          * controllable regulator, or a fixed supply.
 336          *
 337          * temporary HACK: ocr_mask instead of fixed supply
 338          */
 339         mmc->slots[0].ocr_mask = c->ocr_mask;
 340
 341         if (cpu_is_omap3517() || cpu_is_omap3505())
 342                 mmc->slots[0].set_power = nop_mmc_set_power;
 343         else
 344                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 345
 346         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 347                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 348
 349         switch (c->mmc) {
 350         case 1:
 351                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 352                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 353                         if (cpu_is_omap44xx()) {
 354                                 mmc->slots[0].before_set_reg =
 355                                                 omap4_hsmmc1_before_set_reg;
 356                                 mmc->slots[0].after_set_reg =
 357                                                 omap4_hsmmc1_after_set_reg;
 358                         } else {
 359                                 mmc->slots[0].before_set_reg =
 360                                                 omap_hsmmc1_before_set_reg;
 361                                 mmc->slots[0].after_set_reg =
 362                                                 omap_hsmmc1_after_set_reg;
 363                         }
 364                 }
 365
 366                 /* OMAP3630 HSMMC1 supports only 4-bit */
 367                 if (cpu_is_omap3630() &&
 368                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 369                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 370                         c->caps |= MMC_CAP_4_BIT_DATA;
 371                         mmc->slots[0].caps = c->caps;
 372                 }
 373                 break;
 374         case 2:
 375                 if (c->ext_clock)
 376                         c->transceiver = 1;
 377                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 378                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 379                         c->caps |= MMC_CAP_4_BIT_DATA;
 380                 }
 381                 /* FALLTHROUGH */
 382         case 3:
 383                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 384                         /* off-chip level shifting, or none */
 385                         mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
 386                         mmc->slots[0].after_set_reg = NULL;
 387                 }
 388                 break;
 389         case 4:
 390         case 5:
 391                 mmc->slots[0].before_set_reg = NULL;
 392                 mmc->slots[0].after_set_reg = NULL;
 393                 break;
 394         default:
 395                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 396                 kfree(hc_name);
 397                 return -ENODEV;
 398         }
 399         return 0;
 400 }
 401
 402 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 403
 404 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 405 {
 406         struct omap_hwmod *oh;
 407         struct platform_device *pdev;
 408         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 409         struct omap_mmc_platform_data *mmc_data;
 410         struct omap_mmc_dev_attr *mmc_dev_attr;
 411         char *name;
 412         int l;
 413
 414         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 415         if (!mmc_data) {
 416                 pr_err("Cannot allocate memory for mmc device!\n");
 417                 goto done;
 418         }
 419
 420         if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
 421                 pr_err("%s fails!\n", __func__);
 422                 goto done;
 423         }
 424         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 425
 426         name = "omap_hsmmc";
 427
 428         l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 429                      "mmc%d", ctrl_nr);
 430         WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 431              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 432         oh = omap_hwmod_lookup(oh_name);
 433         if (!oh) {
 434                 pr_err("Could not look up %s\n", oh_name);
 435                 kfree(mmc_data->slots[0].name);
 436                 goto done;
 437         }
 438
 439         if (oh->dev_attr != NULL) {
 440                 mmc_dev_attr = oh->dev_attr;
 441                 mmc_data->controller_flags = mmc_dev_attr->flags;
 442         }
 443
 444         pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
 445                 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
 446         if (IS_ERR(pdev)) {
 447                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
 448                 kfree(mmc_data->slots[0].name);
 449                 goto done;
 450         }
 451         /*
 452          * return device handle to board setup code
 453          * required to populate for regulator framework structure
 454          */
 455         hsmmcinfo->dev = &pdev->dev;
 456
 457 done:
 458         kfree(mmc_data);
 459 }
 460
 461 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 462 {
 463         u32 reg;
 464
 465         if (!cpu_is_omap44xx()) {
 466                 if (cpu_is_omap2430()) {
 467                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 468                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 469                 } else {
 470                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 471                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 472                 }
 473         } else {
 474                 control_pbias_offset =
 475                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 476                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 477                 reg = omap4_ctrl_pad_readl(control_mmc1);
 478                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 479                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 480                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 481                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 482                 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
 483                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 484                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 485                 omap4_ctrl_pad_writel(reg, control_mmc1);
 486         }
 487
 488         for (; controllers->mmc; controllers++)
 489                 omap_init_hsmmc(controllers, controllers->mmc);
 490
 491 }
 492
 493 #endif