?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
staging: brcm80211: assure common sources are truly common
[zen-stable.git] / drivers / scsi / lpfc / lpfc_hw.h
blob96ed3ba6ba952fd7db3d64bc355548797fc735ea
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2010 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
66
67
68 /* vendor ID used in SCSI netlink calls */
69 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
70
71 /* Common Transport structures and definitions */
72
73 union CtRevisionId {
74 /* Structure is in Big Endian format */
75 struct {
76 uint32_t Revision:8;
77 uint32_t InId:24;
78 } bits;
79 uint32_t word;
80 };
81
82 union CtCommandResponse {
83 /* Structure is in Big Endian format */
84 struct {
85 uint32_t CmdRsp:16;
86 uint32_t Size:16;
87 } bits;
88 uint32_t word;
89 };
90
91 #define FC4_FEATURE_INIT 0x2
92 #define FC4_FEATURE_TARGET 0x1
93
94 struct lpfc_sli_ct_request {
95 /* Structure is in Big Endian format */
96 union CtRevisionId RevisionId;
97 uint8_t FsType;
98 uint8_t FsSubType;
99 uint8_t Options;
100 uint8_t Rsrvd1;
101 union CtCommandResponse CommandResponse;
102 uint8_t Rsrvd2;
103 uint8_t ReasonCode;
104 uint8_t Explanation;
105 uint8_t VendorUnique;
106
107 union {
108 uint32_t PortID;
109 struct gid {
110 uint8_t PortType; /* for GID_PT requests */
111 uint8_t DomainScope;
112 uint8_t AreaScope;
113 uint8_t Fc4Type; /* for GID_FT requests */
114 } gid;
115 struct rft {
116 uint32_t PortId; /* For RFT_ID requests */
117
118 #ifdef __BIG_ENDIAN_BITFIELD
119 uint32_t rsvd0:16;
120 uint32_t rsvd1:7;
121 uint32_t fcpReg:1; /* Type 8 */
122 uint32_t rsvd2:2;
123 uint32_t ipReg:1; /* Type 5 */
124 uint32_t rsvd3:5;
125 #else /* __LITTLE_ENDIAN_BITFIELD */
126 uint32_t rsvd0:16;
127 uint32_t fcpReg:1; /* Type 8 */
128 uint32_t rsvd1:7;
129 uint32_t rsvd3:5;
130 uint32_t ipReg:1; /* Type 5 */
131 uint32_t rsvd2:2;
132 #endif
133
134 uint32_t rsvd[7];
135 } rft;
136 struct rnn {
137 uint32_t PortId; /* For RNN_ID requests */
138 uint8_t wwnn[8];
139 } rnn;
140 struct rsnn { /* For RSNN_ID requests */
141 uint8_t wwnn[8];
142 uint8_t len;
143 uint8_t symbname[255];
144 } rsnn;
145 struct da_id { /* For DA_ID requests */
146 uint32_t port_id;
147 } da_id;
148 struct rspn { /* For RSPN_ID requests */
149 uint32_t PortId;
150 uint8_t len;
151 uint8_t symbname[255];
152 } rspn;
153 struct gff {
154 uint32_t PortId;
155 } gff;
156 struct gff_acc {
157 uint8_t fbits[128];
158 } gff_acc;
159 #define FCP_TYPE_FEATURE_OFFSET 7
160 struct rff {
161 uint32_t PortId;
162 uint8_t reserved[2];
163 uint8_t fbits;
164 uint8_t type_code; /* type=8 for FCP */
165 } rff;
166 } un;
167 };
168
169 #define SLI_CT_REVISION 1
170 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 sizeof(struct gid))
172 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct gff))
174 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct rft))
176 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rff))
178 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rnn))
180 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rsnn))
182 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 sizeof(struct da_id))
184 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
185 sizeof(struct rspn))
186
187 /*
188 * FsType Definitions
189 */
190
191 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
192 #define SLI_CT_TIME_SERVICE 0xFB
193 #define SLI_CT_DIRECTORY_SERVICE 0xFC
194 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
195
196 /*
197 * Directory Service Subtypes
198 */
199
200 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
201
202 /*
203 * Response Codes
204 */
205
206 #define SLI_CT_RESPONSE_FS_RJT 0x8001
207 #define SLI_CT_RESPONSE_FS_ACC 0x8002
208
209 /*
210 * Reason Codes
211 */
212
213 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
214 #define SLI_CT_INVALID_COMMAND 0x01
215 #define SLI_CT_INVALID_VERSION 0x02
216 #define SLI_CT_LOGICAL_ERROR 0x03
217 #define SLI_CT_INVALID_IU_SIZE 0x04
218 #define SLI_CT_LOGICAL_BUSY 0x05
219 #define SLI_CT_PROTOCOL_ERROR 0x07
220 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
221 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
222 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
223 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
224 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
225 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
226 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
227 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
228 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
229 #define SLI_CT_VENDOR_UNIQUE 0xff
230
231 /*
232 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
233 */
234
235 #define SLI_CT_NO_PORT_ID 0x01
236 #define SLI_CT_NO_PORT_NAME 0x02
237 #define SLI_CT_NO_NODE_NAME 0x03
238 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
239 #define SLI_CT_NO_IP_ADDRESS 0x05
240 #define SLI_CT_NO_IPA 0x06
241 #define SLI_CT_NO_FC4_TYPES 0x07
242 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
243 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
244 #define SLI_CT_NO_PORT_TYPE 0x0A
245 #define SLI_CT_ACCESS_DENIED 0x10
246 #define SLI_CT_INVALID_PORT_ID 0x11
247 #define SLI_CT_DATABASE_EMPTY 0x12
248
249 /*
250 * Name Server Command Codes
251 */
252
253 #define SLI_CTNS_GA_NXT 0x0100
254 #define SLI_CTNS_GPN_ID 0x0112
255 #define SLI_CTNS_GNN_ID 0x0113
256 #define SLI_CTNS_GCS_ID 0x0114
257 #define SLI_CTNS_GFT_ID 0x0117
258 #define SLI_CTNS_GSPN_ID 0x0118
259 #define SLI_CTNS_GPT_ID 0x011A
260 #define SLI_CTNS_GFF_ID 0x011F
261 #define SLI_CTNS_GID_PN 0x0121
262 #define SLI_CTNS_GID_NN 0x0131
263 #define SLI_CTNS_GIP_NN 0x0135
264 #define SLI_CTNS_GIPA_NN 0x0136
265 #define SLI_CTNS_GSNN_NN 0x0139
266 #define SLI_CTNS_GNN_IP 0x0153
267 #define SLI_CTNS_GIPA_IP 0x0156
268 #define SLI_CTNS_GID_FT 0x0171
269 #define SLI_CTNS_GID_PT 0x01A1
270 #define SLI_CTNS_RPN_ID 0x0212
271 #define SLI_CTNS_RNN_ID 0x0213
272 #define SLI_CTNS_RCS_ID 0x0214
273 #define SLI_CTNS_RFT_ID 0x0217
274 #define SLI_CTNS_RSPN_ID 0x0218
275 #define SLI_CTNS_RPT_ID 0x021A
276 #define SLI_CTNS_RFF_ID 0x021F
277 #define SLI_CTNS_RIP_NN 0x0235
278 #define SLI_CTNS_RIPA_NN 0x0236
279 #define SLI_CTNS_RSNN_NN 0x0239
280 #define SLI_CTNS_DA_ID 0x0300
281
282 /*
283 * Port Types
284 */
285
286 #define SLI_CTPT_N_PORT 0x01
287 #define SLI_CTPT_NL_PORT 0x02
288 #define SLI_CTPT_FNL_PORT 0x03
289 #define SLI_CTPT_IP 0x04
290 #define SLI_CTPT_FCP 0x08
291 #define SLI_CTPT_NX_PORT 0x7F
292 #define SLI_CTPT_F_PORT 0x81
293 #define SLI_CTPT_FL_PORT 0x82
294 #define SLI_CTPT_E_PORT 0x84
295
296 #define SLI_CT_LAST_ENTRY 0x80000000
297
298 /* Fibre Channel Service Parameter definitions */
299
300 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
301 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
302 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
303 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
304
305 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
306 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
307 #define FC_PH3 0x20 /* FC-PH-3 version */
308
309 #define FF_FRAME_SIZE 2048
310
311 struct lpfc_name {
312 union {
313 struct {
314 #ifdef __BIG_ENDIAN_BITFIELD
315 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
317 8:11 of IEEE ext */
318 #else /* __LITTLE_ENDIAN_BITFIELD */
319 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
320 8:11 of IEEE ext */
321 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
322 #endif
323
324 #define NAME_IEEE 0x1 /* IEEE name - nameType */
325 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
326 #define NAME_FC_TYPE 0x3 /* FC native name type */
327 #define NAME_IP_TYPE 0x4 /* IP address */
328 #define NAME_CCITT_TYPE 0xC
329 #define NAME_CCITT_GR_TYPE 0xE
330 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
331 extended Lsb */
332 uint8_t IEEE[6]; /* FC IEEE address */
333 } s;
334 uint8_t wwn[8];
335 } u;
336 };
337
338 struct csp {
339 uint8_t fcphHigh; /* FC Word 0, byte 0 */
340 uint8_t fcphLow;
341 uint8_t bbCreditMsb;
342 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
343
344 #ifdef __BIG_ENDIAN_BITFIELD
345 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
346 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
347 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
348 uint16_t fPort:1; /* FC Word 1, bit 28 */
349 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
350 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
351 uint16_t multicast:1; /* FC Word 1, bit 25 */
352 uint16_t broadcast:1; /* FC Word 1, bit 24 */
353
354 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
355 uint16_t simplex:1; /* FC Word 1, bit 22 */
356 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
357 uint16_t dhd:1; /* FC Word 1, bit 18 */
358 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
359 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
360 #else /* __LITTLE_ENDIAN_BITFIELD */
361 uint16_t broadcast:1; /* FC Word 1, bit 24 */
362 uint16_t multicast:1; /* FC Word 1, bit 25 */
363 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
364 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
365 uint16_t fPort:1; /* FC Word 1, bit 28 */
366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
367 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
368 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
369
370 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
371 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
372 uint16_t dhd:1; /* FC Word 1, bit 18 */
373 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
374 uint16_t simplex:1; /* FC Word 1, bit 22 */
375 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
376 #endif
377
378 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
379 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
380 union {
381 struct {
382 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
383
384 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
385 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
386
387 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
388 } nPort;
389 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
390 } w2;
391
392 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
393 };
394
395 struct class_parms {
396 #ifdef __BIG_ENDIAN_BITFIELD
397 uint8_t classValid:1; /* FC Word 0, bit 31 */
398 uint8_t intermix:1; /* FC Word 0, bit 30 */
399 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
400 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
401 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
402 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
403 #else /* __LITTLE_ENDIAN_BITFIELD */
404 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
405 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
406 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
407 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
408 uint8_t intermix:1; /* FC Word 0, bit 30 */
409 uint8_t classValid:1; /* FC Word 0, bit 31 */
410
411 #endif
412
413 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
414
415 #ifdef __BIG_ENDIAN_BITFIELD
416 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
417 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
418 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
419 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
420 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
421 #else /* __LITTLE_ENDIAN_BITFIELD */
422 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
423 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
424 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
425 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
426 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
427 #endif
428
429 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
430
431 #ifdef __BIG_ENDIAN_BITFIELD
432 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
433 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
435 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
437 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
438 #else /* __LITTLE_ENDIAN_BITFIELD */
439 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
440 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
441 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
442 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
443 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
444 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
445 #endif
446
447 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
448 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
449 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
450
451 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
452 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
453 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
454 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
455
456 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
457 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
458 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
459 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
460 };
461
462 struct serv_parm { /* Structure is in Big Endian format */
463 struct csp cmn;
464 struct lpfc_name portName;
465 struct lpfc_name nodeName;
466 struct class_parms cls1;
467 struct class_parms cls2;
468 struct class_parms cls3;
469 struct class_parms cls4;
470 uint8_t vendorVersion[16];
471 };
472
473 /*
474 * Virtual Fabric Tagging Header
475 */
476 struct fc_vft_header {
477 uint32_t word0;
478 #define fc_vft_hdr_r_ctl_SHIFT 24
479 #define fc_vft_hdr_r_ctl_MASK 0xFF
480 #define fc_vft_hdr_r_ctl_WORD word0
481 #define fc_vft_hdr_ver_SHIFT 22
482 #define fc_vft_hdr_ver_MASK 0x3
483 #define fc_vft_hdr_ver_WORD word0
484 #define fc_vft_hdr_type_SHIFT 18
485 #define fc_vft_hdr_type_MASK 0xF
486 #define fc_vft_hdr_type_WORD word0
487 #define fc_vft_hdr_e_SHIFT 16
488 #define fc_vft_hdr_e_MASK 0x1
489 #define fc_vft_hdr_e_WORD word0
490 #define fc_vft_hdr_priority_SHIFT 13
491 #define fc_vft_hdr_priority_MASK 0x7
492 #define fc_vft_hdr_priority_WORD word0
493 #define fc_vft_hdr_vf_id_SHIFT 1
494 #define fc_vft_hdr_vf_id_MASK 0xFFF
495 #define fc_vft_hdr_vf_id_WORD word0
496 uint32_t word1;
497 #define fc_vft_hdr_hopct_SHIFT 24
498 #define fc_vft_hdr_hopct_MASK 0xFF
499 #define fc_vft_hdr_hopct_WORD word1
500 };
501
502 /*
503 * Extended Link Service LS_COMMAND codes (Payload Word 0)
504 */
505 #ifdef __BIG_ENDIAN_BITFIELD
506 #define ELS_CMD_MASK 0xffff0000
507 #define ELS_RSP_MASK 0xff000000
508 #define ELS_CMD_LS_RJT 0x01000000
509 #define ELS_CMD_ACC 0x02000000
510 #define ELS_CMD_PLOGI 0x03000000
511 #define ELS_CMD_FLOGI 0x04000000
512 #define ELS_CMD_LOGO 0x05000000
513 #define ELS_CMD_ABTX 0x06000000
514 #define ELS_CMD_RCS 0x07000000
515 #define ELS_CMD_RES 0x08000000
516 #define ELS_CMD_RSS 0x09000000
517 #define ELS_CMD_RSI 0x0A000000
518 #define ELS_CMD_ESTS 0x0B000000
519 #define ELS_CMD_ESTC 0x0C000000
520 #define ELS_CMD_ADVC 0x0D000000
521 #define ELS_CMD_RTV 0x0E000000
522 #define ELS_CMD_RLS 0x0F000000
523 #define ELS_CMD_ECHO 0x10000000
524 #define ELS_CMD_TEST 0x11000000
525 #define ELS_CMD_RRQ 0x12000000
526 #define ELS_CMD_PRLI 0x20100014
527 #define ELS_CMD_PRLO 0x21100014
528 #define ELS_CMD_PRLO_ACC 0x02100014
529 #define ELS_CMD_PDISC 0x50000000
530 #define ELS_CMD_FDISC 0x51000000
531 #define ELS_CMD_ADISC 0x52000000
532 #define ELS_CMD_FARP 0x54000000
533 #define ELS_CMD_FARPR 0x55000000
534 #define ELS_CMD_RPS 0x56000000
535 #define ELS_CMD_RPL 0x57000000
536 #define ELS_CMD_FAN 0x60000000
537 #define ELS_CMD_RSCN 0x61040000
538 #define ELS_CMD_SCR 0x62000000
539 #define ELS_CMD_RNID 0x78000000
540 #define ELS_CMD_LIRR 0x7A000000
541 #else /* __LITTLE_ENDIAN_BITFIELD */
542 #define ELS_CMD_MASK 0xffff
543 #define ELS_RSP_MASK 0xff
544 #define ELS_CMD_LS_RJT 0x01
545 #define ELS_CMD_ACC 0x02
546 #define ELS_CMD_PLOGI 0x03
547 #define ELS_CMD_FLOGI 0x04
548 #define ELS_CMD_LOGO 0x05
549 #define ELS_CMD_ABTX 0x06
550 #define ELS_CMD_RCS 0x07
551 #define ELS_CMD_RES 0x08
552 #define ELS_CMD_RSS 0x09
553 #define ELS_CMD_RSI 0x0A
554 #define ELS_CMD_ESTS 0x0B
555 #define ELS_CMD_ESTC 0x0C
556 #define ELS_CMD_ADVC 0x0D
557 #define ELS_CMD_RTV 0x0E
558 #define ELS_CMD_RLS 0x0F
559 #define ELS_CMD_ECHO 0x10
560 #define ELS_CMD_TEST 0x11
561 #define ELS_CMD_RRQ 0x12
562 #define ELS_CMD_PRLI 0x14001020
563 #define ELS_CMD_PRLO 0x14001021
564 #define ELS_CMD_PRLO_ACC 0x14001002
565 #define ELS_CMD_PDISC 0x50
566 #define ELS_CMD_FDISC 0x51
567 #define ELS_CMD_ADISC 0x52
568 #define ELS_CMD_FARP 0x54
569 #define ELS_CMD_FARPR 0x55
570 #define ELS_CMD_RPS 0x56
571 #define ELS_CMD_RPL 0x57
572 #define ELS_CMD_FAN 0x60
573 #define ELS_CMD_RSCN 0x0461
574 #define ELS_CMD_SCR 0x62
575 #define ELS_CMD_RNID 0x78
576 #define ELS_CMD_LIRR 0x7A
577 #endif
578
579 /*
580 * LS_RJT Payload Definition
581 */
582
583 struct ls_rjt { /* Structure is in Big Endian format */
584 union {
585 uint32_t lsRjtError;
586 struct {
587 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
588
589 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
590 /* LS_RJT reason codes */
591 #define LSRJT_INVALID_CMD 0x01
592 #define LSRJT_LOGICAL_ERR 0x03
593 #define LSRJT_LOGICAL_BSY 0x05
594 #define LSRJT_PROTOCOL_ERR 0x07
595 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
596 #define LSRJT_CMD_UNSUPPORTED 0x0B
597 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
598
599 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
600 /* LS_RJT reason explanation */
601 #define LSEXP_NOTHING_MORE 0x00
602 #define LSEXP_SPARM_OPTIONS 0x01
603 #define LSEXP_SPARM_ICTL 0x03
604 #define LSEXP_SPARM_RCTL 0x05
605 #define LSEXP_SPARM_RCV_SIZE 0x07
606 #define LSEXP_SPARM_CONCUR_SEQ 0x09
607 #define LSEXP_SPARM_CREDIT 0x0B
608 #define LSEXP_INVALID_PNAME 0x0D
609 #define LSEXP_INVALID_NNAME 0x0E
610 #define LSEXP_INVALID_CSP 0x0F
611 #define LSEXP_INVALID_ASSOC_HDR 0x11
612 #define LSEXP_ASSOC_HDR_REQ 0x13
613 #define LSEXP_INVALID_O_SID 0x15
614 #define LSEXP_INVALID_OX_RX 0x17
615 #define LSEXP_CMD_IN_PROGRESS 0x19
616 #define LSEXP_PORT_LOGIN_REQ 0x1E
617 #define LSEXP_INVALID_NPORT_ID 0x1F
618 #define LSEXP_INVALID_SEQ_ID 0x21
619 #define LSEXP_INVALID_XCHG 0x23
620 #define LSEXP_INACTIVE_XCHG 0x25
621 #define LSEXP_RQ_REQUIRED 0x27
622 #define LSEXP_OUT_OF_RESOURCE 0x29
623 #define LSEXP_CANT_GIVE_DATA 0x2A
624 #define LSEXP_REQ_UNSUPPORTED 0x2C
625 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
626 } b;
627 } un;
628 };
629
630 /*
631 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
632 */
633
634 typedef struct _LOGO { /* Structure is in Big Endian format */
635 union {
636 uint32_t nPortId32; /* Access nPortId as a word */
637 struct {
638 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
639 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
640 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
641 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
642 } b;
643 } un;
644 struct lpfc_name portName; /* N_port name field */
645 } LOGO;
646
647 /*
648 * FCP Login (PRLI Request / ACC) Payload Definition
649 */
650
651 #define PRLX_PAGE_LEN 0x10
652 #define TPRLO_PAGE_LEN 0x14
653
654 typedef struct _PRLI { /* Structure is in Big Endian format */
655 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
656
657 #define PRLI_FCP_TYPE 0x08
658 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
659
660 #ifdef __BIG_ENDIAN_BITFIELD
661 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
662 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
663 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
664
665 /* ACC = imagePairEstablished */
666 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
667 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
668 #else /* __LITTLE_ENDIAN_BITFIELD */
669 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
670 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
671 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
672 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
673 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
674 /* ACC = imagePairEstablished */
675 #endif
676
677 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
678 #define PRLI_NO_RESOURCES 0x2
679 #define PRLI_INIT_INCOMPLETE 0x3
680 #define PRLI_NO_SUCH_PA 0x4
681 #define PRLI_PREDEF_CONFIG 0x5
682 #define PRLI_PARTIAL_SUCCESS 0x6
683 #define PRLI_INVALID_PAGE_CNT 0x7
684 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
685
686 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
687
688 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
689
690 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
691 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
692
693 #ifdef __BIG_ENDIAN_BITFIELD
694 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
695 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
696 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
697 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
698 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
699 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
700 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
701 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
702 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
703 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
704 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
705 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
706 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
707 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
708 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
709 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
710 #else /* __LITTLE_ENDIAN_BITFIELD */
711 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
712 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
713 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
714 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
715 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
716 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
717 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
718 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
719 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
720 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
721 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
722 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
723 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
724 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
725 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
726 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
727 #endif
728 } PRLI;
729
730 /*
731 * FCP Logout (PRLO Request / ACC) Payload Definition
732 */
733
734 typedef struct _PRLO { /* Structure is in Big Endian format */
735 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
736
737 #define PRLO_FCP_TYPE 0x08
738 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
739
740 #ifdef __BIG_ENDIAN_BITFIELD
741 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
742 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
743 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
744 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
745 #else /* __LITTLE_ENDIAN_BITFIELD */
746 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
747 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
748 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
749 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
750 #endif
751
752 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
753 #define PRLO_NO_SUCH_IMAGE 0x4
754 #define PRLO_INVALID_PAGE_CNT 0x7
755
756 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
757
758 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
759
760 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
761
762 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
763 } PRLO;
764
765 typedef struct _ADISC { /* Structure is in Big Endian format */
766 uint32_t hardAL_PA;
767 struct lpfc_name portName;
768 struct lpfc_name nodeName;
769 uint32_t DID;
770 } ADISC;
771
772 typedef struct _FARP { /* Structure is in Big Endian format */
773 uint32_t Mflags:8;
774 uint32_t Odid:24;
775 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
776 action */
777 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
778 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
779 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
780 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
781 supported */
782 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
783 supported */
784 uint32_t Rflags:8;
785 uint32_t Rdid:24;
786 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
787 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
788 struct lpfc_name OportName;
789 struct lpfc_name OnodeName;
790 struct lpfc_name RportName;
791 struct lpfc_name RnodeName;
792 uint8_t Oipaddr[16];
793 uint8_t Ripaddr[16];
794 } FARP;
795
796 typedef struct _FAN { /* Structure is in Big Endian format */
797 uint32_t Fdid;
798 struct lpfc_name FportName;
799 struct lpfc_name FnodeName;
800 } FAN;
801
802 typedef struct _SCR { /* Structure is in Big Endian format */
803 uint8_t resvd1;
804 uint8_t resvd2;
805 uint8_t resvd3;
806 uint8_t Function;
807 #define SCR_FUNC_FABRIC 0x01
808 #define SCR_FUNC_NPORT 0x02
809 #define SCR_FUNC_FULL 0x03
810 #define SCR_CLEAR 0xff
811 } SCR;
812
813 typedef struct _RNID_TOP_DISC {
814 struct lpfc_name portName;
815 uint8_t resvd[8];
816 uint32_t unitType;
817 #define RNID_HBA 0x7
818 #define RNID_HOST 0xa
819 #define RNID_DRIVER 0xd
820 uint32_t physPort;
821 uint32_t attachedNodes;
822 uint16_t ipVersion;
823 #define RNID_IPV4 0x1
824 #define RNID_IPV6 0x2
825 uint16_t UDPport;
826 uint8_t ipAddr[16];
827 uint16_t resvd1;
828 uint16_t flags;
829 #define RNID_TD_SUPPORT 0x1
830 #define RNID_LP_VALID 0x2
831 } RNID_TOP_DISC;
832
833 typedef struct _RNID { /* Structure is in Big Endian format */
834 uint8_t Format;
835 #define RNID_TOPOLOGY_DISC 0xdf
836 uint8_t CommonLen;
837 uint8_t resvd1;
838 uint8_t SpecificLen;
839 struct lpfc_name portName;
840 struct lpfc_name nodeName;
841 union {
842 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
843 } un;
844 } RNID;
845
846 typedef struct _RPS { /* Structure is in Big Endian format */
847 union {
848 uint32_t portNum;
849 struct lpfc_name portName;
850 } un;
851 } RPS;
852
853 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
854 uint16_t rsvd1;
855 uint16_t portStatus;
856 uint32_t linkFailureCnt;
857 uint32_t lossSyncCnt;
858 uint32_t lossSignalCnt;
859 uint32_t primSeqErrCnt;
860 uint32_t invalidXmitWord;
861 uint32_t crcCnt;
862 } RPS_RSP;
863
864 struct RLS { /* Structure is in Big Endian format */
865 uint32_t rls;
866 #define rls_rsvd_SHIFT 24
867 #define rls_rsvd_MASK 0x000000ff
868 #define rls_rsvd_WORD rls
869 #define rls_did_SHIFT 0
870 #define rls_did_MASK 0x00ffffff
871 #define rls_did_WORD rls
872 };
873
874 struct RLS_RSP { /* Structure is in Big Endian format */
875 uint32_t linkFailureCnt;
876 uint32_t lossSyncCnt;
877 uint32_t lossSignalCnt;
878 uint32_t primSeqErrCnt;
879 uint32_t invalidXmitWord;
880 uint32_t crcCnt;
881 };
882
883 struct RRQ { /* Structure is in Big Endian format */
884 uint32_t rrq;
885 #define rrq_rsvd_SHIFT 24
886 #define rrq_rsvd_MASK 0x000000ff
887 #define rrq_rsvd_WORD rrq
888 #define rrq_did_SHIFT 0
889 #define rrq_did_MASK 0x00ffffff
890 #define rrq_did_WORD rrq
891 uint32_t rrq_exchg;
892 #define rrq_oxid_SHIFT 16
893 #define rrq_oxid_MASK 0xffff
894 #define rrq_oxid_WORD rrq_exchg
895 #define rrq_rxid_SHIFT 0
896 #define rrq_rxid_MASK 0xffff
897 #define rrq_rxid_WORD rrq_exchg
898 };
899
900
901 struct RTV_RSP { /* Structure is in Big Endian format */
902 uint32_t ratov;
903 uint32_t edtov;
904 uint32_t qtov;
905 #define qtov_rsvd0_SHIFT 28
906 #define qtov_rsvd0_MASK 0x0000000f
907 #define qtov_rsvd0_WORD qtov /* reserved */
908 #define qtov_edtovres_SHIFT 27
909 #define qtov_edtovres_MASK 0x00000001
910 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
911 #define qtov__rsvd1_SHIFT 19
912 #define qtov_rsvd1_MASK 0x0000003f
913 #define qtov_rsvd1_WORD qtov /* reserved */
914 #define qtov_rttov_SHIFT 18
915 #define qtov_rttov_MASK 0x00000001
916 #define qtov_rttov_WORD qtov /* R_T_TOV value */
917 #define qtov_rsvd2_SHIFT 0
918 #define qtov_rsvd2_MASK 0x0003ffff
919 #define qtov_rsvd2_WORD qtov /* reserved */
920 };
921
922
923 typedef struct _RPL { /* Structure is in Big Endian format */
924 uint32_t maxsize;
925 uint32_t index;
926 } RPL;
927
928 typedef struct _PORT_NUM_BLK {
929 uint32_t portNum;
930 uint32_t portID;
931 struct lpfc_name portName;
932 } PORT_NUM_BLK;
933
934 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
935 uint32_t listLen;
936 uint32_t index;
937 PORT_NUM_BLK port_num_blk;
938 } RPL_RSP;
939
940 /* This is used for RSCN command */
941 typedef struct _D_ID { /* Structure is in Big Endian format */
942 union {
943 uint32_t word;
944 struct {
945 #ifdef __BIG_ENDIAN_BITFIELD
946 uint8_t resv;
947 uint8_t domain;
948 uint8_t area;
949 uint8_t id;
950 #else /* __LITTLE_ENDIAN_BITFIELD */
951 uint8_t id;
952 uint8_t area;
953 uint8_t domain;
954 uint8_t resv;
955 #endif
956 } b;
957 } un;
958 } D_ID;
959
960 #define RSCN_ADDRESS_FORMAT_PORT 0x0
961 #define RSCN_ADDRESS_FORMAT_AREA 0x1
962 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
963 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
964 #define RSCN_ADDRESS_FORMAT_MASK 0x3
965
966 /*
967 * Structure to define all ELS Payload types
968 */
969
970 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
971 uint8_t elsCode; /* FC Word 0, bit 24:31 */
972 uint8_t elsByte1;
973 uint8_t elsByte2;
974 uint8_t elsByte3;
975 union {
976 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
977 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
978 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
979 PRLI prli; /* Payload for PRLI/ACC */
980 PRLO prlo; /* Payload for PRLO/ACC */
981 ADISC adisc; /* Payload for ADISC/ACC */
982 FARP farp; /* Payload for FARP/ACC */
983 FAN fan; /* Payload for FAN */
984 SCR scr; /* Payload for SCR/ACC */
985 RNID rnid; /* Payload for RNID */
986 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
987 } un;
988 } ELS_PKT;
989
990 /*
991 * FDMI
992 * HBA MAnagement Operations Command Codes
993 */
994 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
995 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
996 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
997 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
998 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
999 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
1000 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1001 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1002 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1003 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1004
1005 /*
1006 * Management Service Subtypes
1007 */
1008 #define SLI_CT_FDMI_Subtypes 0x10
1009
1010 /*
1011 * HBA Management Service Reject Code
1012 */
1013 #define REJECT_CODE 0x9 /* Unable to perform command request */
1014
1015 /*
1016 * HBA Management Service Reject Reason Code
1017 * Please refer to the Reason Codes above
1018 */
1019
1020 /*
1021 * HBA Attribute Types
1022 */
1023 #define NODE_NAME 0x1
1024 #define MANUFACTURER 0x2
1025 #define SERIAL_NUMBER 0x3
1026 #define MODEL 0x4
1027 #define MODEL_DESCRIPTION 0x5
1028 #define HARDWARE_VERSION 0x6
1029 #define DRIVER_VERSION 0x7
1030 #define OPTION_ROM_VERSION 0x8
1031 #define FIRMWARE_VERSION 0x9
1032 #define OS_NAME_VERSION 0xa
1033 #define MAX_CT_PAYLOAD_LEN 0xb
1034
1035 /*
1036 * Port Attrubute Types
1037 */
1038 #define SUPPORTED_FC4_TYPES 0x1
1039 #define SUPPORTED_SPEED 0x2
1040 #define PORT_SPEED 0x3
1041 #define MAX_FRAME_SIZE 0x4
1042 #define OS_DEVICE_NAME 0x5
1043 #define HOST_NAME 0x6
1044
1045 union AttributesDef {
1046 /* Structure is in Big Endian format */
1047 struct {
1048 uint32_t AttrType:16;
1049 uint32_t AttrLen:16;
1050 } bits;
1051 uint32_t word;
1052 };
1053
1054
1055 /*
1056 * HBA Attribute Entry (8 - 260 bytes)
1057 */
1058 typedef struct {
1059 union AttributesDef ad;
1060 union {
1061 uint32_t VendorSpecific;
1062 uint8_t Manufacturer[64];
1063 uint8_t SerialNumber[64];
1064 uint8_t Model[256];
1065 uint8_t ModelDescription[256];
1066 uint8_t HardwareVersion[256];
1067 uint8_t DriverVersion[256];
1068 uint8_t OptionROMVersion[256];
1069 uint8_t FirmwareVersion[256];
1070 struct lpfc_name NodeName;
1071 uint8_t SupportFC4Types[32];
1072 uint32_t SupportSpeed;
1073 uint32_t PortSpeed;
1074 uint32_t MaxFrameSize;
1075 uint8_t OsDeviceName[256];
1076 uint8_t OsNameVersion[256];
1077 uint32_t MaxCTPayloadLen;
1078 uint8_t HostName[256];
1079 } un;
1080 } ATTRIBUTE_ENTRY;
1081
1082 /*
1083 * HBA Attribute Block
1084 */
1085 typedef struct {
1086 uint32_t EntryCnt; /* Number of HBA attribute entries */
1087 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1088 } ATTRIBUTE_BLOCK;
1089
1090 /*
1091 * Port Entry
1092 */
1093 typedef struct {
1094 struct lpfc_name PortName;
1095 } PORT_ENTRY;
1096
1097 /*
1098 * HBA Identifier
1099 */
1100 typedef struct {
1101 struct lpfc_name PortName;
1102 } HBA_IDENTIFIER;
1103
1104 /*
1105 * Registered Port List Format
1106 */
1107 typedef struct {
1108 uint32_t EntryCnt;
1109 PORT_ENTRY pe; /* Variable-length array */
1110 } REG_PORT_LIST;
1111
1112 /*
1113 * Register HBA(RHBA)
1114 */
1115 typedef struct {
1116 HBA_IDENTIFIER hi;
1117 REG_PORT_LIST rpl; /* variable-length array */
1118 /* ATTRIBUTE_BLOCK ab; */
1119 } REG_HBA;
1120
1121 /*
1122 * Register HBA Attributes (RHAT)
1123 */
1124 typedef struct {
1125 struct lpfc_name HBA_PortName;
1126 ATTRIBUTE_BLOCK ab;
1127 } REG_HBA_ATTRIBUTE;
1128
1129 /*
1130 * Register Port Attributes (RPA)
1131 */
1132 typedef struct {
1133 struct lpfc_name PortName;
1134 ATTRIBUTE_BLOCK ab;
1135 } REG_PORT_ATTRIBUTE;
1136
1137 /*
1138 * Get Registered HBA List (GRHL) Accept Payload Format
1139 */
1140 typedef struct {
1141 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1142 struct lpfc_name HBA_PortName; /* Variable-length array */
1143 } GRHL_ACC_PAYLOAD;
1144
1145 /*
1146 * Get Registered Port List (GRPL) Accept Payload Format
1147 */
1148 typedef struct {
1149 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1150 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1151 } GRPL_ACC_PAYLOAD;
1152
1153 /*
1154 * Get Port Attributes (GPAT) Accept Payload Format
1155 */
1156
1157 typedef struct {
1158 ATTRIBUTE_BLOCK pab;
1159 } GPAT_ACC_PAYLOAD;
1160
1161
1162 /*
1163 * Begin HBA configuration parameters.
1164 * The PCI configuration register BAR assignments are:
1165 * BAR0, offset 0x10 - SLIM base memory address
1166 * BAR1, offset 0x14 - SLIM base memory high address
1167 * BAR2, offset 0x18 - REGISTER base memory address
1168 * BAR3, offset 0x1c - REGISTER base memory high address
1169 * BAR4, offset 0x20 - BIU I/O registers
1170 * BAR5, offset 0x24 - REGISTER base io high address
1171 */
1172
1173 /* Number of rings currently used and available. */
1174 #define MAX_CONFIGURED_RINGS 3
1175 #define MAX_RINGS 4
1176
1177 /* IOCB / Mailbox is owned by FireFly */
1178 #define OWN_CHIP 1
1179
1180 /* IOCB / Mailbox is owned by Host */
1181 #define OWN_HOST 0
1182
1183 /* Number of 4-byte words in an IOCB. */
1184 #define IOCB_WORD_SZ 8
1185
1186 /* network headers for Dfctl field */
1187 #define FC_NET_HDR 0x20
1188
1189 /* Start FireFly Register definitions */
1190 #define PCI_VENDOR_ID_EMULEX 0x10df
1191 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1192 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1193 #define PCI_DEVICE_ID_BALIUS 0xe131
1194 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1195 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1196 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1197 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1198 #define PCI_DEVICE_ID_SAT_MID 0xf015
1199 #define PCI_DEVICE_ID_RFLY 0xf095
1200 #define PCI_DEVICE_ID_PFLY 0xf098
1201 #define PCI_DEVICE_ID_LP101 0xf0a1
1202 #define PCI_DEVICE_ID_TFLY 0xf0a5
1203 #define PCI_DEVICE_ID_BSMB 0xf0d1
1204 #define PCI_DEVICE_ID_BMID 0xf0d5
1205 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1206 #define PCI_DEVICE_ID_ZMID 0xf0e5
1207 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1208 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1209 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1210 #define PCI_DEVICE_ID_SAT 0xf100
1211 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1212 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1213 #define PCI_DEVICE_ID_FALCON 0xf180
1214 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1215 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1216 #define PCI_DEVICE_ID_CENTAUR 0xf900
1217 #define PCI_DEVICE_ID_PEGASUS 0xf980
1218 #define PCI_DEVICE_ID_THOR 0xfa00
1219 #define PCI_DEVICE_ID_VIPER 0xfb00
1220 #define PCI_DEVICE_ID_LP10000S 0xfc00
1221 #define PCI_DEVICE_ID_LP11000S 0xfc10
1222 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1223 #define PCI_DEVICE_ID_SAT_S 0xfc40
1224 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1225 #define PCI_DEVICE_ID_HELIOS 0xfd00
1226 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1227 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1228 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1229 #define PCI_DEVICE_ID_HORNET 0xfe05
1230 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1231 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1232 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1233 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1234 #define PCI_DEVICE_ID_TOMCAT 0x0714
1235
1236 #define JEDEC_ID_ADDRESS 0x0080001c
1237 #define FIREFLY_JEDEC_ID 0x1ACC
1238 #define SUPERFLY_JEDEC_ID 0x0020
1239 #define DRAGONFLY_JEDEC_ID 0x0021
1240 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1241 #define CENTAUR_2G_JEDEC_ID 0x0026
1242 #define CENTAUR_1G_JEDEC_ID 0x0028
1243 #define PEGASUS_ORION_JEDEC_ID 0x0036
1244 #define PEGASUS_JEDEC_ID 0x0038
1245 #define THOR_JEDEC_ID 0x0012
1246 #define HELIOS_JEDEC_ID 0x0364
1247 #define ZEPHYR_JEDEC_ID 0x0577
1248 #define VIPER_JEDEC_ID 0x4838
1249 #define SATURN_JEDEC_ID 0x1004
1250 #define HORNET_JDEC_ID 0x2057706D
1251
1252 #define JEDEC_ID_MASK 0x0FFFF000
1253 #define JEDEC_ID_SHIFT 12
1254 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1255
1256 typedef struct { /* FireFly BIU registers */
1257 uint32_t hostAtt; /* See definitions for Host Attention
1258 register */
1259 uint32_t chipAtt; /* See definitions for Chip Attention
1260 register */
1261 uint32_t hostStatus; /* See definitions for Host Status register */
1262 uint32_t hostControl; /* See definitions for Host Control register */
1263 uint32_t buiConfig; /* See definitions for BIU configuration
1264 register */
1265 } FF_REGS;
1266
1267 /* IO Register size in bytes */
1268 #define FF_REG_AREA_SIZE 256
1269
1270 /* Host Attention Register */
1271
1272 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1273
1274 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1275 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1276 #define HA_R0ATT 0x00000008 /* Bit 3 */
1277 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1278 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1279 #define HA_R1ATT 0x00000080 /* Bit 7 */
1280 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1281 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1282 #define HA_R2ATT 0x00000800 /* Bit 11 */
1283 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1284 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1285 #define HA_R3ATT 0x00008000 /* Bit 15 */
1286 #define HA_LATT 0x20000000 /* Bit 29 */
1287 #define HA_MBATT 0x40000000 /* Bit 30 */
1288 #define HA_ERATT 0x80000000 /* Bit 31 */
1289
1290 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1291 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1292 #define HA_RXATT 0x00000008 /* Bit 3 */
1293 #define HA_RXMASK 0x0000000f
1294
1295 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1296 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1297 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1298 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1299
1300 #define HA_R0_POS 3
1301 #define HA_R1_POS 7
1302 #define HA_R2_POS 11
1303 #define HA_R3_POS 15
1304 #define HA_LE_POS 29
1305 #define HA_MB_POS 30
1306 #define HA_ER_POS 31
1307 /* Chip Attention Register */
1308
1309 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1310
1311 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1312 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1313 #define CA_R0ATT 0x00000008 /* Bit 3 */
1314 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1315 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1316 #define CA_R1ATT 0x00000080 /* Bit 7 */
1317 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1318 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1319 #define CA_R2ATT 0x00000800 /* Bit 11 */
1320 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1321 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1322 #define CA_R3ATT 0x00008000 /* Bit 15 */
1323 #define CA_MBATT 0x40000000 /* Bit 30 */
1324
1325 /* Host Status Register */
1326
1327 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1328
1329 #define HS_MBRDY 0x00400000 /* Bit 22 */
1330 #define HS_FFRDY 0x00800000 /* Bit 23 */
1331 #define HS_FFER8 0x01000000 /* Bit 24 */
1332 #define HS_FFER7 0x02000000 /* Bit 25 */
1333 #define HS_FFER6 0x04000000 /* Bit 26 */
1334 #define HS_FFER5 0x08000000 /* Bit 27 */
1335 #define HS_FFER4 0x10000000 /* Bit 28 */
1336 #define HS_FFER3 0x20000000 /* Bit 29 */
1337 #define HS_FFER2 0x40000000 /* Bit 30 */
1338 #define HS_FFER1 0x80000000 /* Bit 31 */
1339 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1340 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1341
1342 /* Host Control Register */
1343
1344 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1345
1346 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1347 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1348 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1349 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1350 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1351 #define HC_INITHBI 0x02000000 /* Bit 25 */
1352 #define HC_INITMB 0x04000000 /* Bit 26 */
1353 #define HC_INITFF 0x08000000 /* Bit 27 */
1354 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1355 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1356
1357 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1358 #define MSIX_DFLT_ID 0
1359 #define MSIX_RNG0_ID 0
1360 #define MSIX_RNG1_ID 1
1361 #define MSIX_RNG2_ID 2
1362 #define MSIX_RNG3_ID 3
1363
1364 #define MSIX_LINK_ID 4
1365 #define MSIX_MBOX_ID 5
1366
1367 #define MSIX_SPARE0_ID 6
1368 #define MSIX_SPARE1_ID 7
1369
1370 /* Mailbox Commands */
1371 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1372 #define MBX_LOAD_SM 0x01
1373 #define MBX_READ_NV 0x02
1374 #define MBX_WRITE_NV 0x03
1375 #define MBX_RUN_BIU_DIAG 0x04
1376 #define MBX_INIT_LINK 0x05
1377 #define MBX_DOWN_LINK 0x06
1378 #define MBX_CONFIG_LINK 0x07
1379 #define MBX_CONFIG_RING 0x09
1380 #define MBX_RESET_RING 0x0A
1381 #define MBX_READ_CONFIG 0x0B
1382 #define MBX_READ_RCONFIG 0x0C
1383 #define MBX_READ_SPARM 0x0D
1384 #define MBX_READ_STATUS 0x0E
1385 #define MBX_READ_RPI 0x0F
1386 #define MBX_READ_XRI 0x10
1387 #define MBX_READ_REV 0x11
1388 #define MBX_READ_LNK_STAT 0x12
1389 #define MBX_REG_LOGIN 0x13
1390 #define MBX_UNREG_LOGIN 0x14
1391 #define MBX_CLEAR_LA 0x16
1392 #define MBX_DUMP_MEMORY 0x17
1393 #define MBX_DUMP_CONTEXT 0x18
1394 #define MBX_RUN_DIAGS 0x19
1395 #define MBX_RESTART 0x1A
1396 #define MBX_UPDATE_CFG 0x1B
1397 #define MBX_DOWN_LOAD 0x1C
1398 #define MBX_DEL_LD_ENTRY 0x1D
1399 #define MBX_RUN_PROGRAM 0x1E
1400 #define MBX_SET_MASK 0x20
1401 #define MBX_SET_VARIABLE 0x21
1402 #define MBX_UNREG_D_ID 0x23
1403 #define MBX_KILL_BOARD 0x24
1404 #define MBX_CONFIG_FARP 0x25
1405 #define MBX_BEACON 0x2A
1406 #define MBX_CONFIG_MSI 0x30
1407 #define MBX_HEARTBEAT 0x31
1408 #define MBX_WRITE_VPARMS 0x32
1409 #define MBX_ASYNCEVT_ENABLE 0x33
1410 #define MBX_READ_EVENT_LOG_STATUS 0x37
1411 #define MBX_READ_EVENT_LOG 0x38
1412 #define MBX_WRITE_EVENT_LOG 0x39
1413
1414 #define MBX_PORT_CAPABILITIES 0x3B
1415 #define MBX_PORT_IOV_CONTROL 0x3C
1416
1417 #define MBX_CONFIG_HBQ 0x7C
1418 #define MBX_LOAD_AREA 0x81
1419 #define MBX_RUN_BIU_DIAG64 0x84
1420 #define MBX_CONFIG_PORT 0x88
1421 #define MBX_READ_SPARM64 0x8D
1422 #define MBX_READ_RPI64 0x8F
1423 #define MBX_REG_LOGIN64 0x93
1424 #define MBX_READ_TOPOLOGY 0x95
1425 #define MBX_REG_VPI 0x96
1426 #define MBX_UNREG_VPI 0x97
1427
1428 #define MBX_WRITE_WWN 0x98
1429 #define MBX_SET_DEBUG 0x99
1430 #define MBX_LOAD_EXP_ROM 0x9C
1431 #define MBX_SLI4_CONFIG 0x9B
1432 #define MBX_SLI4_REQ_FTRS 0x9D
1433 #define MBX_MAX_CMDS 0x9E
1434 #define MBX_RESUME_RPI 0x9E
1435 #define MBX_SLI2_CMD_MASK 0x80
1436 #define MBX_REG_VFI 0x9F
1437 #define MBX_REG_FCFI 0xA0
1438 #define MBX_UNREG_VFI 0xA1
1439 #define MBX_UNREG_FCFI 0xA2
1440 #define MBX_INIT_VFI 0xA3
1441 #define MBX_INIT_VPI 0xA4
1442
1443 #define MBX_AUTH_PORT 0xF8
1444 #define MBX_SECURITY_MGMT 0xF9
1445
1446 /* IOCB Commands */
1447
1448 #define CMD_RCV_SEQUENCE_CX 0x01
1449 #define CMD_XMIT_SEQUENCE_CR 0x02
1450 #define CMD_XMIT_SEQUENCE_CX 0x03
1451 #define CMD_XMIT_BCAST_CN 0x04
1452 #define CMD_XMIT_BCAST_CX 0x05
1453 #define CMD_QUE_RING_BUF_CN 0x06
1454 #define CMD_QUE_XRI_BUF_CX 0x07
1455 #define CMD_IOCB_CONTINUE_CN 0x08
1456 #define CMD_RET_XRI_BUF_CX 0x09
1457 #define CMD_ELS_REQUEST_CR 0x0A
1458 #define CMD_ELS_REQUEST_CX 0x0B
1459 #define CMD_RCV_ELS_REQ_CX 0x0D
1460 #define CMD_ABORT_XRI_CN 0x0E
1461 #define CMD_ABORT_XRI_CX 0x0F
1462 #define CMD_CLOSE_XRI_CN 0x10
1463 #define CMD_CLOSE_XRI_CX 0x11
1464 #define CMD_CREATE_XRI_CR 0x12
1465 #define CMD_CREATE_XRI_CX 0x13
1466 #define CMD_GET_RPI_CN 0x14
1467 #define CMD_XMIT_ELS_RSP_CX 0x15
1468 #define CMD_GET_RPI_CR 0x16
1469 #define CMD_XRI_ABORTED_CX 0x17
1470 #define CMD_FCP_IWRITE_CR 0x18
1471 #define CMD_FCP_IWRITE_CX 0x19
1472 #define CMD_FCP_IREAD_CR 0x1A
1473 #define CMD_FCP_IREAD_CX 0x1B
1474 #define CMD_FCP_ICMND_CR 0x1C
1475 #define CMD_FCP_ICMND_CX 0x1D
1476 #define CMD_FCP_TSEND_CX 0x1F
1477 #define CMD_FCP_TRECEIVE_CX 0x21
1478 #define CMD_FCP_TRSP_CX 0x23
1479 #define CMD_FCP_AUTO_TRSP_CX 0x29
1480
1481 #define CMD_ADAPTER_MSG 0x20
1482 #define CMD_ADAPTER_DUMP 0x22
1483
1484 /* SLI_2 IOCB Command Set */
1485
1486 #define CMD_ASYNC_STATUS 0x7C
1487 #define CMD_RCV_SEQUENCE64_CX 0x81
1488 #define CMD_XMIT_SEQUENCE64_CR 0x82
1489 #define CMD_XMIT_SEQUENCE64_CX 0x83
1490 #define CMD_XMIT_BCAST64_CN 0x84
1491 #define CMD_XMIT_BCAST64_CX 0x85
1492 #define CMD_QUE_RING_BUF64_CN 0x86
1493 #define CMD_QUE_XRI_BUF64_CX 0x87
1494 #define CMD_IOCB_CONTINUE64_CN 0x88
1495 #define CMD_RET_XRI_BUF64_CX 0x89
1496 #define CMD_ELS_REQUEST64_CR 0x8A
1497 #define CMD_ELS_REQUEST64_CX 0x8B
1498 #define CMD_ABORT_MXRI64_CN 0x8C
1499 #define CMD_RCV_ELS_REQ64_CX 0x8D
1500 #define CMD_XMIT_ELS_RSP64_CX 0x95
1501 #define CMD_XMIT_BLS_RSP64_CX 0x97
1502 #define CMD_FCP_IWRITE64_CR 0x98
1503 #define CMD_FCP_IWRITE64_CX 0x99
1504 #define CMD_FCP_IREAD64_CR 0x9A
1505 #define CMD_FCP_IREAD64_CX 0x9B
1506 #define CMD_FCP_ICMND64_CR 0x9C
1507 #define CMD_FCP_ICMND64_CX 0x9D
1508 #define CMD_FCP_TSEND64_CX 0x9F
1509 #define CMD_FCP_TRECEIVE64_CX 0xA1
1510 #define CMD_FCP_TRSP64_CX 0xA3
1511
1512 #define CMD_QUE_XRI64_CX 0xB3
1513 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1514 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1515 #define CMD_IOCB_RET_XRI64_CX 0xB9
1516 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1517
1518 #define CMD_GEN_REQUEST64_CR 0xC2
1519 #define CMD_GEN_REQUEST64_CX 0xC3
1520
1521 /* Unhandled SLI-3 Commands */
1522 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1523 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1524 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1525 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1526 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1527 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1528 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1529 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1530 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1531 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1532 #define CMD_IOCB_LOGENTRY_CN 0x94
1533 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1534
1535 /* Data Security SLI Commands */
1536 #define DSSCMD_IWRITE64_CR 0xF8
1537 #define DSSCMD_IWRITE64_CX 0xF9
1538 #define DSSCMD_IREAD64_CR 0xFA
1539 #define DSSCMD_IREAD64_CX 0xFB
1540
1541 #define CMD_MAX_IOCB_CMD 0xFB
1542 #define CMD_IOCB_MASK 0xff
1543
1544 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1545 iocb */
1546 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1547 /*
1548 * Define Status
1549 */
1550 #define MBX_SUCCESS 0
1551 #define MBXERR_NUM_RINGS 1
1552 #define MBXERR_NUM_IOCBS 2
1553 #define MBXERR_IOCBS_EXCEEDED 3
1554 #define MBXERR_BAD_RING_NUMBER 4
1555 #define MBXERR_MASK_ENTRIES_RANGE 5
1556 #define MBXERR_MASKS_EXCEEDED 6
1557 #define MBXERR_BAD_PROFILE 7
1558 #define MBXERR_BAD_DEF_CLASS 8
1559 #define MBXERR_BAD_MAX_RESPONDER 9
1560 #define MBXERR_BAD_MAX_ORIGINATOR 10
1561 #define MBXERR_RPI_REGISTERED 11
1562 #define MBXERR_RPI_FULL 12
1563 #define MBXERR_NO_RESOURCES 13
1564 #define MBXERR_BAD_RCV_LENGTH 14
1565 #define MBXERR_DMA_ERROR 15
1566 #define MBXERR_ERROR 16
1567 #define MBXERR_LINK_DOWN 0x33
1568 #define MBXERR_SEC_NO_PERMISSION 0xF02
1569 #define MBX_NOT_FINISHED 255
1570
1571 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1572 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1573
1574 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1575
1576 /*
1577 * Begin Structure Definitions for Mailbox Commands
1578 */
1579
1580 typedef struct {
1581 #ifdef __BIG_ENDIAN_BITFIELD
1582 uint8_t tval;
1583 uint8_t tmask;
1584 uint8_t rval;
1585 uint8_t rmask;
1586 #else /* __LITTLE_ENDIAN_BITFIELD */
1587 uint8_t rmask;
1588 uint8_t rval;
1589 uint8_t tmask;
1590 uint8_t tval;
1591 #endif
1592 } RR_REG;
1593
1594 struct ulp_bde {
1595 uint32_t bdeAddress;
1596 #ifdef __BIG_ENDIAN_BITFIELD
1597 uint32_t bdeReserved:4;
1598 uint32_t bdeAddrHigh:4;
1599 uint32_t bdeSize:24;
1600 #else /* __LITTLE_ENDIAN_BITFIELD */
1601 uint32_t bdeSize:24;
1602 uint32_t bdeAddrHigh:4;
1603 uint32_t bdeReserved:4;
1604 #endif
1605 };
1606
1607 typedef struct ULP_BDL { /* SLI-2 */
1608 #ifdef __BIG_ENDIAN_BITFIELD
1609 uint32_t bdeFlags:8; /* BDL Flags */
1610 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1611 #else /* __LITTLE_ENDIAN_BITFIELD */
1612 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1613 uint32_t bdeFlags:8; /* BDL Flags */
1614 #endif
1615
1616 uint32_t addrLow; /* Address 0:31 */
1617 uint32_t addrHigh; /* Address 32:63 */
1618 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1619 } ULP_BDL;
1620
1621 /*
1622 * BlockGuard Definitions
1623 */
1624
1625 enum lpfc_protgrp_type {
1626 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1627 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1628 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1629 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1630 };
1631
1632 /* PDE Descriptors */
1633 #define LPFC_PDE5_DESCRIPTOR 0x85
1634 #define LPFC_PDE6_DESCRIPTOR 0x86
1635 #define LPFC_PDE7_DESCRIPTOR 0x87
1636
1637 /* BlockGuard Opcodes */
1638 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1639 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1640 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1641 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1642 #define BG_OP_IN_CRC_OUT_CRC 0x4
1643 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1644 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1645 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1646
1647 struct lpfc_pde5 {
1648 uint32_t word0;
1649 #define pde5_type_SHIFT 24
1650 #define pde5_type_MASK 0x000000ff
1651 #define pde5_type_WORD word0
1652 #define pde5_rsvd0_SHIFT 0
1653 #define pde5_rsvd0_MASK 0x00ffffff
1654 #define pde5_rsvd0_WORD word0
1655 uint32_t reftag; /* Reference Tag Value */
1656 uint32_t reftagtr; /* Reference Tag Translation Value */
1657 };
1658
1659 struct lpfc_pde6 {
1660 uint32_t word0;
1661 #define pde6_type_SHIFT 24
1662 #define pde6_type_MASK 0x000000ff
1663 #define pde6_type_WORD word0
1664 #define pde6_rsvd0_SHIFT 0
1665 #define pde6_rsvd0_MASK 0x00ffffff
1666 #define pde6_rsvd0_WORD word0
1667 uint32_t word1;
1668 #define pde6_rsvd1_SHIFT 26
1669 #define pde6_rsvd1_MASK 0x0000003f
1670 #define pde6_rsvd1_WORD word1
1671 #define pde6_na_SHIFT 25
1672 #define pde6_na_MASK 0x00000001
1673 #define pde6_na_WORD word1
1674 #define pde6_rsvd2_SHIFT 16
1675 #define pde6_rsvd2_MASK 0x000001FF
1676 #define pde6_rsvd2_WORD word1
1677 #define pde6_apptagtr_SHIFT 0
1678 #define pde6_apptagtr_MASK 0x0000ffff
1679 #define pde6_apptagtr_WORD word1
1680 uint32_t word2;
1681 #define pde6_optx_SHIFT 28
1682 #define pde6_optx_MASK 0x0000000f
1683 #define pde6_optx_WORD word2
1684 #define pde6_oprx_SHIFT 24
1685 #define pde6_oprx_MASK 0x0000000f
1686 #define pde6_oprx_WORD word2
1687 #define pde6_nr_SHIFT 23
1688 #define pde6_nr_MASK 0x00000001
1689 #define pde6_nr_WORD word2
1690 #define pde6_ce_SHIFT 22
1691 #define pde6_ce_MASK 0x00000001
1692 #define pde6_ce_WORD word2
1693 #define pde6_re_SHIFT 21
1694 #define pde6_re_MASK 0x00000001
1695 #define pde6_re_WORD word2
1696 #define pde6_ae_SHIFT 20
1697 #define pde6_ae_MASK 0x00000001
1698 #define pde6_ae_WORD word2
1699 #define pde6_ai_SHIFT 19
1700 #define pde6_ai_MASK 0x00000001
1701 #define pde6_ai_WORD word2
1702 #define pde6_bs_SHIFT 16
1703 #define pde6_bs_MASK 0x00000007
1704 #define pde6_bs_WORD word2
1705 #define pde6_apptagval_SHIFT 0
1706 #define pde6_apptagval_MASK 0x0000ffff
1707 #define pde6_apptagval_WORD word2
1708 };
1709
1710
1711 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1712
1713 typedef struct {
1714 #ifdef __BIG_ENDIAN_BITFIELD
1715 uint32_t rsvd2:25;
1716 uint32_t acknowledgment:1;
1717 uint32_t version:1;
1718 uint32_t erase_or_prog:1;
1719 uint32_t update_flash:1;
1720 uint32_t update_ram:1;
1721 uint32_t method:1;
1722 uint32_t load_cmplt:1;
1723 #else /* __LITTLE_ENDIAN_BITFIELD */
1724 uint32_t load_cmplt:1;
1725 uint32_t method:1;
1726 uint32_t update_ram:1;
1727 uint32_t update_flash:1;
1728 uint32_t erase_or_prog:1;
1729 uint32_t version:1;
1730 uint32_t acknowledgment:1;
1731 uint32_t rsvd2:25;
1732 #endif
1733
1734 uint32_t dl_to_adr_low;
1735 uint32_t dl_to_adr_high;
1736 uint32_t dl_len;
1737 union {
1738 uint32_t dl_from_mbx_offset;
1739 struct ulp_bde dl_from_bde;
1740 struct ulp_bde64 dl_from_bde64;
1741 } un;
1742
1743 } LOAD_SM_VAR;
1744
1745 /* Structure for MB Command READ_NVPARM (02) */
1746
1747 typedef struct {
1748 uint32_t rsvd1[3]; /* Read as all one's */
1749 uint32_t rsvd2; /* Read as all zero's */
1750 uint32_t portname[2]; /* N_PORT name */
1751 uint32_t nodename[2]; /* NODE name */
1752
1753 #ifdef __BIG_ENDIAN_BITFIELD
1754 uint32_t pref_DID:24;
1755 uint32_t hardAL_PA:8;
1756 #else /* __LITTLE_ENDIAN_BITFIELD */
1757 uint32_t hardAL_PA:8;
1758 uint32_t pref_DID:24;
1759 #endif
1760
1761 uint32_t rsvd3[21]; /* Read as all one's */
1762 } READ_NV_VAR;
1763
1764 /* Structure for MB Command WRITE_NVPARMS (03) */
1765
1766 typedef struct {
1767 uint32_t rsvd1[3]; /* Must be all one's */
1768 uint32_t rsvd2; /* Must be all zero's */
1769 uint32_t portname[2]; /* N_PORT name */
1770 uint32_t nodename[2]; /* NODE name */
1771
1772 #ifdef __BIG_ENDIAN_BITFIELD
1773 uint32_t pref_DID:24;
1774 uint32_t hardAL_PA:8;
1775 #else /* __LITTLE_ENDIAN_BITFIELD */
1776 uint32_t hardAL_PA:8;
1777 uint32_t pref_DID:24;
1778 #endif
1779
1780 uint32_t rsvd3[21]; /* Must be all one's */
1781 } WRITE_NV_VAR;
1782
1783 /* Structure for MB Command RUN_BIU_DIAG (04) */
1784 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1785
1786 typedef struct {
1787 uint32_t rsvd1;
1788 union {
1789 struct {
1790 struct ulp_bde xmit_bde;
1791 struct ulp_bde rcv_bde;
1792 } s1;
1793 struct {
1794 struct ulp_bde64 xmit_bde64;
1795 struct ulp_bde64 rcv_bde64;
1796 } s2;
1797 } un;
1798 } BIU_DIAG_VAR;
1799
1800 /* Structure for MB command READ_EVENT_LOG (0x38) */
1801 struct READ_EVENT_LOG_VAR {
1802 uint32_t word1;
1803 #define lpfc_event_log_SHIFT 29
1804 #define lpfc_event_log_MASK 0x00000001
1805 #define lpfc_event_log_WORD word1
1806 #define USE_MAILBOX_RESPONSE 1
1807 uint32_t offset;
1808 struct ulp_bde64 rcv_bde64;
1809 };
1810
1811 /* Structure for MB Command INIT_LINK (05) */
1812
1813 typedef struct {
1814 #ifdef __BIG_ENDIAN_BITFIELD
1815 uint32_t rsvd1:24;
1816 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1817 #else /* __LITTLE_ENDIAN_BITFIELD */
1818 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1819 uint32_t rsvd1:24;
1820 #endif
1821
1822 #ifdef __BIG_ENDIAN_BITFIELD
1823 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1824 uint8_t rsvd2;
1825 uint16_t link_flags;
1826 #else /* __LITTLE_ENDIAN_BITFIELD */
1827 uint16_t link_flags;
1828 uint8_t rsvd2;
1829 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1830 #endif
1831
1832 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1833 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1834 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1835 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1836 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1837 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1838 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1839
1840 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1841 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1842 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1843
1844 uint32_t link_speed;
1845 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
1846 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
1847 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
1848 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
1849 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
1850 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
1851 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
1852
1853 } INIT_LINK_VAR;
1854
1855 /* Structure for MB Command DOWN_LINK (06) */
1856
1857 typedef struct {
1858 uint32_t rsvd1;
1859 } DOWN_LINK_VAR;
1860
1861 /* Structure for MB Command CONFIG_LINK (07) */
1862
1863 typedef struct {
1864 #ifdef __BIG_ENDIAN_BITFIELD
1865 uint32_t cr:1;
1866 uint32_t ci:1;
1867 uint32_t cr_delay:6;
1868 uint32_t cr_count:8;
1869 uint32_t rsvd1:8;
1870 uint32_t MaxBBC:8;
1871 #else /* __LITTLE_ENDIAN_BITFIELD */
1872 uint32_t MaxBBC:8;
1873 uint32_t rsvd1:8;
1874 uint32_t cr_count:8;
1875 uint32_t cr_delay:6;
1876 uint32_t ci:1;
1877 uint32_t cr:1;
1878 #endif
1879
1880 uint32_t myId;
1881 uint32_t rsvd2;
1882 uint32_t edtov;
1883 uint32_t arbtov;
1884 uint32_t ratov;
1885 uint32_t rttov;
1886 uint32_t altov;
1887 uint32_t crtov;
1888 uint32_t citov;
1889 #ifdef __BIG_ENDIAN_BITFIELD
1890 uint32_t rrq_enable:1;
1891 uint32_t rrq_immed:1;
1892 uint32_t rsvd4:29;
1893 uint32_t ack0_enable:1;
1894 #else /* __LITTLE_ENDIAN_BITFIELD */
1895 uint32_t ack0_enable:1;
1896 uint32_t rsvd4:29;
1897 uint32_t rrq_immed:1;
1898 uint32_t rrq_enable:1;
1899 #endif
1900 } CONFIG_LINK;
1901
1902 /* Structure for MB Command PART_SLIM (08)
1903 * will be removed since SLI1 is no longer supported!
1904 */
1905 typedef struct {
1906 #ifdef __BIG_ENDIAN_BITFIELD
1907 uint16_t offCiocb;
1908 uint16_t numCiocb;
1909 uint16_t offRiocb;
1910 uint16_t numRiocb;
1911 #else /* __LITTLE_ENDIAN_BITFIELD */
1912 uint16_t numCiocb;
1913 uint16_t offCiocb;
1914 uint16_t numRiocb;
1915 uint16_t offRiocb;
1916 #endif
1917 } RING_DEF;
1918
1919 typedef struct {
1920 #ifdef __BIG_ENDIAN_BITFIELD
1921 uint32_t unused1:24;
1922 uint32_t numRing:8;
1923 #else /* __LITTLE_ENDIAN_BITFIELD */
1924 uint32_t numRing:8;
1925 uint32_t unused1:24;
1926 #endif
1927
1928 RING_DEF ringdef[4];
1929 uint32_t hbainit;
1930 } PART_SLIM_VAR;
1931
1932 /* Structure for MB Command CONFIG_RING (09) */
1933
1934 typedef struct {
1935 #ifdef __BIG_ENDIAN_BITFIELD
1936 uint32_t unused2:6;
1937 uint32_t recvSeq:1;
1938 uint32_t recvNotify:1;
1939 uint32_t numMask:8;
1940 uint32_t profile:8;
1941 uint32_t unused1:4;
1942 uint32_t ring:4;
1943 #else /* __LITTLE_ENDIAN_BITFIELD */
1944 uint32_t ring:4;
1945 uint32_t unused1:4;
1946 uint32_t profile:8;
1947 uint32_t numMask:8;
1948 uint32_t recvNotify:1;
1949 uint32_t recvSeq:1;
1950 uint32_t unused2:6;
1951 #endif
1952
1953 #ifdef __BIG_ENDIAN_BITFIELD
1954 uint16_t maxRespXchg;
1955 uint16_t maxOrigXchg;
1956 #else /* __LITTLE_ENDIAN_BITFIELD */
1957 uint16_t maxOrigXchg;
1958 uint16_t maxRespXchg;
1959 #endif
1960
1961 RR_REG rrRegs[6];
1962 } CONFIG_RING_VAR;
1963
1964 /* Structure for MB Command RESET_RING (10) */
1965
1966 typedef struct {
1967 uint32_t ring_no;
1968 } RESET_RING_VAR;
1969
1970 /* Structure for MB Command READ_CONFIG (11) */
1971
1972 typedef struct {
1973 #ifdef __BIG_ENDIAN_BITFIELD
1974 uint32_t cr:1;
1975 uint32_t ci:1;
1976 uint32_t cr_delay:6;
1977 uint32_t cr_count:8;
1978 uint32_t InitBBC:8;
1979 uint32_t MaxBBC:8;
1980 #else /* __LITTLE_ENDIAN_BITFIELD */
1981 uint32_t MaxBBC:8;
1982 uint32_t InitBBC:8;
1983 uint32_t cr_count:8;
1984 uint32_t cr_delay:6;
1985 uint32_t ci:1;
1986 uint32_t cr:1;
1987 #endif
1988
1989 #ifdef __BIG_ENDIAN_BITFIELD
1990 uint32_t topology:8;
1991 uint32_t myDid:24;
1992 #else /* __LITTLE_ENDIAN_BITFIELD */
1993 uint32_t myDid:24;
1994 uint32_t topology:8;
1995 #endif
1996
1997 /* Defines for topology (defined previously) */
1998 #ifdef __BIG_ENDIAN_BITFIELD
1999 uint32_t AR:1;
2000 uint32_t IR:1;
2001 uint32_t rsvd1:29;
2002 uint32_t ack0:1;
2003 #else /* __LITTLE_ENDIAN_BITFIELD */
2004 uint32_t ack0:1;
2005 uint32_t rsvd1:29;
2006 uint32_t IR:1;
2007 uint32_t AR:1;
2008 #endif
2009
2010 uint32_t edtov;
2011 uint32_t arbtov;
2012 uint32_t ratov;
2013 uint32_t rttov;
2014 uint32_t altov;
2015 uint32_t lmt;
2016 #define LMT_RESERVED 0x000 /* Not used */
2017 #define LMT_1Gb 0x004
2018 #define LMT_2Gb 0x008
2019 #define LMT_4Gb 0x040
2020 #define LMT_8Gb 0x080
2021 #define LMT_10Gb 0x100
2022 #define LMT_16Gb 0x200
2023 uint32_t rsvd2;
2024 uint32_t rsvd3;
2025 uint32_t max_xri;
2026 uint32_t max_iocb;
2027 uint32_t max_rpi;
2028 uint32_t avail_xri;
2029 uint32_t avail_iocb;
2030 uint32_t avail_rpi;
2031 uint32_t max_vpi;
2032 uint32_t rsvd4;
2033 uint32_t rsvd5;
2034 uint32_t avail_vpi;
2035 } READ_CONFIG_VAR;
2036
2037 /* Structure for MB Command READ_RCONFIG (12) */
2038
2039 typedef struct {
2040 #ifdef __BIG_ENDIAN_BITFIELD
2041 uint32_t rsvd2:7;
2042 uint32_t recvNotify:1;
2043 uint32_t numMask:8;
2044 uint32_t profile:8;
2045 uint32_t rsvd1:4;
2046 uint32_t ring:4;
2047 #else /* __LITTLE_ENDIAN_BITFIELD */
2048 uint32_t ring:4;
2049 uint32_t rsvd1:4;
2050 uint32_t profile:8;
2051 uint32_t numMask:8;
2052 uint32_t recvNotify:1;
2053 uint32_t rsvd2:7;
2054 #endif
2055
2056 #ifdef __BIG_ENDIAN_BITFIELD
2057 uint16_t maxResp;
2058 uint16_t maxOrig;
2059 #else /* __LITTLE_ENDIAN_BITFIELD */
2060 uint16_t maxOrig;
2061 uint16_t maxResp;
2062 #endif
2063
2064 RR_REG rrRegs[6];
2065
2066 #ifdef __BIG_ENDIAN_BITFIELD
2067 uint16_t cmdRingOffset;
2068 uint16_t cmdEntryCnt;
2069 uint16_t rspRingOffset;
2070 uint16_t rspEntryCnt;
2071 uint16_t nextCmdOffset;
2072 uint16_t rsvd3;
2073 uint16_t nextRspOffset;
2074 uint16_t rsvd4;
2075 #else /* __LITTLE_ENDIAN_BITFIELD */
2076 uint16_t cmdEntryCnt;
2077 uint16_t cmdRingOffset;
2078 uint16_t rspEntryCnt;
2079 uint16_t rspRingOffset;
2080 uint16_t rsvd3;
2081 uint16_t nextCmdOffset;
2082 uint16_t rsvd4;
2083 uint16_t nextRspOffset;
2084 #endif
2085 } READ_RCONF_VAR;
2086
2087 /* Structure for MB Command READ_SPARM (13) */
2088 /* Structure for MB Command READ_SPARM64 (0x8D) */
2089
2090 typedef struct {
2091 uint32_t rsvd1;
2092 uint32_t rsvd2;
2093 union {
2094 struct ulp_bde sp; /* This BDE points to struct serv_parm
2095 structure */
2096 struct ulp_bde64 sp64;
2097 } un;
2098 #ifdef __BIG_ENDIAN_BITFIELD
2099 uint16_t rsvd3;
2100 uint16_t vpi;
2101 #else /* __LITTLE_ENDIAN_BITFIELD */
2102 uint16_t vpi;
2103 uint16_t rsvd3;
2104 #endif
2105 } READ_SPARM_VAR;
2106
2107 /* Structure for MB Command READ_STATUS (14) */
2108
2109 typedef struct {
2110 #ifdef __BIG_ENDIAN_BITFIELD
2111 uint32_t rsvd1:31;
2112 uint32_t clrCounters:1;
2113 uint16_t activeXriCnt;
2114 uint16_t activeRpiCnt;
2115 #else /* __LITTLE_ENDIAN_BITFIELD */
2116 uint32_t clrCounters:1;
2117 uint32_t rsvd1:31;
2118 uint16_t activeRpiCnt;
2119 uint16_t activeXriCnt;
2120 #endif
2121
2122 uint32_t xmitByteCnt;
2123 uint32_t rcvByteCnt;
2124 uint32_t xmitFrameCnt;
2125 uint32_t rcvFrameCnt;
2126 uint32_t xmitSeqCnt;
2127 uint32_t rcvSeqCnt;
2128 uint32_t totalOrigExchanges;
2129 uint32_t totalRespExchanges;
2130 uint32_t rcvPbsyCnt;
2131 uint32_t rcvFbsyCnt;
2132 } READ_STATUS_VAR;
2133
2134 /* Structure for MB Command READ_RPI (15) */
2135 /* Structure for MB Command READ_RPI64 (0x8F) */
2136
2137 typedef struct {
2138 #ifdef __BIG_ENDIAN_BITFIELD
2139 uint16_t nextRpi;
2140 uint16_t reqRpi;
2141 uint32_t rsvd2:8;
2142 uint32_t DID:24;
2143 #else /* __LITTLE_ENDIAN_BITFIELD */
2144 uint16_t reqRpi;
2145 uint16_t nextRpi;
2146 uint32_t DID:24;
2147 uint32_t rsvd2:8;
2148 #endif
2149
2150 union {
2151 struct ulp_bde sp;
2152 struct ulp_bde64 sp64;
2153 } un;
2154
2155 } READ_RPI_VAR;
2156
2157 /* Structure for MB Command READ_XRI (16) */
2158
2159 typedef struct {
2160 #ifdef __BIG_ENDIAN_BITFIELD
2161 uint16_t nextXri;
2162 uint16_t reqXri;
2163 uint16_t rsvd1;
2164 uint16_t rpi;
2165 uint32_t rsvd2:8;
2166 uint32_t DID:24;
2167 uint32_t rsvd3:8;
2168 uint32_t SID:24;
2169 uint32_t rsvd4;
2170 uint8_t seqId;
2171 uint8_t rsvd5;
2172 uint16_t seqCount;
2173 uint16_t oxId;
2174 uint16_t rxId;
2175 uint32_t rsvd6:30;
2176 uint32_t si:1;
2177 uint32_t exchOrig:1;
2178 #else /* __LITTLE_ENDIAN_BITFIELD */
2179 uint16_t reqXri;
2180 uint16_t nextXri;
2181 uint16_t rpi;
2182 uint16_t rsvd1;
2183 uint32_t DID:24;
2184 uint32_t rsvd2:8;
2185 uint32_t SID:24;
2186 uint32_t rsvd3:8;
2187 uint32_t rsvd4;
2188 uint16_t seqCount;
2189 uint8_t rsvd5;
2190 uint8_t seqId;
2191 uint16_t rxId;
2192 uint16_t oxId;
2193 uint32_t exchOrig:1;
2194 uint32_t si:1;
2195 uint32_t rsvd6:30;
2196 #endif
2197 } READ_XRI_VAR;
2198
2199 /* Structure for MB Command READ_REV (17) */
2200
2201 typedef struct {
2202 #ifdef __BIG_ENDIAN_BITFIELD
2203 uint32_t cv:1;
2204 uint32_t rr:1;
2205 uint32_t rsvd2:2;
2206 uint32_t v3req:1;
2207 uint32_t v3rsp:1;
2208 uint32_t rsvd1:25;
2209 uint32_t rv:1;
2210 #else /* __LITTLE_ENDIAN_BITFIELD */
2211 uint32_t rv:1;
2212 uint32_t rsvd1:25;
2213 uint32_t v3rsp:1;
2214 uint32_t v3req:1;
2215 uint32_t rsvd2:2;
2216 uint32_t rr:1;
2217 uint32_t cv:1;
2218 #endif
2219
2220 uint32_t biuRev;
2221 uint32_t smRev;
2222 union {
2223 uint32_t smFwRev;
2224 struct {
2225 #ifdef __BIG_ENDIAN_BITFIELD
2226 uint8_t ProgType;
2227 uint8_t ProgId;
2228 uint16_t ProgVer:4;
2229 uint16_t ProgRev:4;
2230 uint16_t ProgFixLvl:2;
2231 uint16_t ProgDistType:2;
2232 uint16_t DistCnt:4;
2233 #else /* __LITTLE_ENDIAN_BITFIELD */
2234 uint16_t DistCnt:4;
2235 uint16_t ProgDistType:2;
2236 uint16_t ProgFixLvl:2;
2237 uint16_t ProgRev:4;
2238 uint16_t ProgVer:4;
2239 uint8_t ProgId;
2240 uint8_t ProgType;
2241 #endif
2242
2243 } b;
2244 } un;
2245 uint32_t endecRev;
2246 #ifdef __BIG_ENDIAN_BITFIELD
2247 uint8_t feaLevelHigh;
2248 uint8_t feaLevelLow;
2249 uint8_t fcphHigh;
2250 uint8_t fcphLow;
2251 #else /* __LITTLE_ENDIAN_BITFIELD */
2252 uint8_t fcphLow;
2253 uint8_t fcphHigh;
2254 uint8_t feaLevelLow;
2255 uint8_t feaLevelHigh;
2256 #endif
2257
2258 uint32_t postKernRev;
2259 uint32_t opFwRev;
2260 uint8_t opFwName[16];
2261 uint32_t sli1FwRev;
2262 uint8_t sli1FwName[16];
2263 uint32_t sli2FwRev;
2264 uint8_t sli2FwName[16];
2265 uint32_t sli3Feat;
2266 uint32_t RandomData[6];
2267 } READ_REV_VAR;
2268
2269 /* Structure for MB Command READ_LINK_STAT (18) */
2270
2271 typedef struct {
2272 uint32_t rsvd1;
2273 uint32_t linkFailureCnt;
2274 uint32_t lossSyncCnt;
2275
2276 uint32_t lossSignalCnt;
2277 uint32_t primSeqErrCnt;
2278 uint32_t invalidXmitWord;
2279 uint32_t crcCnt;
2280 uint32_t primSeqTimeout;
2281 uint32_t elasticOverrun;
2282 uint32_t arbTimeout;
2283 } READ_LNK_VAR;
2284
2285 /* Structure for MB Command REG_LOGIN (19) */
2286 /* Structure for MB Command REG_LOGIN64 (0x93) */
2287
2288 typedef struct {
2289 #ifdef __BIG_ENDIAN_BITFIELD
2290 uint16_t rsvd1;
2291 uint16_t rpi;
2292 uint32_t rsvd2:8;
2293 uint32_t did:24;
2294 #else /* __LITTLE_ENDIAN_BITFIELD */
2295 uint16_t rpi;
2296 uint16_t rsvd1;
2297 uint32_t did:24;
2298 uint32_t rsvd2:8;
2299 #endif
2300
2301 union {
2302 struct ulp_bde sp;
2303 struct ulp_bde64 sp64;
2304 } un;
2305
2306 #ifdef __BIG_ENDIAN_BITFIELD
2307 uint16_t rsvd6;
2308 uint16_t vpi;
2309 #else /* __LITTLE_ENDIAN_BITFIELD */
2310 uint16_t vpi;
2311 uint16_t rsvd6;
2312 #endif
2313
2314 } REG_LOGIN_VAR;
2315
2316 /* Word 30 contents for REG_LOGIN */
2317 typedef union {
2318 struct {
2319 #ifdef __BIG_ENDIAN_BITFIELD
2320 uint16_t rsvd1:12;
2321 uint16_t wd30_class:4;
2322 uint16_t xri;
2323 #else /* __LITTLE_ENDIAN_BITFIELD */
2324 uint16_t xri;
2325 uint16_t wd30_class:4;
2326 uint16_t rsvd1:12;
2327 #endif
2328 } f;
2329 uint32_t word;
2330 } REG_WD30;
2331
2332 /* Structure for MB Command UNREG_LOGIN (20) */
2333
2334 typedef struct {
2335 #ifdef __BIG_ENDIAN_BITFIELD
2336 uint16_t rsvd1;
2337 uint16_t rpi;
2338 uint32_t rsvd2;
2339 uint32_t rsvd3;
2340 uint32_t rsvd4;
2341 uint32_t rsvd5;
2342 uint16_t rsvd6;
2343 uint16_t vpi;
2344 #else /* __LITTLE_ENDIAN_BITFIELD */
2345 uint16_t rpi;
2346 uint16_t rsvd1;
2347 uint32_t rsvd2;
2348 uint32_t rsvd3;
2349 uint32_t rsvd4;
2350 uint32_t rsvd5;
2351 uint16_t vpi;
2352 uint16_t rsvd6;
2353 #endif
2354 } UNREG_LOGIN_VAR;
2355
2356 /* Structure for MB Command REG_VPI (0x96) */
2357 typedef struct {
2358 #ifdef __BIG_ENDIAN_BITFIELD
2359 uint32_t rsvd1;
2360 uint32_t rsvd2:7;
2361 uint32_t upd:1;
2362 uint32_t sid:24;
2363 uint32_t wwn[2];
2364 uint32_t rsvd5;
2365 uint16_t vfi;
2366 uint16_t vpi;
2367 #else /* __LITTLE_ENDIAN */
2368 uint32_t rsvd1;
2369 uint32_t sid:24;
2370 uint32_t upd:1;
2371 uint32_t rsvd2:7;
2372 uint32_t wwn[2];
2373 uint32_t rsvd5;
2374 uint16_t vpi;
2375 uint16_t vfi;
2376 #endif
2377 } REG_VPI_VAR;
2378
2379 /* Structure for MB Command UNREG_VPI (0x97) */
2380 typedef struct {
2381 uint32_t rsvd1;
2382 #ifdef __BIG_ENDIAN_BITFIELD
2383 uint16_t rsvd2;
2384 uint16_t sli4_vpi;
2385 #else /* __LITTLE_ENDIAN */
2386 uint16_t sli4_vpi;
2387 uint16_t rsvd2;
2388 #endif
2389 uint32_t rsvd3;
2390 uint32_t rsvd4;
2391 uint32_t rsvd5;
2392 #ifdef __BIG_ENDIAN_BITFIELD
2393 uint16_t rsvd6;
2394 uint16_t vpi;
2395 #else /* __LITTLE_ENDIAN */
2396 uint16_t vpi;
2397 uint16_t rsvd6;
2398 #endif
2399 } UNREG_VPI_VAR;
2400
2401 /* Structure for MB Command UNREG_D_ID (0x23) */
2402
2403 typedef struct {
2404 uint32_t did;
2405 uint32_t rsvd2;
2406 uint32_t rsvd3;
2407 uint32_t rsvd4;
2408 uint32_t rsvd5;
2409 #ifdef __BIG_ENDIAN_BITFIELD
2410 uint16_t rsvd6;
2411 uint16_t vpi;
2412 #else
2413 uint16_t vpi;
2414 uint16_t rsvd6;
2415 #endif
2416 } UNREG_D_ID_VAR;
2417
2418 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2419 struct lpfc_mbx_read_top {
2420 uint32_t eventTag; /* Event tag */
2421 uint32_t word2;
2422 #define lpfc_mbx_read_top_fa_SHIFT 12
2423 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2424 #define lpfc_mbx_read_top_fa_WORD word2
2425 #define lpfc_mbx_read_top_mm_SHIFT 11
2426 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2427 #define lpfc_mbx_read_top_mm_WORD word2
2428 #define lpfc_mbx_read_top_pb_SHIFT 9
2429 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2430 #define lpfc_mbx_read_top_pb_WORD word2
2431 #define lpfc_mbx_read_top_il_SHIFT 8
2432 #define lpfc_mbx_read_top_il_MASK 0x00000001
2433 #define lpfc_mbx_read_top_il_WORD word2
2434 #define lpfc_mbx_read_top_att_type_SHIFT 0
2435 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2436 #define lpfc_mbx_read_top_att_type_WORD word2
2437 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2438 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2439 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2440 uint32_t word3;
2441 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2442 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2443 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2444 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2445 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2446 #define lpfc_mbx_read_top_lip_alps_WORD word3
2447 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2448 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2449 #define lpfc_mbx_read_top_lip_type_WORD word3
2450 #define lpfc_mbx_read_top_topology_SHIFT 0
2451 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2452 #define lpfc_mbx_read_top_topology_WORD word3
2453 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2454 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2455 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2456 /* store the LILP AL_PA position map into */
2457 struct ulp_bde64 lilpBde64;
2458 #define LPFC_ALPA_MAP_SIZE 128
2459 uint32_t word7;
2460 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2461 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2462 #define lpfc_mbx_read_top_ld_lu_WORD word7
2463 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2464 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2465 #define lpfc_mbx_read_top_ld_tf_WORD word7
2466 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2467 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2468 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2469 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2470 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2471 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2472 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2473 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2474 #define lpfc_mbx_read_top_ld_tx_WORD word7
2475 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2476 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2477 #define lpfc_mbx_read_top_ld_rx_WORD word7
2478 uint32_t word8;
2479 #define lpfc_mbx_read_top_lu_SHIFT 31
2480 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2481 #define lpfc_mbx_read_top_lu_WORD word8
2482 #define lpfc_mbx_read_top_tf_SHIFT 30
2483 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2484 #define lpfc_mbx_read_top_tf_WORD word8
2485 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2486 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2487 #define lpfc_mbx_read_top_link_spd_WORD word8
2488 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2489 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2490 #define lpfc_mbx_read_top_nl_port_WORD word8
2491 #define lpfc_mbx_read_top_tx_SHIFT 2
2492 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2493 #define lpfc_mbx_read_top_tx_WORD word8
2494 #define lpfc_mbx_read_top_rx_SHIFT 0
2495 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2496 #define lpfc_mbx_read_top_rx_WORD word8
2497 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2498 #define LPFC_LINK_SPEED_1GHZ 0x04
2499 #define LPFC_LINK_SPEED_2GHZ 0x08
2500 #define LPFC_LINK_SPEED_4GHZ 0x10
2501 #define LPFC_LINK_SPEED_8GHZ 0x20
2502 #define LPFC_LINK_SPEED_10GHZ 0x40
2503 #define LPFC_LINK_SPEED_16GHZ 0x80
2504 };
2505
2506 /* Structure for MB Command CLEAR_LA (22) */
2507
2508 typedef struct {
2509 uint32_t eventTag; /* Event tag */
2510 uint32_t rsvd1;
2511 } CLEAR_LA_VAR;
2512
2513 /* Structure for MB Command DUMP */
2514
2515 typedef struct {
2516 #ifdef __BIG_ENDIAN_BITFIELD
2517 uint32_t rsvd:25;
2518 uint32_t ra:1;
2519 uint32_t co:1;
2520 uint32_t cv:1;
2521 uint32_t type:4;
2522 uint32_t entry_index:16;
2523 uint32_t region_id:16;
2524 #else /* __LITTLE_ENDIAN_BITFIELD */
2525 uint32_t type:4;
2526 uint32_t cv:1;
2527 uint32_t co:1;
2528 uint32_t ra:1;
2529 uint32_t rsvd:25;
2530 uint32_t region_id:16;
2531 uint32_t entry_index:16;
2532 #endif
2533
2534 uint32_t sli4_length;
2535 uint32_t word_cnt;
2536 uint32_t resp_offset;
2537 } DUMP_VAR;
2538
2539 #define DMP_MEM_REG 0x1
2540 #define DMP_NV_PARAMS 0x2
2541
2542 #define DMP_REGION_VPD 0xe
2543 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2544 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2545 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2546
2547 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2548 #define DMP_VPORT_REGION_SIZE 0x200
2549 #define DMP_MBOX_OFFSET_WORD 0x5
2550
2551 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2552 #define DMP_RGN23_SIZE 0x400
2553
2554 #define WAKE_UP_PARMS_REGION_ID 4
2555 #define WAKE_UP_PARMS_WORD_SIZE 15
2556
2557 struct vport_rec {
2558 uint8_t wwpn[8];
2559 uint8_t wwnn[8];
2560 };
2561
2562 #define VPORT_INFO_SIG 0x32324752
2563 #define VPORT_INFO_REV_MASK 0xff
2564 #define VPORT_INFO_REV 0x1
2565 #define MAX_STATIC_VPORT_COUNT 16
2566 struct static_vport_info {
2567 uint32_t signature;
2568 uint32_t rev;
2569 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2570 uint32_t resvd[66];
2571 };
2572
2573 /* Option rom version structure */
2574 struct prog_id {
2575 #ifdef __BIG_ENDIAN_BITFIELD
2576 uint8_t type;
2577 uint8_t id;
2578 uint32_t ver:4; /* Major Version */
2579 uint32_t rev:4; /* Revision */
2580 uint32_t lev:2; /* Level */
2581 uint32_t dist:2; /* Dist Type */
2582 uint32_t num:4; /* number after dist type */
2583 #else /* __LITTLE_ENDIAN_BITFIELD */
2584 uint32_t num:4; /* number after dist type */
2585 uint32_t dist:2; /* Dist Type */
2586 uint32_t lev:2; /* Level */
2587 uint32_t rev:4; /* Revision */
2588 uint32_t ver:4; /* Major Version */
2589 uint8_t id;
2590 uint8_t type;
2591 #endif
2592 };
2593
2594 /* Structure for MB Command UPDATE_CFG (0x1B) */
2595
2596 struct update_cfg_var {
2597 #ifdef __BIG_ENDIAN_BITFIELD
2598 uint32_t rsvd2:16;
2599 uint32_t type:8;
2600 uint32_t rsvd:1;
2601 uint32_t ra:1;
2602 uint32_t co:1;
2603 uint32_t cv:1;
2604 uint32_t req:4;
2605 uint32_t entry_length:16;
2606 uint32_t region_id:16;
2607 #else /* __LITTLE_ENDIAN_BITFIELD */
2608 uint32_t req:4;
2609 uint32_t cv:1;
2610 uint32_t co:1;
2611 uint32_t ra:1;
2612 uint32_t rsvd:1;
2613 uint32_t type:8;
2614 uint32_t rsvd2:16;
2615 uint32_t region_id:16;
2616 uint32_t entry_length:16;
2617 #endif
2618
2619 uint32_t resp_info;
2620 uint32_t byte_cnt;
2621 uint32_t data_offset;
2622 };
2623
2624 struct hbq_mask {
2625 #ifdef __BIG_ENDIAN_BITFIELD
2626 uint8_t tmatch;
2627 uint8_t tmask;
2628 uint8_t rctlmatch;
2629 uint8_t rctlmask;
2630 #else /* __LITTLE_ENDIAN */
2631 uint8_t rctlmask;
2632 uint8_t rctlmatch;
2633 uint8_t tmask;
2634 uint8_t tmatch;
2635 #endif
2636 };
2637
2638
2639 /* Structure for MB Command CONFIG_HBQ (7c) */
2640
2641 struct config_hbq_var {
2642 #ifdef __BIG_ENDIAN_BITFIELD
2643 uint32_t rsvd1 :7;
2644 uint32_t recvNotify :1; /* Receive Notification */
2645 uint32_t numMask :8; /* # Mask Entries */
2646 uint32_t profile :8; /* Selection Profile */
2647 uint32_t rsvd2 :8;
2648 #else /* __LITTLE_ENDIAN */
2649 uint32_t rsvd2 :8;
2650 uint32_t profile :8; /* Selection Profile */
2651 uint32_t numMask :8; /* # Mask Entries */
2652 uint32_t recvNotify :1; /* Receive Notification */
2653 uint32_t rsvd1 :7;
2654 #endif
2655
2656 #ifdef __BIG_ENDIAN_BITFIELD
2657 uint32_t hbqId :16;
2658 uint32_t rsvd3 :12;
2659 uint32_t ringMask :4;
2660 #else /* __LITTLE_ENDIAN */
2661 uint32_t ringMask :4;
2662 uint32_t rsvd3 :12;
2663 uint32_t hbqId :16;
2664 #endif
2665
2666 #ifdef __BIG_ENDIAN_BITFIELD
2667 uint32_t entry_count :16;
2668 uint32_t rsvd4 :8;
2669 uint32_t headerLen :8;
2670 #else /* __LITTLE_ENDIAN */
2671 uint32_t headerLen :8;
2672 uint32_t rsvd4 :8;
2673 uint32_t entry_count :16;
2674 #endif
2675
2676 uint32_t hbqaddrLow;
2677 uint32_t hbqaddrHigh;
2678
2679 #ifdef __BIG_ENDIAN_BITFIELD
2680 uint32_t rsvd5 :31;
2681 uint32_t logEntry :1;
2682 #else /* __LITTLE_ENDIAN */
2683 uint32_t logEntry :1;
2684 uint32_t rsvd5 :31;
2685 #endif
2686
2687 uint32_t rsvd6; /* w7 */
2688 uint32_t rsvd7; /* w8 */
2689 uint32_t rsvd8; /* w9 */
2690
2691 struct hbq_mask hbqMasks[6];
2692
2693
2694 union {
2695 uint32_t allprofiles[12];
2696
2697 struct {
2698 #ifdef __BIG_ENDIAN_BITFIELD
2699 uint32_t seqlenoff :16;
2700 uint32_t maxlen :16;
2701 #else /* __LITTLE_ENDIAN */
2702 uint32_t maxlen :16;
2703 uint32_t seqlenoff :16;
2704 #endif
2705 #ifdef __BIG_ENDIAN_BITFIELD
2706 uint32_t rsvd1 :28;
2707 uint32_t seqlenbcnt :4;
2708 #else /* __LITTLE_ENDIAN */
2709 uint32_t seqlenbcnt :4;
2710 uint32_t rsvd1 :28;
2711 #endif
2712 uint32_t rsvd[10];
2713 } profile2;
2714
2715 struct {
2716 #ifdef __BIG_ENDIAN_BITFIELD
2717 uint32_t seqlenoff :16;
2718 uint32_t maxlen :16;
2719 #else /* __LITTLE_ENDIAN */
2720 uint32_t maxlen :16;
2721 uint32_t seqlenoff :16;
2722 #endif
2723 #ifdef __BIG_ENDIAN_BITFIELD
2724 uint32_t cmdcodeoff :28;
2725 uint32_t rsvd1 :12;
2726 uint32_t seqlenbcnt :4;
2727 #else /* __LITTLE_ENDIAN */
2728 uint32_t seqlenbcnt :4;
2729 uint32_t rsvd1 :12;
2730 uint32_t cmdcodeoff :28;
2731 #endif
2732 uint32_t cmdmatch[8];
2733
2734 uint32_t rsvd[2];
2735 } profile3;
2736
2737 struct {
2738 #ifdef __BIG_ENDIAN_BITFIELD
2739 uint32_t seqlenoff :16;
2740 uint32_t maxlen :16;
2741 #else /* __LITTLE_ENDIAN */
2742 uint32_t maxlen :16;
2743 uint32_t seqlenoff :16;
2744 #endif
2745 #ifdef __BIG_ENDIAN_BITFIELD
2746 uint32_t cmdcodeoff :28;
2747 uint32_t rsvd1 :12;
2748 uint32_t seqlenbcnt :4;
2749 #else /* __LITTLE_ENDIAN */
2750 uint32_t seqlenbcnt :4;
2751 uint32_t rsvd1 :12;
2752 uint32_t cmdcodeoff :28;
2753 #endif
2754 uint32_t cmdmatch[8];
2755
2756 uint32_t rsvd[2];
2757 } profile5;
2758
2759 } profiles;
2760
2761 };
2762
2763
2764
2765 /* Structure for MB Command CONFIG_PORT (0x88) */
2766 typedef struct {
2767 #ifdef __BIG_ENDIAN_BITFIELD
2768 uint32_t cBE : 1;
2769 uint32_t cET : 1;
2770 uint32_t cHpcb : 1;
2771 uint32_t cMA : 1;
2772 uint32_t sli_mode : 4;
2773 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2774 * config block */
2775 #else /* __LITTLE_ENDIAN */
2776 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2777 * config block */
2778 uint32_t sli_mode : 4;
2779 uint32_t cMA : 1;
2780 uint32_t cHpcb : 1;
2781 uint32_t cET : 1;
2782 uint32_t cBE : 1;
2783 #endif
2784
2785 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2786 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2787 uint32_t hbainit[5];
2788 #ifdef __BIG_ENDIAN_BITFIELD
2789 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2790 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2791 #else /* __LITTLE_ENDIAN */
2792 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2793 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2794 #endif
2795
2796 #ifdef __BIG_ENDIAN_BITFIELD
2797 uint32_t rsvd1 : 19; /* Reserved */
2798 uint32_t cdss : 1; /* Configure Data Security SLI */
2799 uint32_t rsvd2 : 3; /* Reserved */
2800 uint32_t cbg : 1; /* Configure BlockGuard */
2801 uint32_t cmv : 1; /* Configure Max VPIs */
2802 uint32_t ccrp : 1; /* Config Command Ring Polling */
2803 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2804 uint32_t chbs : 1; /* Cofigure Host Backing store */
2805 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2806 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2807 uint32_t cmx : 1; /* Configure Max XRIs */
2808 uint32_t cmr : 1; /* Configure Max RPIs */
2809 #else /* __LITTLE_ENDIAN */
2810 uint32_t cmr : 1; /* Configure Max RPIs */
2811 uint32_t cmx : 1; /* Configure Max XRIs */
2812 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2813 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2814 uint32_t chbs : 1; /* Cofigure Host Backing store */
2815 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2816 uint32_t ccrp : 1; /* Config Command Ring Polling */
2817 uint32_t cmv : 1; /* Configure Max VPIs */
2818 uint32_t cbg : 1; /* Configure BlockGuard */
2819 uint32_t rsvd2 : 3; /* Reserved */
2820 uint32_t cdss : 1; /* Configure Data Security SLI */
2821 uint32_t rsvd1 : 19; /* Reserved */
2822 #endif
2823 #ifdef __BIG_ENDIAN_BITFIELD
2824 uint32_t rsvd3 : 19; /* Reserved */
2825 uint32_t gdss : 1; /* Configure Data Security SLI */
2826 uint32_t rsvd4 : 3; /* Reserved */
2827 uint32_t gbg : 1; /* Grant BlockGuard */
2828 uint32_t gmv : 1; /* Grant Max VPIs */
2829 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2830 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2831 uint32_t ghbs : 1; /* Grant Host Backing Store */
2832 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2833 uint32_t gerbm : 1; /* Grant ERBM Request */
2834 uint32_t gmx : 1; /* Grant Max XRIs */
2835 uint32_t gmr : 1; /* Grant Max RPIs */
2836 #else /* __LITTLE_ENDIAN */
2837 uint32_t gmr : 1; /* Grant Max RPIs */
2838 uint32_t gmx : 1; /* Grant Max XRIs */
2839 uint32_t gerbm : 1; /* Grant ERBM Request */
2840 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2841 uint32_t ghbs : 1; /* Grant Host Backing Store */
2842 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2843 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2844 uint32_t gmv : 1; /* Grant Max VPIs */
2845 uint32_t gbg : 1; /* Grant BlockGuard */
2846 uint32_t rsvd4 : 3; /* Reserved */
2847 uint32_t gdss : 1; /* Configure Data Security SLI */
2848 uint32_t rsvd3 : 19; /* Reserved */
2849 #endif
2850
2851 #ifdef __BIG_ENDIAN_BITFIELD
2852 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2853 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2854 #else /* __LITTLE_ENDIAN */
2855 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2856 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2857 #endif
2858
2859 #ifdef __BIG_ENDIAN_BITFIELD
2860 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2861 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2862 #else /* __LITTLE_ENDIAN */
2863 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2864 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2865 #endif
2866
2867 uint32_t rsvd6; /* Reserved */
2868
2869 #ifdef __BIG_ENDIAN_BITFIELD
2870 uint32_t fips_rev : 3; /* FIPS Spec Revision */
2871 uint32_t fips_level : 4; /* FIPS Level */
2872 uint32_t sec_err : 9; /* security crypto error */
2873 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2874 #else /* __LITTLE_ENDIAN */
2875 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2876 uint32_t sec_err : 9; /* security crypto error */
2877 uint32_t fips_level : 4; /* FIPS Level */
2878 uint32_t fips_rev : 3; /* FIPS Spec Revision */
2879 #endif
2880
2881 } CONFIG_PORT_VAR;
2882
2883 /* Structure for MB Command CONFIG_MSI (0x30) */
2884 struct config_msi_var {
2885 #ifdef __BIG_ENDIAN_BITFIELD
2886 uint32_t dfltMsgNum:8; /* Default message number */
2887 uint32_t rsvd1:11; /* Reserved */
2888 uint32_t NID:5; /* Number of secondary attention IDs */
2889 uint32_t rsvd2:5; /* Reserved */
2890 uint32_t dfltPresent:1; /* Default message number present */
2891 uint32_t addFlag:1; /* Add association flag */
2892 uint32_t reportFlag:1; /* Report association flag */
2893 #else /* __LITTLE_ENDIAN_BITFIELD */
2894 uint32_t reportFlag:1; /* Report association flag */
2895 uint32_t addFlag:1; /* Add association flag */
2896 uint32_t dfltPresent:1; /* Default message number present */
2897 uint32_t rsvd2:5; /* Reserved */
2898 uint32_t NID:5; /* Number of secondary attention IDs */
2899 uint32_t rsvd1:11; /* Reserved */
2900 uint32_t dfltMsgNum:8; /* Default message number */
2901 #endif
2902 uint32_t attentionConditions[2];
2903 uint8_t attentionId[16];
2904 uint8_t messageNumberByHA[64];
2905 uint8_t messageNumberByID[16];
2906 uint32_t autoClearHA[2];
2907 #ifdef __BIG_ENDIAN_BITFIELD
2908 uint32_t rsvd3:16;
2909 uint32_t autoClearID:16;
2910 #else /* __LITTLE_ENDIAN_BITFIELD */
2911 uint32_t autoClearID:16;
2912 uint32_t rsvd3:16;
2913 #endif
2914 uint32_t rsvd4;
2915 };
2916
2917 /* SLI-2 Port Control Block */
2918
2919 /* SLIM POINTER */
2920 #define SLIMOFF 0x30 /* WORD */
2921
2922 typedef struct _SLI2_RDSC {
2923 uint32_t cmdEntries;
2924 uint32_t cmdAddrLow;
2925 uint32_t cmdAddrHigh;
2926
2927 uint32_t rspEntries;
2928 uint32_t rspAddrLow;
2929 uint32_t rspAddrHigh;
2930 } SLI2_RDSC;
2931
2932 typedef struct _PCB {
2933 #ifdef __BIG_ENDIAN_BITFIELD
2934 uint32_t type:8;
2935 #define TYPE_NATIVE_SLI2 0x01;
2936 uint32_t feature:8;
2937 #define FEATURE_INITIAL_SLI2 0x01;
2938 uint32_t rsvd:12;
2939 uint32_t maxRing:4;
2940 #else /* __LITTLE_ENDIAN_BITFIELD */
2941 uint32_t maxRing:4;
2942 uint32_t rsvd:12;
2943 uint32_t feature:8;
2944 #define FEATURE_INITIAL_SLI2 0x01;
2945 uint32_t type:8;
2946 #define TYPE_NATIVE_SLI2 0x01;
2947 #endif
2948
2949 uint32_t mailBoxSize;
2950 uint32_t mbAddrLow;
2951 uint32_t mbAddrHigh;
2952
2953 uint32_t hgpAddrLow;
2954 uint32_t hgpAddrHigh;
2955
2956 uint32_t pgpAddrLow;
2957 uint32_t pgpAddrHigh;
2958 SLI2_RDSC rdsc[MAX_RINGS];
2959 } PCB_t;
2960
2961 /* NEW_FEATURE */
2962 typedef struct {
2963 #ifdef __BIG_ENDIAN_BITFIELD
2964 uint32_t rsvd0:27;
2965 uint32_t discardFarp:1;
2966 uint32_t IPEnable:1;
2967 uint32_t nodeName:1;
2968 uint32_t portName:1;
2969 uint32_t filterEnable:1;
2970 #else /* __LITTLE_ENDIAN_BITFIELD */
2971 uint32_t filterEnable:1;
2972 uint32_t portName:1;
2973 uint32_t nodeName:1;
2974 uint32_t IPEnable:1;
2975 uint32_t discardFarp:1;
2976 uint32_t rsvd:27;
2977 #endif
2978
2979 uint8_t portname[8]; /* Used to be struct lpfc_name */
2980 uint8_t nodename[8];
2981 uint32_t rsvd1;
2982 uint32_t rsvd2;
2983 uint32_t rsvd3;
2984 uint32_t IPAddress;
2985 } CONFIG_FARP_VAR;
2986
2987 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
2988
2989 typedef struct {
2990 #ifdef __BIG_ENDIAN_BITFIELD
2991 uint32_t rsvd:30;
2992 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2993 #else /* __LITTLE_ENDIAN */
2994 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2995 uint32_t rsvd:30;
2996 #endif
2997 } ASYNCEVT_ENABLE_VAR;
2998
2999 /* Union of all Mailbox Command types */
3000 #define MAILBOX_CMD_WSIZE 32
3001 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3002 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3003 #define MAILBOX_EXT_WSIZE 512
3004 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3005 #define MAILBOX_HBA_EXT_OFFSET 0x100
3006 /* max mbox xmit size is a page size for sysfs IO operations */
3007 #define MAILBOX_MAX_XMIT_SIZE PAGE_SIZE
3008
3009 typedef union {
3010 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3011 * feature/max ring number
3012 */
3013 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3014 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3015 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3016 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3017 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3018 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3019 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3020 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3021 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3022 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3023 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3024 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3025 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3026 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3027 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3028 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3029 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3030 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3031 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3032 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3033 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3034 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3035 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3036 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3037 * NEW_FEATURE
3038 */
3039 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3040 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3041 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3042 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3043 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3044 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3045 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3046 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3047 * (READ_EVENT_LOG)
3048 */
3049 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3050 } MAILVARIANTS;
3051
3052 /*
3053 * SLI-2 specific structures
3054 */
3055
3056 struct lpfc_hgp {
3057 __le32 cmdPutInx;
3058 __le32 rspGetInx;
3059 };
3060
3061 struct lpfc_pgp {
3062 __le32 cmdGetInx;
3063 __le32 rspPutInx;
3064 };
3065
3066 struct sli2_desc {
3067 uint32_t unused1[16];
3068 struct lpfc_hgp host[MAX_RINGS];
3069 struct lpfc_pgp port[MAX_RINGS];
3070 };
3071
3072 struct sli3_desc {
3073 struct lpfc_hgp host[MAX_RINGS];
3074 uint32_t reserved[8];
3075 uint32_t hbq_put[16];
3076 };
3077
3078 struct sli3_pgp {
3079 struct lpfc_pgp port[MAX_RINGS];
3080 uint32_t hbq_get[16];
3081 };
3082
3083 union sli_var {
3084 struct sli2_desc s2;
3085 struct sli3_desc s3;
3086 struct sli3_pgp s3_pgp;
3087 };
3088
3089 typedef struct {
3090 #ifdef __BIG_ENDIAN_BITFIELD
3091 uint16_t mbxStatus;
3092 uint8_t mbxCommand;
3093 uint8_t mbxReserved:6;
3094 uint8_t mbxHc:1;
3095 uint8_t mbxOwner:1; /* Low order bit first word */
3096 #else /* __LITTLE_ENDIAN_BITFIELD */
3097 uint8_t mbxOwner:1; /* Low order bit first word */
3098 uint8_t mbxHc:1;
3099 uint8_t mbxReserved:6;
3100 uint8_t mbxCommand;
3101 uint16_t mbxStatus;
3102 #endif
3103
3104 MAILVARIANTS un;
3105 union sli_var us;
3106 } MAILBOX_t;
3107
3108 /*
3109 * Begin Structure Definitions for IOCB Commands
3110 */
3111
3112 typedef struct {
3113 #ifdef __BIG_ENDIAN_BITFIELD
3114 uint8_t statAction;
3115 uint8_t statRsn;
3116 uint8_t statBaExp;
3117 uint8_t statLocalError;
3118 #else /* __LITTLE_ENDIAN_BITFIELD */
3119 uint8_t statLocalError;
3120 uint8_t statBaExp;
3121 uint8_t statRsn;
3122 uint8_t statAction;
3123 #endif
3124 /* statRsn P/F_RJT reason codes */
3125 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3126 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3127 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3128 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3129 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3130 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3131 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3132 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3133 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3134 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3135 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3136 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3137 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3138 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3139 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3140 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3141 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3142 #define RJT_PROT_ERR 0x12 /* Protocol error */
3143 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3144 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3145 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3146 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3147 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3148 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3149 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3150 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3151
3152 #define IOERR_SUCCESS 0x00 /* statLocalError */
3153 #define IOERR_MISSING_CONTINUE 0x01
3154 #define IOERR_SEQUENCE_TIMEOUT 0x02
3155 #define IOERR_INTERNAL_ERROR 0x03
3156 #define IOERR_INVALID_RPI 0x04
3157 #define IOERR_NO_XRI 0x05
3158 #define IOERR_ILLEGAL_COMMAND 0x06
3159 #define IOERR_XCHG_DROPPED 0x07
3160 #define IOERR_ILLEGAL_FIELD 0x08
3161 #define IOERR_BAD_CONTINUE 0x09
3162 #define IOERR_TOO_MANY_BUFFERS 0x0A
3163 #define IOERR_RCV_BUFFER_WAITING 0x0B
3164 #define IOERR_NO_CONNECTION 0x0C
3165 #define IOERR_TX_DMA_FAILED 0x0D
3166 #define IOERR_RX_DMA_FAILED 0x0E
3167 #define IOERR_ILLEGAL_FRAME 0x0F
3168 #define IOERR_EXTRA_DATA 0x10
3169 #define IOERR_NO_RESOURCES 0x11
3170 #define IOERR_RESERVED 0x12
3171 #define IOERR_ILLEGAL_LENGTH 0x13
3172 #define IOERR_UNSUPPORTED_FEATURE 0x14
3173 #define IOERR_ABORT_IN_PROGRESS 0x15
3174 #define IOERR_ABORT_REQUESTED 0x16
3175 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3176 #define IOERR_LOOP_OPEN_FAILURE 0x18
3177 #define IOERR_RING_RESET 0x19
3178 #define IOERR_LINK_DOWN 0x1A
3179 #define IOERR_CORRUPTED_DATA 0x1B
3180 #define IOERR_CORRUPTED_RPI 0x1C
3181 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3182 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3183 #define IOERR_DUP_FRAME 0x1F
3184 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3185 #define IOERR_BAD_HOST_ADDRESS 0x21
3186 #define IOERR_RCV_HDRBUF_WAITING 0x22
3187 #define IOERR_MISSING_HDR_BUFFER 0x23
3188 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3189 #define IOERR_ABORTMULT_REQUESTED 0x25
3190 #define IOERR_BUFFER_SHORTAGE 0x28
3191 #define IOERR_DEFAULT 0x29
3192 #define IOERR_CNT 0x2A
3193 #define IOERR_SLER_FAILURE 0x46
3194 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3195 #define IOERR_SLER_REC_RJT_ERR 0x48
3196 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3197 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3198 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3199 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3200 #define IOERR_SLER_ABTS_ERR 0x4E
3201
3202 #define IOERR_DRVR_MASK 0x100
3203 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3204 #define IOERR_SLI_BRESET 0x102
3205 #define IOERR_SLI_ABORTED 0x103
3206 } PARM_ERR;
3207
3208 typedef union {
3209 struct {
3210 #ifdef __BIG_ENDIAN_BITFIELD
3211 uint8_t Rctl; /* R_CTL field */
3212 uint8_t Type; /* TYPE field */
3213 uint8_t Dfctl; /* DF_CTL field */
3214 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3215 #else /* __LITTLE_ENDIAN_BITFIELD */
3216 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3217 uint8_t Dfctl; /* DF_CTL field */
3218 uint8_t Type; /* TYPE field */
3219 uint8_t Rctl; /* R_CTL field */
3220 #endif
3221
3222 #define BC 0x02 /* Broadcast Received - Fctl */
3223 #define SI 0x04 /* Sequence Initiative */
3224 #define LA 0x08 /* Ignore Link Attention state */
3225 #define LS 0x80 /* Last Sequence */
3226 } hcsw;
3227 uint32_t reserved;
3228 } WORD5;
3229
3230 /* IOCB Command template for a generic response */
3231 typedef struct {
3232 uint32_t reserved[4];
3233 PARM_ERR perr;
3234 } GENERIC_RSP;
3235
3236 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3237 typedef struct {
3238 struct ulp_bde xrsqbde[2];
3239 uint32_t xrsqRo; /* Starting Relative Offset */
3240 WORD5 w5; /* Header control/status word */
3241 } XR_SEQ_FIELDS;
3242
3243 /* IOCB Command template for ELS_REQUEST */
3244 typedef struct {
3245 struct ulp_bde elsReq;
3246 struct ulp_bde elsRsp;
3247
3248 #ifdef __BIG_ENDIAN_BITFIELD
3249 uint32_t word4Rsvd:7;
3250 uint32_t fl:1;
3251 uint32_t myID:24;
3252 uint32_t word5Rsvd:8;
3253 uint32_t remoteID:24;
3254 #else /* __LITTLE_ENDIAN_BITFIELD */
3255 uint32_t myID:24;
3256 uint32_t fl:1;
3257 uint32_t word4Rsvd:7;
3258 uint32_t remoteID:24;
3259 uint32_t word5Rsvd:8;
3260 #endif
3261 } ELS_REQUEST;
3262
3263 /* IOCB Command template for RCV_ELS_REQ */
3264 typedef struct {
3265 struct ulp_bde elsReq[2];
3266 uint32_t parmRo;
3267
3268 #ifdef __BIG_ENDIAN_BITFIELD
3269 uint32_t word5Rsvd:8;
3270 uint32_t remoteID:24;
3271 #else /* __LITTLE_ENDIAN_BITFIELD */
3272 uint32_t remoteID:24;
3273 uint32_t word5Rsvd:8;
3274 #endif
3275 } RCV_ELS_REQ;
3276
3277 /* IOCB Command template for ABORT / CLOSE_XRI */
3278 typedef struct {
3279 uint32_t rsvd[3];
3280 uint32_t abortType;
3281 #define ABORT_TYPE_ABTX 0x00000000
3282 #define ABORT_TYPE_ABTS 0x00000001
3283 uint32_t parm;
3284 #ifdef __BIG_ENDIAN_BITFIELD
3285 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3286 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3287 #else /* __LITTLE_ENDIAN_BITFIELD */
3288 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3289 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3290 #endif
3291 } AC_XRI;
3292
3293 /* IOCB Command template for ABORT_MXRI64 */
3294 typedef struct {
3295 uint32_t rsvd[3];
3296 uint32_t abortType;
3297 uint32_t parm;
3298 uint32_t iotag32;
3299 } A_MXRI64;
3300
3301 /* IOCB Command template for GET_RPI */
3302 typedef struct {
3303 uint32_t rsvd[4];
3304 uint32_t parmRo;
3305 #ifdef __BIG_ENDIAN_BITFIELD
3306 uint32_t word5Rsvd:8;
3307 uint32_t remoteID:24;
3308 #else /* __LITTLE_ENDIAN_BITFIELD */
3309 uint32_t remoteID:24;
3310 uint32_t word5Rsvd:8;
3311 #endif
3312 } GET_RPI;
3313
3314 /* IOCB Command template for all FCP Initiator commands */
3315 typedef struct {
3316 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3317 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3318 uint32_t fcpi_parm;
3319 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3320 } FCPI_FIELDS;
3321
3322 /* IOCB Command template for all FCP Target commands */
3323 typedef struct {
3324 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3325 uint32_t fcpt_Offset;
3326 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3327 } FCPT_FIELDS;
3328
3329 /* SLI-2 IOCB structure definitions */
3330
3331 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3332 typedef struct {
3333 ULP_BDL bdl;
3334 uint32_t xrsqRo; /* Starting Relative Offset */
3335 WORD5 w5; /* Header control/status word */
3336 } XMT_SEQ_FIELDS64;
3337
3338 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3339 typedef struct {
3340 struct ulp_bde64 rcvBde;
3341 uint32_t rsvd1;
3342 uint32_t xrsqRo; /* Starting Relative Offset */
3343 WORD5 w5; /* Header control/status word */
3344 } RCV_SEQ_FIELDS64;
3345
3346 /* IOCB Command template for ELS_REQUEST64 */
3347 typedef struct {
3348 ULP_BDL bdl;
3349 #ifdef __BIG_ENDIAN_BITFIELD
3350 uint32_t word4Rsvd:7;
3351 uint32_t fl:1;
3352 uint32_t myID:24;
3353 uint32_t word5Rsvd:8;
3354 uint32_t remoteID:24;
3355 #else /* __LITTLE_ENDIAN_BITFIELD */
3356 uint32_t myID:24;
3357 uint32_t fl:1;
3358 uint32_t word4Rsvd:7;
3359 uint32_t remoteID:24;
3360 uint32_t word5Rsvd:8;
3361 #endif
3362 } ELS_REQUEST64;
3363
3364 /* IOCB Command template for GEN_REQUEST64 */
3365 typedef struct {
3366 ULP_BDL bdl;
3367 uint32_t xrsqRo; /* Starting Relative Offset */
3368 WORD5 w5; /* Header control/status word */
3369 } GEN_REQUEST64;
3370
3371 /* IOCB Command template for RCV_ELS_REQ64 */
3372 typedef struct {
3373 struct ulp_bde64 elsReq;
3374 uint32_t rcvd1;
3375 uint32_t parmRo;
3376
3377 #ifdef __BIG_ENDIAN_BITFIELD
3378 uint32_t word5Rsvd:8;
3379 uint32_t remoteID:24;
3380 #else /* __LITTLE_ENDIAN_BITFIELD */
3381 uint32_t remoteID:24;
3382 uint32_t word5Rsvd:8;
3383 #endif
3384 } RCV_ELS_REQ64;
3385
3386 /* IOCB Command template for RCV_SEQ64 */
3387 struct rcv_seq64 {
3388 struct ulp_bde64 elsReq;
3389 uint32_t hbq_1;
3390 uint32_t parmRo;
3391 #ifdef __BIG_ENDIAN_BITFIELD
3392 uint32_t rctl:8;
3393 uint32_t type:8;
3394 uint32_t dfctl:8;
3395 uint32_t ls:1;
3396 uint32_t fs:1;
3397 uint32_t rsvd2:3;
3398 uint32_t si:1;
3399 uint32_t bc:1;
3400 uint32_t rsvd3:1;
3401 #else /* __LITTLE_ENDIAN_BITFIELD */
3402 uint32_t rsvd3:1;
3403 uint32_t bc:1;
3404 uint32_t si:1;
3405 uint32_t rsvd2:3;
3406 uint32_t fs:1;
3407 uint32_t ls:1;
3408 uint32_t dfctl:8;
3409 uint32_t type:8;
3410 uint32_t rctl:8;
3411 #endif
3412 };
3413
3414 /* IOCB Command template for all 64 bit FCP Initiator commands */
3415 typedef struct {
3416 ULP_BDL bdl;
3417 uint32_t fcpi_parm;
3418 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3419 } FCPI_FIELDS64;
3420
3421 /* IOCB Command template for all 64 bit FCP Target commands */
3422 typedef struct {
3423 ULP_BDL bdl;
3424 uint32_t fcpt_Offset;
3425 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3426 } FCPT_FIELDS64;
3427
3428 /* IOCB Command template for Async Status iocb commands */
3429 typedef struct {
3430 uint32_t rsvd[4];
3431 uint32_t param;
3432 #ifdef __BIG_ENDIAN_BITFIELD
3433 uint16_t evt_code; /* High order bits word 5 */
3434 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3435 #else /* __LITTLE_ENDIAN_BITFIELD */
3436 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3437 uint16_t evt_code; /* Low order bits word 5 */
3438 #endif
3439 } ASYNCSTAT_FIELDS;
3440 #define ASYNC_TEMP_WARN 0x100
3441 #define ASYNC_TEMP_SAFE 0x101
3442
3443 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3444 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3445
3446 struct rcv_sli3 {
3447 uint32_t word8Rsvd;
3448 #ifdef __BIG_ENDIAN_BITFIELD
3449 uint16_t vpi;
3450 uint16_t word9Rsvd;
3451 #else /* __LITTLE_ENDIAN */
3452 uint16_t word9Rsvd;
3453 uint16_t vpi;
3454 #endif
3455 uint32_t word10Rsvd;
3456 uint32_t acc_len; /* accumulated length */
3457 struct ulp_bde64 bde2;
3458 };
3459
3460 /* Structure used for a single HBQ entry */
3461 struct lpfc_hbq_entry {
3462 struct ulp_bde64 bde;
3463 uint32_t buffer_tag;
3464 };
3465
3466 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3467 typedef struct {
3468 struct lpfc_hbq_entry buff;
3469 uint32_t rsvd;
3470 uint32_t rsvd1;
3471 } QUE_XRI64_CX_FIELDS;
3472
3473 struct que_xri64cx_ext_fields {
3474 uint32_t iotag64_low;
3475 uint32_t iotag64_high;
3476 uint32_t ebde_count;
3477 uint32_t rsvd;
3478 struct lpfc_hbq_entry buff[5];
3479 };
3480
3481 struct sli3_bg_fields {
3482 uint32_t filler[6]; /* word 8-13 in IOCB */
3483 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3484 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3485 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3486 #define BGS_BIDIR_BG_PROF_SHIFT 24
3487 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3488 #define BGS_BIDIR_ERR_COND_SHIFT 16
3489 #define BGS_BG_PROFILE_MASK 0x0000ff00
3490 #define BGS_BG_PROFILE_SHIFT 8
3491 #define BGS_INVALID_PROF_MASK 0x00000020
3492 #define BGS_INVALID_PROF_SHIFT 5
3493 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3494 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3495 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3496 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3497 #define BGS_REFTAG_ERR_MASK 0x00000004
3498 #define BGS_REFTAG_ERR_SHIFT 2
3499 #define BGS_APPTAG_ERR_MASK 0x00000002
3500 #define BGS_APPTAG_ERR_SHIFT 1
3501 #define BGS_GUARD_ERR_MASK 0x00000001
3502 #define BGS_GUARD_ERR_SHIFT 0
3503 uint32_t bgstat; /* word 15 - BlockGuard Status */
3504 };
3505
3506 static inline uint32_t
3507 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3508 {
3509 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3510 BGS_BIDIR_BG_PROF_SHIFT;
3511 }
3512
3513 static inline uint32_t
3514 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3515 {
3516 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3517 BGS_BIDIR_ERR_COND_SHIFT;
3518 }
3519
3520 static inline uint32_t
3521 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3522 {
3523 return (bgstat & BGS_BG_PROFILE_MASK) >>
3524 BGS_BG_PROFILE_SHIFT;
3525 }
3526
3527 static inline uint32_t
3528 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3529 {
3530 return (bgstat & BGS_INVALID_PROF_MASK) >>
3531 BGS_INVALID_PROF_SHIFT;
3532 }
3533
3534 static inline uint32_t
3535 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3536 {
3537 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3538 BGS_UNINIT_DIF_BLOCK_SHIFT;
3539 }
3540
3541 static inline uint32_t
3542 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3543 {
3544 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3545 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3546 }
3547
3548 static inline uint32_t
3549 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3550 {
3551 return (bgstat & BGS_REFTAG_ERR_MASK) >>
3552 BGS_REFTAG_ERR_SHIFT;
3553 }
3554
3555 static inline uint32_t
3556 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3557 {
3558 return (bgstat & BGS_APPTAG_ERR_MASK) >>
3559 BGS_APPTAG_ERR_SHIFT;
3560 }
3561
3562 static inline uint32_t
3563 lpfc_bgs_get_guard_err(uint32_t bgstat)
3564 {
3565 return (bgstat & BGS_GUARD_ERR_MASK) >>
3566 BGS_GUARD_ERR_SHIFT;
3567 }
3568
3569 #define LPFC_EXT_DATA_BDE_COUNT 3
3570 struct fcp_irw_ext {
3571 uint32_t io_tag64_low;
3572 uint32_t io_tag64_high;
3573 #ifdef __BIG_ENDIAN_BITFIELD
3574 uint8_t reserved1;
3575 uint8_t reserved2;
3576 uint8_t reserved3;
3577 uint8_t ebde_count;
3578 #else /* __LITTLE_ENDIAN */
3579 uint8_t ebde_count;
3580 uint8_t reserved3;
3581 uint8_t reserved2;
3582 uint8_t reserved1;
3583 #endif
3584 uint32_t reserved4;
3585 struct ulp_bde64 rbde; /* response bde */
3586 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3587 uint8_t icd[32]; /* immediate command data (32 bytes) */
3588 };
3589
3590 typedef struct _IOCB { /* IOCB structure */
3591 union {
3592 GENERIC_RSP grsp; /* Generic response */
3593 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3594 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3595 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3596 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3597 A_MXRI64 amxri; /* abort multiple xri command overlay */
3598 GET_RPI getrpi; /* GET_RPI template */
3599 FCPI_FIELDS fcpi; /* FCP Initiator template */
3600 FCPT_FIELDS fcpt; /* FCP target template */
3601
3602 /* SLI-2 structures */
3603
3604 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3605 * bde_64s */
3606 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3607 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3608 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3609 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3610 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3611 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3612 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3613 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3614 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3615 struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */
3616 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3617 } un;
3618 union {
3619 struct {
3620 #ifdef __BIG_ENDIAN_BITFIELD
3621 uint16_t ulpContext; /* High order bits word 6 */
3622 uint16_t ulpIoTag; /* Low order bits word 6 */
3623 #else /* __LITTLE_ENDIAN_BITFIELD */
3624 uint16_t ulpIoTag; /* Low order bits word 6 */
3625 uint16_t ulpContext; /* High order bits word 6 */
3626 #endif
3627 } t1;
3628 struct {
3629 #ifdef __BIG_ENDIAN_BITFIELD
3630 uint16_t ulpContext; /* High order bits word 6 */
3631 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3632 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3633 #else /* __LITTLE_ENDIAN_BITFIELD */
3634 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3635 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3636 uint16_t ulpContext; /* High order bits word 6 */
3637 #endif
3638 } t2;
3639 } un1;
3640 #define ulpContext un1.t1.ulpContext
3641 #define ulpIoTag un1.t1.ulpIoTag
3642 #define ulpIoTag0 un1.t2.ulpIoTag0
3643
3644 #ifdef __BIG_ENDIAN_BITFIELD
3645 uint32_t ulpTimeout:8;
3646 uint32_t ulpXS:1;
3647 uint32_t ulpFCP2Rcvy:1;
3648 uint32_t ulpPU:2;
3649 uint32_t ulpIr:1;
3650 uint32_t ulpClass:3;
3651 uint32_t ulpCommand:8;
3652 uint32_t ulpStatus:4;
3653 uint32_t ulpBdeCount:2;
3654 uint32_t ulpLe:1;
3655 uint32_t ulpOwner:1; /* Low order bit word 7 */
3656 #else /* __LITTLE_ENDIAN_BITFIELD */
3657 uint32_t ulpOwner:1; /* Low order bit word 7 */
3658 uint32_t ulpLe:1;
3659 uint32_t ulpBdeCount:2;
3660 uint32_t ulpStatus:4;
3661 uint32_t ulpCommand:8;
3662 uint32_t ulpClass:3;
3663 uint32_t ulpIr:1;
3664 uint32_t ulpPU:2;
3665 uint32_t ulpFCP2Rcvy:1;
3666 uint32_t ulpXS:1;
3667 uint32_t ulpTimeout:8;
3668 #endif
3669
3670 union {
3671 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3672
3673 /* words 8-31 used for que_xri_cx iocb */
3674 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3675 struct fcp_irw_ext fcp_ext;
3676 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3677
3678 /* words 8-15 for BlockGuard */
3679 struct sli3_bg_fields sli3_bg;
3680 } unsli3;
3681
3682 #define ulpCt_h ulpXS
3683 #define ulpCt_l ulpFCP2Rcvy
3684
3685 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3686 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3687 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3688 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3689 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3690 #define PARM_NPIV_DID 3
3691 #define CLASS1 0 /* Class 1 */
3692 #define CLASS2 1 /* Class 2 */
3693 #define CLASS3 2 /* Class 3 */
3694 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3695
3696 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3697 #define IOSTAT_FCP_RSP_ERROR 0x1
3698 #define IOSTAT_REMOTE_STOP 0x2
3699 #define IOSTAT_LOCAL_REJECT 0x3
3700 #define IOSTAT_NPORT_RJT 0x4
3701 #define IOSTAT_FABRIC_RJT 0x5
3702 #define IOSTAT_NPORT_BSY 0x6
3703 #define IOSTAT_FABRIC_BSY 0x7
3704 #define IOSTAT_INTERMED_RSP 0x8
3705 #define IOSTAT_LS_RJT 0x9
3706 #define IOSTAT_BA_RJT 0xA
3707 #define IOSTAT_RSVD1 0xB
3708 #define IOSTAT_RSVD2 0xC
3709 #define IOSTAT_RSVD3 0xD
3710 #define IOSTAT_RSVD4 0xE
3711 #define IOSTAT_NEED_BUFFER 0xF
3712 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3713 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3714 #define IOSTAT_CNT 0x11
3715
3716 } IOCB_t;
3717
3718
3719 #define SLI1_SLIM_SIZE (4 * 1024)
3720
3721 /* Up to 498 IOCBs will fit into 16k
3722 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3723 */
3724 #define SLI2_SLIM_SIZE (64 * 1024)
3725
3726 /* Maximum IOCBs that will fit in SLI2 slim */
3727 #define MAX_SLI2_IOCB 498
3728 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3729 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3730 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3731
3732 /* HBQ entries are 4 words each = 4k */
3733 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3734 lpfc_sli_hbq_count())
3735
3736 struct lpfc_sli2_slim {
3737 MAILBOX_t mbx;
3738 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
3739 PCB_t pcb;
3740 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3741 };
3742
3743 /*
3744 * This function checks PCI device to allow special handling for LC HBAs.
3745 *
3746 * Parameters:
3747 * device : struct pci_dev 's device field
3748 *
3749 * return 1 => TRUE
3750 * 0 => FALSE
3751 */
3752 static inline int
3753 lpfc_is_LC_HBA(unsigned short device)
3754 {
3755 if ((device == PCI_DEVICE_ID_TFLY) ||
3756 (device == PCI_DEVICE_ID_PFLY) ||
3757 (device == PCI_DEVICE_ID_LP101) ||
3758 (device == PCI_DEVICE_ID_BMID) ||
3759 (device == PCI_DEVICE_ID_BSMB) ||
3760 (device == PCI_DEVICE_ID_ZMID) ||
3761 (device == PCI_DEVICE_ID_ZSMB) ||
3762 (device == PCI_DEVICE_ID_SAT_MID) ||
3763 (device == PCI_DEVICE_ID_SAT_SMB) ||
3764 (device == PCI_DEVICE_ID_RFLY))
3765 return 1;
3766 else
3767 return 0;
3768 }
3769
3770 /*
3771 * Determine if an IOCB failed because of a link event or firmware reset.
3772 */
3773
3774 static inline int
3775 lpfc_error_lost_link(IOCB_t *iocbp)
3776 {
3777 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3778 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3779 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3780 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3781 }
3782
3783 #define MENLO_TRANSPORT_TYPE 0xfe
3784 #define MENLO_CONTEXT 0
3785 #define MENLO_PU 3
3786 #define MENLO_TIMEOUT 30
3787 #define SETVAR_MLOMNT 0x103107
3788 #define SETVAR_MLORST 0x103007
3789
3790 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */