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usb: otg: mv_otg: Add dependence
[zen-stable.git] / drivers / edac / i82975x_edac.c
blob4184e0171f0079ccc09f63f39bdbfccac1a3b474
1 /*
2 * Intel 82975X Memory Controller kernel module
3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Arvind R.
9 * Copied from i82875p_edac.c source:
10 */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
18
19 #define I82975X_REVISION " Ver: 1.0.0"
20 #define EDAC_MOD_STR "i82975x_edac"
21
22 #define i82975x_printk(level, fmt, arg...) \
23 edac_printk(level, "i82975x", fmt, ##arg)
24
25 #define i82975x_mc_printk(mci, level, fmt, arg...) \
26 edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
27
28 #ifndef PCI_DEVICE_ID_INTEL_82975_0
29 #define PCI_DEVICE_ID_INTEL_82975_0 0x277c
30 #endif /* PCI_DEVICE_ID_INTEL_82975_0 */
31
32 #define I82975X_NR_CSROWS(nr_chans) (8/(nr_chans))
33
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
36 *
37 * 31:7 128 byte cache-line address
38 * 6:1 reserved
39 * 0 0: CH0; 1: CH1
40 */
41
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
43 *
44 * 7:0 DRAM ECC Syndrome
45 */
46
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
48 * 0h: Processor Memory Reads
49 * 1h:7h reserved
50 * More - See Page 65 of Intel DocSheet.
51 */
52
53 #define I82975X_ERRSTS 0xc8 /* Error Status Register (16b)
54 *
55 * 15:12 reserved
56 * 11 Thermal Sensor Event
57 * 10 reserved
58 * 9 non-DRAM lock error (ndlock)
59 * 8 Refresh Timeout
60 * 7:2 reserved
61 * 1 ECC UE (multibit DRAM error)
62 * 0 ECC CE (singlebit DRAM error)
63 */
64
65 /* Error Reporting is supported by 3 mechanisms:
66 1. DMI SERR generation ( ERRCMD )
67 2. SMI DMI generation ( SMICMD )
68 3. SCI DMI generation ( SCICMD )
69 NOTE: Only ONE of the three must be enabled
70 */
71 #define I82975X_ERRCMD 0xca /* Error Command (16b)
72 *
73 * 15:12 reserved
74 * 11 Thermal Sensor Event
75 * 10 reserved
76 * 9 non-DRAM lock error (ndlock)
77 * 8 Refresh Timeout
78 * 7:2 reserved
79 * 1 ECC UE (multibit DRAM error)
80 * 0 ECC CE (singlebit DRAM error)
81 */
82
83 #define I82975X_SMICMD 0xcc /* Error Command (16b)
84 *
85 * 15:2 reserved
86 * 1 ECC UE (multibit DRAM error)
87 * 0 ECC CE (singlebit DRAM error)
88 */
89
90 #define I82975X_SCICMD 0xce /* Error Command (16b)
91 *
92 * 15:2 reserved
93 * 1 ECC UE (multibit DRAM error)
94 * 0 ECC CE (singlebit DRAM error)
95 */
96
97 #define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b)
98 *
99 * 7:1 reserved
100 * 0 Bit32 of the Dram Error Address
101 */
102
103 #define I82975X_MCHBAR 0x44 /*
104 *
105 * 31:14 Base Addr of 16K memory-mapped
106 * configuration space
107 * 13:1 reserverd
108 * 0 mem-mapped config space enable
109 */
110
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
112 /* Intel 82975x memory mapped register space */
113
114 #define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */
115
116 #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
117 *
118 * 7 set to 1 in highest DRB of
119 * channel if 4GB in ch.
120 * 6:2 upper boundary of rank in
121 * 32MB grains
122 * 1:0 set to 0
123 */
124 #define I82975X_DRB_CH0R0 0x100
125 #define I82975X_DRB_CH0R1 0x101
126 #define I82975X_DRB_CH0R2 0x102
127 #define I82975X_DRB_CH0R3 0x103
128 #define I82975X_DRB_CH1R0 0x180
129 #define I82975X_DRB_CH1R1 0x181
130 #define I82975X_DRB_CH1R2 0x182
131 #define I82975X_DRB_CH1R3 0x183
132
133
134 #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
135 * defines the PAGE SIZE to be used
136 * for the rank
137 * 7 reserved
138 * 6:4 row attr of odd rank, i.e. 1
139 * 3 reserved
140 * 2:0 row attr of even rank, i.e. 0
141 *
142 * 000 = unpopulated
143 * 001 = reserved
144 * 010 = 4KiB
145 * 011 = 8KiB
146 * 100 = 16KiB
147 * others = reserved
148 */
149 #define I82975X_DRA_CH0R01 0x108
150 #define I82975X_DRA_CH0R23 0x109
151 #define I82975X_DRA_CH1R01 0x188
152 #define I82975X_DRA_CH1R23 0x189
153
154
155 #define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b)
156 *
157 * 15:8 reserved
158 * 7:6 Rank 3 architecture
159 * 5:4 Rank 2 architecture
160 * 3:2 Rank 1 architecture
161 * 1:0 Rank 0 architecture
162 *
163 * 00 => 4 banks
164 * 01 => 8 banks
165 */
166 #define I82975X_C0BNKARC 0x10e
167 #define I82975X_C1BNKARC 0x18e
168
169
170
171 #define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b)
172 *
173 * 31:30 reserved
174 * 29 init complete
175 * 28:11 reserved, according to Intel
176 * 22:21 number of channels
177 * 00=1 01=2 in 82875
178 * seems to be ECC mode
179 * bits in 82975 in Asus
180 * P5W
181 * 19:18 Data Integ Mode
182 * 00=none 01=ECC in 82875
183 * 10:8 refresh mode
184 * 7 reserved
185 * 6:4 mode select
186 * 3:2 reserved
187 * 1:0 DRAM type 10=Second Revision
188 * DDR2 SDRAM
189 * 00, 01, 11 reserved
190 */
191 #define I82975X_DRC_CH0M0 0x120
192 #define I82975X_DRC_CH1M0 0x1A0
193
194
195 #define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b)
196 * 31 0=Standard Address Map
197 * 1=Enhanced Address Map
198 * 30:0 reserved
199 */
200
201 #define I82975X_DRC_CH0M1 0x124
202 #define I82975X_DRC_CH1M1 0x1A4
203
204 enum i82975x_chips {
205 I82975X = 0,
206 };
207
208 struct i82975x_pvt {
209 void __iomem *mch_window;
210 };
211
212 struct i82975x_dev_info {
213 const char *ctl_name;
214 };
215
216 struct i82975x_error_info {
217 u16 errsts;
218 u32 eap;
219 u8 des;
220 u8 derrsyn;
221 u16 errsts2;
222 u8 chan; /* the channel is bit 0 of EAP */
223 u8 xeap; /* extended eap bit */
224 };
225
226 static const struct i82975x_dev_info i82975x_devs[] = {
227 [I82975X] = {
228 .ctl_name = "i82975x"
229 },
230 };
231
232 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
233 * already registered driver
234 */
235
236 static int i82975x_registered = 1;
237
238 static void i82975x_get_error_info(struct mem_ctl_info *mci,
239 struct i82975x_error_info *info)
240 {
241 struct pci_dev *pdev;
242
243 pdev = to_pci_dev(mci->dev);
244
245 /*
246 * This is a mess because there is no atomic way to read all the
247 * registers at once and the registers can transition from CE being
248 * overwritten by UE.
249 */
250 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
251 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
252 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
253 pci_read_config_byte(pdev, I82975X_DES, &info->des);
254 pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
255 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
256
257 pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
258
259 /*
260 * If the error is the same then we can for both reads then
261 * the first set of reads is valid. If there is a change then
262 * there is a CE no info and the second set of reads is valid
263 * and should be UE info.
264 */
265 if (!(info->errsts2 & 0x0003))
266 return;
267
268 if ((info->errsts ^ info->errsts2) & 0x0003) {
269 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
270 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
271 pci_read_config_byte(pdev, I82975X_DES, &info->des);
272 pci_read_config_byte(pdev, I82975X_DERRSYN,
273 &info->derrsyn);
274 }
275 }
276
277 static int i82975x_process_error_info(struct mem_ctl_info *mci,
278 struct i82975x_error_info *info, int handle_errors)
279 {
280 int row, chan;
281 unsigned long offst, page;
282
283 if (!(info->errsts2 & 0x0003))
284 return 0;
285
286 if (!handle_errors)
287 return 1;
288
289 if ((info->errsts ^ info->errsts2) & 0x0003) {
290 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
291 info->errsts = info->errsts2;
292 }
293
294 page = (unsigned long) info->eap;
295 page >>= 1;
296 if (info->xeap & 1)
297 page |= 0x80000000;
298 page >>= (PAGE_SHIFT - 1);
299 row = edac_mc_find_csrow_by_page(mci, page);
300
301 if (row == -1) {
302 i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
303 "\tXEAP=%u\n"
304 "\t EAP=0x%08x\n"
305 "\tPAGE=0x%08x\n",
306 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
307 return 0;
308 }
309 chan = (mci->csrows[row].nr_channels == 1) ? 0 : info->eap & 1;
310 offst = info->eap
311 & ((1 << PAGE_SHIFT) -
312 (1 << mci->csrows[row].grain));
313
314 if (info->errsts & 0x0002)
315 edac_mc_handle_ue(mci, page, offst , row, "i82975x UE");
316 else
317 edac_mc_handle_ce(mci, page, offst, info->derrsyn, row,
318 chan, "i82975x CE");
319
320 return 1;
321 }
322
323 static void i82975x_check(struct mem_ctl_info *mci)
324 {
325 struct i82975x_error_info info;
326
327 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
328 i82975x_get_error_info(mci, &info);
329 i82975x_process_error_info(mci, &info, 1);
330 }
331
332 /* Return 1 if dual channel mode is active. Else return 0. */
333 static int dual_channel_active(void __iomem *mch_window)
334 {
335 /*
336 * We treat interleaved-symmetric configuration as dual-channel - EAP's
337 * bit-0 giving the channel of the error location.
338 *
339 * All other configurations are treated as single channel - the EAP's
340 * bit-0 will resolve ok in symmetric area of mixed
341 * (symmetric/asymmetric) configurations
342 */
343 u8 drb[4][2];
344 int row;
345 int dualch;
346
347 for (dualch = 1, row = 0; dualch && (row < 4); row++) {
348 drb[row][0] = readb(mch_window + I82975X_DRB + row);
349 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
350 dualch = dualch && (drb[row][0] == drb[row][1]);
351 }
352 return dualch;
353 }
354
355 static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
356 {
357 /*
358 * ECC is possible on i92975x ONLY with DEV_X8
359 */
360 return DEV_X8;
361 }
362
363 static void i82975x_init_csrows(struct mem_ctl_info *mci,
364 struct pci_dev *pdev, void __iomem *mch_window)
365 {
366 static const char *labels[4] = {
367 "DIMM A1", "DIMM A2",
368 "DIMM B1", "DIMM B2"
369 };
370 struct csrow_info *csrow;
371 unsigned long last_cumul_size;
372 u8 value;
373 u32 cumul_size;
374 int index, chan;
375
376 last_cumul_size = 0;
377
378 /*
379 * 82875 comment:
380 * The dram row boundary (DRB) reg values are boundary address
381 * for each DRAM row with a granularity of 32 or 64MB (single/dual
382 * channel operation). DRB regs are cumulative; therefore DRB7 will
383 * contain the total memory contained in all rows.
384 *
385 */
386
387 for (index = 0; index < mci->nr_csrows; index++) {
388 csrow = &mci->csrows[index];
389
390 value = readb(mch_window + I82975X_DRB + index +
391 ((index >= 4) ? 0x80 : 0));
392 cumul_size = value;
393 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
394 /*
395 * Adjust cumul_size w.r.t number of channels
396 *
397 */
398 if (csrow->nr_channels > 1)
399 cumul_size <<= 1;
400 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
401 cumul_size);
402
403 /*
404 * Initialise dram labels
405 * index values:
406 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
407 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
408 */
409 for (chan = 0; chan < csrow->nr_channels; chan++)
410 strncpy(csrow->channels[chan].label,
411 labels[(index >> 1) + (chan * 2)],
412 EDAC_MC_LABEL_LEN);
413
414 if (cumul_size == last_cumul_size)
415 continue; /* not populated */
416
417 csrow->first_page = last_cumul_size;
418 csrow->last_page = cumul_size - 1;
419 csrow->nr_pages = cumul_size - last_cumul_size;
420 last_cumul_size = cumul_size;
421 csrow->grain = 1 << 7; /* 128Byte cache-line resolution */
422 csrow->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
423 csrow->dtype = i82975x_dram_type(mch_window, index);
424 csrow->edac_mode = EDAC_SECDED; /* only supported */
425 }
426 }
427
428 /* #define i82975x_DEBUG_IOMEM */
429
430 #ifdef i82975x_DEBUG_IOMEM
431 static void i82975x_print_dram_timings(void __iomem *mch_window)
432 {
433 /*
434 * The register meanings are from Intel specs;
435 * (shows 13-5-5-5 for 800-DDR2)
436 * Asus P5W Bios reports 15-5-4-4
437 * What's your religion?
438 */
439 static const int caslats[4] = { 5, 4, 3, 6 };
440 u32 dtreg[2];
441
442 dtreg[0] = readl(mch_window + 0x114);
443 dtreg[1] = readl(mch_window + 0x194);
444 i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n"
445 " RAS Active Min = %d %d\n"
446 " CAS latency = %d %d\n"
447 " RAS to CAS = %d %d\n"
448 " RAS precharge = %d %d\n",
449 (dtreg[0] >> 19 ) & 0x0f,
450 (dtreg[1] >> 19) & 0x0f,
451 caslats[(dtreg[0] >> 8) & 0x03],
452 caslats[(dtreg[1] >> 8) & 0x03],
453 ((dtreg[0] >> 4) & 0x07) + 2,
454 ((dtreg[1] >> 4) & 0x07) + 2,
455 (dtreg[0] & 0x07) + 2,
456 (dtreg[1] & 0x07) + 2
457 );
458
459 }
460 #endif
461
462 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
463 {
464 int rc = -ENODEV;
465 struct mem_ctl_info *mci;
466 struct i82975x_pvt *pvt;
467 void __iomem *mch_window;
468 u32 mchbar;
469 u32 drc[2];
470 struct i82975x_error_info discard;
471 int chans;
472 #ifdef i82975x_DEBUG_IOMEM
473 u8 c0drb[4];
474 u8 c1drb[4];
475 #endif
476
477 debugf0("%s()\n", __func__);
478
479 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
480 if (!(mchbar & 1)) {
481 debugf3("%s(): failed, MCHBAR disabled!\n", __func__);
482 goto fail0;
483 }
484 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */
485 mch_window = ioremap_nocache(mchbar, 0x1000);
486
487 #ifdef i82975x_DEBUG_IOMEM
488 i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
489 mchbar, mch_window);
490
491 c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
492 c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
493 c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
494 c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
495 c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
496 c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
497 c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
498 c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
499 i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
500 i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
501 i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
502 i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
503 i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
504 i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
505 i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
506 i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
507 #endif
508
509 drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
510 drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
511 #ifdef i82975x_DEBUG_IOMEM
512 i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
513 ((drc[0] >> 21) & 3) == 1 ?
514 "ECC enabled" : "ECC disabled");
515 i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
516 ((drc[1] >> 21) & 3) == 1 ?
517 "ECC enabled" : "ECC disabled");
518
519 i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
520 readw(mch_window + I82975X_C0BNKARC));
521 i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
522 readw(mch_window + I82975X_C1BNKARC));
523 i82975x_print_dram_timings(mch_window);
524 goto fail1;
525 #endif
526 if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
527 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
528 goto fail1;
529 }
530
531 chans = dual_channel_active(mch_window) + 1;
532
533 /* assuming only one controller, index thus is 0 */
534 mci = edac_mc_alloc(sizeof(*pvt), I82975X_NR_CSROWS(chans),
535 chans, 0);
536 if (!mci) {
537 rc = -ENOMEM;
538 goto fail1;
539 }
540
541 debugf3("%s(): init mci\n", __func__);
542 mci->dev = &pdev->dev;
543 mci->mtype_cap = MEM_FLAG_DDR2;
544 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
545 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
546 mci->mod_name = EDAC_MOD_STR;
547 mci->mod_ver = I82975X_REVISION;
548 mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
549 mci->dev_name = pci_name(pdev);
550 mci->edac_check = i82975x_check;
551 mci->ctl_page_to_phys = NULL;
552 debugf3("%s(): init pvt\n", __func__);
553 pvt = (struct i82975x_pvt *) mci->pvt_info;
554 pvt->mch_window = mch_window;
555 i82975x_init_csrows(mci, pdev, mch_window);
556 mci->scrub_mode = SCRUB_HW_SRC;
557 i82975x_get_error_info(mci, &discard); /* clear counters */
558
559 /* finalize this instance of memory controller with edac core */
560 if (edac_mc_add_mc(mci)) {
561 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
562 goto fail2;
563 }
564
565 /* get this far and it's successful */
566 debugf3("%s(): success\n", __func__);
567 return 0;
568
569 fail2:
570 edac_mc_free(mci);
571
572 fail1:
573 iounmap(mch_window);
574 fail0:
575 return rc;
576 }
577
578 /* returns count (>= 0), or negative on error */
579 static int __devinit i82975x_init_one(struct pci_dev *pdev,
580 const struct pci_device_id *ent)
581 {
582 int rc;
583
584 debugf0("%s()\n", __func__);
585
586 if (pci_enable_device(pdev) < 0)
587 return -EIO;
588
589 rc = i82975x_probe1(pdev, ent->driver_data);
590
591 if (mci_pdev == NULL)
592 mci_pdev = pci_dev_get(pdev);
593
594 return rc;
595 }
596
597 static void __devexit i82975x_remove_one(struct pci_dev *pdev)
598 {
599 struct mem_ctl_info *mci;
600 struct i82975x_pvt *pvt;
601
602 debugf0("%s()\n", __func__);
603
604 mci = edac_mc_del_mc(&pdev->dev);
605 if (mci == NULL)
606 return;
607
608 pvt = mci->pvt_info;
609 if (pvt->mch_window)
610 iounmap( pvt->mch_window );
611
612 edac_mc_free(mci);
613 }
614
615 static const struct pci_device_id i82975x_pci_tbl[] __devinitdata = {
616 {
617 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
618 I82975X
619 },
620 {
621 0,
622 } /* 0 terminated list. */
623 };
624
625 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
626
627 static struct pci_driver i82975x_driver = {
628 .name = EDAC_MOD_STR,
629 .probe = i82975x_init_one,
630 .remove = __devexit_p(i82975x_remove_one),
631 .id_table = i82975x_pci_tbl,
632 };
633
634 static int __init i82975x_init(void)
635 {
636 int pci_rc;
637
638 debugf3("%s()\n", __func__);
639
640 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
641 opstate_init();
642
643 pci_rc = pci_register_driver(&i82975x_driver);
644 if (pci_rc < 0)
645 goto fail0;
646
647 if (mci_pdev == NULL) {
648 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
649 PCI_DEVICE_ID_INTEL_82975_0, NULL);
650
651 if (!mci_pdev) {
652 debugf0("i82975x pci_get_device fail\n");
653 pci_rc = -ENODEV;
654 goto fail1;
655 }
656
657 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
658
659 if (pci_rc < 0) {
660 debugf0("i82975x init fail\n");
661 pci_rc = -ENODEV;
662 goto fail1;
663 }
664 }
665
666 return 0;
667
668 fail1:
669 pci_unregister_driver(&i82975x_driver);
670
671 fail0:
672 if (mci_pdev != NULL)
673 pci_dev_put(mci_pdev);
674
675 return pci_rc;
676 }
677
678 static void __exit i82975x_exit(void)
679 {
680 debugf3("%s()\n", __func__);
681
682 pci_unregister_driver(&i82975x_driver);
683
684 if (!i82975x_registered) {
685 i82975x_remove_one(mci_pdev);
686 pci_dev_put(mci_pdev);
687 }
688 }
689
690 module_init(i82975x_init);
691 module_exit(i82975x_exit);
692
693 MODULE_LICENSE("GPL");
694 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
695 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
696
697 module_param(edac_op_state, int, 0444);
698 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");