3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2011, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef _MEI_HW_TYPES_H_
18 #define _MEI_HW_TYPES_H_
20 #include <linux/uuid.h>
25 #define MEI_INTEROP_TIMEOUT (HZ * 7)
26 #define MEI_CONNECT_TIMEOUT 3 /* at least 2 seconds */
28 #define CONNECT_TIMEOUT 15 /* HPS definition */
29 #define INIT_CLIENTS_TIMEOUT 15 /* HPS definition */
31 #define IAMTHIF_STALL_TIMER 12 /* seconds */
32 #define IAMTHIF_READ_TIMER 10000 /* ms */
35 * Internal Clients Number
37 #define MEI_WD_HOST_CLIENT_ID 1
38 #define MEI_IAMTHIF_HOST_CLIENT_ID 2
43 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
44 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
45 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
46 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
48 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
49 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
51 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
52 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
53 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
54 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
55 #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
57 #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
58 #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
59 #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
60 #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
61 #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
63 #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
64 #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
65 #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
66 #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
68 #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
69 #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
70 #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
71 #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
73 #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
74 #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
76 #define MEI_DEV_ID_CPT_1 0x1C3A /* Cougerpoint */
77 #define MEI_DEV_ID_PBG_1 0x1D3A /* PBG */
79 #define MEI_DEV_ID_PPT_1 0x1E3A /* Pantherpoint PPT */
80 #define MEI_DEV_ID_PPT_2 0x1CBA /* Pantherpoint PPT */
81 #define MEI_DEV_ID_PPT_3 0x1DBA /* Pantherpoint PPT */
89 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
91 /* H_CSR - Host Control Status register */
93 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
95 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
99 /* register bits of H_CSR (Host Control Status register) */
100 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
101 #define H_CBD 0xFF000000
102 /* Host Circular Buffer Write Pointer */
103 #define H_CBWP 0x00FF0000
104 /* Host Circular Buffer Read Pointer */
105 #define H_CBRP 0x0000FF00
107 #define H_RST 0x00000010
109 #define H_RDY 0x00000008
110 /* Host Interrupt Generate */
111 #define H_IG 0x00000004
112 /* Host Interrupt Status */
113 #define H_IS 0x00000002
114 /* Host Interrupt Enable */
115 #define H_IE 0x00000001
118 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
119 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
121 #define ME_CBD_HRA 0xFF000000
122 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
123 #define ME_CBWP_HRA 0x00FF0000
124 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
125 #define ME_CBRP_HRA 0x0000FF00
126 /* ME Reset HRA - host read only access to ME_RST */
127 #define ME_RST_HRA 0x00000010
128 /* ME Ready HRA - host read only access to ME_RDY */
129 #define ME_RDY_HRA 0x00000008
130 /* ME Interrupt Generate HRA - host read only access to ME_IG */
131 #define ME_IG_HRA 0x00000004
132 /* ME Interrupt Status HRA - host read only access to ME_IS */
133 #define ME_IS_HRA 0x00000002
134 /* ME Interrupt Enable HRA - host read only access to ME_IE */
135 #define ME_IE_HRA 0x00000001
140 #define HBM_MINOR_VERSION 0
141 #define HBM_MAJOR_VERSION 1
142 #define HBM_TIMEOUT 1 /* 1 second */
145 * MEI Bus Message Command IDs
147 #define HOST_START_REQ_CMD 0x01
148 #define HOST_START_RES_CMD 0x81
150 #define HOST_STOP_REQ_CMD 0x02
151 #define HOST_STOP_RES_CMD 0x82
153 #define ME_STOP_REQ_CMD 0x03
155 #define HOST_ENUM_REQ_CMD 0x04
156 #define HOST_ENUM_RES_CMD 0x84
158 #define HOST_CLIENT_PROPERTIES_REQ_CMD 0x05
159 #define HOST_CLIENT_PROPERTIES_RES_CMD 0x85
161 #define CLIENT_CONNECT_REQ_CMD 0x06
162 #define CLIENT_CONNECT_RES_CMD 0x86
164 #define CLIENT_DISCONNECT_REQ_CMD 0x07
165 #define CLIENT_DISCONNECT_RES_CMD 0x87
167 #define MEI_FLOW_CONTROL_CMD 0x08
171 * used by hbm_host_stop_request.reason
173 enum mei_stop_reason_types
{
174 DRIVER_STOP_REQUEST
= 0x00,
175 DEVICE_D1_ENTRY
= 0x01,
176 DEVICE_D2_ENTRY
= 0x02,
177 DEVICE_D3_ENTRY
= 0x03,
178 SYSTEM_S1_ENTRY
= 0x04,
179 SYSTEM_S2_ENTRY
= 0x05,
180 SYSTEM_S3_ENTRY
= 0x06,
181 SYSTEM_S4_ENTRY
= 0x07,
182 SYSTEM_S5_ENTRY
= 0x08
186 * Client Connect Status
187 * used by hbm_client_connect_response.status
189 enum client_connect_status_types
{
191 CCS_NOT_FOUND
= 0x01,
192 CCS_ALREADY_STARTED
= 0x02,
193 CCS_OUT_OF_RESOURCES
= 0x03,
194 CCS_MESSAGE_SMALL
= 0x04
198 * Client Disconnect Status
200 enum client_disconnect_status_types
{
205 * MEI BUS Interface Section
222 struct mei_bus_message
{
224 u8 command_specific_data
[];
232 struct hbm_host_version_request
{
235 struct hbm_version host_version
;
238 struct hbm_host_version_response
{
240 int host_version_supported
;
241 struct hbm_version me_max_version
;
244 struct hbm_host_stop_request
{
250 struct hbm_host_stop_response
{
255 struct hbm_me_stop_request
{
261 struct hbm_host_enum_request
{
266 struct hbm_host_enum_response
{
269 u8 valid_addresses
[32];
272 struct mei_client_properties
{
273 uuid_le protocol_name
;
275 u8 max_number_of_connections
;
281 struct hbm_props_request
{
288 struct hbm_props_response
{
293 struct mei_client_properties client_properties
;
296 struct hbm_client_connect_request
{
303 struct hbm_client_connect_response
{
310 struct hbm_client_disconnect_request
{
317 #define MEI_FC_MESSAGE_RESERVED_LENGTH 5
319 struct hbm_flow_control
{
323 u8 reserved
[MEI_FC_MESSAGE_RESERVED_LENGTH
];
326 struct mei_me_client
{
327 struct mei_client_properties props
;
329 u8 mei_flow_ctrl_creds
;