drivers/staging/et131x/et1310_rx.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
  10  *
  11  *------------------------------------------------------------------------------
  12  *
  13  * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
  14  *               reception.
  15  *
  16  *------------------------------------------------------------------------------
  17  *
  18  * SOFTWARE LICENSE
  19  *
  20  * This software is provided subject to the following terms and conditions,
  21  * which you should read carefully before using the software.  Using this
  22  * software indicates your acceptance of these terms and conditions.  If you do
  23  * not agree with these terms and conditions, do not use the software.
  24  *
  25  * Copyright © 2005 Agere Systems Inc.
  26  * All rights reserved.
  27  *
  28  * Redistribution and use in source or binary forms, with or without
  29  * modifications, are permitted provided that the following conditions are met:
  30  *
  31  * . Redistributions of source code must retain the above copyright notice, this
  32  *    list of conditions and the following Disclaimer as comments in the code as
  33  *    well as in the documentation and/or other materials provided with the
  34  *    distribution.
  35  *
  36  * . Redistributions in binary form must reproduce the above copyright notice,
  37  *    this list of conditions and the following Disclaimer in the documentation
  38  *    and/or other materials provided with the distribution.
  39  *
  40  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  41  *    may be used to endorse or promote products derived from this software
  42  *    without specific prior written permission.
  43  *
  44  * Disclaimer
  45  *
  46  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  47  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  49  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  50  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  51  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  52  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  53  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  54  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  55  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  56  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  57  * DAMAGE.
  58  *
  59  */
  60
  61 #ifndef __ET1310_RX_H__
  62 #define __ET1310_RX_H__
  63
  64 #include "et1310_address_map.h"
  65
  66 #define USE_FBR0 true
  67
  68 #ifdef USE_FBR0
  69 /* #define FBR0_BUFFER_SIZE 256 */
  70 #endif
  71
  72 /* #define FBR1_BUFFER_SIZE 2048 */
  73
  74 #define FBR_CHUNKS 32
  75
  76 #define MAX_DESC_PER_RING_RX         1024
  77
  78 /* number of RFDs - default and min */
  79 #ifdef USE_FBR0
  80 #define RFD_LOW_WATER_MARK      40
  81 #define NIC_MIN_NUM_RFD         64
  82 #define NIC_DEFAULT_NUM_RFD     1024
  83 #else
  84 #define RFD_LOW_WATER_MARK      20
  85 #define NIC_MIN_NUM_RFD         64
  86 #define NIC_DEFAULT_NUM_RFD     256
  87 #endif
  88
  89 #define NUM_PACKETS_HANDLED     256
  90
  91 #define ALCATEL_BAD_STATUS      0xe47f0000
  92 #define ALCATEL_MULTICAST_PKT   0x01000000
  93 #define ALCATEL_BROADCAST_PKT   0x02000000
  94
  95 /* typedefs for Free Buffer Descriptors */
  96 struct fbr_desc {
  97         u32 addr_lo;
  98         u32 addr_hi;
  99         u32 word2;              /* Bits 10-31 reserved, 0-9 descriptor */
 100 };
 101
 102 /* Packet Status Ring Descriptors
 103  *
 104  * Word 0:
 105  *
 106  * top 16 bits are from the Alcatel Status Word as enumerated in
 107  * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
 108  *
 109  * 0: hp                        hash pass
 110  * 1: ipa                       IP checksum assist
 111  * 2: ipp                       IP checksum pass
 112  * 3: tcpa                      TCP checksum assist
 113  * 4: tcpp                      TCP checksum pass
 114  * 5: wol                       WOL Event
 115  * 6: rxmac_error               RXMAC Error Indicator
 116  * 7: drop                      Drop packet
 117  * 8: ft                        Frame Truncated
 118  * 9: jp                        Jumbo Packet
 119  * 10: vp                       VLAN Packet
 120  * 11-15: unused
 121  * 16: asw_prev_pkt_dropped     e.g. IFG too small on previous
 122  * 17: asw_RX_DV_event          short receive event detected
 123  * 18: asw_false_carrier_event  bad carrier since last good packet
 124  * 19: asw_code_err             one or more nibbles signalled as errors
 125  * 20: asw_CRC_err              CRC error
 126  * 21: asw_len_chk_err          frame length field incorrect
 127  * 22: asw_too_long             frame length > 1518 bytes
 128  * 23: asw_OK                   valid CRC + no code error
 129  * 24: asw_multicast            has a multicast address
 130  * 25: asw_broadcast            has a broadcast address
 131  * 26: asw_dribble_nibble       spurious bits after EOP
 132  * 27: asw_control_frame        is a control frame
 133  * 28: asw_pause_frame          is a pause frame
 134  * 29: asw_unsupported_op       unsupported OP code
 135  * 30: asw_VLAN_tag             VLAN tag detected
 136  * 31: asw_long_evt             Rx long event
 137  *
 138  * Word 1:
 139  * 0-15: length                 length in bytes
 140  * 16-25: bi                    Buffer Index
 141  * 26-27: ri                    Ring Index
 142  * 28-31: reserved
 143  */
 144
 145 struct pkt_stat_desc {
 146         u32 word0;
 147         u32 word1;
 148 };
 149
 150 /* Typedefs for the RX DMA status word */
 151
 152 /*
 153  * rx status word 0 holds part of the status bits of the Rx DMA engine
 154  * that get copied out to memory by the ET-1310.  Word 0 is a 32 bit word
 155  * which contains the Free Buffer ring 0 and 1 available offset.
 156  *
 157  * bit 0-9 FBR1 offset
 158  * bit 10 Wrap flag for FBR1
 159  * bit 16-25 FBR0 offset
 160  * bit 26 Wrap flag for FBR0
 161  */
 162
 163 /*
 164  * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
 165  * that get copied out to memory by the ET-1310.  Word 3 is a 32 bit word
 166  * which contains the Packet Status Ring available offset.
 167  *
 168  * bit 0-15 reserved
 169  * bit 16-27 PSRoffset
 170  * bit 28 PSRwrap
 171  * bit 29-31 unused
 172  */
 173
 174 /*
 175  * struct rx_status_block is a structure representing the status of the Rx
 176  * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
 177  */
 178 struct rx_status_block {
 179         u32 word0;
 180         u32 word1;
 181 };
 182
 183 /*
 184  * Structure for look-up table holding free buffer ring pointers
 185  */
 186 struct fbr_lookup {
 187         void *virt[MAX_DESC_PER_RING_RX];
 188         void *buffer1[MAX_DESC_PER_RING_RX];
 189         void *buffer2[MAX_DESC_PER_RING_RX];
 190         u32 bus_high[MAX_DESC_PER_RING_RX];
 191         u32 bus_low[MAX_DESC_PER_RING_RX];
 192 };
 193
 194 /*
 195  * struct rx_ring is the sructure representing the adaptor's local
 196  * reference(s) to the rings
 197  */
 198 struct rx_ring {
 199 #ifdef USE_FBR0
 200         void *fbr0_ring_virtaddr;
 201         dma_addr_t fbr0_ring_physaddr;
 202         void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
 203         dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
 204         uint64_t fbr0_real_physaddr;
 205         uint64_t fbr0_offset;
 206         u32 local_fbr0_full;
 207         u32 fbr0_num_entries;
 208         u32 fbr0_buffsize;
 209 #endif
 210         void *fbr1_ring_virtaddr;
 211         dma_addr_t fbr1_ring_physaddr;
 212         void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
 213         dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
 214         uint64_t fbr1_real_physaddr;
 215         uint64_t fbr1_offset;
 216         struct fbr_lookup *fbr[2];      /* One per ring */
 217         u32 local_fbr1_full;
 218         u32 fbr1_num_entries;
 219         u32 fbr1_buffsize;
 220
 221         void *ps_ring_virtaddr;
 222         dma_addr_t ps_ring_physaddr;
 223         u32 local_psr_full;
 224         u32 psr_num_entries;
 225
 226         struct rx_status_block *rx_status_block;
 227         dma_addr_t rx_status_bus;
 228
 229         struct list_head recv_buff_pool;
 230
 231         /* RECV */
 232         struct list_head recv_list;
 233         u32 num_ready_recv;
 234
 235         u32 num_rfd;
 236
 237         bool unfinished_receives;
 238
 239         struct list_head recv_packet_pool;
 240
 241         /* lookaside lists */
 242         struct kmem_cache *recv_lookaside;
 243 };
 244
 245 #endif /* __ET1310_RX_H__ */