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staging: brcm80211: remove brcms_b_dotxstatus wrapper function
[zen-stable.git] / drivers / staging / xgifb / vb_init.c
blobce5bf6839cf682931b91f409b51b75bd1673758b
1 #include <linux/types.h>
2 #include <linux/delay.h> /* udelay */
3 #include "vgatypes.h"
4 #include "XGIfb.h"
5
6 #include "vb_def.h"
7 #include "vb_struct.h"
8 #include "vb_util.h"
9 #include "vb_setmode.h"
10 #include "vb_init.h"
11 #include "vb_ext.h"
12
13
14 #include <linux/io.h>
15
16 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
17
18 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
19 { 2, 13, 9, 64, 0x45},
20 { 2, 12, 9, 32, 0x35},
21 { 2, 12, 8, 16, 0x31},
22 { 2, 11, 8, 8, 0x21} };
23
24 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
25 { 2, 14, 11, 128, 0x5D},
26 { 2, 14, 10, 64, 0x59},
27 { 2, 13, 11, 64, 0x4D},
28 { 2, 14, 9, 32, 0x55},
29 { 2, 13, 10, 32, 0x49},
30 { 2, 12, 11, 32, 0x3D},
31 { 2, 14, 8, 16, 0x51},
32 { 2, 13, 9, 16, 0x45},
33 { 2, 12, 10, 16, 0x39},
34 { 2, 13, 8, 8, 0x41},
35 { 2, 12, 9, 8, 0x35},
36 { 2, 12, 8, 4, 0x31} };
37
38 static int XGINew_RAMType;
39
40 static unsigned char
41 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
42 struct vb_device_info *pVBInfo)
43 {
44 unsigned char data, temp;
45
46 if (HwDeviceExtension->jChipType < XG20) {
47 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
48 data = *pVBInfo->pSoftSetting & 0x07;
49 return data;
50 } else {
51 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
52 if (data == 0)
53 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
54 0x02) >> 1;
55 return data;
56 }
57 } else if (HwDeviceExtension->jChipType == XG27) {
58 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
59 data = *pVBInfo->pSoftSetting & 0x07;
60 return data;
61 }
62 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
63 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
64 if ((temp & 0x88) == 0x80)
65 data = 0; /* DDR */
66 else
67 data = 1; /* DDRII */
68 return data;
69 } else if (HwDeviceExtension->jChipType == XG21) {
70 /* Independent GPIO control */
71 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
72 udelay(800);
73 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
74 /* GPIOF 0:DVI 1:DVO */
75 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
76 /* HOTPLUG_SUPPORT */
77 /* for current XG20 & XG21, GPIOH is floating, driver will
78 * fix DDR temporarily */
79 if (temp & 0x01) /* DVI read GPIOH */
80 data = 1; /* DDRII */
81 else
82 data = 0; /* DDR */
83 /* ~HOTPLUG_SUPPORT */
84 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
85 return data;
86 } else {
87 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
88
89 if (data == 1)
90 data++;
91
92 return data;
93 }
94 }
95
96 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
97 struct vb_device_info *pVBInfo)
98 {
99 xgifb_reg_set(P3c4, 0x18, 0x01);
100 xgifb_reg_set(P3c4, 0x19, 0x20);
101 xgifb_reg_set(P3c4, 0x16, 0x00);
102 xgifb_reg_set(P3c4, 0x16, 0x80);
103
104 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
105 mdelay(3);
106 xgifb_reg_set(P3c4, 0x18, 0x00);
107 xgifb_reg_set(P3c4, 0x19, 0x20);
108 xgifb_reg_set(P3c4, 0x16, 0x00);
109 xgifb_reg_set(P3c4, 0x16, 0x80);
110 }
111
112 udelay(60);
113 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
114 xgifb_reg_set(P3c4, 0x19, 0x01);
115 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
116 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
117 mdelay(1);
118 xgifb_reg_set(P3c4, 0x1B, 0x03);
119 udelay(500);
120 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
121 xgifb_reg_set(P3c4, 0x19, 0x00);
122 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
123 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
124 xgifb_reg_set(P3c4, 0x1B, 0x00);
125 }
126
127 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
128 struct vb_device_info *pVBInfo)
129 {
130
131 xgifb_reg_set(pVBInfo->P3c4,
132 0x28,
133 pVBInfo->MCLKData[XGINew_RAMType].SR28);
134 xgifb_reg_set(pVBInfo->P3c4,
135 0x29,
136 pVBInfo->MCLKData[XGINew_RAMType].SR29);
137 xgifb_reg_set(pVBInfo->P3c4,
138 0x2A,
139 pVBInfo->MCLKData[XGINew_RAMType].SR2A);
140
141 xgifb_reg_set(pVBInfo->P3c4,
142 0x2E,
143 pVBInfo->ECLKData[XGINew_RAMType].SR2E);
144 xgifb_reg_set(pVBInfo->P3c4,
145 0x2F,
146 pVBInfo->ECLKData[XGINew_RAMType].SR2F);
147 xgifb_reg_set(pVBInfo->P3c4,
148 0x30,
149 pVBInfo->ECLKData[XGINew_RAMType].SR30);
150
151 /* [Vicent] 2004/07/07,
152 * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
153 /* [Hsuan] 2004/08/20,
154 * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
155 * Set SR32 D[1:0] = 10b */
156 if (HwDeviceExtension->jChipType == XG42) {
157 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
158 (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
159 (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
160 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
161 ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
162 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
163 xgifb_reg_set(pVBInfo->P3c4,
164 0x32,
165 ((unsigned char) xgifb_reg_get(
166 pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
167 }
168 }
169
170 static void XGINew_DDRII_Bootup_XG27(
171 struct xgi_hw_device_info *HwDeviceExtension,
172 unsigned long P3c4, struct vb_device_info *pVBInfo)
173 {
174 unsigned long P3d4 = P3c4 + 0x10;
175 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
176 pVBInfo);
177 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
178
179 /* Set Double Frequency */
180 /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
181 xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
182
183 udelay(200);
184
185 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
186 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
187 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
188 udelay(15);
189 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
190 udelay(15);
191
192 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
193 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
194 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
195 udelay(15);
196 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
197 udelay(15);
198
199 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
200 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
201 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
202 udelay(30);
203 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
204 udelay(15);
205
206 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
207 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
208 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
209 udelay(30);
210 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
211 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
212 /* udelay(15); */
213
214 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
215 udelay(60);
216 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
217
218 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
219 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
220 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
221
222 udelay(30);
223 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
224 udelay(15);
225
226 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
227 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
228 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
229 udelay(30);
230 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
231 udelay(15);
232
233 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
234 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
235 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
236 udelay(30);
237 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
238 udelay(15);
239
240 /* Set SR1B refresh control 000:close; 010:open */
241 xgifb_reg_set(P3c4, 0x1B, 0x04);
242 udelay(200);
243
244 }
245
246 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
247 unsigned long P3c4, struct vb_device_info *pVBInfo)
248 {
249 unsigned long P3d4 = P3c4 + 0x10;
250
251 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
252 pVBInfo);
253 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
254
255 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
256
257 udelay(200);
258 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
259 xgifb_reg_set(P3c4, 0x19, 0x80);
260 xgifb_reg_set(P3c4, 0x16, 0x05);
261 xgifb_reg_set(P3c4, 0x16, 0x85);
262
263 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
264 xgifb_reg_set(P3c4, 0x19, 0xC0);
265 xgifb_reg_set(P3c4, 0x16, 0x05);
266 xgifb_reg_set(P3c4, 0x16, 0x85);
267
268 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
269 xgifb_reg_set(P3c4, 0x19, 0x40);
270 xgifb_reg_set(P3c4, 0x16, 0x05);
271 xgifb_reg_set(P3c4, 0x16, 0x85);
272
273 /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
274 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
275 xgifb_reg_set(P3c4, 0x19, 0x02);
276 xgifb_reg_set(P3c4, 0x16, 0x05);
277 xgifb_reg_set(P3c4, 0x16, 0x85);
278
279 udelay(15);
280 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
281 udelay(30);
282 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
283 udelay(100);
284
285 /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
286 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
287 xgifb_reg_set(P3c4, 0x19, 0x00);
288 xgifb_reg_set(P3c4, 0x16, 0x05);
289 xgifb_reg_set(P3c4, 0x16, 0x85);
290
291 udelay(200);
292 }
293
294 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
295 struct vb_device_info *pVBInfo)
296 {
297 xgifb_reg_set(P3c4, 0x18, 0x01);
298 xgifb_reg_set(P3c4, 0x19, 0x40);
299 xgifb_reg_set(P3c4, 0x16, 0x00);
300 xgifb_reg_set(P3c4, 0x16, 0x80);
301 udelay(60);
302
303 xgifb_reg_set(P3c4, 0x18, 0x00);
304 xgifb_reg_set(P3c4, 0x19, 0x40);
305 xgifb_reg_set(P3c4, 0x16, 0x00);
306 xgifb_reg_set(P3c4, 0x16, 0x80);
307 udelay(60);
308 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
309 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
310 xgifb_reg_set(P3c4, 0x19, 0x01);
311 xgifb_reg_set(P3c4, 0x16, 0x03);
312 xgifb_reg_set(P3c4, 0x16, 0x83);
313 mdelay(1);
314 xgifb_reg_set(P3c4, 0x1B, 0x03);
315 udelay(500);
316 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
317 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
318 xgifb_reg_set(P3c4, 0x19, 0x00);
319 xgifb_reg_set(P3c4, 0x16, 0x03);
320 xgifb_reg_set(P3c4, 0x16, 0x83);
321 xgifb_reg_set(P3c4, 0x1B, 0x00);
322 }
323
324 static void XGINew_DDR1x_DefaultRegister(
325 struct xgi_hw_device_info *HwDeviceExtension,
326 unsigned long Port, struct vb_device_info *pVBInfo)
327 {
328 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
329
330 if (HwDeviceExtension->jChipType >= XG20) {
331 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
332 xgifb_reg_set(P3d4,
333 0x82,
334 pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
335 xgifb_reg_set(P3d4,
336 0x85,
337 pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
338 xgifb_reg_set(P3d4,
339 0x86,
340 pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
341
342 xgifb_reg_set(P3d4, 0x98, 0x01);
343 xgifb_reg_set(P3d4, 0x9A, 0x02);
344
345 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
346 } else {
347 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
348
349 switch (HwDeviceExtension->jChipType) {
350 case XG41:
351 case XG42:
352 /* CR82 */
353 xgifb_reg_set(P3d4,
354 0x82,
355 pVBInfo->CR40[11][XGINew_RAMType]);
356 /* CR85 */
357 xgifb_reg_set(P3d4,
358 0x85,
359 pVBInfo->CR40[12][XGINew_RAMType]);
360 /* CR86 */
361 xgifb_reg_set(P3d4,
362 0x86,
363 pVBInfo->CR40[13][XGINew_RAMType]);
364 break;
365 default:
366 xgifb_reg_set(P3d4, 0x82, 0x88);
367 xgifb_reg_set(P3d4, 0x86, 0x00);
368 /* Insert read command for delay */
369 xgifb_reg_get(P3d4, 0x86);
370 xgifb_reg_set(P3d4, 0x86, 0x88);
371 xgifb_reg_get(P3d4, 0x86);
372 xgifb_reg_set(P3d4,
373 0x86,
374 pVBInfo->CR40[13][XGINew_RAMType]);
375 xgifb_reg_set(P3d4, 0x82, 0x77);
376 xgifb_reg_set(P3d4, 0x85, 0x00);
377
378 /* Insert read command for delay */
379 xgifb_reg_get(P3d4, 0x85);
380 xgifb_reg_set(P3d4, 0x85, 0x88);
381
382 /* Insert read command for delay */
383 xgifb_reg_get(P3d4, 0x85);
384 /* CR85 */
385 xgifb_reg_set(P3d4,
386 0x85,
387 pVBInfo->CR40[12][XGINew_RAMType]);
388 /* CR82 */
389 xgifb_reg_set(P3d4,
390 0x82,
391 pVBInfo->CR40[11][XGINew_RAMType]);
392 break;
393 }
394
395 xgifb_reg_set(P3d4, 0x97, 0x00);
396 xgifb_reg_set(P3d4, 0x98, 0x01);
397 xgifb_reg_set(P3d4, 0x9A, 0x02);
398 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
399 }
400 }
401
402 static void XGINew_DDR2_DefaultRegister(
403 struct xgi_hw_device_info *HwDeviceExtension,
404 unsigned long Port, struct vb_device_info *pVBInfo)
405 {
406 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
407
408 /* keep following setting sequence, each setting in
409 * the same reg insert idle */
410 xgifb_reg_set(P3d4, 0x82, 0x77);
411 xgifb_reg_set(P3d4, 0x86, 0x00);
412 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
413 xgifb_reg_set(P3d4, 0x86, 0x88);
414 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
415 /* CR86 */
416 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
417 xgifb_reg_set(P3d4, 0x82, 0x77);
418 xgifb_reg_set(P3d4, 0x85, 0x00);
419 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
420 xgifb_reg_set(P3d4, 0x85, 0x88);
421 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
422 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
423 if (HwDeviceExtension->jChipType == XG27)
424 /* CR82 */
425 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
426 else
427 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
428
429 xgifb_reg_set(P3d4, 0x98, 0x01);
430 xgifb_reg_set(P3d4, 0x9A, 0x02);
431 if (HwDeviceExtension->jChipType == XG27)
432 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
433 else
434 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
435 }
436
437 static void XGINew_SetDRAMDefaultRegister340(
438 struct xgi_hw_device_info *HwDeviceExtension,
439 unsigned long Port, struct vb_device_info *pVBInfo)
440 {
441 unsigned char temp, temp1, temp2, temp3, i, j, k;
442
443 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
444
445 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
446 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
447 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
448 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
449
450 temp2 = 0;
451 for (i = 0; i < 4; i++) {
452 /* CR6B DQS fine tune delay */
453 temp = pVBInfo->CR6B[XGINew_RAMType][i];
454 for (j = 0; j < 4; j++) {
455 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
456 temp2 |= temp1;
457 xgifb_reg_set(P3d4, 0x6B, temp2);
458 /* Insert read command for delay */
459 xgifb_reg_get(P3d4, 0x6B);
460 temp2 &= 0xF0;
461 temp2 += 0x10;
462 }
463 }
464
465 temp2 = 0;
466 for (i = 0; i < 4; i++) {
467 /* CR6E DQM fine tune delay */
468 temp = pVBInfo->CR6E[XGINew_RAMType][i];
469 for (j = 0; j < 4; j++) {
470 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
471 temp2 |= temp1;
472 xgifb_reg_set(P3d4, 0x6E, temp2);
473 /* Insert read command for delay */
474 xgifb_reg_get(P3d4, 0x6E);
475 temp2 &= 0xF0;
476 temp2 += 0x10;
477 }
478 }
479
480 temp3 = 0;
481 for (k = 0; k < 4; k++) {
482 /* CR6E_D[1:0] select channel */
483 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
484 temp2 = 0;
485 for (i = 0; i < 8; i++) {
486 /* CR6F DQ fine tune delay */
487 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
488 for (j = 0; j < 4; j++) {
489 temp1 = (temp >> (2 * j)) & 0x03;
490 temp2 |= temp1;
491 xgifb_reg_set(P3d4, 0x6F, temp2);
492 /* Insert read command for delay */
493 xgifb_reg_get(P3d4, 0x6F);
494 temp2 &= 0xF8;
495 temp2 += 0x08;
496 }
497 }
498 temp3 += 0x01;
499 }
500
501 xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
502 xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
503
504 temp2 = 0x80;
505 /* CR89 terminator type select */
506 temp = pVBInfo->CR89[XGINew_RAMType][0];
507 for (j = 0; j < 4; j++) {
508 temp1 = (temp >> (2 * j)) & 0x03;
509 temp2 |= temp1;
510 xgifb_reg_set(P3d4, 0x89, temp2);
511 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
512 temp2 &= 0xF0;
513 temp2 += 0x10;
514 }
515
516 temp = pVBInfo->CR89[XGINew_RAMType][1];
517 temp1 = temp & 0x03;
518 temp2 |= temp1;
519 xgifb_reg_set(P3d4, 0x89, temp2);
520
521 temp = pVBInfo->CR40[3][XGINew_RAMType];
522 temp1 = temp & 0x0F;
523 temp2 = (temp >> 4) & 0x07;
524 temp3 = temp & 0x80;
525 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
526 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
527 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
528 xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
529
530 if (HwDeviceExtension->jChipType == XG27)
531 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
532
533 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
534 xgifb_reg_set(P3d4, (0x90 + j),
535 pVBInfo->CR40[14 + j][XGINew_RAMType]);
536
537 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
538 xgifb_reg_set(P3d4, (0xC3 + j),
539 pVBInfo->CR40[21 + j][XGINew_RAMType]);
540
541 for (j = 0; j < 2; j++) /* CR8A - CR8B */
542 xgifb_reg_set(P3d4, (0x8A + j),
543 pVBInfo->CR40[1 + j][XGINew_RAMType]);
544
545 if ((HwDeviceExtension->jChipType == XG41) ||
546 (HwDeviceExtension->jChipType == XG42))
547 xgifb_reg_set(P3d4, 0x8C, 0x87);
548
549 xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
550
551 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
552 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
553 xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
554 if (XGINew_RAMType) {
555 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
556 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
557 if (HwDeviceExtension->jChipType == XG27)
558 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
559
560 } else {
561 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
562 }
563 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
564
565 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
566 if (temp == 0) {
567 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
568 } else {
569 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
570 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
571 }
572 xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
573 }
574
575 static void XGINew_SetDRAMSizingType(int index,
576 unsigned short DRAMTYPE_TABLE[][5],
577 struct vb_device_info *pVBInfo)
578 {
579 unsigned short data;
580
581 data = DRAMTYPE_TABLE[index][4];
582 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
583 udelay(15);
584 /* should delay 50 ns */
585 }
586
587 static unsigned short XGINew_SetDRAMSizeReg(int index,
588 unsigned short DRAMTYPE_TABLE[][5],
589 struct vb_device_info *pVBInfo)
590 {
591 unsigned short data = 0, memsize = 0;
592 int RankSize;
593 unsigned char ChannelNo;
594
595 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
596 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
597 data &= 0x80;
598
599 if (data == 0x80)
600 RankSize *= 2;
601
602 data = 0;
603
604 if (XGINew_ChannelAB == 3)
605 ChannelNo = 4;
606 else
607 ChannelNo = XGINew_ChannelAB;
608
609 if (ChannelNo * RankSize <= 256) {
610 while ((RankSize >>= 1) > 0)
611 data += 0x10;
612
613 memsize = data >> 4;
614
615 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
616 xgifb_reg_set(pVBInfo->P3c4,
617 0x14,
618 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
619 (data & 0xF0));
620
621 /* data |= XGINew_ChannelAB << 2; */
622 /* data |= (XGINew_DataBusWidth / 64) << 1; */
623 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
624
625 /* should delay */
626 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
627 }
628 return memsize;
629 }
630
631 static unsigned short XGINew_SetDRAMSize20Reg(int index,
632 unsigned short DRAMTYPE_TABLE[][5],
633 struct vb_device_info *pVBInfo)
634 {
635 unsigned short data = 0, memsize = 0;
636 int RankSize;
637 unsigned char ChannelNo;
638
639 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
640 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
641 data &= 0x80;
642
643 if (data == 0x80)
644 RankSize *= 2;
645
646 data = 0;
647
648 if (XGINew_ChannelAB == 3)
649 ChannelNo = 4;
650 else
651 ChannelNo = XGINew_ChannelAB;
652
653 if (ChannelNo * RankSize <= 256) {
654 while ((RankSize >>= 1) > 0)
655 data += 0x10;
656
657 memsize = data >> 4;
658
659 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
660 xgifb_reg_set(pVBInfo->P3c4,
661 0x14,
662 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
663 (data & 0xF0));
664 udelay(15);
665
666 /* data |= XGINew_ChannelAB << 2; */
667 /* data |= (XGINew_DataBusWidth / 64) << 1; */
668 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
669
670 /* should delay */
671 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
672 }
673 return memsize;
674 }
675
676 static int XGINew_ReadWriteRest(unsigned short StopAddr,
677 unsigned short StartAddr, struct vb_device_info *pVBInfo)
678 {
679 int i;
680 unsigned long Position = 0;
681 void __iomem *fbaddr = pVBInfo->FBAddr;
682
683 writel(Position, fbaddr + Position);
684
685 for (i = StartAddr; i <= StopAddr; i++) {
686 Position = 1 << i;
687 writel(Position, fbaddr + Position);
688 }
689
690 udelay(500); /* [Vicent] 2004/04/16.
691 Fix #1759 Memory Size error in Multi-Adapter. */
692
693 Position = 0;
694
695 if (readl(fbaddr + Position) != Position)
696 return 0;
697
698 for (i = StartAddr; i <= StopAddr; i++) {
699 Position = 1 << i;
700 if (readl(fbaddr + Position) != Position)
701 return 0;
702 }
703 return 1;
704 }
705
706 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
707 {
708 unsigned char data;
709
710 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
711
712 if ((data & 0x10) == 0) {
713 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
714 data = (data & 0x02) >> 1;
715 return data;
716 } else {
717 return data & 0x01;
718 }
719 }
720
721 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
722 struct vb_device_info *pVBInfo)
723 {
724 unsigned char data;
725
726 switch (HwDeviceExtension->jChipType) {
727 case XG20:
728 case XG21:
729 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
730 data = data & 0x01;
731 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
732
733 if (data == 0) { /* Single_32_16 */
734
735 if ((HwDeviceExtension->ulVideoMemorySize - 1)
736 > 0x1000000) {
737
738 XGINew_DataBusWidth = 32; /* 32 bits */
739 /* 22bit + 2 rank + 32bit */
740 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
741 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
742 udelay(15);
743
744 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
745 return;
746
747 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
748 0x800000) {
749 /* 22bit + 1 rank + 32bit */
750 xgifb_reg_set(pVBInfo->P3c4,
751 0x13,
752 0x31);
753 xgifb_reg_set(pVBInfo->P3c4,
754 0x14,
755 0x42);
756 udelay(15);
757
758 if (XGINew_ReadWriteRest(23,
759 23,
760 pVBInfo) == 1)
761 return;
762 }
763 }
764
765 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
766 0x800000) {
767 XGINew_DataBusWidth = 16; /* 16 bits */
768 /* 22bit + 2 rank + 16bit */
769 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
770 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
771 udelay(15);
772
773 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
774 return;
775 else
776 xgifb_reg_set(pVBInfo->P3c4,
777 0x13,
778 0x31);
779 udelay(15);
780 }
781
782 } else { /* Dual_16_8 */
783 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
784 0x800000) {
785 XGINew_DataBusWidth = 16; /* 16 bits */
786 /* (0x31:12x8x2) 22bit + 2 rank */
787 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
788 /* 0x41:16Mx16 bit*/
789 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
790 udelay(15);
791
792 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
793 return;
794
795 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
796 0x400000) {
797 /* (0x31:12x8x2) 22bit + 1 rank */
798 xgifb_reg_set(pVBInfo->P3c4,
799 0x13,
800 0x31);
801 /* 0x31:8Mx16 bit*/
802 xgifb_reg_set(pVBInfo->P3c4,
803 0x14,
804 0x31);
805 udelay(15);
806
807 if (XGINew_ReadWriteRest(22,
808 22,
809 pVBInfo) == 1)
810 return;
811 }
812 }
813
814 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
815 0x400000) {
816 XGINew_DataBusWidth = 8; /* 8 bits */
817 /* (0x31:12x8x2) 22bit + 2 rank */
818 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
819 /* 0x30:8Mx8 bit*/
820 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
821 udelay(15);
822
823 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
824 return;
825 else /* (0x31:12x8x2) 22bit + 1 rank */
826 xgifb_reg_set(pVBInfo->P3c4,
827 0x13,
828 0x31);
829 udelay(15);
830 }
831 }
832 break;
833
834 case XG27:
835 XGINew_DataBusWidth = 16; /* 16 bits */
836 XGINew_ChannelAB = 1; /* Single channel */
837 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
838 break;
839 case XG41:
840 if (XGINew_CheckFrequence(pVBInfo) == 1) {
841 XGINew_DataBusWidth = 32; /* 32 bits */
842 XGINew_ChannelAB = 3; /* Quad Channel */
843 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
844 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
845
846 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
847 return;
848
849 XGINew_ChannelAB = 2; /* Dual channels */
850 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
851
852 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
853 return;
854
855 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
856
857 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
858 return;
859
860 XGINew_ChannelAB = 3;
861 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
862 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
863
864 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
865 return;
866
867 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
868
869 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
870 return;
871 else
872 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
873 } else { /* DDR */
874 XGINew_DataBusWidth = 64; /* 64 bits */
875 XGINew_ChannelAB = 2; /* Dual channels */
876 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
877 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
878
879 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
880 return;
881
882 XGINew_ChannelAB = 1; /* Single channels */
883 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
884
885 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
886 return;
887
888 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
889
890 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
891 return;
892
893 XGINew_ChannelAB = 2; /* Dual channels */
894 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
895 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
896
897 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
898 return;
899
900 XGINew_ChannelAB = 1; /* Single channels */
901 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
902
903 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
904 return;
905 else
906 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
907 }
908
909 break;
910
911 case XG42:
912 /*
913 XG42 SR14 D[3] Reserve
914 D[2] = 1, Dual Channel
915 = 0, Single Channel
916
917 It's Different from Other XG40 Series.
918 */
919 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
920 XGINew_DataBusWidth = 32; /* 32 bits */
921 XGINew_ChannelAB = 2; /* 2 Channel */
922 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
923 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
924
925 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
926 return;
927
928 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
929 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
930 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
931 return;
932
933 XGINew_ChannelAB = 1; /* Single Channel */
934 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
935 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
936
937 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
938 return;
939 else {
940 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
941 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
942 }
943 } else { /* DDR */
944 XGINew_DataBusWidth = 64; /* 64 bits */
945 XGINew_ChannelAB = 1; /* 1 channels */
946 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
947 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
948
949 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
950 return;
951 else {
952 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
953 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
954 }
955 }
956
957 break;
958
959 default: /* XG40 */
960
961 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
962 XGINew_DataBusWidth = 32; /* 32 bits */
963 XGINew_ChannelAB = 3;
964 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
965 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
966
967 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
968 return;
969
970 XGINew_ChannelAB = 2; /* 2 channels */
971 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
972
973 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
974 return;
975
976 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
977 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
978
979 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
980 XGINew_ChannelAB = 3; /* 4 channels */
981 } else {
982 XGINew_ChannelAB = 2; /* 2 channels */
983 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
984 }
985 } else { /* DDR */
986 XGINew_DataBusWidth = 64; /* 64 bits */
987 XGINew_ChannelAB = 2; /* 2 channels */
988 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
989 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
990
991 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
992 return;
993 } else {
994 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
995 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
996 }
997 }
998 break;
999 }
1000 }
1001
1002 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1003 struct vb_device_info *pVBInfo)
1004 {
1005 int i;
1006 unsigned short memsize, addr;
1007
1008 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1009 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1010 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1011
1012 if (HwDeviceExtension->jChipType >= XG20) {
1013 for (i = 0; i < 12; i++) {
1014 XGINew_SetDRAMSizingType(i,
1015 XGINew_DDRDRAM_TYPE20,
1016 pVBInfo);
1017 memsize = XGINew_SetDRAMSize20Reg(i,
1018 XGINew_DDRDRAM_TYPE20,
1019 pVBInfo);
1020 if (memsize == 0)
1021 continue;
1022
1023 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1024 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1025 (unsigned long) (1 << addr))
1026 continue;
1027
1028 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1029 return 1;
1030 }
1031 } else {
1032 for (i = 0; i < 4; i++) {
1033 XGINew_SetDRAMSizingType(i,
1034 XGINew_DDRDRAM_TYPE340,
1035 pVBInfo);
1036 memsize = XGINew_SetDRAMSizeReg(i,
1037 XGINew_DDRDRAM_TYPE340,
1038 pVBInfo);
1039
1040 if (memsize == 0)
1041 continue;
1042
1043 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1044 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1045 (unsigned long) (1 << addr))
1046 continue;
1047
1048 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1049 return 1;
1050 }
1051 }
1052 return 0;
1053 }
1054
1055 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1056 struct vb_device_info *pVBInfo)
1057 {
1058 unsigned short data;
1059
1060 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1061 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1062
1063 XGISetModeNew(HwDeviceExtension, 0x2e);
1064
1065 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1066 /* disable read cache */
1067 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1068 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1069
1070 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1071 /* data |= 0x20 ; */
1072 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1073 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1074 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1075 /* enable read cache */
1076 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1077 }
1078
1079 static void ReadVBIOSTablData(unsigned char ChipType,
1080 struct vb_device_info *pVBInfo)
1081 {
1082 volatile unsigned char *pVideoMemory =
1083 (unsigned char *) pVBInfo->ROMAddr;
1084 unsigned long i;
1085 unsigned char j, k;
1086 /* Volari customize data area end */
1087
1088 if (ChipType == XG21) {
1089 pVBInfo->IF_DEF_LVDS = 0;
1090 if (pVideoMemory[0x65] & 0x1) {
1091 pVBInfo->IF_DEF_LVDS = 1;
1092 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1093 j = pVideoMemory[i - 1];
1094 if (j != 0xff) {
1095 k = 0;
1096 do {
1097 pVBInfo->XG21_LVDSCapList[k].
1098 LVDS_Capability
1099 = pVideoMemory[i] |
1100 (pVideoMemory[i + 1] << 8);
1101 pVBInfo->XG21_LVDSCapList[k].LVDSHT
1102 = pVideoMemory[i + 2] |
1103 (pVideoMemory[i + 3] << 8);
1104 pVBInfo->XG21_LVDSCapList[k].LVDSVT
1105 = pVideoMemory[i + 4] |
1106 (pVideoMemory[i + 5] << 8);
1107 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1108 = pVideoMemory[i + 6] |
1109 (pVideoMemory[i + 7] << 8);
1110 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1111 = pVideoMemory[i + 8] |
1112 (pVideoMemory[i + 9] << 8);
1113 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1114 = pVideoMemory[i + 10] |
1115 (pVideoMemory[i + 11] << 8);
1116 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1117 = pVideoMemory[i + 12] |
1118 (pVideoMemory[i + 13] << 8);
1119 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1120 = pVideoMemory[i + 14] |
1121 (pVideoMemory[i + 15] << 8);
1122 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1123 = pVideoMemory[i + 16] |
1124 (pVideoMemory[i + 17] << 8);
1125 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1126 = pVideoMemory[i + 18];
1127 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1128 = pVideoMemory[i + 19];
1129 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1130 = pVideoMemory[i + 20];
1131 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1132 = pVideoMemory[i + 21];
1133 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1134 = pVideoMemory[i + 22];
1135 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1136 = pVideoMemory[i + 23];
1137 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1138 = pVideoMemory[i + 24];
1139 i += 25;
1140 j--;
1141 k++;
1142 } while ((j > 0) &&
1143 (k < (sizeof(XGI21_LCDCapList) /
1144 sizeof(struct
1145 XGI21_LVDSCapStruct))));
1146 } else {
1147 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1148 = pVideoMemory[i] |
1149 (pVideoMemory[i + 1] << 8);
1150 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1151 = pVideoMemory[i + 2] |
1152 (pVideoMemory[i + 3] << 8);
1153 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1154 = pVideoMemory[i + 4] |
1155 (pVideoMemory[i + 5] << 8);
1156 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1157 = pVideoMemory[i + 6] |
1158 (pVideoMemory[i + 7] << 8);
1159 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1160 = pVideoMemory[i + 8] |
1161 (pVideoMemory[i + 9] << 8);
1162 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1163 = pVideoMemory[i + 10] |
1164 (pVideoMemory[i + 11] << 8);
1165 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1166 = pVideoMemory[i + 12] |
1167 (pVideoMemory[i + 13] << 8);
1168 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1169 = pVideoMemory[i + 14] |
1170 (pVideoMemory[i + 15] << 8);
1171 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1172 = pVideoMemory[i + 16] |
1173 (pVideoMemory[i + 17] << 8);
1174 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1175 = pVideoMemory[i + 18];
1176 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1177 = pVideoMemory[i + 19];
1178 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1179 = pVideoMemory[i + 20];
1180 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1181 = pVideoMemory[i + 21];
1182 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1183 = pVideoMemory[i + 22];
1184 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1185 = pVideoMemory[i + 23];
1186 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1187 = pVideoMemory[i + 24];
1188 }
1189 }
1190 }
1191 }
1192
1193 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1194 struct vb_device_info *pVBInfo)
1195 {
1196 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1197
1198 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1199
1200 if (temp & Monitor1Sense)
1201 tempbx |= ActiveCRT1;
1202 if (temp & LCDSense)
1203 tempbx |= ActiveLCD;
1204 if (temp & Monitor2Sense)
1205 tempbx |= ActiveCRT2;
1206 if (temp & TVSense) {
1207 tempbx |= ActiveTV;
1208 if (temp & AVIDEOSense)
1209 tempbx |= (ActiveAVideo << 8);
1210 if (temp & SVIDEOSense)
1211 tempbx |= (ActiveSVideo << 8);
1212 if (temp & SCARTSense)
1213 tempbx |= (ActiveSCART << 8);
1214 if (temp & HiTVSense)
1215 tempbx |= (ActiveHiTV << 8);
1216 if (temp & YPbPrSense)
1217 tempbx |= (ActiveYPbPr << 8);
1218 }
1219
1220 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1221 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1222
1223 if (tempbx & tempcx) {
1224 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1225 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1226 tempcx = 0x1FF0;
1227 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1228 tempbx = 0x1FF0;
1229 }
1230 } else {
1231 tempcx = 0x1FF0;
1232 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1233 tempbx = 0x1FF0;
1234 }
1235
1236 tempbx &= tempcx;
1237 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1238 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1239 }
1240
1241 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1242 struct vb_device_info *pVBInfo)
1243 {
1244 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1245
1246 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1247 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1248 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1249
1250 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1251 if (temp & ActiveCRT2)
1252 tempcl = SetCRT2ToRAMDAC;
1253 }
1254
1255 if (temp & ActiveLCD) {
1256 tempcl |= SetCRT2ToLCD;
1257 if (temp & DriverMode) {
1258 if (temp & ActiveTV) {
1259 tempch = SetToLCDA | EnableDualEdge;
1260 temp ^= SetCRT2ToLCD;
1261
1262 if ((temp >> 8) & ActiveAVideo)
1263 tempcl |= SetCRT2ToAVIDEO;
1264 if ((temp >> 8) & ActiveSVideo)
1265 tempcl |= SetCRT2ToSVIDEO;
1266 if ((temp >> 8) & ActiveSCART)
1267 tempcl |= SetCRT2ToSCART;
1268
1269 if (pVBInfo->IF_DEF_HiVision == 1) {
1270 if ((temp >> 8) & ActiveHiTV)
1271 tempcl |= SetCRT2ToHiVisionTV;
1272 }
1273
1274 if (pVBInfo->IF_DEF_YPbPr == 1) {
1275 if ((temp >> 8) & ActiveYPbPr)
1276 tempch |= SetYPbPr;
1277 }
1278 }
1279 }
1280 } else {
1281 if ((temp >> 8) & ActiveAVideo)
1282 tempcl |= SetCRT2ToAVIDEO;
1283 if ((temp >> 8) & ActiveSVideo)
1284 tempcl |= SetCRT2ToSVIDEO;
1285 if ((temp >> 8) & ActiveSCART)
1286 tempcl |= SetCRT2ToSCART;
1287
1288 if (pVBInfo->IF_DEF_HiVision == 1) {
1289 if ((temp >> 8) & ActiveHiTV)
1290 tempcl |= SetCRT2ToHiVisionTV;
1291 }
1292
1293 if (pVBInfo->IF_DEF_YPbPr == 1) {
1294 if ((temp >> 8) & ActiveYPbPr)
1295 tempch |= SetYPbPr;
1296 }
1297 }
1298
1299 tempcl |= SetSimuScanMode;
1300 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1301 || (temp & ActiveCRT2)))
1302 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1303 if ((temp & ActiveLCD) && (temp & ActiveTV))
1304 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1305 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1306
1307 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1308 CR31Data &= ~(SetNotSimuMode >> 8);
1309 if (!(temp & ActiveCRT1))
1310 CR31Data |= (SetNotSimuMode >> 8);
1311 CR31Data &= ~(DisableCRT2Display >> 8);
1312 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1313 CR31Data |= (DisableCRT2Display >> 8);
1314 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1315
1316 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1317 CR38Data &= ~SetYPbPr;
1318 CR38Data |= tempch;
1319 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1320
1321 }
1322
1323 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1324 struct vb_device_info *pVBInfo)
1325 {
1326 unsigned char Temp;
1327 volatile unsigned char *pVideoMemory =
1328 (unsigned char *) pVBInfo->ROMAddr;
1329
1330 pVBInfo->IF_DEF_LVDS = 0;
1331
1332 #if 1
1333 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1334 pVBInfo->IF_DEF_LVDS = 1;
1335 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1336 /* LVDS on chip */
1337 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1338 } else {
1339 #endif
1340 /* Enable GPIOA/B read */
1341 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1342 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1343 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1344 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1345 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1346 /* Enable read GPIOF */
1347 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1348 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1349 if (!Temp)
1350 xgifb_reg_and_or(pVBInfo->P3d4,
1351 0x38,
1352 ~0xE0,
1353 0x80); /* TMDS on chip */
1354 else
1355 xgifb_reg_and_or(pVBInfo->P3d4,
1356 0x38,
1357 ~0xE0,
1358 0xA0); /* Only DVO on chip */
1359 /* Disable read GPIOF */
1360 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1361 }
1362 #if 1
1363 }
1364 #endif
1365 }
1366
1367 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1368 struct vb_device_info *pVBInfo)
1369 {
1370 unsigned char Temp, bCR4A;
1371
1372 pVBInfo->IF_DEF_LVDS = 0;
1373 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1374 /* Enable GPIOA/B/C read */
1375 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1376 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1377 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1378
1379 if (Temp <= 0x02) {
1380 pVBInfo->IF_DEF_LVDS = 1;
1381 /* LVDS setting */
1382 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1383 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1384 } else {
1385 /* TMDS/DVO setting */
1386 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1387 }
1388 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1389
1390 }
1391
1392 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1393 {
1394 unsigned char CR38, CR4A, temp;
1395
1396 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1397 /* enable GPIOE read */
1398 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1399 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1400 temp = 0;
1401 if ((CR38 & 0xE0) > 0x80) {
1402 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1403 temp &= 0x08;
1404 temp >>= 3;
1405 }
1406
1407 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1408
1409 return temp;
1410 }
1411
1412 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1413 {
1414 unsigned char CR4A, temp;
1415
1416 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1417 /* enable GPIOA/B/C read */
1418 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1419 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1420 if (temp <= 2)
1421 temp &= 0x03;
1422 else
1423 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1424
1425 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1426
1427 return temp;
1428 }
1429
1430 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1431 {
1432 struct vb_device_info VBINF;
1433 struct vb_device_info *pVBInfo = &VBINF;
1434 unsigned char i, temp = 0, temp1;
1435 /* VBIOSVersion[5]; */
1436 volatile unsigned char *pVideoMemory;
1437
1438 /* unsigned long j, k; */
1439
1440 unsigned long Temp;
1441
1442 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1443
1444 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1445
1446 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1447
1448 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1449
1450 /* Newdebugcode(0x99); */
1451
1452
1453 /* if (pVBInfo->ROMAddr == 0) */
1454 /* return(0); */
1455
1456 if (pVBInfo->FBAddr == NULL) {
1457 printk("\n pVBInfo->FBAddr == 0 ");
1458 return 0;
1459 }
1460 printk("1");
1461 if (pVBInfo->BaseAddr == 0) {
1462 printk("\npVBInfo->BaseAddr == 0 ");
1463 return 0;
1464 }
1465 printk("2");
1466
1467 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1468
1469 pVBInfo->ISXPDOS = 0;
1470 printk("3");
1471
1472 printk("4");
1473
1474 /* VBIOSVersion[4] = 0x0; */
1475
1476 /* 09/07/99 modify by domao */
1477
1478 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1479 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1480 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1481 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1482 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1483 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1484 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1485 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1486 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1487 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1488 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1489 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1490 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1491 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1492 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1493 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1494 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1495 printk("5");
1496
1497 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1498 /* Run XGI_GetVBType before InitTo330Pointer */
1499 XGI_GetVBType(pVBInfo);
1500
1501 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1502
1503 /* ReadVBIOSData */
1504 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1505
1506 /* 1.Openkey */
1507 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1508 printk("6");
1509
1510 /* GetXG21Sense (GPIO) */
1511 if (HwDeviceExtension->jChipType == XG21)
1512 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1513
1514 if (HwDeviceExtension->jChipType == XG27)
1515 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1516
1517 printk("7");
1518
1519 /* 2.Reset Extended register */
1520
1521 for (i = 0x06; i < 0x20; i++)
1522 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1523
1524 for (i = 0x21; i <= 0x27; i++)
1525 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1526
1527 /* for(i = 0x06; i <= 0x27; i++) */
1528 /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1529
1530 printk("8");
1531
1532 for (i = 0x31; i <= 0x3B; i++)
1533 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1534 printk("9");
1535
1536 /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1537 if (HwDeviceExtension->jChipType == XG42)
1538 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1539
1540 /* for (i = 0x30; i <= 0x3F; i++) */
1541 /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1542
1543 for (i = 0x79; i <= 0x7C; i++)
1544 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1545
1546 printk("10");
1547
1548 if (HwDeviceExtension->jChipType >= XG20)
1549 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1550
1551 /* 3.SetMemoryClock
1552
1553 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
1554 pVBInfo);
1555 */
1556
1557 printk("11");
1558
1559 /* 4.SetDefExt1Regs begin */
1560 xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1561 if (HwDeviceExtension->jChipType == XG27) {
1562 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1563 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1564 }
1565 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1566 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1567 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1568 /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1569 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1570 /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1571 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1572 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1573 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1574
1575 /* SR11 = 0x0F; */
1576 /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1577
1578 printk("12");
1579
1580 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1581 /* Set AGP Rate */
1582 /*
1583 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1584 temp1 &= 0x02;
1585 if (temp1 == 0x02) {
1586 outl(0x80000000, 0xcf8);
1587 ChipsetID = inl(0x0cfc);
1588 outl(0x8000002C, 0xcf8);
1589 VendorID = inl(0x0cfc);
1590 VendorID &= 0x0000FFFF;
1591 outl(0x8001002C, 0xcf8);
1592 GraphicVendorID = inl(0x0cfc);
1593 GraphicVendorID &= 0x0000FFFF;
1594
1595 if (ChipsetID == 0x7301039)
1596 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1597
1598 ChipsetID &= 0x0000FFFF;
1599
1600 if ((ChipsetID == 0x700E) ||
1601 (ChipsetID == 0x1022) ||
1602 (ChipsetID == 0x1106) ||
1603 (ChipsetID == 0x10DE)) {
1604 if (ChipsetID == 0x1106) {
1605 if ((VendorID == 0x1019) &&
1606 (GraphicVendorID == 0x1019))
1607 xgifb_reg_set(pVBInfo->P3d4,
1608 0x5F,
1609 0x0D);
1610 else
1611 xgifb_reg_set(pVBInfo->P3d4,
1612 0x5F,
1613 0x0B);
1614 } else {
1615 xgifb_reg_set(pVBInfo->P3d4,
1616 0x5F,
1617 0x0B);
1618 }
1619 }
1620 }
1621 */
1622
1623 printk("13");
1624
1625 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1626 for (i = 0x47; i <= 0x4C; i++)
1627 xgifb_reg_set(pVBInfo->P3d4,
1628 i,
1629 pVBInfo->AGPReg[i - 0x47]);
1630
1631 for (i = 0x70; i <= 0x71; i++)
1632 xgifb_reg_set(pVBInfo->P3d4,
1633 i,
1634 pVBInfo->AGPReg[6 + i - 0x70]);
1635
1636 for (i = 0x74; i <= 0x77; i++)
1637 xgifb_reg_set(pVBInfo->P3d4,
1638 i,
1639 pVBInfo->AGPReg[8 + i - 0x74]);
1640 /* Set AGP customize registers (in SetDefAGPRegs) End */
1641 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1642 /* outl(0x80000000, 0xcf8); */
1643 /* ChipsetID = inl(0x0cfc); */
1644 /* if (ChipsetID == 0x25308086) */
1645 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1646
1647 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
1648 0x50,
1649 0,
1650 &Temp); /* Get */
1651 Temp >>= 20;
1652 Temp &= 0xF;
1653
1654 if (Temp == 1)
1655 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1656 printk("14");
1657 } /* != XG20 */
1658
1659 /* Set PCI */
1660 xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1661 xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1662 xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1663 printk("15");
1664
1665 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1666 /* Set VB */
1667 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1668 /* alan, disable VideoCapture */
1669 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1670 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1671 /* chk if BCLK>=100MHz */
1672 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1673 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1674
1675 xgifb_reg_set(pVBInfo->Part1Port,
1676 0x02,
1677 (*pVBInfo->pCRT2Data_1_2));
1678
1679 printk("16");
1680
1681 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1682 } /* != XG20 */
1683
1684 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1685
1686 if ((HwDeviceExtension->jChipType == XG42) &&
1687 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1688 /* Not DDR */
1689 xgifb_reg_set(pVBInfo->P3c4,
1690 0x31,
1691 (*pVBInfo->pSR31 & 0x3F) | 0x40);
1692 xgifb_reg_set(pVBInfo->P3c4,
1693 0x32,
1694 (*pVBInfo->pSR32 & 0xFC) | 0x01);
1695 } else {
1696 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1697 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1698 }
1699 xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1700 printk("17");
1701
1702 /*
1703 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1704
1705 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1706 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1707 if (pVBInfo->IF_DEF_LVDS == 0) {
1708 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1709 xgifb_reg_set(pVBInfo->Part4Port,
1710 0x0D,
1711 *pVBInfo->pCRT2Data_4_D);
1712 xgifb_reg_set(pVBInfo->Part4Port,
1713 0x0E,
1714 *pVBInfo->pCRT2Data_4_E);
1715 xgifb_reg_set(pVBInfo->Part4Port,
1716 0x10,
1717 *pVBInfo->pCRT2Data_4_10);
1718 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1719 }
1720
1721 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1722 }
1723 } /* != XG20 */
1724 printk("18");
1725
1726 printk("181");
1727
1728 printk("182");
1729
1730 XGI_SenseCRT1(pVBInfo);
1731
1732 printk("183");
1733 /* XGINew_DetectMonitor(HwDeviceExtension); */
1734 if (HwDeviceExtension->jChipType == XG21) {
1735 printk("186");
1736
1737 xgifb_reg_and_or(pVBInfo->P3d4,
1738 0x32,
1739 ~Monitor1Sense,
1740 Monitor1Sense); /* Z9 default has CRT */
1741 temp = GetXG21FPBits(pVBInfo);
1742 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1743 printk("187");
1744
1745 }
1746 if (HwDeviceExtension->jChipType == XG27) {
1747 xgifb_reg_and_or(pVBInfo->P3d4,
1748 0x32,
1749 ~Monitor1Sense,
1750 Monitor1Sense); /* Z9 default has CRT */
1751 temp = GetXG27FPBits(pVBInfo);
1752 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1753 }
1754 printk("19");
1755
1756 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
1757 pVBInfo);
1758
1759 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1760 pVBInfo->P3d4,
1761 pVBInfo);
1762
1763 printk("20");
1764 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1765 printk("21");
1766
1767 printk("22");
1768
1769 /* SetDefExt2Regs begin */
1770 /*
1771 AGP = 1;
1772 temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1773 temp &= 0x30;
1774 if (temp == 0x30)
1775 AGP = 0;
1776
1777 if (AGP == 0)
1778 *pVBInfo->pSR21 &= 0xEF;
1779
1780 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1781 if (AGP == 1)
1782 *pVBInfo->pSR22 &= 0x20;
1783 xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1784 */
1785 /* base = 0x80000000; */
1786 /* OutPortLong(0xcf8, base); */
1787 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1788 /* if (Temp == 0x1039) { */
1789 xgifb_reg_set(pVBInfo->P3c4,
1790 0x22,
1791 (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1792 /* } else { */
1793 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1794 /* } */
1795
1796 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1797
1798 printk("23");
1799
1800 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1801 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1802
1803 printk("24");
1804
1805 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1806 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1807 printk("25");
1808
1809 return 1;
1810 } /* end of init */