drivers/staging/brcm80211/util/nicpci.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/pci.h>
  20 #include <bcmdefs.h>
  21 #include <osl.h>
  22 #include <bcmutils.h>
  23 #include <siutils.h>
  24 #include <hndsoc.h>
  25 #include <bcmdevs.h>
  26 #include <sbchipc.h>
  27 #include <pci_core.h>
  28 #include <pcie_core.h>
  29 #include <nicpci.h>
  30 #include <pcicfg.h>
  31
  32 typedef struct {
  33         union {
  34                 sbpcieregs_t *pcieregs;
  35                 struct sbpciregs *pciregs;
  36         } regs;                 /* Memory mapped register to the core */
  37
  38         si_t *sih;              /* System interconnect handle */
  39         struct pci_dev *dev;
  40         struct osl_info *osh;           /* OSL handle */
  41         u8 pciecap_lcreg_offset;        /* PCIE capability LCreg offset in the config space */
  42         bool pcie_pr42767;
  43         u8 pcie_polarity;
  44         u8 pcie_war_aspm_ovr;   /* Override ASPM/Clkreq settings */
  45
  46         u8 pmecap_offset;       /* PM Capability offset in the config space */
  47         bool pmecap;            /* Capable of generating PME */
  48 } pcicore_info_t;
  49
  50 /* debug/trace */
  51 #define PCI_ERROR(args)
  52 #define PCIE_PUB(sih) \
  53         (((sih)->bustype == PCI_BUS) && ((sih)->buscoretype == PCIE_CORE_ID))
  54
  55 /* routines to access mdio slave device registers */
  56 static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk);
  57 static int pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr,
  58                        bool write, uint *val);
  59 static int pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint readdr,
  60                           uint val);
  61 static int pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint readdr,
  62                          uint *ret_val);
  63
  64 static void pcie_extendL1timer(pcicore_info_t *pi, bool extend);
  65 static void pcie_clkreq_upd(pcicore_info_t *pi, uint state);
  66
  67 static void pcie_war_aspm_clkreq(pcicore_info_t *pi);
  68 static void pcie_war_serdes(pcicore_info_t *pi);
  69 static void pcie_war_noplldown(pcicore_info_t *pi);
  70 static void pcie_war_polarity(pcicore_info_t *pi);
  71 static void pcie_war_pci_setup(pcicore_info_t *pi);
  72
  73 static bool pcicore_pmecap(pcicore_info_t *pi);
  74
  75 #define PCIE_ASPM(sih)  ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5)))
  76
  77
  78 /* delay needed between the mdio control/ mdiodata register data access */
  79 #define PR28829_DELAY() udelay(10)
  80
  81 /* Initialize the PCI core. It's caller's responsibility to make sure that this is done
  82  * only once
  83  */
  84 void *pcicore_init(si_t *sih, struct osl_info *osh, void *regs)
  85 {
  86         pcicore_info_t *pi;
  87
  88         ASSERT(sih->bustype == PCI_BUS);
  89
  90         /* alloc pcicore_info_t */
  91         pi = kzalloc(sizeof(pcicore_info_t), GFP_ATOMIC);
  92         if (pi == NULL) {
  93                 PCI_ERROR(("pci_attach: malloc failed!\n"));
  94                 return NULL;
  95         }
  96
  97         pi->sih = sih;
  98         pi->osh = osh;
  99         pi->dev = osh->pdev;
 100
 101         if (sih->buscoretype == PCIE_CORE_ID) {
 102                 u8 cap_ptr;
 103                 pi->regs.pcieregs = (sbpcieregs_t *) regs;
 104                 cap_ptr =
 105                     pcicore_find_pci_capability(pi->dev, PCI_CAP_PCIECAP_ID,
 106                                                 NULL, NULL);
 107                 ASSERT(cap_ptr);
 108                 pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
 109         } else
 110                 pi->regs.pciregs = (struct sbpciregs *) regs;
 111
 112         return pi;
 113 }
 114
 115 void pcicore_deinit(void *pch)
 116 {
 117         pcicore_info_t *pi = (pcicore_info_t *) pch;
 118
 119         if (pi == NULL)
 120                 return;
 121         kfree(pi);
 122 }
 123
 124 /* return cap_offset if requested capability exists in the PCI config space */
 125 /* Note that it's caller's responsibility to make sure it's a pci bus */
 126 u8
 127 pcicore_find_pci_capability(void *dev, u8 req_cap_id,
 128                             unsigned char *buf, u32 *buflen)
 129 {
 130         u8 cap_id;
 131         u8 cap_ptr = 0;
 132         u32 bufsize;
 133         u8 byte_val;
 134
 135         /* check for Header type 0 */
 136         pci_read_config_byte(dev, PCI_CFG_HDR, &byte_val);
 137         if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
 138                 goto end;
 139
 140         /* check if the capability pointer field exists */
 141         pci_read_config_byte(dev, PCI_CFG_STAT, &byte_val);
 142         if (!(byte_val & PCI_CAPPTR_PRESENT))
 143                 goto end;
 144
 145         pci_read_config_byte(dev, PCI_CFG_CAPPTR, &cap_ptr);
 146         /* check if the capability pointer is 0x00 */
 147         if (cap_ptr == 0x00)
 148                 goto end;
 149
 150         /* loop thr'u the capability list and see if the pcie capabilty exists */
 151
 152         pci_read_config_byte(dev, cap_ptr, &cap_id);
 153
 154         while (cap_id != req_cap_id) {
 155                 pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
 156                 if (cap_ptr == 0x00)
 157                         break;
 158                 pci_read_config_byte(dev, cap_ptr, &cap_id);
 159         }
 160         if (cap_id != req_cap_id) {
 161                 goto end;
 162         }
 163         /* found the caller requested capability */
 164         if ((buf != NULL) && (buflen != NULL)) {
 165                 u8 cap_data;
 166
 167                 bufsize = *buflen;
 168                 if (!bufsize)
 169                         goto end;
 170                 *buflen = 0;
 171                 /* copy the cpability data excluding cap ID and next ptr */
 172                 cap_data = cap_ptr + 2;
 173                 if ((bufsize + cap_data) > SZPCR)
 174                         bufsize = SZPCR - cap_data;
 175                 *buflen = bufsize;
 176                 while (bufsize--) {
 177                         pci_read_config_byte(dev, cap_data, buf);
 178                         cap_data++;
 179                         buf++;
 180                 }
 181         }
 182  end:
 183         return cap_ptr;
 184 }
 185
 186 /* ***** Register Access API */
 187 uint
 188 pcie_readreg(struct osl_info *osh, sbpcieregs_t *pcieregs, uint addrtype,
 189              uint offset)
 190 {
 191         uint retval = 0xFFFFFFFF;
 192
 193         ASSERT(pcieregs != NULL);
 194
 195         switch (addrtype) {
 196         case PCIE_CONFIGREGS:
 197                 W_REG((&pcieregs->configaddr), offset);
 198                 (void)R_REG((&pcieregs->configaddr));
 199                 retval = R_REG(&(pcieregs->configdata));
 200                 break;
 201         case PCIE_PCIEREGS:
 202                 W_REG(&(pcieregs->pcieindaddr), offset);
 203                 (void)R_REG((&pcieregs->pcieindaddr));
 204                 retval = R_REG(&(pcieregs->pcieinddata));
 205                 break;
 206         default:
 207                 ASSERT(0);
 208                 break;
 209         }
 210
 211         return retval;
 212 }
 213
 214 uint
 215 pcie_writereg(struct osl_info *osh, sbpcieregs_t *pcieregs, uint addrtype,
 216               uint offset, uint val)
 217 {
 218         ASSERT(pcieregs != NULL);
 219
 220         switch (addrtype) {
 221         case PCIE_CONFIGREGS:
 222                 W_REG((&pcieregs->configaddr), offset);
 223                 W_REG((&pcieregs->configdata), val);
 224                 break;
 225         case PCIE_PCIEREGS:
 226                 W_REG((&pcieregs->pcieindaddr), offset);
 227                 W_REG((&pcieregs->pcieinddata), val);
 228                 break;
 229         default:
 230                 ASSERT(0);
 231                 break;
 232         }
 233         return 0;
 234 }
 235
 236 static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
 237 {
 238         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 239         uint mdiodata, i = 0;
 240         uint pcie_serdes_spinwait = 200;
 241
 242         mdiodata =
 243             MDIODATA_START | MDIODATA_WRITE | (MDIODATA_DEV_ADDR <<
 244                                                MDIODATA_DEVADDR_SHF) |
 245             (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk <<
 246                                                                          4);
 247         W_REG(&pcieregs->mdiodata, mdiodata);
 248
 249         PR28829_DELAY();
 250         /* retry till the transaction is complete */
 251         while (i < pcie_serdes_spinwait) {
 252                 if (R_REG(&(pcieregs->mdiocontrol)) &
 253                     MDIOCTL_ACCESS_DONE) {
 254                         break;
 255                 }
 256                 udelay(1000);
 257                 i++;
 258         }
 259
 260         if (i >= pcie_serdes_spinwait) {
 261                 PCI_ERROR(("pcie_mdiosetblock: timed out\n"));
 262                 return false;
 263         }
 264
 265         return true;
 266 }
 267
 268 static int
 269 pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
 270             uint *val)
 271 {
 272         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 273         uint mdiodata;
 274         uint i = 0;
 275         uint pcie_serdes_spinwait = 10;
 276
 277         /* enable mdio access to SERDES */
 278         W_REG((&pcieregs->mdiocontrol),
 279               MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
 280
 281         if (pi->sih->buscorerev >= 10) {
 282                 /* new serdes is slower in rw, using two layers of reg address mapping */
 283                 if (!pcie_mdiosetblock(pi, physmedia))
 284                         return 1;
 285                 mdiodata = (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
 286                     (regaddr << MDIODATA_REGADDR_SHF);
 287                 pcie_serdes_spinwait *= 20;
 288         } else {
 289                 mdiodata = (physmedia << MDIODATA_DEVADDR_SHF_OLD) |
 290                     (regaddr << MDIODATA_REGADDR_SHF_OLD);
 291         }
 292
 293         if (!write)
 294                 mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
 295         else
 296                 mdiodata |=
 297                     (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val);
 298
 299         W_REG(&pcieregs->mdiodata, mdiodata);
 300
 301         PR28829_DELAY();
 302
 303         /* retry till the transaction is complete */
 304         while (i < pcie_serdes_spinwait) {
 305                 if (R_REG(&(pcieregs->mdiocontrol)) &
 306                     MDIOCTL_ACCESS_DONE) {
 307                         if (!write) {
 308                                 PR28829_DELAY();
 309                                 *val =
 310                                     (R_REG(&(pcieregs->mdiodata)) &
 311                                      MDIODATA_MASK);
 312                         }
 313                         /* Disable mdio access to SERDES */
 314                         W_REG((&pcieregs->mdiocontrol), 0);
 315                         return 0;
 316                 }
 317                 udelay(1000);
 318                 i++;
 319         }
 320
 321         PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
 322         /* Disable mdio access to SERDES */
 323         W_REG((&pcieregs->mdiocontrol), 0);
 324         return 1;
 325 }
 326
 327 /* use the mdio interface to read from mdio slaves */
 328 static int
 329 pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint regaddr, uint *regval)
 330 {
 331         return pcie_mdioop(pi, physmedia, regaddr, false, regval);
 332 }
 333
 334 /* use the mdio interface to write to mdio slaves */
 335 static int
 336 pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
 337 {
 338         return pcie_mdioop(pi, physmedia, regaddr, true, &val);
 339 }
 340
 341 /* ***** Support functions ***** */
 342 u8 pcie_clkreq(void *pch, u32 mask, u32 val)
 343 {
 344         pcicore_info_t *pi = (pcicore_info_t *) pch;
 345         u32 reg_val;
 346         u8 offset;
 347
 348         offset = pi->pciecap_lcreg_offset;
 349         if (!offset)
 350                 return 0;
 351
 352         pci_read_config_dword(pi->dev, offset, &reg_val);
 353         /* set operation */
 354         if (mask) {
 355                 if (val)
 356                         reg_val |= PCIE_CLKREQ_ENAB;
 357                 else
 358                         reg_val &= ~PCIE_CLKREQ_ENAB;
 359                 pci_write_config_dword(pi->dev, offset, reg_val);
 360                 pci_read_config_dword(pi->dev, offset, &reg_val);
 361         }
 362         if (reg_val & PCIE_CLKREQ_ENAB)
 363                 return 1;
 364         else
 365                 return 0;
 366 }
 367
 368 static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
 369 {
 370         u32 w;
 371         si_t *sih = pi->sih;
 372         struct osl_info *osh = pi->osh;
 373         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 374
 375         if (!PCIE_PUB(sih) || sih->buscorerev < 7)
 376                 return;
 377
 378         w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
 379         if (extend)
 380                 w |= PCIE_ASPMTIMER_EXTEND;
 381         else
 382                 w &= ~PCIE_ASPMTIMER_EXTEND;
 383         pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
 384         w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
 385 }
 386
 387 /* centralized clkreq control policy */
 388 static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
 389 {
 390         si_t *sih = pi->sih;
 391         ASSERT(PCIE_PUB(sih));
 392
 393         switch (state) {
 394         case SI_DOATTACH:
 395                 if (PCIE_ASPM(sih))
 396                         pcie_clkreq((void *)pi, 1, 0);
 397                 break;
 398         case SI_PCIDOWN:
 399                 if (sih->buscorerev == 6) {     /* turn on serdes PLL down */
 400                         si_corereg(sih, SI_CC_IDX,
 401                                    offsetof(chipcregs_t, chipcontrol_addr), ~0,
 402                                    0);
 403                         si_corereg(sih, SI_CC_IDX,
 404                                    offsetof(chipcregs_t, chipcontrol_data),
 405                                    ~0x40, 0);
 406                 } else if (pi->pcie_pr42767) {
 407                         pcie_clkreq((void *)pi, 1, 1);
 408                 }
 409                 break;
 410         case SI_PCIUP:
 411                 if (sih->buscorerev == 6) {     /* turn off serdes PLL down */
 412                         si_corereg(sih, SI_CC_IDX,
 413                                    offsetof(chipcregs_t, chipcontrol_addr), ~0,
 414                                    0);
 415                         si_corereg(sih, SI_CC_IDX,
 416                                    offsetof(chipcregs_t, chipcontrol_data),
 417                                    ~0x40, 0x40);
 418                 } else if (PCIE_ASPM(sih)) {    /* disable clkreq */
 419                         pcie_clkreq((void *)pi, 1, 0);
 420                 }
 421                 break;
 422         default:
 423                 ASSERT(0);
 424                 break;
 425         }
 426 }
 427
 428 /* ***** PCI core WARs ***** */
 429 /* Done only once at attach time */
 430 static void pcie_war_polarity(pcicore_info_t *pi)
 431 {
 432         u32 w;
 433
 434         if (pi->pcie_polarity != 0)
 435                 return;
 436
 437         w = pcie_readreg(pi->osh, pi->regs.pcieregs, PCIE_PCIEREGS,
 438                          PCIE_PLP_STATUSREG);
 439
 440         /* Detect the current polarity at attach and force that polarity and
 441          * disable changing the polarity
 442          */
 443         if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
 444                 pi->pcie_polarity = (SERDES_RX_CTRL_FORCE);
 445         else
 446                 pi->pcie_polarity =
 447                     (SERDES_RX_CTRL_FORCE | SERDES_RX_CTRL_POLARITY);
 448 }
 449
 450 /* enable ASPM and CLKREQ if srom doesn't have it */
 451 /* Needs to happen when update to shadow SROM is needed
 452  *   : Coming out of 'standby'/'hibernate'
 453  *   : If pcie_war_aspm_ovr state changed
 454  */
 455 static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
 456 {
 457         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 458         si_t *sih = pi->sih;
 459         u16 val16, *reg16;
 460         u32 w;
 461
 462         if (!PCIE_ASPM(sih))
 463                 return;
 464
 465         /* bypass this on QT or VSIM */
 466         if (!ISSIM_ENAB(sih)) {
 467
 468                 reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
 469                 val16 = R_REG(reg16);
 470
 471                 val16 &= ~SRSH_ASPM_ENB;
 472                 if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
 473                         val16 |= SRSH_ASPM_ENB;
 474                 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
 475                         val16 |= SRSH_ASPM_L1_ENB;
 476                 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
 477                         val16 |= SRSH_ASPM_L0s_ENB;
 478
 479                 W_REG(reg16, val16);
 480
 481                 pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset,
 482                                         &w);
 483                 w &= ~PCIE_ASPM_ENAB;
 484                 w |= pi->pcie_war_aspm_ovr;
 485                 pci_write_config_dword(pi->dev,
 486                                         pi->pciecap_lcreg_offset, w);
 487         }
 488
 489         reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
 490         val16 = R_REG(reg16);
 491
 492         if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
 493                 val16 |= SRSH_CLKREQ_ENB;
 494                 pi->pcie_pr42767 = true;
 495         } else
 496                 val16 &= ~SRSH_CLKREQ_ENB;
 497
 498         W_REG(reg16, val16);
 499 }
 500
 501 /* Apply the polarity determined at the start */
 502 /* Needs to happen when coming out of 'standby'/'hibernate' */
 503 static void pcie_war_serdes(pcicore_info_t *pi)
 504 {
 505         u32 w = 0;
 506
 507         if (pi->pcie_polarity != 0)
 508                 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
 509                                pi->pcie_polarity);
 510
 511         pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
 512         if (w & PLL_CTRL_FREQDET_EN) {
 513                 w &= ~PLL_CTRL_FREQDET_EN;
 514                 pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
 515         }
 516 }
 517
 518 /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
 519 /* Needs to happen when coming out of 'standby'/'hibernate' */
 520 static void pcie_misc_config_fixup(pcicore_info_t *pi)
 521 {
 522         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 523         u16 val16, *reg16;
 524
 525         reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
 526         val16 = R_REG(reg16);
 527
 528         if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
 529                 val16 |= SRSH_L23READY_EXIT_NOPERST;
 530                 W_REG(reg16, val16);
 531         }
 532 }
 533
 534 /* quick hack for testing */
 535 /* Needs to happen when coming out of 'standby'/'hibernate' */
 536 static void pcie_war_noplldown(pcicore_info_t *pi)
 537 {
 538         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 539         u16 *reg16;
 540
 541         ASSERT(pi->sih->buscorerev == 7);
 542
 543         /* turn off serdes PLL down */
 544         si_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
 545                    CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
 546
 547         /*  clear srom shadow backdoor */
 548         reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
 549         W_REG(reg16, 0);
 550 }
 551
 552 /* Needs to happen when coming out of 'standby'/'hibernate' */
 553 static void pcie_war_pci_setup(pcicore_info_t *pi)
 554 {
 555         si_t *sih = pi->sih;
 556         struct osl_info *osh = pi->osh;
 557         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 558         u32 w;
 559
 560         if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
 561                 w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
 562                                  PCIE_TLP_WORKAROUNDSREG);
 563                 w |= 0x8;
 564                 pcie_writereg(osh, pcieregs, PCIE_PCIEREGS,
 565                               PCIE_TLP_WORKAROUNDSREG, w);
 566         }
 567
 568         if (sih->buscorerev == 1) {
 569                 w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
 570                 w |= (0x40);
 571                 pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
 572         }
 573
 574         if (sih->buscorerev == 0) {
 575                 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
 576                 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
 577                 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
 578         } else if (PCIE_ASPM(sih)) {
 579                 /* Change the L1 threshold for better performance */
 580                 w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
 581                                  PCIE_DLLP_PMTHRESHREG);
 582                 w &= ~(PCIE_L1THRESHOLDTIME_MASK);
 583                 w |= (PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT);
 584                 pcie_writereg(osh, pcieregs, PCIE_PCIEREGS,
 585                               PCIE_DLLP_PMTHRESHREG, w);
 586
 587                 pcie_war_serdes(pi);
 588
 589                 pcie_war_aspm_clkreq(pi);
 590         } else if (pi->sih->buscorerev == 7)
 591                 pcie_war_noplldown(pi);
 592
 593         /* Note that the fix is actually in the SROM, that's why this is open-ended */
 594         if (pi->sih->buscorerev >= 6)
 595                 pcie_misc_config_fixup(pi);
 596 }
 597
 598 void pcie_war_ovr_aspm_update(void *pch, u8 aspm)
 599 {
 600         pcicore_info_t *pi = (pcicore_info_t *) pch;
 601
 602         if (!PCIE_ASPM(pi->sih))
 603                 return;
 604
 605         /* Validate */
 606         if (aspm > PCIE_ASPM_ENAB)
 607                 return;
 608
 609         pi->pcie_war_aspm_ovr = aspm;
 610
 611         /* Update the current state */
 612         pcie_war_aspm_clkreq(pi);
 613 }
 614
 615 /* ***** Functions called during driver state changes ***** */
 616 void pcicore_attach(void *pch, char *pvars, int state)
 617 {
 618         pcicore_info_t *pi = (pcicore_info_t *) pch;
 619         si_t *sih = pi->sih;
 620
 621         /* Determine if this board needs override */
 622         if (PCIE_ASPM(sih)) {
 623                 if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
 624                         pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
 625                 } else {
 626                         pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
 627                 }
 628         }
 629
 630         /* These need to happen in this order only */
 631         pcie_war_polarity(pi);
 632
 633         pcie_war_serdes(pi);
 634
 635         pcie_war_aspm_clkreq(pi);
 636
 637         pcie_clkreq_upd(pi, state);
 638
 639 }
 640
 641 void pcicore_hwup(void *pch)
 642 {
 643         pcicore_info_t *pi = (pcicore_info_t *) pch;
 644
 645         if (!pi || !PCIE_PUB(pi->sih))
 646                 return;
 647
 648         pcie_war_pci_setup(pi);
 649 }
 650
 651 void pcicore_up(void *pch, int state)
 652 {
 653         pcicore_info_t *pi = (pcicore_info_t *) pch;
 654
 655         if (!pi || !PCIE_PUB(pi->sih))
 656                 return;
 657
 658         /* Restore L1 timer for better performance */
 659         pcie_extendL1timer(pi, true);
 660
 661         pcie_clkreq_upd(pi, state);
 662 }
 663
 664 /* When the device is going to enter D3 state (or the system is going to enter S3/S4 states */
 665 void pcicore_sleep(void *pch)
 666 {
 667         pcicore_info_t *pi = (pcicore_info_t *) pch;
 668         u32 w;
 669
 670         if (!pi || !PCIE_ASPM(pi->sih))
 671                 return;
 672
 673         pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
 674         w &= ~PCIE_CAP_LCREG_ASPML1;
 675         pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
 676
 677         pi->pcie_pr42767 = false;
 678 }
 679
 680 void pcicore_down(void *pch, int state)
 681 {
 682         pcicore_info_t *pi = (pcicore_info_t *) pch;
 683
 684         if (!pi || !PCIE_PUB(pi->sih))
 685                 return;
 686
 687         pcie_clkreq_upd(pi, state);
 688
 689         /* Reduce L1 timer for better power savings */
 690         pcie_extendL1timer(pi, false);
 691 }
 692
 693 /* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */
 694 /* Just uses PCI config accesses to find out, when needed before sb_attach is done */
 695 bool pcicore_pmecap_fast(void *pch)
 696 {
 697         pcicore_info_t *pi = (pcicore_info_t *) pch;
 698         u8 cap_ptr;
 699         u32 pmecap;
 700
 701         cap_ptr =
 702             pcicore_find_pci_capability(pi->dev, PCI_CAP_POWERMGMTCAP_ID, NULL,
 703                                         NULL);
 704
 705         if (!cap_ptr)
 706                 return false;
 707
 708         pci_read_config_dword(pi->dev, cap_ptr, &pmecap);
 709
 710         return (pmecap & PME_CAP_PM_STATES) != 0;
 711 }
 712
 713 /* return true if PM capability exists in the pci config space
 714  * Uses and caches the information using core handle
 715  */
 716 static bool pcicore_pmecap(pcicore_info_t *pi)
 717 {
 718         u8 cap_ptr;
 719         u32 pmecap;
 720
 721         if (!pi->pmecap_offset) {
 722                 cap_ptr =
 723                     pcicore_find_pci_capability(pi->dev,
 724                                                 PCI_CAP_POWERMGMTCAP_ID, NULL,
 725                                                 NULL);
 726                 if (!cap_ptr)
 727                         return false;
 728
 729                 pi->pmecap_offset = cap_ptr;
 730
 731                 pci_read_config_dword(pi->dev, pi->pmecap_offset,
 732                                         &pmecap);
 733
 734                 /* At least one state can generate PME */
 735                 pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
 736         }
 737
 738         return pi->pmecap;
 739 }
 740
 741 /* Enable PME generation */
 742 void pcicore_pmeen(void *pch)
 743 {
 744         pcicore_info_t *pi = (pcicore_info_t *) pch;
 745         u32 w;
 746
 747         /* if not pmecapable return */
 748         if (!pcicore_pmecap(pi))
 749                 return;
 750
 751         pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
 752                                 &w);
 753         w |= (PME_CSR_PME_EN);
 754         pci_write_config_dword(pi->dev,
 755                                 pi->pmecap_offset + PME_CSR_OFFSET, w);
 756 }
 757
 758 /*
 759  * Return true if PME status set
 760  */
 761 bool pcicore_pmestat(void *pch)
 762 {
 763         pcicore_info_t *pi = (pcicore_info_t *) pch;
 764         u32 w;
 765
 766         if (!pcicore_pmecap(pi))
 767                 return false;
 768
 769         pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
 770                                 &w);
 771
 772         return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
 773 }
 774
 775 /* Disable PME generation, clear the PME status bit if set
 776  */
 777 void pcicore_pmeclr(void *pch)
 778 {
 779         pcicore_info_t *pi = (pcicore_info_t *) pch;
 780         u32 w;
 781
 782         if (!pcicore_pmecap(pi))
 783                 return;
 784
 785         pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
 786                                 &w);
 787
 788         PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
 789
 790         /* PMESTAT is cleared by writing 1 to it */
 791         w &= ~(PME_CSR_PME_EN);
 792
 793         pci_write_config_dword(pi->dev,
 794                                 pi->pmecap_offset + PME_CSR_OFFSET, w);
 795 }
 796
 797 u32 pcie_lcreg(void *pch, u32 mask, u32 val)
 798 {
 799         pcicore_info_t *pi = (pcicore_info_t *) pch;
 800         u8 offset;
 801         u32 tmpval;
 802
 803         offset = pi->pciecap_lcreg_offset;
 804         if (!offset)
 805                 return 0;
 806
 807         /* set operation */
 808         if (mask)
 809                 pci_write_config_dword(pi->dev, offset, val);
 810
 811         pci_read_config_dword(pi->dev, offset, &tmpval);
 812         return tmpval;
 813 }
 814
 815 u32
 816 pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
 817 {
 818         u32 reg_val = 0;
 819         pcicore_info_t *pi = (pcicore_info_t *) pch;
 820         sbpcieregs_t *pcieregs = pi->regs.pcieregs;
 821         struct osl_info *osh = pi->osh;
 822
 823         if (mask) {
 824                 PCI_ERROR(("PCIEREG: 0x%x writeval  0x%x\n", offset, val));
 825                 pcie_writereg(osh, pcieregs, type, offset, val);
 826         }
 827
 828         /* Should not read register 0x154 */
 829         if (pi->sih->buscorerev <= 5 && offset == PCIE_DLLP_PCIE11
 830             && type == PCIE_PCIEREGS)
 831                 return reg_val;
 832
 833         reg_val = pcie_readreg(osh, pcieregs, type, offset);
 834         PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val));
 835
 836         return reg_val;
 837 }
 838
 839 u32
 840 pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
 841                       u32 val)
 842 {
 843         u32 reg_val = 0;
 844         pcicore_info_t *pi = (pcicore_info_t *) pch;
 845
 846         if (mask) {
 847                 PCI_ERROR(("PCIEMDIOREG: 0x%x writeval  0x%x\n", offset, val));
 848                 pcie_mdiowrite(pi, mdioslave, offset, val);
 849         }
 850
 851         if (pcie_mdioread(pi, mdioslave, offset, &reg_val))
 852                 reg_val = 0xFFFFFFFF;
 853         PCI_ERROR(("PCIEMDIOREG: dev 0x%x offset 0x%x read 0x%x\n", mdioslave,
 854                    offset, reg_val));
 855
 856         return reg_val;
 857 }