module/zcommon/zfs_fletcher_intel.c

   1 /*
   2  * Implement fast Fletcher4 with AVX2 instructions. (x86_64)
   3  *
   4  * Use the 256-bit AVX2 SIMD instructions and registers to compute
   5  * Fletcher4 in four incremental 64-bit parallel accumulator streams,
   6  * and then combine the streams to form the final four checksum words.
   7  *
   8  * Copyright (C) 2015 Intel Corporation.
   9  *
  10  * Authors:
  11  *      James Guilford <james.guilford@intel.com>
  12  *      Jinshan Xiong <jinshan.xiong@intel.com>
  13  *
  14  * This software is available to you under a choice of one of two
  15  * licenses.  You may choose to be licensed under the terms of the GNU
  16  * General Public License (GPL) Version 2, available from the file
  17  * COPYING in the main directory of this source tree, or the
  18  * OpenIB.org BSD license below:
  19  *
  20  *     Redistribution and use in source and binary forms, with or
  21  *     without modification, are permitted provided that the following
  22  *     conditions are met:
  23  *
  24  *      - Redistributions of source code must retain the above
  25  *        copyright notice, this list of conditions and the following
  26  *        disclaimer.
  27  *
  28  *      - Redistributions in binary form must reproduce the above
  29  *        copyright notice, this list of conditions and the following
  30  *        disclaimer in the documentation and/or other materials
  31  *        provided with the distribution.
  32  *
  33  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  35  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  37  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  38  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  39  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  40  * SOFTWARE.
  41  */
  42
  43 #if defined(HAVE_AVX) && defined(HAVE_AVX2)
  44
  45 #include <sys/spa_checksum.h>
  46 #include <sys/string.h>
  47 #include <sys/simd.h>
  48 #include <zfs_fletcher.h>
  49
  50 static void
  51 fletcher_4_avx2_init(fletcher_4_ctx_t *ctx)
  52 {
  53         memset(ctx->avx, 0, 4 * sizeof (zfs_fletcher_avx_t));
  54 }
  55
  56 static void
  57 fletcher_4_avx2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
  58 {
  59         uint64_t A, B, C, D;
  60
  61         A = ctx->avx[0].v[0] + ctx->avx[0].v[1] +
  62             ctx->avx[0].v[2] + ctx->avx[0].v[3];
  63         B = 0 - ctx->avx[0].v[1] - 2 * ctx->avx[0].v[2] - 3 * ctx->avx[0].v[3] +
  64             4 * ctx->avx[1].v[0] + 4 * ctx->avx[1].v[1] + 4 * ctx->avx[1].v[2] +
  65             4 * ctx->avx[1].v[3];
  66
  67         C = ctx->avx[0].v[2] + 3 * ctx->avx[0].v[3] - 6 * ctx->avx[1].v[0] -
  68             10 * ctx->avx[1].v[1] - 14 * ctx->avx[1].v[2] -
  69             18 * ctx->avx[1].v[3] + 16 * ctx->avx[2].v[0] +
  70             16 * ctx->avx[2].v[1] + 16 * ctx->avx[2].v[2] +
  71             16 * ctx->avx[2].v[3];
  72
  73         D = 0 - ctx->avx[0].v[3] + 4 * ctx->avx[1].v[0] +
  74             10 * ctx->avx[1].v[1] + 20 * ctx->avx[1].v[2] +
  75             34 * ctx->avx[1].v[3] - 48 * ctx->avx[2].v[0] -
  76             64 * ctx->avx[2].v[1] - 80 * ctx->avx[2].v[2] -
  77             96 * ctx->avx[2].v[3] + 64 * ctx->avx[3].v[0] +
  78             64 * ctx->avx[3].v[1] + 64 * ctx->avx[3].v[2] +
  79             64 * ctx->avx[3].v[3];
  80
  81         ZIO_SET_CHECKSUM(zcp, A, B, C, D);
  82 }
  83
  84 #define FLETCHER_4_AVX2_RESTORE_CTX(ctx)                                \
  85 {                                                                       \
  86         asm volatile("vmovdqu %0, %%ymm0" :: "m" ((ctx)->avx[0]));      \
  87         asm volatile("vmovdqu %0, %%ymm1" :: "m" ((ctx)->avx[1]));      \
  88         asm volatile("vmovdqu %0, %%ymm2" :: "m" ((ctx)->avx[2]));      \
  89         asm volatile("vmovdqu %0, %%ymm3" :: "m" ((ctx)->avx[3]));      \
  90 }
  91
  92 #define FLETCHER_4_AVX2_SAVE_CTX(ctx)                                   \
  93 {                                                                       \
  94         asm volatile("vmovdqu %%ymm0, %0" : "=m" ((ctx)->avx[0]));      \
  95         asm volatile("vmovdqu %%ymm1, %0" : "=m" ((ctx)->avx[1]));      \
  96         asm volatile("vmovdqu %%ymm2, %0" : "=m" ((ctx)->avx[2]));      \
  97         asm volatile("vmovdqu %%ymm3, %0" : "=m" ((ctx)->avx[3]));      \
  98 }
  99
 100
 101 static void
 102 fletcher_4_avx2_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
 103 {
 104         const uint64_t *ip = buf;
 105         const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
 106
 107         FLETCHER_4_AVX2_RESTORE_CTX(ctx);
 108
 109         do {
 110                 asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
 111                 asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
 112                 asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
 113                 asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
 114                 asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
 115         } while ((ip += 2) < ipend);
 116
 117         FLETCHER_4_AVX2_SAVE_CTX(ctx);
 118         asm volatile("vzeroupper");
 119 }
 120
 121 static void
 122 fletcher_4_avx2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
 123 {
 124         static const zfs_fletcher_avx_t mask = {
 125                 .v = { 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B,
 126                     0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B }
 127         };
 128         const uint64_t *ip = buf;
 129         const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
 130
 131         FLETCHER_4_AVX2_RESTORE_CTX(ctx);
 132
 133         asm volatile("vmovdqu %0, %%ymm5" :: "m" (mask));
 134
 135         do {
 136                 asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
 137                 asm volatile("vpshufb %ymm5, %ymm4, %ymm4");
 138
 139                 asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
 140                 asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
 141                 asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
 142                 asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
 143         } while ((ip += 2) < ipend);
 144
 145         FLETCHER_4_AVX2_SAVE_CTX(ctx);
 146         asm volatile("vzeroupper");
 147 }
 148
 149 static boolean_t fletcher_4_avx2_valid(void)
 150 {
 151         return (kfpu_allowed() && zfs_avx_available() && zfs_avx2_available());
 152 }
 153
 154 const fletcher_4_ops_t fletcher_4_avx2_ops = {
 155         .init_native = fletcher_4_avx2_init,
 156         .fini_native = fletcher_4_avx2_fini,
 157         .compute_native = fletcher_4_avx2_native,
 158         .init_byteswap = fletcher_4_avx2_init,
 159         .fini_byteswap = fletcher_4_avx2_fini,
 160         .compute_byteswap = fletcher_4_avx2_byteswap,
 161         .valid = fletcher_4_avx2_valid,
 162         .uses_fpu = B_TRUE,
 163         .name = "avx2"
 164 };
 165
 166 #endif /* defined(HAVE_AVX) && defined(HAVE_AVX2) */