zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd

   1 -- top module of
   2 -- Spartan-3E Starter Kit Board
   3 --
   4 -- using following external connections:
   5 -- rotary pushbutton as reset
   6 -- LEDs   for output
   7 -- RS232 (DCE, the left one)
   8 --
   9
  10
  11 library ieee;
  12 use ieee.std_logic_1164.all;
  13
  14 library zpu;
  15 use zpu.zpupkg.all;                     -- zpu_dbgo_t
  16
  17 library unisim;
  18 use unisim.vcomponents.dcm_sp;
  19
  20
  21 entity top is
  22     port (
  23         -- pragma translate_off
  24         stop_simulation : out   std_logic;
  25         -- pragma translate_on
  26         --
  27         -- Analog-to-Digital Converter (ADC)
  28         ad_conv         : out   std_logic;
  29         -- Programmable Gain Amplifier (AMP)
  30         amp_cs          : out   std_logic;  -- active low chip select
  31         amp_dout        : in    std_logic;
  32         amp_shdn        : out   std_logic;  -- active high shutdown, reset
  33         -- Pushbuttons (BTN)
  34         btn_east        : in    std_logic;
  35         btn_north       : in    std_logic;
  36         btn_south       : in    std_logic;
  37         btn_west        : in    std_logic;
  38         -- Clock inputs (CLK)
  39         clk_50mhz       : in    std_logic;
  40         clk_aux         : in    std_logic;
  41         clk_sma         : in    std_logic;
  42         -- Digital-to-Analog Converter (DAC)
  43         dac_clr         : out   std_logic;  -- async, active low reset input
  44         dac_cs          : out   std_logic;  -- active low chip select, conv start with rising edge
  45         -- 1-Wire Secure EEPROM (DS)
  46         ds_wire         : inout std_logic;
  47         -- Ethernet PHY (E)
  48         e_col           : in    std_logic;  -- MII collision detect
  49         e_crs           : in    std_logic;  -- carrier sense
  50         e_mdc           : out   std_logic;  -- management clock
  51         e_mdio          : inout std_logic;  -- management data io
  52         e_rx_clk        : in    std_logic;  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
  53         e_rx_dv         : in    std_logic;  -- receive data valid
  54         e_rxd           : in    std_logic_vector(3 downto 0);
  55         e_rx_er         : in    std_logic;
  56         e_tx_clk        : in    std_logic;  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
  57         e_tx_en         : out   std_logic;  -- transmit enable
  58         e_txd           : out   std_logic_vector(3 downto 0);
  59         e_tx_er         : out   std_logic;
  60         -- FPGA Configuration Mode, INIT_B Pins (FPGA)
  61         fpga_m0         : inout std_logic;
  62         fpga_m1         : inout std_logic;
  63         fpga_m2         : inout std_logic;
  64         fpga_init_b     : inout std_logic;
  65         fpga_rdwr_b     : in    std_logic;
  66         fpga_hswap      : in    std_logic;
  67         -- FX2 Connector (FX2)
  68         fx2_clkin       : inout std_logic;
  69         fx2_clkio       : inout std_logic;
  70         fx2_clkout      : inout std_logic;
  71         fx2_io          : inout std_logic_vector(40 downto 1);
  72         -- These are shared connections with the FX2 connector
  73         --j1              : inout std_logic_vector(3 downto 0);
  74         --j2              : inout std_logic_vector(3 downto 0);
  75         --j4              : inout std_logic_vector(3 downto 0);
  76         --led             : out   std_logic_vector(7 downto 0);
  77         -- Character LCD (LCD)
  78         lcd_e           : out   std_logic;
  79         lcd_rs          : out   std_logic;
  80         lcd_rw          : out   std_logic;
  81         -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
  82         --sf_d          : inout std_ulogic_vector(11 downto 8);
  83         -- PS/2 Mouse/Keyboard Port (PS2)
  84         ps2_clk         : inout std_logic;
  85         ps2_data        : inout std_logic;
  86         -- Rotary Pushbutton Switch (ROT)
  87         rot_a           : in    std_logic;
  88         rot_b           : in    std_logic;
  89         rot_center      : in    std_logic;
  90         -- RS-232 Serial Ports (RS232)
  91         rs232_dce_rxd   : in    std_logic;
  92         rs232_dce_txd   : out   std_logic;
  93         rs232_dte_rxd   : in    std_logic;
  94         rs232_dte_txd   : out   std_logic;
  95         -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
  96         sd_a            : out   std_logic_vector(12 downto 0);  -- address inputs
  97         sd_dq           : inout std_logic_vector(15 downto 0);  -- data io
  98         sd_ba           : out   std_logic_vector(1 downto 0);   -- bank address inputs
  99         sd_ras          : out   std_logic;                      -- command output
 100         sd_cas          : out   std_logic;                      -- command output
 101         sd_we           : out   std_logic;                      -- command output
 102         sd_udm          : out   std_logic;                      -- data mask
 103         sd_ldm          : out   std_logic;                      -- data mask
 104         sd_udqs         : inout std_logic;                      -- data strobe
 105         sd_ldqs         : inout std_logic;                      -- data strobe
 106         sd_cs           : out   std_logic;                      -- active low chip select
 107         sd_cke          : out   std_logic;                      -- active high clock enable
 108         sd_ck_n         : out   std_logic;                      -- differential clock
 109         sd_ck_p         : out   std_logic;                      -- differential clock
 110         -- Path to allow connection to top DCM connection
 111         sd_ck_fb        : in    std_logic;
 112         -- Intel StrataFlash Parallel NOR Flash (SF)
 113         sf_a            : out   std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32
 114         sf_byte         : out   std_logic;
 115         sf_ce0          : out   std_logic;
 116         sf_d            : inout std_logic_vector(15 downto 1);
 117         sf_oe           : out   std_logic;
 118         sf_sts          : in    std_logic;
 119         sf_we           : out   std_logic;
 120         -- STMicro SPI serial Flash (SPI)
 121         spi_mosi        : out   std_logic;  -- master out slave in
 122         spi_miso        : in    std_logic;  -- master in  slave out
 123         spi_sck         : out   std_logic;  -- clock
 124         spi_ss_b        : out   std_logic;  -- active low slave select
 125         spi_alt_cs_jp11 : out   std_logic;
 126         -- Slide Switches (SW)
 127         sw              : in    std_logic_vector(3 downto 0);
 128         -- VGA Port (VGA)
 129         vga_blue        : out   std_logic;
 130         vga_green       : out   std_logic;
 131         vga_hsync       : out   std_logic;
 132         vga_red         : out   std_logic;
 133         vga_vsync       : out   std_logic;
 134         -- Xilinx CPLD (XC)
 135         xc_cmd          : out   std_logic_vector(1 downto 0);
 136         xc_cpld_en      : out   std_logic;
 137         xc_d            : inout std_logic_vector(2 downto 0);
 138         xc_trig         : in    std_logic;
 139         xc_gck0         : inout std_logic;
 140         gclk10          : inout std_logic
 141         );
 142 end entity top;
 143
 144
 145 architecture rtl of top is
 146
 147     ---------------------------
 148     -- type declarations
 149     type zpu_type is (zpu_small, zpu_medium);
 150
 151     ---------------------------
 152     -- constant declarations
 153     constant zpu_flavour : zpu_type := zpu_medium;  -- choose your flavour HERE
 154     --  modify frequency here
 155     constant clk_multiply : positive := 3;  -- 2 for small, 3 for medium
 156     constant clk_divide   : positive := 2;  -- 1 for small, 2 for medium
 157     --
 158     constant word_size_c  : natural  := 32; -- 32 bits data path
 159     constant addr_w_c     : natural  := 18; -- 18 bits address space=256 kB, 128 kB I/O
 160
 161
 162     constant spi_ss_b_disable    : std_ulogic := '1';  -- 1 = disable SPI serial flash
 163     constant dac_cs_disable      : std_ulogic := '1';  -- 1 = disable DAC
 164     constant amp_cs_disable      : std_ulogic := '1';  -- 1 = disable programmable pre-amplifier
 165     constant ad_conv_disable     : std_ulogic := '0';  -- 0 = disable ADC
 166     constant sf_ce0_disable      : std_ulogic := '1';
 167     constant fpga_init_b_disable : std_ulogic := '1';  -- 1 = disable pflatform flash PROM
 168     --
 169     -- connect ldc to fpga
 170     constant sf_ce0_lcd_to_fpga  : std_ulogic := '1';
 171     --
 172     constant clk_frequency       : positive   := 50;   -- input frequency for correct calculation
 173
 174
 175     ---------------------------
 176     -- component declarations
 177     component zpu_small1 is
 178         generic (
 179             word_size  : natural   := 32;      -- 32 bits data path
 180             d_care_val : std_logic := '0';     -- Fill value
 181             clk_freq   : positive  := 50;      -- 50 MHz clock
 182             brate      : positive  := 115200;  -- RS232 baudrate
 183             addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
 184             bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
 185             );
 186         port (
 187             clk_i      : in  std_logic;        -- CPU clock
 188             rst_i      : in  std_logic;        -- Reset
 189             break_o    : out std_logic;        -- Break executed
 190             dbg_o      : out zpu_dbgo_t;       -- Debug info
 191             rs232_tx_o : out std_logic;        -- UART Tx
 192             rs232_rx_i : in  std_logic;        -- UART Rx
 193             gpio_in    : in  std_logic_vector(31 downto 0);
 194             gpio_out   : out std_logic_vector(31 downto 0);
 195             gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
 196             );
 197     end component zpu_small1;
 198
 199     component zpu_med1 is
 200         generic(
 201             word_size  : natural   := 32;      -- 32 bits data path
 202             d_care_val : std_logic := '0';     -- Fill value
 203             clk_freq   : positive  := 50;      -- 50 MHz clock
 204             brate      : positive  := 115200;  -- RS232 baudrate
 205             addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
 206             bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
 207             );
 208         port(
 209             clk_i      : in  std_logic;        -- CPU clock
 210             rst_i      : in  std_logic;        -- Reset
 211             break_o    : out std_logic;        -- Break executed
 212             dbg_o      : out zpu_dbgo_t;       -- Debug info
 213             rs232_tx_o : out std_logic;        -- UART Tx
 214             rs232_rx_i : in  std_logic;        -- UART Rx
 215             gpio_in    : in  std_logic_vector(31 downto 0);
 216             gpio_out   : out std_logic_vector(31 downto 0);
 217             gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
 218             );
 219     end component zpu_med1;
 220
 221
 222     ---------------------------
 223     -- signal declarations
 224     signal dcm_sp_i0_clk0  : std_ulogic;
 225     signal dcm_sp_i0_clkfx : std_ulogic;
 226     signal clk_fb          : std_ulogic;
 227     signal clk             : std_ulogic;
 228     --
 229     signal reset_shift_reg : std_ulogic_vector(3 downto 0);
 230     signal reset_sync      : std_ulogic;
 231     --
 232     signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info
 233     signal zpu_i0_break    : std_logic;
 234     --
 235     signal gpio_in         : std_logic_vector(31 downto 0);
 236     signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
 237     signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
 238
 239     ---------------------------
 240     -- alias declarations
 241     alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
 242
 243
 244 begin
 245
 246     -- default output drivers
 247     -- to pass bitgen DRC
 248     -- outputs used by design are commented
 249     --
 250     ad_conv           <= ad_conv_disable;
 251     amp_cs            <= amp_cs_disable;
 252     amp_shdn          <= '1';
 253     --
 254     dac_clr           <= '0';
 255     dac_cs            <= dac_cs_disable;
 256     --
 257     ds_wire           <= 'Z';
 258     --
 259     e_txd(3 downto 0) <= (others => '1');
 260     e_tx_en           <= '0';
 261     e_tx_er           <= '0';
 262     e_mdc             <= '1';
 263     e_mdio            <= 'Z';
 264     --
 265     fpga_m0           <= 'Z';
 266     fpga_m1           <= 'Z';
 267     fpga_m2           <= 'Z';
 268     fpga_init_b       <= fpga_init_b_disable;
 269     --
 270     fx2_clkin         <= 'Z';
 271     fx2_clkio         <= 'Z';
 272     fx2_clkout        <= 'Z';
 273     fx2_io            <= (others => 'Z');
 274     --
 275     lcd_e             <= '0';
 276     lcd_rs            <= '0';
 277     lcd_rw            <= '0';
 278     --
 279     ps2_clk           <= 'Z';
 280     ps2_data          <= 'Z';
 281     --
 282     --rs232_dce_txd     <= '1';
 283     rs232_dte_txd     <= '1';
 284     --
 285     sd_a              <= (others => '1');
 286     sd_dq             <= (others => 'Z');
 287     sd_ba             <= (others => '1');
 288     sd_ras            <= '0';
 289     sd_cas            <= '0';
 290     sd_we             <= '0';
 291     sd_udm            <= '1';
 292     sd_ldm            <= '1';
 293     sd_udqs           <= '1';
 294     sd_ldqs           <= '1';
 295     sd_cs             <= '1';
 296     sd_cke            <= '1';
 297     sd_ck_n           <= '0';
 298     sd_ck_p           <= '1';
 299     --
 300     sf_a              <= (others => '0');
 301     sf_byte           <= '0';
 302     sf_ce0            <= sf_ce0_lcd_to_fpga;
 303     sf_d              <= (others => 'Z');
 304     sf_oe             <= '1';
 305     sf_we             <= '0';
 306     --
 307     spi_mosi          <= '0';
 308     spi_sck           <= '0';
 309     spi_ss_b          <= spi_ss_b_disable;
 310     spi_alt_cs_jp11   <= spi_ss_b_disable;
 311     --
 312     vga_red           <= '0';
 313     vga_green         <= '0';
 314     vga_blue          <= '0';
 315     vga_hsync         <= '0';
 316     vga_vsync         <= '0';
 317     --
 318     xc_cmd            <= "00";
 319     xc_d              <= (others => 'Z');
 320     xc_cpld_en        <= '0';
 321     xc_gck0           <= 'Z';
 322     gclk10            <= 'Z';
 323     -- led out
 324     --fx2_io(20 downto 13) <= (others => '0');
 325
 326
 327     -- digital clock manager (DCM)
 328     -- to generate higher/other system clock frequencys
 329     dcm_sp_i0 : dcm_sp
 330         generic map (
 331             startup_wait   => true,     -- wait with DONE till locked
 332             clkfx_multiply => clk_multiply,
 333             clkfx_divide   => clk_divide,
 334             clk_feedback   => "1X"
 335             )
 336         port map (
 337             clkin => clk_50mhz,
 338             clk0  => dcm_sp_i0_clk0,
 339             clkfx => dcm_sp_i0_clkfx,
 340             clkfb => clk_fb
 341             );
 342
 343     clk_fb <= dcm_sp_i0_clk0;
 344     clk    <= dcm_sp_i0_clkfx;
 345
 346
 347     -- reset synchronizer
 348     -- generate synchronous reset
 349     reset_synchronizer : process(clk, rot_center)
 350     begin
 351         if rot_center = '1' then
 352             reset_shift_reg <= (others => '1');
 353         elsif rising_edge(clk) then
 354             reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
 355         end if;
 356     end process;
 357     reset_sync <= reset_shift_reg(reset_shift_reg'high);
 358
 359
 360     -- select instance of zpu
 361     zpu_i0_small : if zpu_flavour = zpu_small generate
 362         zpu_i0 : zpu_small1
 363             generic map (
 364                 addr_w    => addr_w_c,
 365                 word_size => word_size_c,
 366                 clk_freq  => clk_frequency * clk_multiply / clk_divide
 367                 )
 368             port map (
 369                 clk_i      => clk,             -- : in  std_logic;   -- CPU clock
 370                 rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
 371                 break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
 372                 dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
 373                 rs232_tx_o => rs232_dce_txd,   -- : out std_logic;   -- UART Tx
 374                 rs232_rx_i => rs232_dce_rxd,   -- : in  std_logic    -- UART Rx
 375                 gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
 376                 gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
 377                 gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
 378                 );
 379     end generate zpu_i0_small;
 380
 381     zpu_i0_medium : if zpu_flavour = zpu_medium generate
 382         zpu_i0 : zpu_med1
 383             generic map (
 384                 addr_w    => addr_w_c,
 385                 word_size => word_size_c,
 386                 clk_freq  => clk_frequency * clk_multiply / clk_divide
 387                 )
 388             port map (
 389                 clk_i      => clk,             -- : in  std_logic;   -- CPU clock
 390                 rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
 391                 break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
 392                 dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
 393                 rs232_tx_o => rs232_dce_txd,   -- : out std_logic;   -- UART Tx
 394                 rs232_rx_i => rs232_dce_rxd,   -- : in  std_logic    -- UART Rx
 395                 gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
 396                 gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
 397                 gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
 398                 );
 399     end generate zpu_i0_medium;
 400
 401
 402     -- pragma translate_off
 403     stop_simulation <= zpu_i0_break;
 404
 405
 406     trace_mod : trace
 407         generic map (
 408             addr_w    => addr_w_c,
 409             word_size => word_size_c,
 410             log_file  => "zpu_trace.log"
 411             )
 412         port map (
 413             clk_i  => clk,
 414             dbg_i  => zpu_i0_dbg,
 415             stop_i => zpu_i0_break,
 416             busy_i => '0'
 417             );
 418     -- pragma translate_on
 419
 420
 421     -- assign GPIOs
 422     -- no bidirectional pins (e.g. headers), so
 423     -- gpio_dir is unused
 424     --
 425     -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16
 426     --
 427     --  in   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
 428     -- out   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
 429     --
 430     --
 431     -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
 432     --
 433     --  in   -- -- -- -- sw(3.....0)  -- ra rb rc be bn bs bw
 434     -- out   -- -- -- -- -- -- -- --  led(7................0)
 435
 436     gpio_in <= ((11) => sw(3),
 437                 (10) => sw(2),
 438                 ( 9) => sw(1),
 439                 ( 8) => sw(0),
 440                 --
 441                 ( 6) => rot_a,
 442                 ( 5) => rot_b,
 443                 ( 4) => rot_center,
 444                 --
 445                 ( 3) => btn_east,
 446                 ( 2) => btn_north,
 447                 ( 1) => btn_south,
 448                 ( 0) => btn_west,
 449                 others => '0');
 450
 451
 452     -- switch on all LEDs in case of break
 453     process
 454     begin
 455         wait until rising_edge(clk);
 456         led <= zpu_i0_gpio_out(7 downto 0);
 457         if zpu_i0_break = '1' then
 458             led <= (others => '1');
 459         end if;
 460     end process;
 461
 462
 463
 464 end architecture rtl;