misc/wishbone/src/wishbone_pkg.vhd

   1 library IEEE;
   2 use IEEE.STD_LOGIC_1164.all;
   3 use IEEE.STD_LOGIC_UNSIGNED.ALL;
   4
   5 package wishbone_pkg is
   6
   7         type wishbone_bus_in is record
   8                 adr                     : std_logic_vector(31 downto 0);
   9                 sel                     : std_logic_vector(3 downto 0);
  10                 we                      : std_logic;
  11                 dat                     : std_logic_vector(31 downto 0);        -- Note! Data written with 'we'
  12                 cyc                     : std_logic;
  13                 stb                     : std_logic;
  14         end record;
  15
  16         type wishbone_bus_out is record
  17                 dat             : std_logic_vector(31 downto 0);
  18                 ack                     : std_logic;
  19         end record;
  20
  21         type wishbone_bus is record
  22                 insig           : wishbone_bus_in;
  23                 outsig          : wishbone_bus_out;
  24         end record;
  25
  26         component atomic32_access is
  27         port (  cpu_clk                 : in std_logic;
  28                         areset                  : in std_logic;
  29
  30                         -- Wishbone from CPU interface
  31                         wb_16_i                 : in wishbone_bus_in;
  32                         wb_16_o         : out wishbone_bus_out;
  33                         -- Wishbone to FPGA registers and ethernet core
  34                         wb_32_i                 : in wishbone_bus_out;
  35                         wb_32_o                 : out wishbone_bus_in);
  36         end component;
  37
  38         component eth_access_corr is
  39         port (  cpu_clk                 : in std_logic;
  40                         areset                  : in std_logic;
  41
  42                         -- Wishbone from Wishbone MUX
  43                         eth_raw_o               : out wishbone_bus_out;
  44                         eth_raw_i               : in wishbone_bus_in;
  45
  46                         -- Wishbone ethernet core
  47                         eth_slave_i     : in wishbone_bus_out;
  48                         eth_slave_o             : out wishbone_bus_in);
  49         end component;
  50
  51
  52 end wishbone_pkg;