zpu/hdl/example_medium/sim_fpga_top.vhd

   1 --------------------------------------------------------------------------------
   2 -- ZPU
   3 --
   4 -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
   5 --
   6 -- The FreeBSD license
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  12 -- 1. Redistributions of source code must retain the above copyright
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  23 -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  24 -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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  35 --------------------------------------------------------------------------------
  36
  37 library ieee;
  38 use ieee.std_logic_1164.all;
  39
  40 library work;
  41 use work.zpu_config.all;
  42
  43
  44 entity fpga_top is
  45 end fpga_top;
  46
  47 use work.zpupkg.all;
  48
  49 architecture behave of fpga_top is
  50
  51
  52     signal clk    : std_logic;
  53
  54     signal areset : std_logic := '1';
  55
  56
  57     component  zpu_io is
  58         generic (
  59             log_file:       string  := "log.txt"
  60         );
  61         port (
  62             clk         : in  std_logic;
  63             areset      : in  std_logic;
  64             busy        : out std_logic;
  65             writeEnable : in  std_logic;
  66             readEnable  : in  std_logic;
  67             write       : in  std_logic_vector(wordSize-1 downto 0);
  68             read        : out std_logic_vector(wordSize-1 downto 0);
  69             addr        : in  std_logic_vector(maxAddrBit downto minAddrBit)
  70         );
  71     end component;
  72
  73
  74     signal mem_busy             : std_logic;
  75     signal mem_read             : std_logic_vector(wordSize-1 downto 0);
  76     signal mem_write            : std_logic_vector(wordSize-1 downto 0);
  77     signal mem_addr             : std_logic_vector(maxAddrBitIncIO downto 0);
  78     signal mem_writeEnable      : std_logic;
  79     signal mem_readEnable       : std_logic;
  80     signal mem_writeMask        : std_logic_vector(wordBytes-1 downto 0);
  81
  82     signal enable               : std_logic;
  83
  84     signal dram_mem_busy        : std_logic;
  85     signal dram_mem_read        : std_logic_vector(wordSize-1 downto 0);
  86     signal dram_mem_write       : std_logic_vector(wordSize-1 downto 0);
  87     signal dram_mem_writeEnable : std_logic;
  88     signal dram_mem_readEnable  : std_logic;
  89     signal dram_mem_writeMask   : std_logic_vector(wordBytes-1 downto 0);
  90
  91     signal io_busy              : std_logic;
  92
  93     signal io_mem_read          : std_logic_vector(wordSize-1 downto 0);
  94     signal io_mem_writeEnable   : std_logic;
  95     signal io_mem_readEnable    : std_logic;
  96
  97     signal dram_ready           : std_logic;
  98     signal io_ready             : std_logic;
  99     signal io_reading           : std_logic;
 100
 101     signal break                : std_logic;
 102
 103 begin
 104
 105     zpu: zpu_core
 106     port map (
 107         clk                 => clk,
 108         reset               => areset,
 109         enable              => enable,
 110         in_mem_busy         => mem_busy,
 111         mem_read            => mem_read,
 112         mem_write           => mem_write,
 113         out_mem_addr        => mem_addr,
 114         out_mem_writeEnable => mem_writeEnable,
 115         out_mem_readEnable  => mem_readEnable,
 116         mem_writeMask       => mem_writeMask,
 117         interrupt           => '0',
 118         break               => break
 119     );
 120
 121     dram_imp: dram
 122     port map (
 123         clk             => clk ,
 124         areset          => areset,
 125         mem_busy        => dram_mem_busy,
 126         mem_read        => dram_mem_read,
 127         mem_write       => mem_write,
 128         mem_addr        => mem_addr(maxAddrBit downto 0),
 129         mem_writeEnable => dram_mem_writeEnable,
 130         mem_readEnable  => dram_mem_readEnable,
 131         mem_writeMask   => mem_writeMask
 132     );
 133
 134
 135     ioMap: zpu_io
 136     port map (
 137         clk         => clk,
 138         areset      => areset,
 139         busy        => io_busy,
 140         writeEnable => io_mem_writeEnable,
 141         readEnable  => io_mem_readEnable,
 142         write       => mem_write(wordSize-1 downto 0),
 143         read        => io_mem_read,
 144         addr        => mem_addr(maxAddrBit downto minAddrBit)
 145     );
 146
 147     dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
 148     dram_mem_readEnable  <= mem_readEnable  and not mem_addr(ioBit);
 149     io_mem_writeEnable   <= mem_writeEnable and mem_addr(ioBit);
 150     io_mem_readEnable    <= mem_readEnable  and mem_addr(ioBit);
 151     mem_busy             <= io_busy or dram_mem_busy or io_busy;
 152
 153
 154     -- Memory reads either come from IO or DRAM. We need to pick the right one.
 155     memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
 156     begin
 157         mem_read <= (others => 'U');
 158         if dram_ready='1' then
 159             mem_read <= dram_mem_read;
 160         end if;
 161
 162         if io_ready='1' then
 163             mem_read <= io_mem_read;
 164         end if;
 165     end process;
 166
 167
 168     io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
 169
 170     memoryControlSync: process(clk, areset)
 171     begin
 172         if areset = '1' then
 173             enable     <= '0';
 174             io_reading <= '0';
 175             dram_ready <= '0';
 176         elsif rising_edge(clk) then
 177             enable     <= '1';
 178             io_reading <= io_busy or io_mem_readEnable;
 179             dram_ready <= dram_mem_readEnable;
 180         end if;
 181     end process;
 182
 183     -- wiggle the clock @ 100MHz
 184     clock : process
 185        begin
 186             clk <= '0';
 187            wait for 5 ns;
 188             clk <= '1';
 189            wait for 5 ns;
 190            areset <= '0';
 191     end process clock;
 192
 193
 194 end architecture behave;