zpu/hdl/zealot/devices/rx_unit.vhdl

   1 ------------------------------------------------------------------------------
   2 ----                                                                      ----
   3 ----  RS-232 simple Rx module                                             ----
   4 ----                                                                      ----
   5 ----  http://www.opencores.org/                                           ----
   6 ----                                                                      ----
   7 ----  Description:                                                        ----
   8 ----  Implements a simple 8N1 rx module for RS-232.                       ----
   9 ----                                                                      ----
  10 ----  To Do:                                                              ----
  11 ----  -                                                                   ----
  12 ----                                                                      ----
  13 ----  Author:                                                             ----
  14 ----    - Philippe Carton, philippe.carton2 libertysurf.fr                ----
  15 ----    - Juan Pablo Daniel Borgna, jpdborgna gmail.com                   ----
  16 ----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
  17 ----                                                                      ----
  18 ------------------------------------------------------------------------------
  19 ----                                                                      ----
  20 ---- Copyright (c) 2001-2003 Philippe Carton                              ----
  21 ---- Copyright (c) 2005 Juan Pablo Daniel Borgna                          ----
  22 ---- Copyright (c) 2005-2008 Salvador E. Tropea                           ----
  23 ---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial  ----
  24 ----                                                                      ----
  25 ---- Distributed under the GPL license                                    ----
  26 ----                                                                      ----
  27 ------------------------------------------------------------------------------
  28 ----                                                                      ----
  29 ---- Design unit:      RxUnit(Behaviour) (Entity and architecture)        ----
  30 ---- File name:        rx_unit.vhdl                                       ----
  31 ---- Note:             None                                               ----
  32 ---- Limitations:      None known                                         ----
  33 ---- Errors:           None known                                         ----
  34 ---- Library:          zpu                                                ----
  35 ---- Dependencies:     IEEE.std_logic_1164                                ----
  36 ---- Target FPGA:      Spartan                                            ----
  37 ---- Language:         VHDL                                               ----
  38 ---- Wishbone:         No                                                 ----
  39 ---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
  40 ---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
  41 ---- Text editor:      SETEdit 0.5.x                                      ----
  42 ----                                                                      ----
  43 ------------------------------------------------------------------------------
  44
  45 library IEEE;
  46 use IEEE.std_logic_1164.all;
  47
  48 entity RxUnit is
  49    port(
  50       clk_i    : in  std_logic;  -- System clock signal
  51       reset_i  : in  std_logic;  -- Reset input (sync)
  52       enable_i : in  std_logic;  -- Enable input (rate*4)
  53       read_i   : in  std_logic;  -- Received Byte Read
  54       rxd_i    : in  std_logic;  -- RS-232 data input
  55       rxav_o   : out std_logic;  -- Byte available
  56       datao_o  : out std_logic_vector(7 downto 0)); -- Byte received
  57 end entity RxUnit;
  58
  59 architecture Behaviour of RxUnit is
  60    signal r_r      : std_logic_vector(7 downto 0); -- Receive register
  61    signal bavail_r : std_logic:='0';               -- Byte received
  62 begin
  63    rxav_o <= bavail_r;
  64    -- Rx Process
  65    RxProc:
  66    process (clk_i)
  67       variable bitpos    : integer range 0 to 10; -- Position of the bit in the frame
  68       variable samplecnt : integer range 0 to 3;  -- Count from 0 to 3 in each bit
  69    begin
  70       if rising_edge(clk_i) then
  71          if reset_i='1' then
  72             bavail_r <= '0';
  73             bitpos:=0;
  74          else -- reset_i='0'
  75             if read_i='1' then
  76                bavail_r <= '0';
  77             end if;
  78             if enable_i='1' then
  79                case bitpos is
  80                     when 0 => -- idle
  81                          bavail_r <= '0';
  82                          if rxd_i='0' then -- Start Bit
  83                             samplecnt:=0;
  84                             bitpos:=1;
  85                          end if;
  86                     when 10 => -- Stop Bit
  87                          bitpos:=0;    -- next is idle
  88                          bavail_r <= '1';    -- Indicate byte received
  89                          datao_o  <= r_r; -- Store received byte
  90                     when others =>
  91                          if samplecnt=1 and bitpos>=2 then -- Sample RxD on 1
  92                             r_r(bitpos-2) <= rxd_i; -- Deserialisation
  93                          end if;
  94                          if samplecnt=3 then -- Increment BitPos on 3
  95                             bitpos:=bitpos+1;
  96                          end if;
  97                end case;
  98                if samplecnt=3 then
  99                   samplecnt:=0;
 100                else
 101                   samplecnt:=samplecnt+1;
 102                end if;
 103             end if; -- enable_i='1'
 104          end if; -- reset_i='0'
 105       end if; -- rising_edge(clk_i)
 106    end process RxProc;
 107 end architecture Behaviour;
 108