zpu/hdl/zealot/devices/tx_unit.vhdl

   1 ------------------------------------------------------------------------------
   2 ----                                                                      ----
   3 ----  RS-232 simple Tx module                                             ----
   4 ----                                                                      ----
   5 ----  http://www.opencores.org/                                           ----
   6 ----                                                                      ----
   7 ----  Description:                                                        ----
   8 ----  Implements a simple 8N1 tx module for RS-232.                       ----
   9 ----                                                                      ----
  10 ----  To Do:                                                              ----
  11 ----  -                                                                   ----
  12 ----                                                                      ----
  13 ----  Author:                                                             ----
  14 ----    - Philippe Carton, philippe.carton2 libertysurf.fr                ----
  15 ----    - Juan Pablo Daniel Borgna, jpdborgna gmail.com                   ----
  16 ----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
  17 ----                                                                      ----
  18 ------------------------------------------------------------------------------
  19 ----                                                                      ----
  20 ---- Copyright (c) 2001-2003 Philippe Carton                              ----
  21 ---- Copyright (c) 2005 Juan Pablo Daniel Borgna                          ----
  22 ---- Copyright (c) 2005-2008 Salvador E. Tropea                           ----
  23 ---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial  ----
  24 ----                                                                      ----
  25 ---- Distributed under the GPL license                                    ----
  26 ----                                                                      ----
  27 ------------------------------------------------------------------------------
  28 ----                                                                      ----
  29 ---- Design unit:      TxUnit(Behaviour) (Entity and architecture)        ----
  30 ---- File name:        Txunit.vhdl                                        ----
  31 ---- Note:             None                                               ----
  32 ---- Limitations:      None known                                         ----
  33 ---- Errors:           None known                                         ----
  34 ---- Library:          zpu                                                ----
  35 ---- Dependencies:     IEEE.std_logic_1164                                ----
  36 ----                   zpu.UART                                           ----
  37 ---- Target FPGA:      Spartan                                            ----
  38 ---- Language:         VHDL                                               ----
  39 ---- Wishbone:         No                                                 ----
  40 ---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
  41 ---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
  42 ---- Text editor:      SETEdit 0.5.x                                      ----
  43 ----                                                                      ----
  44 ------------------------------------------------------------------------------
  45
  46 library IEEE;
  47 use IEEE.std_logic_1164.all;
  48 library zpu;
  49 use zpu.UART.all;
  50
  51 entity TxUnit is
  52   port (
  53      clk_i    : in  std_logic;  -- Clock signal
  54      reset_i  : in  std_logic;  -- Reset input
  55      enable_i : in  std_logic;  -- Enable input
  56      load_i   : in  std_logic;  -- Load input
  57      txd_o    : out std_logic;  -- RS-232 data output
  58      busy_o   : out std_logic;  -- Tx Busy
  59      datai_i  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
  60 end entity TxUnit;
  61
  62 architecture Behaviour of TxUnit is
  63    signal tbuff_r  : std_logic_vector(7 downto 0); -- transmit buffer
  64    signal t_r      : std_logic_vector(7 downto 0); -- transmit register
  65    signal loaded_r : std_logic:='0';  -- Buffer loaded
  66    signal txd_r    : std_logic:='1';  -- Tx buffer ready
  67 begin
  68   busy_o <= load_i or loaded_r;
  69   txd_o  <= txd_r;
  70
  71   -- Tx process
  72   TxProc:
  73   process (clk_i)
  74      variable bitpos : integer range 0 to 10; -- Bit position in the frame
  75   begin
  76      if rising_edge(clk_i) then
  77         if reset_i='1' then
  78            loaded_r <= '0';
  79            bitpos:=0;
  80            txd_r <= '1';
  81         else -- reset_i='0'
  82            if load_i='1' then
  83               tbuff_r  <= datai_i;
  84               loaded_r <= '1';
  85            end if;
  86            if enable_i='1' then
  87               case bitpos is
  88                    when 0 => -- idle or stop bit
  89                         txd_r <= '1';
  90                         if loaded_r='1' then -- start transmit. next is start bit
  91                            t_r <= tbuff_r;
  92                            loaded_r <= '0';
  93                            bitpos:=1;
  94                         end if;
  95                    when 1 => -- Start bit
  96                         txd_r <= '0';
  97                         bitpos:=2;
  98                    when others =>
  99                         txd_r <= t_r(bitpos-2); -- Serialisation of t_r
 100                         bitpos:=bitpos+1;
 101               end case;
 102               if bitpos=10 then -- bit8. next is stop bit
 103                  bitpos:=0;
 104               end if;
 105            end if; -- enable_i='1'
 106         end if; -- reset_i='0'
 107      end if; -- rising_edge(clk_i)
 108   end process TxProc;
 109 end architecture Behaviour;