zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut

   1 -w
   2 -g DebugBitstream:No
   3 -g Binary:no
   4 -g CRC:Enable
   5 -g ConfigRate:6
   6 -g CclkPin:PullUp
   7 -g M0Pin:PullUp
   8 -g M1Pin:PullUp
   9 -g M2Pin:PullUp
  10 -g ProgPin:PullUp
  11 -g DonePin:PullUp
  12 -g HswapenPin:PullUp
  13 -g TckPin:PullUp
  14 -g TdiPin:PullUp
  15 -g TdoPin:PullUp
  16 -g TmsPin:PullUp
  17 -g UnusedPin:PullDown
  18 -g UserID:0xFFFFFFFF
  19 -g DCMShutdown:Disable
  20 -g DCIUpdateMode:AsRequired
  21 -g StartUpClk:CClk
  22 -g DONE_cycle:4
  23 -g GTS_cycle:5
  24 -g GWE_cycle:6
  25 -g LCK_cycle:NoWait
  26 -g Match_cycle:Auto
  27 -g Security:None
  28 -g DonePipe:No
  29 -g DriveDone:No