zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd

   1 -- testbench for
   2 -- Altium LiveDesign Board
   3 --
   4 -- includes "model" for clock generation
   5 -- simulate press on test/reset as reset
   6 --
   7 -- place models for external components (SRAM, PS2) in this file
   8 --
   9
  10
  11 library ieee;
  12 use ieee.std_logic_1164.all;
  13
  14
  15 entity top_tb is
  16 end entity top_tb;
  17
  18 architecture testbench of top_tb is
  19
  20     ---------------------------
  21     -- constant declarations
  22     constant clk_period : time := 1 sec / 50_000_000;  -- 50 MHz
  23
  24
  25     ---------------------------
  26     -- signal declarations
  27     signal simulation_run     : boolean := true;
  28     signal tb_stop_simulation : std_logic;
  29     --
  30     signal tb_clk             : std_logic                     := '0';
  31     signal tb_reset_n         : std_logic;
  32     --
  33     -- soft JTAG
  34     signal tb_soft_tdo        : std_logic;
  35     signal tb_soft_tms        : std_logic                     := '1';
  36     signal tb_soft_tdi        : std_logic                     := '1';
  37     signal tb_soft_tck        : std_logic                     := '1';
  38     --
  39     -- SRAM 0 (256k x 16) pin connections
  40     signal tb_sram0_a         : std_logic_vector(18 downto 0);
  41     signal tb_sram0_d         : std_logic_vector(15 downto 0) := (others => 'Z');
  42     signal tb_sram0_lb_n      : std_logic;
  43     signal tb_sram0_ub_n      : std_logic;
  44     signal tb_sram0_cs_n      : std_logic;     -- chip select
  45     signal tb_sram0_we_n      : std_logic;     -- write-enable
  46     signal tb_sram0_oe_n      : std_logic;     -- output enable
  47     --
  48     -- SRAM 1 (256k x 16) pin connections
  49     signal tb_sram1_a         : std_logic_vector(18 downto 0);
  50     signal tb_sram1_d         : std_logic_vector(15 downto 0) := (others => 'Z');
  51     signal tb_sram1_lb_n      : std_logic;
  52     signal tb_sram1_ub_n      : std_logic;
  53     signal tb_sram1_cs_n      : std_logic;     -- chip select
  54     signal tb_sram1_we_n      : std_logic;     -- write-enable
  55     signal tb_sram1_oe_n      : std_logic;     -- output enable
  56     --
  57     -- RS232
  58     signal tb_rs232_rx        : std_logic                     := '1';
  59     signal tb_rs232_tx        : std_logic;
  60     signal tb_rs232_cts       : std_logic                     := '1';
  61     signal tb_rs232_rts       : std_logic;
  62     --
  63     -- PS2 connectors
  64     signal tb_mouse_clk       : std_logic                     := 'Z';
  65     signal tb_mouse_data      : std_logic                     := 'Z';
  66     signal tb_kbd_clk         : std_logic                     := 'Z';
  67     signal tb_kbd_data        : std_logic                     := 'Z';
  68     --
  69     -- vga output
  70     signal tb_vga_red         : std_logic_vector(7 downto 5);
  71     signal tb_vga_green       : std_logic_vector(7 downto 5);
  72     signal tb_vga_blue        : std_logic_vector(7 downto 5);
  73     signal tb_vga_hsync       : std_logic;
  74     signal tb_vga_vsync       : std_logic;
  75     --
  76     -- Audio out
  77     signal tb_audio_r         : std_logic;
  78     signal tb_audio_l         : std_logic;
  79     --
  80     -- GPIOs
  81     signal tb_switch_n        : std_logic_vector(7 downto 0)  := (others => '1');
  82     signal tb_button_n        : std_logic_vector(5 downto 0)  := (others => '1');
  83     signal tb_led             : std_logic_vector(7 downto 0);
  84     --
  85     -- seven segment display
  86     signal tb_dig0_seg        : std_logic_vector(7 downto 0);
  87     signal tb_dig1_seg        : std_logic_vector(7 downto 0);
  88     signal tb_dig2_seg        : std_logic_vector(7 downto 0);
  89     signal tb_dig3_seg        : std_logic_vector(7 downto 0);
  90     signal tb_dig4_seg        : std_logic_vector(7 downto 0);
  91     signal tb_dig5_seg        : std_logic_vector(7 downto 0);
  92     --
  93     -- User Header A
  94     signal tb_header_a        : std_logic_vector(19 downto 2) := (others => 'Z');
  95     signal tb_header_b        : std_logic_vector(19 downto 2) := (others => 'Z');
  96
  97 begin
  98
  99     -- generate clock
 100     tb_clk <= not tb_clk after clk_period / 2 when simulation_run;
 101
 102     -- generate reset
 103     tb_reset_n <= '0', '1' after 6.66 * clk_period;
 104
 105
 106     -- simulate keypress
 107     tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us;
 108
 109     -- dut
 110     top_i0 : entity work.top
 111         port map (
 112             stop_simulation => tb_stop_simulation, -- : out   std_logic;
 113             --
 114             clk_50     => tb_clk,        -- : in    std_logic;
 115             reset_n    => tb_reset_n,    -- : in    std_logic;
 116             --
 117             -- soft JTAG
 118             soft_tdo   => tb_soft_tdo,   -- : out   std_logic;
 119             soft_tms   => tb_soft_tms,   -- : in    std_logic;
 120             soft_tdi   => tb_soft_tdi,   -- : in    std_logic;
 121             soft_tck   => tb_soft_tck,   -- : in    std_logic;
 122             --
 123             -- SRAM 0 (256k x 16) pin connections
 124             sram0_a    => tb_sram0_a,    -- : out   std_logic_vector(18 downto 0);
 125             sram0_d    => tb_sram0_d,    -- : inout std_logic_vector(15 downto 0);
 126             sram0_lb_n => tb_sram0_lb_n, -- : out   std_logic;
 127             sram0_ub_n => tb_sram0_ub_n, -- : out   std_logic;
 128             sram0_cs_n => tb_sram0_cs_n, -- : out   std_logic;       -- chip select
 129             sram0_we_n => tb_sram0_we_n, -- : out   std_logic;       -- write-enable
 130             sram0_oe_n => tb_sram0_oe_n, -- : out   std_logic;       -- output enable
 131             --
 132             -- SRAM 1 (256k x 16) pin connections
 133             sram1_a    => tb_sram1_a,    -- : out   std_logic_vector(18 downto 0);
 134             sram1_d    => tb_sram1_d,    -- : inout std_logic_vector(15 downto 0);
 135             sram1_lb_n => tb_sram1_lb_n, -- : out   std_logic;
 136             sram1_ub_n => tb_sram1_ub_n, -- : out   std_logic;
 137             sram1_cs_n => tb_sram1_cs_n, -- : out   std_logic;       -- chip select
 138             sram1_we_n => tb_sram1_we_n, -- : out   std_logic;       -- write-enable
 139             sram1_oe_n => tb_sram1_oe_n, -- : out   std_logic;       -- output enable
 140             --
 141             -- RS232
 142             rs232_rx   => tb_rs232_rx,   -- : in    std_logic;
 143             rs232_tx   => tb_rs232_tx,   -- : out   std_logic;
 144             rs232_cts  => tb_rs232_cts,  -- : in    std_logic;
 145             rs232_rts  => tb_rs232_rts,  -- : out   std_logic;
 146             --
 147             -- PS2 connectors
 148             mouse_clk  => tb_mouse_clk,  -- : inout std_logic;
 149             mouse_data => tb_mouse_data, -- : inout std_logic;
 150             kbd_clk    => tb_kbd_clk,    -- : inout std_logic;
 151             kbd_data   => tb_kbd_data,   -- : inout std_logic;
 152             --
 153             -- vga output
 154             vga_red    => tb_vga_red,    -- : out   std_logic_vector(7 downto 5);
 155             vga_green  => tb_vga_green,  -- : out   std_logic_vector(7 downto 5);
 156             vga_blue   => tb_vga_blue,   -- : out   std_logic_vector(7 downto 5);
 157             vga_hsync  => tb_vga_hsync,  -- : out   std_logic;
 158             vga_vsync  => tb_vga_vsync,  -- : out   std_logic;
 159             --
 160             -- Audio out
 161             audio_r    => tb_audio_r,    -- : out   std_logic;
 162             audio_l    => tb_audio_l,    -- : out   std_logic;
 163             --
 164             -- GPIOs
 165             switch_n   => tb_switch_n,   -- : in    std_logic_vector(7 downto 0);
 166             button_n   => tb_button_n,   -- : in    std_logic_vector(5 downto 0);
 167             led        => tb_led,        -- : out   std_logic_vector(7 downto 0);
 168             --
 169             -- seven segment display
 170             dig0_seg   => tb_dig0_seg,   -- : out   std_logic_vector(7 downto 0);
 171             dig1_seg   => tb_dig1_seg,   -- : out   std_logic_vector(7 downto 0);
 172             dig2_seg   => tb_dig2_seg,   -- : out   std_logic_vector(7 downto 0);
 173             dig3_seg   => tb_dig3_seg,   -- : out   std_logic_vector(7 downto 0);
 174             dig4_seg   => tb_dig4_seg,   -- : out   std_logic_vector(7 downto 0);
 175             dig5_seg   => tb_dig5_seg,   -- : out   std_logic_vector(7 downto 0);
 176             --
 177             -- User Header
 178             header_a   => tb_header_a,   -- : inout std_logic_vector(19 downto 2);
 179             header_b   => tb_header_b    -- : inout std_logic_vector(19 downto 2)
 180         );
 181
 182
 183     -- check for simulation stopping
 184     process (tb_stop_simulation)
 185     begin
 186         if tb_stop_simulation = '1' then
 187             report "Simulation end." severity note;
 188             simulation_run <= false;
 189         end if;
 190     end process;
 191
 192
 193 end architecture testbench;
 194