zpu/hdl/zealot/fpga/hello_small1.vhdl

   1 ------------------------------------------------------------------------------
   2 ----                                                                      ----
   3 ----  ZPU Small connection to the FPGA pins                               ----
   4 ----                                                                      ----
   5 ----  http://www.opencores.org/                                           ----
   6 ----                                                                      ----
   7 ----  Description:                                                        ----
   8 ----  This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a     ----
   9 ----  Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from      ----
  10 ----  Pender.                                                             ----
  11 ----                                                                      ----
  12 ----  To Do:                                                              ----
  13 ----  -                                                                   ----
  14 ----                                                                      ----
  15 ----  Author:                                                             ----
  16 ----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
  17 ----                                                                      ----
  18 ------------------------------------------------------------------------------
  19 ----                                                                      ----
  20 ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
  21 ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
  22 ----                                                                      ----
  23 ---- Distributed under the GPL license                                    ----
  24 ----                                                                      ----
  25 ------------------------------------------------------------------------------
  26 ----                                                                      ----
  27 ---- Design unit:      Hello_Small1(FPGA) (Entity and architecture)       ----
  28 ---- File name:        hello_small1.vhdl                                  ----
  29 ---- Note:             None                                               ----
  30 ---- Limitations:      None known                                         ----
  31 ---- Errors:           None known                                         ----
  32 ---- Library:          work                                               ----
  33 ---- Dependencies:     IEEE.std_logic_1164                                ----
  34 ----                   IEEE.numeric_std                                   ----
  35 ----                   zpu.zpu_pkg                                        ----
  36 ---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
  37 ---- Language:         VHDL                                               ----
  38 ---- Wishbone:         No                                                 ----
  39 ---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
  40 ---- Simulation tools: N/A                                                ----
  41 ---- Text editor:      SETEdit 0.5.x                                      ----
  42 ----                                                                      ----
  43 ------------------------------------------------------------------------------
  44
  45 library IEEE;
  46 use IEEE.std_logic_1164.all;
  47 use IEEE.numeric_std.all;
  48
  49 library zpu;
  50 use zpu.zpupkg.all;
  51
  52 entity Hello_Small1 is
  53    generic(
  54       WORD_SIZE  : natural:=32;  -- 32 bits data path
  55       D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
  56       CLK_FREQ   : positive:=50; -- 50 MHz clock
  57       BRATE      : positive:=115200; -- RS-232 baudrate
  58       ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
  59       BRAM_W     : natural:=14); -- 14 bits RAM space=16 kB
  60    port(
  61       clk_i      : in  std_logic;  -- CPU clock
  62       rst_i      : in  std_logic;  -- Reset
  63       rs232_tx_o : out std_logic;  -- UART Tx
  64       rs232_rx_i : in  std_logic); -- UART Rx
  65
  66    constant BRD_PB1_I      : string:="D19";  -- SWITCH8==S2
  67    constant BRD_CLK1_I     : string:="AA12"; -- 50 MHz clock
  68    --constant BRD_CLK1_I     : string:="AB12"; -- 40 MHz clock
  69    -- UART: direct 1:1 cable
  70    constant BRD_TX_O       : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
  71    constant BRD_RX_I       : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
  72
  73    ------------
  74    -- Pinout --
  75    ------------
  76    attribute LOC        : string;
  77    attribute IOSTANDARD : string;
  78    constant  IOSTD      : string:="LVTTL";
  79
  80    attribute LOC        of rst_i       : signal is BRD_PB1_I;
  81    attribute IOSTANDARD of rst_i       : signal is IOSTD;
  82    attribute LOC        of clk_i       : signal is BRD_CLK1_I;
  83    attribute LOC        of rs232_tx_o  : signal is BRD_TX_O;
  84    attribute IOSTANDARD of rs232_tx_o  : signal is IOSTD;
  85    attribute LOC        of rs232_rx_i  : signal is BRD_RX_I;
  86    attribute IOSTANDARD of rs232_rx_i  : signal is IOSTD;
  87 end entity Hello_Small1;
  88
  89 architecture FPGA of Hello_Small1 is
  90    component ZPU_Small1 is
  91       generic(
  92          WORD_SIZE  : natural:=32;  -- 32 bits data path
  93          D_CARE_VAL : std_logic:='0'; -- Fill value
  94          CLK_FREQ   : positive:=50; -- 50 MHz clock
  95          BRATE      : positive:=115200; -- RS232 baudrate
  96          ADDR_W     : natural:=16;  -- 16 bits address space=64 kB, 32 kB I/O
  97          BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
  98       port(
  99          clk_i      : in  std_logic;  -- CPU clock
 100          rst_i      : in  std_logic;  -- Reset
 101          break_o    : out std_logic;  -- Break executed
 102          dbg_o      : out zpu_dbgo_t; -- Debug info
 103          rs232_tx_o : out std_logic;  -- UART Tx
 104          rs232_rx_i : in  std_logic;  -- UART Rx
 105          gpio_in    : in  std_logic_vector(31 downto 0);
 106          gpio_out   : out std_logic_vector(31 downto 0);
 107          gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
 108          );
 109    end component ZPU_Small1;
 110 begin
 111    zpu : ZPU_Small1
 112       generic map(
 113          WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
 114          CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
 115          BRAM_W => BRAM_W)
 116       port map(
 117          clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
 118          rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
 119 end architecture FPGA; -- Entity: Hello_Small1
 120