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(parent: bf4405c) | patch
add: ZPU reference designs for zealot
commit0bf783475d6610a14f71884737aeae33246bb9be
authorBert Lange <b.lange@hzdr.de>
Thu, 13 Oct 2011 10:37:49 +0000 (13 12:37 +0200)
committerBert Lange <b.lange@hzdr.de>
Thu, 13 Oct 2011 10:37:49 +0000 (13 12:37 +0200)
tree8545a4d2e76761131f4945db6eeca7b563f7161etree | snapshot (tar.gz zip)
parentbf4405c61a9c010a8e888da678436a282b9551a3commit | diff
add: ZPU reference designs for zealot
21 files changed:
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh [new file with mode: 0755] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh [new file with mode: 0755] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh [new file with mode: 0755] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh [new file with mode: 0755] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh [new file with mode: 0755] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh [new file with mode: 0755] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd [new file with mode: 0644] blob
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd [new file with mode: 0644] blob
Zylin ZPU - the worlds smallest 32 bit CPU with GCC support