zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh

   1 #!/bin/sh
   2
   3 # need project files:
   4 #    top.xst
   5 #    top.prj
   6 #    top.ut
   7
   8 # need Xilinx tools:
   9 #    xst
  10 #    ngdbuild
  11 #    map
  12 #    par
  13 #    trce
  14 #    bitgen
  15
  16 echo "########################"
  17 echo "generate build directory"
  18 echo "########################"
  19 mkdir build
  20 cd build
  21 mkdir tmp
  22
  23 echo "###############"
  24 echo "start processes"
  25 echo "###############"
  26 xst      -ifn "../synthesis_config/top.xst" -ofn "top.syr"
  27 ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd
  28 map      -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf
  29 par      -w -ol high -t 1 top_map.ncd top.ncd top.pcf
  30 trce     -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
  31 bitgen   -f ../synthesis_config/top.ut top.ncd
  32
  33 echo "###########"
  34 echo "get bitfile"
  35 echo "###########"
  36 cp top.bit ..