toolchain/binutils/gas/config/tc-zpu.c

   1 /* tc-zpu.c -- Assembler code for the Zylin ZPU
   2    Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
   3    Written by Oyvind Harboe <oyvind.harboe@zylin.com>
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #include "as.h"
  23 #include "safe-ctype.h"
  24 #include "subsegs.h"
  25 #include "dwarf2dbg.h"
  26 #include "elf/zpu.h"
  27 #include "opcode/zpu.h"
  28 #include <ctype.h>
  29
  30 const char comment_chars[] = ";!";
  31 const char line_comment_chars[] = "#*";
  32 const char line_separator_chars[] = "";
  33
  34 const char EXP_CHARS[] = "eE";
  35 const char FLT_CHARS[] = "dD";
  36
  37
  38
  39 struct zpu_opcode_def {
  40   int used;
  41   struct zpu_opcode *opcode;
  42 };
  43
  44 static struct zpu_opcode_def *zpu_opcode_defs = 0;
  45 static int zpu_nb_opcode_defs = 0;
  46
  47 /* Local functions.  */
  48 static int cmp_opcode (struct zpu_opcode *, struct zpu_opcode *);
  49 static char *print_opcode_format (struct zpu_opcode *, int);
  50 static char *skip_whites (char *);
  51 static void print_opcode_list (void);
  52 static void get_default_target (void);
  53
  54 static struct zpu_opcode *find_opcode (struct zpu_opcode_def *);
  55
  56
  57
  58
  59 /* Dumps the list of instructions with syntax and then exit:
  60    1 -> Only dumps the list (sorted by name)
  61    2 -> Generate an example (or test) that can be compiled.  */
  62 static short flag_print_opcodes = 0;
  63
  64 /* Opcode hash table.  */
  65 static struct hash_control *zpu_hash;
  66
  67 /* Default cpu determined by 'get_default_target'.  */
  68 static const char *default_cpu;
  69
  70 /* Number of opcodes in the sorted table (filtered by current cpu).  */
  71 static int num_opcodes;
  72
  73 /* The opcodes sorted by name and filtered by current cpu.  */
  74 static struct zpu_opcode *zpu_sorted_opcodes;
  75
  76
  77 static void s_bss PARAMS ((int));
  78
  79 /* This table describes all the machine specific pseudo-ops the assembler
  80    has to support.  The fields are:
  81    pseudo-op name without dot
  82    function to call to execute this pseudo-op
  83    Integer arg to pass to the function.  */
  84 const pseudo_typeS md_pseudo_table[] = {
  85
  86   {"bss", s_bss, 0},
  87   {0, 0, 0}
  88 };
  89 \f
  90 /* Options and initialization.  */
  91
  92 const char *md_shortopts = "Sm:";
  93
  94 struct option md_longopts[] = {
  95
  96   {NULL, no_argument, NULL, 0}
  97 };
  98 size_t md_longopts_size = sizeof (md_longopts);
  99
 100 /* Get the target cpu for the assembler.  This is based on the configure
 101    options and on the   If no option is specified,
 102    we must get the default.  */
 103 const char *
 104 zpu_arch_format (void)
 105 {
 106   get_default_target ();
 107   return "elf32-zpu";
 108 }
 109
 110 enum bfd_architecture
 111 zpu_arch (void)
 112 {
 113   get_default_target ();
 114   return bfd_arch_zpu;
 115 }
 116
 117 int
 118 zpu_mach (void)
 119 {
 120   return 0;
 121 }
 122
 123 /* Listing header selected according to cpu.  */
 124 const char *
 125 zpu_listing_header (void)
 126 {
 127    return "zpu GAS ";
 128 }
 129
 130 void
 131 md_show_usage (FILE *stream)
 132 {
 133   get_default_target ();
 134   fprintf (stream, _("\
 135 Zylin ZPU options:\n\
 136   --print-insn-syntax     print the syntax of instruction in case of error\n\
 137   --print-opcodes         print the list of instructions with syntax\n\
 138   --generate-example      generate an example of each instruction\n\
 139                           (used for testing)\n"));
 140
 141 }
 142 /* Try to identify the default target based on the BFD library.  */
 143 static void
 144 get_default_target (void)
 145 {
 146   const bfd_target *target;
 147   bfd abfd;
 148
 149
 150   default_cpu = "unknown";
 151   target = bfd_find_target (0, &abfd);
 152           default_cpu = "zpu";
 153 }
 154 int
 155 md_parse_option (int c,  char *arg)
 156 {
 157         (void)c;
 158         (void)arg;
 159         return 0;
 160 }
 161 \f
 162 symbolS *
 163 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 164 {
 165   return 0;
 166 }
 167
 168 /* Equal to MAX_PRECISION in atof-ieee.c.  */
 169 #define MAX_LITTLENUMS 6
 170
 171 /* Turn a string in input_line_pointer into a floating point constant
 172    of type TYPE, and store the appropriate bytes in *LITP.  The number
 173    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
 174    returned, or NULL on OK.  */
 175 char *
 176 md_atof (int type, char *litP, int *sizeP)
 177 {
 178   int prec;
 179   LITTLENUM_TYPE words[MAX_LITTLENUMS];
 180   LITTLENUM_TYPE *wordP;
 181   char *t;
 182
 183   switch (type)
 184     {
 185     case 'f':
 186     case 'F':
 187     case 's':
 188     case 'S':
 189       prec = 2;
 190       break;
 191
 192     case 'd':
 193     case 'D':
 194     case 'r':
 195     case 'R':
 196       prec = 4;
 197       break;
 198
 199     case 'x':
 200     case 'X':
 201       prec = 6;
 202       break;
 203
 204     case 'p':
 205     case 'P':
 206       prec = 6;
 207       break;
 208
 209     default:
 210       *sizeP = 0;
 211       return _("Bad call to MD_ATOF()");
 212     }
 213   t = atof_ieee (input_line_pointer, type, words);
 214   if (t)
 215     input_line_pointer = t;
 216
 217   *sizeP = prec * sizeof (LITTLENUM_TYPE);
 218   for (wordP = words; prec--;)
 219     {
 220       md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
 221       litP += sizeof (LITTLENUM_TYPE);
 222     }
 223   return 0;
 224 }
 225
 226 valueT
 227 md_section_align (asection *seg, valueT addr)
 228 {
 229   int align = bfd_get_section_alignment (stdoutput, seg);
 230   return ((addr + (1 << align) - 1) & (-1 << align));
 231 }
 232
 233 static int
 234 cmp_opcode (struct zpu_opcode *op1, struct zpu_opcode *op2)
 235 {
 236   return strcmp (op1->name, op2->name);
 237 }
 238
 239
 240 /* Initialize the assembler.  Create the opcode hash table
 241    (sorted on the names) with the M6811 opcode table
 242    (from opcode library).  */
 243 void
 244 md_begin (void)
 245 {
 246   char *prev_name = "";
 247   struct zpu_opcode *opcodes;
 248   struct zpu_opcode_def *opc = 0;
 249   int i;
 250
 251   get_default_target ();
 252
 253   zpu_hash = hash_new ();
 254
 255   /* Get a writable copy of the opcode table and sort it on the names.  */
 256   opcodes = (struct zpu_opcode *) xmalloc (zpu_num_opcodes *
 257                                                sizeof (struct
 258                                                        zpu_opcode));
 259   zpu_sorted_opcodes = opcodes;
 260   num_opcodes = 0;
 261   for (i = 0; i < zpu_num_opcodes; i++)
 262     {
 263           opcodes[num_opcodes] = zpu_opcodes[i];
 264           num_opcodes++;
 265     }
 266   qsort (opcodes, num_opcodes, sizeof (struct zpu_opcode),
 267          (int (*) (const void*, const void*)) cmp_opcode);
 268
 269   opc = (struct zpu_opcode_def *)
 270     xmalloc (num_opcodes * sizeof (struct zpu_opcode_def));
 271   zpu_opcode_defs = opc--;
 272
 273   /* Insert unique names into hash table.  The M6811 instruction set
 274      has several identical opcode names that have different opcodes based
 275      on the operands.  This hash table then provides a quick index to
 276      the first opcode with a particular name in the opcode table.  */
 277   for (i = 0; i < num_opcodes; i++, opcodes++)
 278     {
 279
 280       if (strcmp (prev_name, opcodes->name))
 281         {
 282           prev_name = (char *) opcodes->name;
 283
 284           opc++;
 285           opc->opcode = opcodes;
 286           opc->used = 0;
 287           hash_insert (zpu_hash, opcodes->name, opc);
 288         }
 289
 290     }
 291   opc++;
 292   zpu_nb_opcode_defs = opc - zpu_opcode_defs;
 293
 294   if (flag_print_opcodes)
 295     {
 296       print_opcode_list ();
 297       exit (EXIT_SUCCESS);
 298     }
 299   linkrelax = 0;
 300 }
 301
 302 void
 303 zpu_init_after_args (void)
 304 {
 305 }
 306 \f
 307 /* Builtin help.  */
 308
 309 /* Return a string that represents the operand format for the instruction.
 310    When example is true, this generates an example of operand.  This is used
 311    to give an example and also to generate a test.  */
 312 static char *
 313 print_opcode_format (struct zpu_opcode *opcode, int example)
 314 {
 315         (void)opcode;
 316         (void)example;
 317   static char buf[128];
 318   char *p;
 319
 320   p = buf;
 321   buf[0] = 0;
 322
 323   return buf;
 324 }
 325
 326 /* Prints the list of instructions with the possible operands.  */
 327 static void
 328 print_opcode_list (void)
 329 {
 330   int i;
 331   char *prev_name = "";
 332   struct zpu_opcode *opcodes;
 333   int example = flag_print_opcodes == 2;
 334
 335
 336   opcodes = zpu_sorted_opcodes;
 337
 338   /* Walk the list sorted on names (by md_begin).  We only report
 339      one instruction per line, and we collect the different operand
 340      formats.  */
 341   for (i = 0; i < num_opcodes; i++, opcodes++)
 342     {
 343       char *fmt = print_opcode_format (opcodes, example);
 344
 345       if (example)
 346         {
 347           printf ("L%d:\t", i);
 348           printf ("%s %s\n", opcodes->name, fmt);
 349         }
 350       else
 351         {
 352           if (strcmp (prev_name, opcodes->name))
 353             {
 354               if (i > 0)
 355                 printf ("\n");
 356
 357               printf ("%-5.5s ", opcodes->name);
 358               prev_name = (char *) opcodes->name;
 359             }
 360           if (fmt[0])
 361             printf ("  [%s]", fmt);
 362         }
 363     }
 364   printf ("\n");
 365 }
 366
 367
 368 static char *
 369 skip_whites (char *p)
 370 {
 371         while (isspace(*p))
 372         {
 373             p++;
 374         }
 375   return p;
 376 }
 377
 378 static int checkRange(int val, int bits)
 379 {
 380         int prevSign;
 381         prevSign=(val>>(bits-1))&1;
 382         if (prevSign)
 383         {
 384                 return ((val>>bits)&0x7f)!=0x7f;
 385         } else
 386         {
 387                 return ((val>>bits)&0x7f)!=0x00;
 388         }
 389 }
 390
 391 static void emit_insn_core(int insn)
 392 {
 393           char *f;
 394           f = frag_more (1);
 395           dwarf2_emit_insn (1);
 396           number_to_chars_bigendian (f, insn, 1);
 397 }
 398
 399 static int immediate=0;
 400 static int prevImmediate=0;
 401
 402 static void emit_insn(int insn)
 403 {
 404         emit_insn_core(insn);
 405 }
 406
 407
 408 static int emit7Bits(int val, int pos)
 409 {
 410         return ((val>>pos)&0x7f)|0x80;
 411 }
 412
 413 /* generate immediate sequence */
 414 static int genImmediate(char *buffer, int val)
 415 {
 416         int first=1;
 417         int i,j;
 418         j=0;
 419         for (i=4; i>=0; i--)
 420         {
 421                 if (!first||(i==0)||checkRange(val, i*7))
 422                 {
 423                         buffer[j++]=emit7Bits(val, i*7);
 424                         first=0;
 425                 }
 426         }
 427         return j;
 428 }
 429
 430 static int flip(int val)
 431 {
 432         int t=0;
 433         int i;
 434         for (i=0; i<32; i++)
 435         {
 436                 t<<=1;
 437                 t|=(val>>i)&1;
 438         }
 439         return t;
 440 }
 441
 442
 443 /* build_insn simple instruction */
 444 static void
 445 build_immediate_insn (expressionS *oper, int fixed14)
 446 {
 447         if (oper->X_op == O_constant)
 448     {
 449         int val;
 450         int length;
 451         int i;
 452         int a;
 453         int b;
 454         char buffer[10]; /* maximum length */
 455
 456         val=oper->X_add_number;
 457
 458                 a=genImmediate(buffer, val);
 459                 b=genImmediate(buffer, flip(val))+1;
 460                 if (b<a)
 461                 {
 462                         length=genImmediate(buffer, flip(val));
 463                         buffer[length++]=ZPU_flip;
 464                 } else
 465                 {
 466                         length=genImmediate(buffer, val);
 467                 }
 468
 469                 for (i=0; i<length; i++)
 470                 {
 471                         emit_insn(buffer[i]);
 472                 }
 473     } else
 474     {
 475         char *f;
 476         if (fixed14)
 477         {
 478                         fix_new_exp (frag_now, frag_now_fix (), 2, oper, 0, BFD_RELOC_ZPU_IM_14_NONRELAX);
 479                         f = frag_more (2);
 480                         dwarf2_emit_insn(2);
 481         } else
 482         {
 483                         fix_new_exp (frag_now, frag_now_fix (), 5, oper, 0, BFD_RELOC_ZPU_IM_32);
 484                         f = frag_more (5);
 485                         dwarf2_emit_insn(5);
 486         }
 487     }
 488 }
 489
 490
 491 static void build_loadstoresp(enum ZPU_OPCODE opcode, expressionS *oper)
 492 {
 493         int offset;
 494         if (oper->X_op != O_constant)
 495         {
 496           as_bad (_("illegal loadsp operand"));
 497         }
 498
 499         offset=oper->X_add_number/4;
 500
 501         if ((offset<0)||(offset>31))
 502         {
 503           as_bad (_("illegal loadsp operand"));
 504         }
 505
 506         /* we invert bit 4. This allows the same sp+offset circuitry to be used
 507          * for addsp & loadsp/storesp */
 508         offset=offset^0x10;
 509         emit_insn(opcode+offset);
 510 }
 511
 512 static void build_addsp(enum ZPU_OPCODE opcode, expressionS *oper)
 513 {
 514         int offset;
 515         if (oper->X_op != O_constant)
 516         {
 517           as_bad (_("illegal addsp operand"));
 518         }
 519
 520         offset=oper->X_add_number/4;
 521
 522         if ((offset<0)||(offset>15))
 523         {
 524           as_bad (_("illegal addsp operand"));
 525         }
 526
 527         emit_insn(opcode+offset);
 528 }
 529
 530
 531 /* Opcode identification and operand analysis.  */
 532
 533
 534 /* Find the real opcode and its associated operands.  We use a progressive
 535    approach here.  On entry, 'opc' points to the first opcode in the
 536    table that matches the opcode name in the source line.  We try to
 537    isolate an operand, find a possible match in the opcode table.
 538    We isolate another operand if no match were found.  The table 'operands'
 539    is filled while operands are recognized.
 540
 541    Returns the opcode pointer that matches the opcode name in the
 542    source line and the associated operands.  */
 543 static struct zpu_opcode *
 544 find_opcode (struct zpu_opcode_def *opc)
 545 {
 546        return opc->opcode;
 547  }
 548
 549 /* Gas line assembler entry point.  */
 550
 551 /* This is the main entry point for the machine-dependent assembler.  str
 552    points to a machine-dependent instruction.  This function is supposed to
 553    emit the frags/bytes it assembles to.  */
 554 void
 555 md_assemble (char *str)
 556 {
 557   struct zpu_opcode_def *opc;
 558   struct zpu_opcode *opcode;
 559
 560   unsigned char *op_start;
 561   unsigned char *op_end;
 562   char name[20];
 563   int nlen = 0;
 564
 565   /* Drop leading whitespace.  */
 566   str=skip_whites(str);
 567
 568   /* Find the opcode end and get the opcode in 'name'.  The opcode is forced
 569      lower case (the opcode table only has lower case op-codes).  */
 570   for (op_start = op_end = (unsigned char *) (str);
 571        *op_end && nlen < 20 && !is_end_of_line[*op_end] && !isspace(*op_end);
 572        op_end++)
 573     {
 574       name[nlen] = TOLOWER (op_start[nlen]);
 575       nlen++;
 576     }
 577   name[nlen] = 0;
 578
 579   if (nlen == 0)
 580     {
 581       as_bad (_("No instruction or missing opcode."));
 582       return;
 583     }
 584
 585   /* Find the opcode definition given its name.  */
 586   opc = (struct zpu_opcode_def *) hash_find (zpu_hash, name);
 587   if (opc==0)
 588   {
 589           as_bad (_("illegal instruction"));
 590       return;
 591   }
 592
 593   input_line_pointer = skip_whites(op_end);
 594
 595   if (opc)
 596     {
 597       opc->used++;
 598       opcode = find_opcode (opc);
 599     }
 600   else
 601     opcode = 0;
 602
 603         immediate=0;
 604
 605         if (opcode->amode==ADDR_IMMEDIATE)
 606         {
 607                 expressionS ex;
 608                 expression (&ex);
 609
 610                 switch (opcode->code)
 611                 {
 612                         case ZPU_addsp:
 613                                 build_addsp(opcode->code, &ex);
 614                         break;
 615                         case ZPU_storesp:
 616                         case ZPU_loadsp:
 617                         {
 618                                 build_loadstoresp(opcode->code, &ex);
 619                         }
 620                         break;
 621
 622                         default:
 623                         immediate=1;
 624                     build_immediate_insn (&ex, (opcode->code==ZPU_im14));
 625                     break;
 626                 }
 627
 628         } else if (opcode->amode==ADDR_PCREL)
 629         {
 630                 char *f;
 631                 expressionS ex;
 632                 expression (&ex);
 633
 634                 immediate=1;
 635                 fix_new_exp (frag_now, frag_now_fix (), 5, &ex, 1, BFD_RELOC_ZPU_IM_32_PCREL);
 636                 f = frag_more (5);
 637                 dwarf2_emit_insn(5);
 638         } else
 639         {
 640             emit_insn(opcode->code);
 641         }
 642         if (immediate&&prevImmediate)
 643         {
 644                 as_bad (_("Two consequtive IM instructions is illegal"));
 645         }
 646         prevImmediate=immediate;
 647 }
 648
 649 /* If while processing a fixup, a reloc really needs to be created
 650    then it is done here.  */
 651 arelent *
 652 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 653 {
 654   arelent *reloc;
 655
 656   reloc = (arelent *) xmalloc (sizeof (arelent));
 657   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
 658   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
 659   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 660           assert(fixp->fx_r_type != 0);
 661         reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
 662
 663   if (reloc->howto == (reloc_howto_type *) NULL)
 664     {
 665       as_bad_where (fixp->fx_file, fixp->fx_line,
 666                     _("Relocation %d is not supported by object file format."),
 667                     (int) fixp->fx_r_type);
 668       return NULL;
 669     }
 670
 671   /* Since we use Rel instead of Rela, encode the vtable entry to be
 672      used in the relocation's section offset.  */
 673   if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
 674     reloc->address = fixp->fx_offset;
 675
 676   reloc->addend = fixp->fx_offset;
 677   return reloc;
 678 }
 679
 680
 681
 682 void
 683 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec ATTRIBUTE_UNUSED,
 684                  fragS *fragP ATTRIBUTE_UNUSED)
 685 {
 686   as_fatal (_("md_convert_frag invoked\n"));
 687 }
 688
 689 /* Force truly undefined symbols to their maximum size, and generally set up
 690    the frag list to be relaxed.  */
 691 int
 692 md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, asection *segment ATTRIBUTE_UNUSED)
 693 {
 694   as_fatal (_("zpu_estimate_size_before_relax invoked\n"));
 695   return 0;
 696 }
 697
 698 void
 699 md_apply_fix3 (fixS *fixP, valueT *valP ATTRIBUTE_UNUSED, segT seg ATTRIBUTE_UNUSED)
 700 {
 701         if (linkrelax)
 702         {
 703                   /* We shouldn't ever get here because linkrelax is nonzero.  */
 704                   abort ();
 705                   fixP->fx_done = 1;
 706         } else
 707         {
 708                   char *where;
 709                   long value = * valP;
 710                   int op_type;
 711
 712                   if (fixP->fx_addsy == (symbolS *) NULL)
 713                     fixP->fx_done = 1;
 714
 715                   /* We don't actually support subtracting a symbol.  */
 716                   if (fixP->fx_subsy != (symbolS *) NULL)
 717                     as_bad_where (fixP->fx_file, fixP->fx_line, _("Expression too complex."));
 718
 719                   op_type = fixP->fx_r_type;
 720
 721                   /* The BFD_RELOC_32 is necessary for the support of --gstabs.  */
 722                   where = fixP->fx_frag->fr_literal + fixP->fx_where;
 723
 724                   switch (fixP->fx_r_type)
 725                     {
 726                         case BFD_RELOC_ZPU_IM_7:
 727                         case BFD_RELOC_ZPU_IM_14:
 728                         case BFD_RELOC_ZPU_IM_21:
 729                         case BFD_RELOC_ZPU_IM_28:
 730                         case BFD_RELOC_ZPU_IM_32:
 731                         case BFD_RELOC_ZPU_IM_7_PCREL:
 732                         case BFD_RELOC_ZPU_IM_14_PCREL:
 733                         case BFD_RELOC_ZPU_IM_21_PCREL:
 734                         case BFD_RELOC_ZPU_IM_28_PCREL:
 735                         case BFD_RELOC_ZPU_IM_32_PCREL:
 736                     case BFD_RELOC_32:
 737                     case BFD_RELOC_16:
 738                         case BFD_RELOC_ZPU_IM_14_NONRELAX:
 739                                   fixP->fx_done = 0;
 740                                 break;
 741
 742             case BFD_RELOC_32_PCREL:
 743                     case BFD_RELOC_24_PCREL:
 744                     case BFD_RELOC_16_PCREL:
 745                     case BFD_RELOC_8_PCREL:
 746                     as_bad_where (fixP->fx_file, fixP->fx_line, _("Unsupported relocatoin type."));
 747                       break;
 748
 749                     case BFD_RELOC_8:
 750                           fixP->fx_done = 1;
 751                       md_number_to_chars (where, value, fixP->fx_size);
 752                       break;
 753                       #if 0
 754                     case BFD_RELOC_32:
 755                       bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
 756                       break;
 757                     case BFD_RELOC_16:
 758                       bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
 759                       break;
 760                 #endif
 761                     default:
 762                       as_fatal (_("Line %d: unknown 1 relocation type: 0x%x."),
 763                                 fixP->fx_line, fixP->fx_r_type);
 764                     }
 765         }
 766 }
 767
 768 long
 769 md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED)
 770 {
 771         return fixP->fx_where + fixP->fx_frag->fr_address;
 772 }
 773
 774 static void
 775 s_bss (ignore)
 776      int ignore ATTRIBUTE_UNUSED;
 777 {
 778   /* We don't support putting frags in the BSS segment, we fake it
 779      by marking in_bss, then looking at s_skip for clues.  */
 780
 781   subseg_set (bss_section, 0);
 782   demand_empty_rest_of_line ();
 783 }
 784
 785 /* See whether we need to force a relocation into the output file.  */
 786 int
 787 tc_zpu_force_relocation (fixS *fixP)
 788 {
 789         switch (fixP->fx_r_type)
 790         {
 791                 case BFD_RELOC_ZPU_IM_7:
 792                 case BFD_RELOC_ZPU_IM_14:
 793                 case BFD_RELOC_ZPU_IM_21:
 794                 case BFD_RELOC_ZPU_IM_28:
 795                 case BFD_RELOC_ZPU_IM_32:
 796                 case BFD_RELOC_ZPU_IM_7_PCREL:
 797                 case BFD_RELOC_ZPU_IM_14_PCREL:
 798                 case BFD_RELOC_ZPU_IM_21_PCREL:
 799                 case BFD_RELOC_ZPU_IM_28_PCREL:
 800                 case BFD_RELOC_ZPU_IM_32_PCREL:
 801                 case BFD_RELOC_ZPU_IM_14_NONRELAX:
 802             return 1;
 803                  default:
 804                  break;
 805         }
 806
 807   return generic_force_reloc (fixP);
 808 }
 809
 810 int
 811 tc_zpu_fix_adjustable (fixS *fixP)
 812 {
 813   switch (fixP->fx_r_type)
 814     {
 815       /* For the linker relaxation to work correctly, these relocs
 816          need to be on the symbol itself.  */
 817     case BFD_RELOC_16:
 818     case BFD_RELOC_32:
 819
 820         /* plus these */
 821                 case BFD_RELOC_ZPU_IM_7:
 822                 case BFD_RELOC_ZPU_IM_14:
 823                 case BFD_RELOC_ZPU_IM_21:
 824                 case BFD_RELOC_ZPU_IM_28:
 825                 case BFD_RELOC_ZPU_IM_32:
 826                 case BFD_RELOC_ZPU_IM_7_PCREL:
 827                 case BFD_RELOC_ZPU_IM_14_PCREL:
 828                 case BFD_RELOC_ZPU_IM_21_PCREL:
 829                 case BFD_RELOC_ZPU_IM_28_PCREL:
 830                 case BFD_RELOC_ZPU_IM_32_PCREL:
 831                 case BFD_RELOC_ZPU_IM_14_NONRELAX:
 832       return 0;
 833
 834     default:
 835       return 1;
 836     }
 837 }