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fixes for host gcc 4.6.1
[zpugcc/jano.git] / toolchain / binutils / opcodes / sparc-dis.c
blob6f360c66051b4045f7b37e19c20634ba102ed6ca
1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2002, 2003, 2004 Free Software Foundation, Inc.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18
19 #include <stdio.h>
20
21 #include "sysdep.h"
22 #include "opcode/sparc.h"
23 #include "dis-asm.h"
24 #include "libiberty.h"
25 #include "opintl.h"
26
27 /* Bitmask of v9 architectures. */
28 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
29 | (1 << SPARC_OPCODE_ARCH_V9A) \
30 | (1 << SPARC_OPCODE_ARCH_V9B))
31 /* 1 if INSN is for v9 only. */
32 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
33 /* 1 if INSN is for v9. */
34 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
35
36 /* The sorted opcode table. */
37 static const struct sparc_opcode **sorted_opcodes;
38
39 /* For faster lookup, after insns are sorted they are hashed. */
40 /* ??? I think there is room for even more improvement. */
41
42 #define HASH_SIZE 256
43 /* It is important that we only look at insn code bits as that is how the
44 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
45 of the main types (0,1,2,3). */
46 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
47 #define HASH_INSN(INSN) \
48 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
49 struct opcode_hash
50 {
51 struct opcode_hash *next;
52 const struct sparc_opcode *opcode;
53 };
54 static struct opcode_hash *opcode_hash_table[HASH_SIZE];
55
56 static void build_hash_table
57 PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
58 static int is_delayed_branch PARAMS ((unsigned long));
59 static int compare_opcodes PARAMS ((const PTR, const PTR));
60 static int compute_arch_mask PARAMS ((unsigned long));
61
62 /* Sign-extend a value which is N bits long. */
63 #define SEX(value, bits) \
64 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
65 >> ((8 * sizeof (int)) - bits) )
66
67 static char *reg_names[] =
68 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
69 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
70 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
71 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
72 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
73 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
74 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
75 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
76 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
77 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
78 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
79 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
80 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
81 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
82 };
83
84 #define freg_names (&reg_names[4 * 8])
85
86 /* These are ordered according to there register number in
87 rdpr and wrpr insns. */
88 static char *v9_priv_reg_names[] =
89 {
90 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
91 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
92 "wstate", "fq"
93 /* "ver" - special cased */
94 };
95
96 /* These are ordered according to there register number in
97 rd and wr insns (-16). */
98 static char *v9a_asr_reg_names[] =
99 {
100 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
101 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
102 };
103
104 /* Macros used to extract instruction fields. Not all fields have
105 macros defined here, only those which are actually used. */
106
107 #define X_RD(i) (((i) >> 25) & 0x1f)
108 #define X_RS1(i) (((i) >> 14) & 0x1f)
109 #define X_LDST_I(i) (((i) >> 13) & 1)
110 #define X_ASI(i) (((i) >> 5) & 0xff)
111 #define X_RS2(i) (((i) >> 0) & 0x1f)
112 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
113 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
114 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
115 #define X_IMM22(i) X_DISP22 (i)
116 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
117
118 /* These are for v9. */
119 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
120 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
121 #define X_MEMBAR(i) ((i) & 0x7f)
122
123 /* Here is the union which was used to extract instruction fields
124 before the shift and mask macros were written.
125
126 union sparc_insn
127 {
128 unsigned long int code;
129 struct
130 {
131 unsigned int anop:2;
132 #define op ldst.anop
133 unsigned int anrd:5;
134 #define rd ldst.anrd
135 unsigned int op3:6;
136 unsigned int anrs1:5;
137 #define rs1 ldst.anrs1
138 unsigned int i:1;
139 unsigned int anasi:8;
140 #define asi ldst.anasi
141 unsigned int anrs2:5;
142 #define rs2 ldst.anrs2
143 #define shcnt rs2
144 } ldst;
145 struct
146 {
147 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
148 unsigned int IMM13:13;
149 #define imm13 IMM13.IMM13
150 } IMM13;
151 struct
152 {
153 unsigned int anop:2;
154 unsigned int a:1;
155 unsigned int cond:4;
156 unsigned int op2:3;
157 unsigned int DISP22:22;
158 #define disp22 branch.DISP22
159 #define imm22 disp22
160 } branch;
161 struct
162 {
163 unsigned int anop:2;
164 unsigned int a:1;
165 unsigned int z:1;
166 unsigned int rcond:3;
167 unsigned int op2:3;
168 unsigned int DISP16HI:2;
169 unsigned int p:1;
170 unsigned int _rs1:5;
171 unsigned int DISP16LO:14;
172 } branch16;
173 struct
174 {
175 unsigned int anop:2;
176 unsigned int adisp30:30;
177 #define disp30 call.adisp30
178 } call;
179 };
180
181 */
182
183 /* Nonzero if INSN is the opcode for a delayed branch. */
184 static int
185 is_delayed_branch (insn)
186 unsigned long insn;
187 {
188 struct opcode_hash *op;
189
190 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
191 {
192 const struct sparc_opcode *opcode = op->opcode;
193 if ((opcode->match & insn) == opcode->match
194 && (opcode->lose & insn) == 0)
195 return (opcode->flags & F_DELAYED);
196 }
197 return 0;
198 }
199
200 /* extern void qsort (); */
201
202 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
203 to compare_opcodes. */
204 static unsigned int current_arch_mask;
205
206 /* Print one instruction from MEMADDR on INFO->STREAM.
207
208 We suffix the instruction with a comment that gives the absolute
209 address involved, as well as its symbolic form, if the instruction
210 is preceded by a findable `sethi' and it either adds an immediate
211 displacement to that register, or it is an `add' or `or' instruction
212 on that register. */
213
214 int
215 print_insn_sparc (memaddr, info)
216 bfd_vma memaddr;
217 disassemble_info *info;
218 {
219 FILE *stream = info->stream;
220 bfd_byte buffer[4];
221 unsigned long insn;
222 register struct opcode_hash *op;
223 /* Nonzero of opcode table has been initialized. */
224 static int opcodes_initialized = 0;
225 /* bfd mach number of last call. */
226 static unsigned long current_mach = 0;
227 bfd_vma (*getword) (const void *);
228
229 if (!opcodes_initialized
230 || info->mach != current_mach)
231 {
232 int i;
233
234 current_arch_mask = compute_arch_mask (info->mach);
235
236 if (!opcodes_initialized)
237 sorted_opcodes = (const struct sparc_opcode **)
238 xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
239 /* Reset the sorted table so we can resort it. */
240 for (i = 0; i < sparc_num_opcodes; ++i)
241 sorted_opcodes[i] = &sparc_opcodes[i];
242 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
243 sizeof (sorted_opcodes[0]), compare_opcodes);
244
245 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
246 current_mach = info->mach;
247 opcodes_initialized = 1;
248 }
249
250 {
251 int status =
252 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
253 if (status != 0)
254 {
255 (*info->memory_error_func) (status, memaddr, info);
256 return -1;
257 }
258 }
259
260 /* On SPARClite variants such as DANlite (sparc86x), instructions
261 are always big-endian even when the machine is in little-endian mode. */
262 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
263 getword = bfd_getb32;
264 else
265 getword = bfd_getl32;
266
267 insn = getword (buffer);
268
269 info->insn_info_valid = 1; /* We do return this info. */
270 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
271 info->branch_delay_insns = 0; /* Assume no delay. */
272 info->target = 0; /* Assume no target known. */
273
274 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
275 {
276 const struct sparc_opcode *opcode = op->opcode;
277
278 /* If the insn isn't supported by the current architecture, skip it. */
279 if (! (opcode->architecture & current_arch_mask))
280 continue;
281
282 if ((opcode->match & insn) == opcode->match
283 && (opcode->lose & insn) == 0)
284 {
285 /* Nonzero means that we have found an instruction which has
286 the effect of adding or or'ing the imm13 field to rs1. */
287 int imm_added_to_rs1 = 0;
288 int imm_ored_to_rs1 = 0;
289
290 /* Nonzero means that we have found a plus sign in the args
291 field of the opcode table. */
292 int found_plus = 0;
293
294 /* Nonzero means we have an annulled branch. */
295 int is_annulled = 0;
296
297 /* Do we have an `add' or `or' instruction combining an
298 immediate with rs1? */
299 if (opcode->match == 0x80102000) /* or */
300 imm_ored_to_rs1 = 1;
301 if (opcode->match == 0x80002000) /* add */
302 imm_added_to_rs1 = 1;
303
304 if (X_RS1 (insn) != X_RD (insn)
305 && strchr (opcode->args, 'r') != 0)
306 /* Can't do simple format if source and dest are different. */
307 continue;
308 if (X_RS2 (insn) != X_RD (insn)
309 && strchr (opcode->args, 'O') != 0)
310 /* Can't do simple format if source and dest are different. */
311 continue;
312
313 (*info->fprintf_func) (stream, opcode->name);
314
315 {
316 register const char *s;
317
318 if (opcode->args[0] != ',')
319 (*info->fprintf_func) (stream, " ");
320
321 for (s = opcode->args; *s != '\0'; ++s)
322 {
323 while (*s == ',')
324 {
325 (*info->fprintf_func) (stream, ",");
326 ++s;
327 switch (*s)
328 {
329 case 'a':
330 (*info->fprintf_func) (stream, "a");
331 is_annulled = 1;
332 ++s;
333 continue;
334 case 'N':
335 (*info->fprintf_func) (stream, "pn");
336 ++s;
337 continue;
338
339 case 'T':
340 (*info->fprintf_func) (stream, "pt");
341 ++s;
342 continue;
343
344 default:
345 break;
346 }
347 }
348
349 (*info->fprintf_func) (stream, " ");
350
351 switch (*s)
352 {
353 case '+':
354 found_plus = 1;
355
356 /* note fall-through */
357 default:
358 (*info->fprintf_func) (stream, "%c", *s);
359 break;
360
361 case '#':
362 (*info->fprintf_func) (stream, "0");
363 break;
364
365 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
366 case '1':
367 case 'r':
368 reg (X_RS1 (insn));
369 break;
370
371 case '2':
372 case 'O':
373 reg (X_RS2 (insn));
374 break;
375
376 case 'd':
377 reg (X_RD (insn));
378 break;
379 #undef reg
380
381 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
382 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
383 case 'e':
384 freg (X_RS1 (insn));
385 break;
386 case 'v': /* double/even */
387 case 'V': /* quad/multiple of 4 */
388 fregx (X_RS1 (insn));
389 break;
390
391 case 'f':
392 freg (X_RS2 (insn));
393 break;
394 case 'B': /* double/even */
395 case 'R': /* quad/multiple of 4 */
396 fregx (X_RS2 (insn));
397 break;
398
399 case 'g':
400 freg (X_RD (insn));
401 break;
402 case 'H': /* double/even */
403 case 'J': /* quad/multiple of 4 */
404 fregx (X_RD (insn));
405 break;
406 #undef freg
407 #undef fregx
408
409 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
410 case 'b':
411 creg (X_RS1 (insn));
412 break;
413
414 case 'c':
415 creg (X_RS2 (insn));
416 break;
417
418 case 'D':
419 creg (X_RD (insn));
420 break;
421 #undef creg
422
423 case 'h':
424 (*info->fprintf_func) (stream, "%%hi(%#x)",
425 ((unsigned) 0xFFFFFFFF
426 & ((int) X_IMM22 (insn) << 10)));
427 break;
428
429 case 'i': /* 13 bit immediate */
430 case 'I': /* 11 bit immediate */
431 case 'j': /* 10 bit immediate */
432 {
433 int imm;
434
435 if (*s == 'i')
436 imm = X_SIMM (insn, 13);
437 else if (*s == 'I')
438 imm = X_SIMM (insn, 11);
439 else
440 imm = X_SIMM (insn, 10);
441
442 /* Check to see whether we have a 1+i, and take
443 note of that fact.
444
445 Note: because of the way we sort the table,
446 we will be matching 1+i rather than i+1,
447 so it is OK to assume that i is after +,
448 not before it. */
449 if (found_plus)
450 imm_added_to_rs1 = 1;
451
452 if (imm <= 9)
453 (*info->fprintf_func) (stream, "%d", imm);
454 else
455 (*info->fprintf_func) (stream, "%#x", imm);
456 }
457 break;
458
459 case 'X': /* 5 bit unsigned immediate */
460 case 'Y': /* 6 bit unsigned immediate */
461 {
462 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
463
464 if (imm <= 9)
465 (info->fprintf_func) (stream, "%d", imm);
466 else
467 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
468 }
469 break;
470
471 case '3':
472 (info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
473 break;
474
475 case 'K':
476 {
477 int mask = X_MEMBAR (insn);
478 int bit = 0x40, printed_one = 0;
479 const char *name;
480
481 if (mask == 0)
482 (info->fprintf_func) (stream, "0");
483 else
484 while (bit)
485 {
486 if (mask & bit)
487 {
488 if (printed_one)
489 (info->fprintf_func) (stream, "|");
490 name = sparc_decode_membar (bit);
491 (info->fprintf_func) (stream, "%s", name);
492 printed_one = 1;
493 }
494 bit >>= 1;
495 }
496 break;
497 }
498
499 case 'k':
500 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
501 (*info->print_address_func) (info->target, info);
502 break;
503
504 case 'G':
505 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
506 (*info->print_address_func) (info->target, info);
507 break;
508
509 case '6':
510 case '7':
511 case '8':
512 case '9':
513 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
514 break;
515
516 case 'z':
517 (*info->fprintf_func) (stream, "%%icc");
518 break;
519
520 case 'Z':
521 (*info->fprintf_func) (stream, "%%xcc");
522 break;
523
524 case 'E':
525 (*info->fprintf_func) (stream, "%%ccr");
526 break;
527
528 case 's':
529 (*info->fprintf_func) (stream, "%%fprs");
530 break;
531
532 case 'o':
533 (*info->fprintf_func) (stream, "%%asi");
534 break;
535
536 case 'W':
537 (*info->fprintf_func) (stream, "%%tick");
538 break;
539
540 case 'P':
541 (*info->fprintf_func) (stream, "%%pc");
542 break;
543
544 case '?':
545 if (X_RS1 (insn) == 31)
546 (*info->fprintf_func) (stream, "%%ver");
547 else if ((unsigned) X_RS1 (insn) < 16)
548 (*info->fprintf_func) (stream, "%%%s",
549 v9_priv_reg_names[X_RS1 (insn)]);
550 else
551 (*info->fprintf_func) (stream, "%%reserved");
552 break;
553
554 case '!':
555 if ((unsigned) X_RD (insn) < 15)
556 (*info->fprintf_func) (stream, "%%%s",
557 v9_priv_reg_names[X_RD (insn)]);
558 else
559 (*info->fprintf_func) (stream, "%%reserved");
560 break;
561
562 case '/':
563 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
564 (*info->fprintf_func) (stream, "%%reserved");
565 else
566 (*info->fprintf_func) (stream, "%%%s",
567 v9a_asr_reg_names[X_RS1 (insn)-16]);
568 break;
569
570 case '_':
571 if (X_RD (insn) < 16 || X_RD (insn) > 25)
572 (*info->fprintf_func) (stream, "%%reserved");
573 else
574 (*info->fprintf_func) (stream, "%%%s",
575 v9a_asr_reg_names[X_RD (insn)-16]);
576 break;
577
578 case '*':
579 {
580 const char *name = sparc_decode_prefetch (X_RD (insn));
581
582 if (name)
583 (*info->fprintf_func) (stream, "%s", name);
584 else
585 (*info->fprintf_func) (stream, "%d", X_RD (insn));
586 break;
587 }
588
589 case 'M':
590 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
591 break;
592
593 case 'm':
594 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
595 break;
596
597 case 'L':
598 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
599 (*info->print_address_func) (info->target, info);
600 break;
601
602 case 'n':
603 (*info->fprintf_func)
604 (stream, "%#x", SEX (X_DISP22 (insn), 22));
605 break;
606
607 case 'l':
608 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
609 (*info->print_address_func) (info->target, info);
610 break;
611
612 case 'A':
613 {
614 const char *name = sparc_decode_asi (X_ASI (insn));
615
616 if (name)
617 (*info->fprintf_func) (stream, "%s", name);
618 else
619 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
620 break;
621 }
622
623 case 'C':
624 (*info->fprintf_func) (stream, "%%csr");
625 break;
626
627 case 'F':
628 (*info->fprintf_func) (stream, "%%fsr");
629 break;
630
631 case 'p':
632 (*info->fprintf_func) (stream, "%%psr");
633 break;
634
635 case 'q':
636 (*info->fprintf_func) (stream, "%%fq");
637 break;
638
639 case 'Q':
640 (*info->fprintf_func) (stream, "%%cq");
641 break;
642
643 case 't':
644 (*info->fprintf_func) (stream, "%%tbr");
645 break;
646
647 case 'w':
648 (*info->fprintf_func) (stream, "%%wim");
649 break;
650
651 case 'x':
652 (*info->fprintf_func) (stream, "%d",
653 ((X_LDST_I (insn) << 8)
654 + X_ASI (insn)));
655 break;
656
657 case 'y':
658 (*info->fprintf_func) (stream, "%%y");
659 break;
660
661 case 'u':
662 case 'U':
663 {
664 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
665 const char *name = sparc_decode_sparclet_cpreg (val);
666
667 if (name)
668 (*info->fprintf_func) (stream, "%s", name);
669 else
670 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
671 break;
672 }
673 }
674 }
675 }
676
677 /* If we are adding or or'ing something to rs1, then
678 check to see whether the previous instruction was
679 a sethi to the same register as in the sethi.
680 If so, attempt to print the result of the add or
681 or (in this context add and or do the same thing)
682 and its symbolic value. */
683 if (imm_ored_to_rs1 || imm_added_to_rs1)
684 {
685 unsigned long prev_insn;
686 int errcode;
687
688 if (memaddr >= 4)
689 errcode =
690 (*info->read_memory_func)
691 (memaddr - 4, buffer, sizeof (buffer), info);
692 else
693 errcode = 1;
694
695 prev_insn = getword (buffer);
696
697 if (errcode == 0)
698 {
699 /* If it is a delayed branch, we need to look at the
700 instruction before the delayed branch. This handles
701 sequences such as:
702
703 sethi %o1, %hi(_foo), %o1
704 call _printf
705 or %o1, %lo(_foo), %o1 */
706
707 if (is_delayed_branch (prev_insn))
708 {
709 if (memaddr >= 8)
710 errcode = (*info->read_memory_func)
711 (memaddr - 8, buffer, sizeof (buffer), info);
712 else
713 errcode = 1;
714
715 prev_insn = getword (buffer);
716 }
717 }
718
719 /* If there was a problem reading memory, then assume
720 the previous instruction was not sethi. */
721 if (errcode == 0)
722 {
723 /* Is it sethi to the same register? */
724 if ((prev_insn & 0xc1c00000) == 0x01000000
725 && X_RD (prev_insn) == X_RS1 (insn))
726 {
727 (*info->fprintf_func) (stream, "\t! ");
728 info->target =
729 ((unsigned) 0xFFFFFFFF
730 & ((int) X_IMM22 (prev_insn) << 10));
731 if (imm_added_to_rs1)
732 info->target += X_SIMM (insn, 13);
733 else
734 info->target |= X_SIMM (insn, 13);
735 (*info->print_address_func) (info->target, info);
736 info->insn_type = dis_dref;
737 info->data_size = 4; /* FIXME!!! */
738 }
739 }
740 }
741
742 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
743 {
744 /* FIXME -- check is_annulled flag */
745 if (opcode->flags & F_UNBR)
746 info->insn_type = dis_branch;
747 if (opcode->flags & F_CONDBR)
748 info->insn_type = dis_condbranch;
749 if (opcode->flags & F_JSR)
750 info->insn_type = dis_jsr;
751 if (opcode->flags & F_DELAYED)
752 info->branch_delay_insns = 1;
753 }
754
755 return sizeof (buffer);
756 }
757 }
758
759 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
760 (*info->fprintf_func) (stream, _("unknown"));
761 return sizeof (buffer);
762 }
763
764 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
765
766 static int
767 compute_arch_mask (mach)
768 unsigned long mach;
769 {
770 switch (mach)
771 {
772 case 0 :
773 case bfd_mach_sparc :
774 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
775 case bfd_mach_sparc_sparclet :
776 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
777 case bfd_mach_sparc_sparclite :
778 case bfd_mach_sparc_sparclite_le :
779 /* sparclites insns are recognized by default (because that's how
780 they've always been treated, for better or worse). Kludge this by
781 indicating generic v8 is also selected. */
782 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
783 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
784 case bfd_mach_sparc_v8plus :
785 case bfd_mach_sparc_v9 :
786 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
787 case bfd_mach_sparc_v8plusa :
788 case bfd_mach_sparc_v9a :
789 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
790 case bfd_mach_sparc_v8plusb :
791 case bfd_mach_sparc_v9b :
792 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
793 }
794 abort ();
795 }
796
797 /* Compare opcodes A and B. */
798
799 static int
800 compare_opcodes (a, b)
801 const PTR a;
802 const PTR b;
803 {
804 struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
805 struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
806 unsigned long int match0 = op0->match, match1 = op1->match;
807 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
808 register unsigned int i;
809
810 /* If one (and only one) insn isn't supported by the current architecture,
811 prefer the one that is. If neither are supported, but they're both for
812 the same architecture, continue processing. Otherwise (both unsupported
813 and for different architectures), prefer lower numbered arch's (fudged
814 by comparing the bitmasks). */
815 if (op0->architecture & current_arch_mask)
816 {
817 if (! (op1->architecture & current_arch_mask))
818 return -1;
819 }
820 else
821 {
822 if (op1->architecture & current_arch_mask)
823 return 1;
824 else if (op0->architecture != op1->architecture)
825 return op0->architecture - op1->architecture;
826 }
827
828 /* If a bit is set in both match and lose, there is something
829 wrong with the opcode table. */
830 if (match0 & lose0)
831 {
832 fprintf
833 (stderr,
834 /* xgettext:c-format */
835 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
836 op0->name, match0, lose0);
837 op0->lose &= ~op0->match;
838 lose0 = op0->lose;
839 }
840
841 if (match1 & lose1)
842 {
843 fprintf
844 (stderr,
845 /* xgettext:c-format */
846 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
847 op1->name, match1, lose1);
848 op1->lose &= ~op1->match;
849 lose1 = op1->lose;
850 }
851
852 /* Because the bits that are variable in one opcode are constant in
853 another, it is important to order the opcodes in the right order. */
854 for (i = 0; i < 32; ++i)
855 {
856 unsigned long int x = 1 << i;
857 int x0 = (match0 & x) != 0;
858 int x1 = (match1 & x) != 0;
859
860 if (x0 != x1)
861 return x1 - x0;
862 }
863
864 for (i = 0; i < 32; ++i)
865 {
866 unsigned long int x = 1 << i;
867 int x0 = (lose0 & x) != 0;
868 int x1 = (lose1 & x) != 0;
869
870 if (x0 != x1)
871 return x1 - x0;
872 }
873
874 /* They are functionally equal. So as long as the opcode table is
875 valid, we can put whichever one first we want, on aesthetic grounds. */
876
877 /* Our first aesthetic ground is that aliases defer to real insns. */
878 {
879 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
880 if (alias_diff != 0)
881 /* Put the one that isn't an alias first. */
882 return alias_diff;
883 }
884
885 /* Except for aliases, two "identical" instructions had
886 better have the same opcode. This is a sanity check on the table. */
887 i = strcmp (op0->name, op1->name);
888 if (i)
889 {
890 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
891 return i;
892 else
893 fprintf (stderr,
894 /* xgettext:c-format */
895 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
896 op0->name, op1->name);
897 }
898
899 /* Fewer arguments are preferred. */
900 {
901 int length_diff = strlen (op0->args) - strlen (op1->args);
902 if (length_diff != 0)
903 /* Put the one with fewer arguments first. */
904 return length_diff;
905 }
906
907 /* Put 1+i before i+1. */
908 {
909 char *p0 = (char *) strchr (op0->args, '+');
910 char *p1 = (char *) strchr (op1->args, '+');
911
912 if (p0 && p1)
913 {
914 /* There is a plus in both operands. Note that a plus
915 sign cannot be the first character in args,
916 so the following [-1]'s are valid. */
917 if (p0[-1] == 'i' && p1[1] == 'i')
918 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
919 return 1;
920 if (p0[1] == 'i' && p1[-1] == 'i')
921 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
922 return -1;
923 }
924 }
925
926 /* Put 1,i before i,1. */
927 {
928 int i0 = strncmp (op0->args, "i,1", 3) == 0;
929 int i1 = strncmp (op1->args, "i,1", 3) == 0;
930
931 if (i0 ^ i1)
932 return i0 - i1;
933 }
934
935 /* They are, as far as we can tell, identical.
936 Since qsort may have rearranged the table partially, there is
937 no way to tell which one was first in the opcode table as
938 written, so just say there are equal. */
939 /* ??? This is no longer true now that we sort a vector of pointers,
940 not the table itself. */
941 return 0;
942 }
943
944 /* Build a hash table from the opcode table.
945 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
946
947 static void
948 build_hash_table (opcode_table, hash_table, num_opcodes)
949 const struct sparc_opcode **opcode_table;
950 struct opcode_hash **hash_table;
951 int num_opcodes;
952 {
953 register int i;
954 int hash_count[HASH_SIZE];
955 static struct opcode_hash *hash_buf = NULL;
956
957 /* Start at the end of the table and work backwards so that each
958 chain is sorted. */
959
960 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
961 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
962 if (hash_buf != NULL)
963 free (hash_buf);
964 hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
965 for (i = num_opcodes - 1; i >= 0; --i)
966 {
967 register int hash = HASH_INSN (opcode_table[i]->match);
968 register struct opcode_hash *h = &hash_buf[i];
969 h->next = hash_table[hash];
970 h->opcode = opcode_table[i];
971 hash_table[hash] = h;
972 ++hash_count[hash];
973 }
974
975 #if 0 /* for debugging */
976 {
977 int min_count = num_opcodes, max_count = 0;
978 int total;
979
980 for (i = 0; i < HASH_SIZE; ++i)
981 {
982 if (hash_count[i] < min_count)
983 min_count = hash_count[i];
984 if (hash_count[i] > max_count)
985 max_count = hash_count[i];
986 total += hash_count[i];
987 }
988
989 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
990 min_count, max_count, (double) total / HASH_SIZE);
991 }
992 #endif
993 }
my patches to zpugcc