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intuition.library: remove not needed include
[AROS.git] / rom / devs / ahci / ahci_attach.c
blob11064ded7b107e5a4a75e6054f5a7070ff81851f
1 /*
2 * (MPSAFE)
3 *
4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 *
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
20 *
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 * SUCH DAMAGE.
50 *
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
52 */
53
54 #include "ahci.h"
55
56 static int ahci_vt8251_attach(device_t);
57 static int ahci_ati_sb600_attach(device_t);
58 static int ahci_ati_sb700_attach(device_t);
59 static int ahci_nvidia_mcp_attach(device_t);
60 static int ahci_pci_attach(device_t);
61 static int ahci_pci_detach(device_t);
62
63 static const struct ahci_device ahci_devices[] = {
64 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
65 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
66 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
67 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
68 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA,
69 ahci_ati_sb700_attach, ahci_pci_detach, "ATI-SB700-SATA" },
70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
71 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
73 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
75 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
77 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" },
78 { 0, 0,
79 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
80 };
81
82 /*
83 * Match during probe and attach. The device does not yet have a softc.
84 */
85 const struct ahci_device *
86 ahci_lookup_device(device_t dev)
87 {
88 const struct ahci_device *ad;
89 u_int16_t vendor = pci_get_vendor(dev);
90 u_int16_t product = pci_get_device(dev);
91 u_int8_t class = pci_get_class(dev);
92 u_int8_t subclass = pci_get_subclass(dev);
93 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
94 int is_ahci;
95
96 /*
97 * Generally speaking if the pci device does not identify as
98 * AHCI we skip it.
99 */
100 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
101 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
102 is_ahci = 1;
103 } else {
104 is_ahci = 0;
105 }
106
107 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
108 if (ad->ad_vendor == vendor && ad->ad_product == product)
109 return (ad);
110 }
111
112 /*
113 * Last ad is the default match if the PCI device matches SATA.
114 */
115 if (is_ahci == 0)
116 ad = NULL;
117 return (ad);
118 }
119
120 /*
121 * Attach functions. They all eventually fall through to ahci_pci_attach().
122 */
123 static int
124 ahci_vt8251_attach(device_t dev)
125 {
126 struct ahci_softc *sc = device_get_softc(dev);
127
128 sc->sc_flags |= AHCI_F_NO_NCQ;
129 return (ahci_pci_attach(dev));
130 }
131
132 static int
133 ahci_ati_sb600_attach(device_t dev)
134 {
135 struct ahci_softc *sc = device_get_softc(dev);
136 pcireg_t magic;
137 u_int8_t subclass = pci_get_subclass(dev);
138 u_int8_t revid;
139
140 if (subclass == PCIS_STORAGE_IDE) {
141 revid = pci_read_config(dev, PCIR_REVID, 1);
142 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
143 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
144 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
145 pci_write_config(dev, PCIR_REVID,
146 (PCIC_STORAGE << 24) |
147 (PCIS_STORAGE_SATA << 16) |
148 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
149 revid, 4);
150 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
151 }
152
153 sc->sc_flags |= AHCI_F_IGN_FR;
154 return (ahci_pci_attach(dev));
155 }
156
157 static int
158 ahci_ati_sb700_attach(device_t dev)
159 {
160 struct ahci_softc *sc = device_get_softc(dev);
161
162 sc->sc_flags |= AHCI_F_IGN_FR;
163 sc->sc_flags |= AHCI_F_NO_PM;
164 return (ahci_pci_attach(dev));
165 }
166
167 static int
168 ahci_nvidia_mcp_attach(device_t dev)
169 {
170 struct ahci_softc *sc = device_get_softc(dev);
171
172 sc->sc_flags |= AHCI_F_IGN_FR;
173 return (ahci_pci_attach(dev));
174 }
175
176 static int
177 ahci_pci_attach(device_t dev)
178 {
179 struct ahci_softc *sc = device_get_softc(dev);
180 struct ahci_port *ap;
181 const char *gen;
182 u_int32_t pi, reg;
183 u_int32_t cap, cap2;
184 bus_addr_t addr;
185 int i;
186 int error, fbs;
187 const char *revision;
188
189 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
190 device_printf(dev, "BIOS disabled PCI interrupt, "
191 "re-enabling\n");
192 pci_write_config(dev, PCIR_COMMAND,
193 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
194 }
195
196
197 /*
198 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
199 */
200 sc->sc_dev = dev;
201 sc->sc_rid_irq = AHCI_IRQ_RID;
202 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
203 RF_SHAREABLE | RF_ACTIVE);
204 if (sc->sc_irq == NULL) {
205 device_printf(dev, "unable to map interrupt\n");
206 ahci_pci_detach(dev);
207 return (ENXIO);
208 }
209
210 /*
211 * When mapping the register window store the tag and handle
212 * separately so we can use the tag with per-port bus handle
213 * sub-spaces.
214 */
215 sc->sc_rid_regs = PCIR_BAR(5);
216 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
217 &sc->sc_rid_regs, RF_ACTIVE);
218 if (sc->sc_regs == NULL) {
219 device_printf(dev, "unable to map registers\n");
220 ahci_pci_detach(dev);
221 return (ENXIO);
222 }
223 sc->sc_iot = rman_get_bustag(sc->sc_regs);
224 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
225
226 /*
227 * Initialize the chipset and then set the interrupt vector up
228 */
229 device_printf(dev, "device flags 0x%x\n", sc->sc_flags);
230 error = ahci_init(sc);
231 if (error) {
232 ahci_pci_detach(dev);
233 return (ENXIO);
234 }
235
236 /*
237 * Get the AHCI capabilities and max number of concurrent
238 * command tags and set up the DMA tags. Adjust the saved
239 * sc_cap according to override flags.
240 */
241 cap = sc->sc_cap = ahci_read(sc, AHCI_REG_CAP);
242 if (sc->sc_flags & AHCI_F_NO_NCQ)
243 sc->sc_cap &= ~AHCI_REG_CAP_SNCQ;
244 if (sc->sc_flags & AHCI_F_NO_PM)
245 cap &= ~AHCI_REG_CAP_SPM;
246 if (sc->sc_flags & AHCI_F_FORCE_FBSS)
247 sc->sc_cap |= AHCI_REG_CAP_FBSS;
248
249 /*
250 * We assume at least 4 commands.
251 */
252 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
253 if (sc->sc_ncmds < 4) {
254 device_printf(dev, "NCS must probe a value >= 4\n");
255 ahci_pci_detach(dev);
256 return (ENXIO);
257 }
258
259 addr = (cap & AHCI_REG_CAP_S64A) ?
260 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
261
262 /*
263 * DMA tags for allocation of DMA memory buffers, lists, and so
264 * forth. These are typically per-port.
265 *
266 * When FIS-based switching is supported we need a rfis for
267 * each target (4K total). The spec also requires 4K alignment
268 * for this case.
269 */
270 fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1;
271 error = 0;
272
273 error += bus_dma_tag_create(
274 NULL, /* parent tag */
275 256 * fbs, /* alignment */
276 PAGE_SIZE, /* boundary */
277 addr, /* loaddr? */
278 BUS_SPACE_MAXADDR, /* hiaddr */
279 NULL, /* filter */
280 NULL, /* filterarg */
281 sizeof(struct ahci_rfis) * fbs, /* [max]size */
282 1, /* maxsegs */
283 sizeof(struct ahci_rfis) * fbs, /* maxsegsz */
284 0, /* flags */
285 &sc->sc_tag_rfis); /* return tag */
286
287 error += bus_dma_tag_create(
288 NULL, /* parent tag */
289 32, /* alignment */
290 1024, /* boundary */
291 addr, /* loaddr? */
292 BUS_SPACE_MAXADDR, /* hiaddr */
293 NULL, /* filter */
294 NULL, /* filterarg */
295 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
296 1, /* maxsegs */
297 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
298 0, /* flags */
299 &sc->sc_tag_cmdh); /* return tag */
300
301 /*
302 * NOTE: ahci_cmd_table is sized to a power of 2
303 */
304 error += bus_dma_tag_create(
305 NULL, /* parent tag */
306 sizeof(struct ahci_cmd_table), /* alignment */
307 1024, /* boundary */
308 addr, /* loaddr? */
309 BUS_SPACE_MAXADDR, /* hiaddr */
310 NULL, /* filter */
311 NULL, /* filterarg */
312 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
313 1, /* maxsegs */
314 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
315 0, /* flags */
316 &sc->sc_tag_cmdt); /* return tag */
317
318 /*
319 * The data tag is used for later dmamaps and not immediately
320 * allocated.
321 */
322 error += bus_dma_tag_create(
323 NULL, /* parent tag */
324 4, /* alignment */
325 0, /* boundary */
326 addr, /* loaddr? */
327 BUS_SPACE_MAXADDR, /* hiaddr */
328 NULL, /* filter */
329 NULL, /* filterarg */
330 4096 * 1024, /* maxiosize */
331 AHCI_MAX_PRDT, /* maxsegs */
332 65536, /* maxsegsz */
333 0, /* flags */
334 &sc->sc_tag_data); /* return tag */
335
336 if (error) {
337 device_printf(dev, "unable to create dma tags\n");
338 ahci_pci_detach(dev);
339 return (ENXIO);
340 }
341
342 switch (cap & AHCI_REG_CAP_ISS) {
343 case AHCI_REG_CAP_ISS_G1:
344 gen = "1 (1.5Gbps)";
345 break;
346 case AHCI_REG_CAP_ISS_G2:
347 gen = "2 (3Gbps)";
348 break;
349 case AHCI_REG_CAP_ISS_G3:
350 gen = "3 (6Gbps)";
351 break;
352 default:
353 gen = "unknown";
354 break;
355 }
356
357 /* check the revision */
358 reg = ahci_read(sc, AHCI_REG_VS);
359
360 switch (reg) {
361 case AHCI_REG_VS_0_95:
362 revision = "AHCI 0.95";
363 break;
364 case AHCI_REG_VS_1_0:
365 revision = "AHCI 1.0";
366 break;
367 case AHCI_REG_VS_1_1:
368 revision = "AHCI 1.1";
369 break;
370 case AHCI_REG_VS_1_2:
371 revision = "AHCI 1.2";
372 break;
373 case AHCI_REG_VS_1_3:
374 revision = "AHCI 1.3";
375 break;
376 case AHCI_REG_VS_1_4:
377 revision = "AHCI 1.4";
378 break;
379 case AHCI_REG_VS_1_5:
380 revision = "AHCI 1.5"; /* future will catch up to us */
381 break;
382 default:
383 device_printf(sc->sc_dev,
384 "Warning: Unknown AHCI revision 0x%08x\n", reg);
385 revision = "AHCI <unknown>";
386 break;
387 }
388 sc->sc_vers = reg;
389
390 if (reg >= AHCI_REG_VS_1_3) {
391 cap2 = ahci_read(sc, AHCI_REG_CAP2);
392 device_printf(dev,
393 "%s cap 0x%b cap2 0x%b, %d ports, "
394 "%d tags/port, gen %s\n",
395 revision,
396 cap, AHCI_FMT_CAP,
397 cap2, AHCI_FMT_CAP2,
398 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
399 } else {
400 cap2 = 0;
401 device_printf(dev,
402 "%s cap 0x%b, %d ports, "
403 "%d tags/port, gen %s\n",
404 revision,
405 cap, AHCI_FMT_CAP,
406 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
407 }
408 sc->sc_cap2 = cap2;
409
410 pi = ahci_read(sc, AHCI_REG_PI);
411 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
412 DEVNAME(sc), pi);
413
414 #ifdef AHCI_COALESCE
415 /* Naive coalescing support - enable for all ports. */
416 if (cap & AHCI_REG_CAP_CCCS) {
417 u_int16_t ccc_timeout = 20;
418 u_int8_t ccc_numcomplete = 12;
419 u_int32_t ccc_ctl;
420
421 /* disable coalescing during reconfiguration. */
422 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
423 ccc_ctl &= ~0x00000001;
424 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
425
426 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
427 if (pi & sc->sc_ccc_mask) {
428 /* A conflict with the implemented port list? */
429 kprintf("%s: coalescing interrupt/implemented port list "
430 "conflict, PI: %08x, ccc_mask: %08x\n",
431 DEVNAME(sc), pi, sc->sc_ccc_mask);
432 sc->sc_ccc_mask = 0;
433 goto noccc;
434 }
435
436 /* ahci_port_start will enable each port when it starts. */
437 sc->sc_ccc_ports = pi;
438 sc->sc_ccc_ports_cur = 0;
439
440 /* program thresholds and enable overall coalescing. */
441 ccc_ctl &= ~0xffffff00;
442 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
443 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
444 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
445 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
446 }
447 noccc:
448 #endif
449 /*
450 * Allocate per-port resources
451 *
452 * Ignore attach errors, leave the port intact for
453 * rescan and continue the loop.
454 *
455 * All ports are attached in parallel but the CAM scan-bus
456 * is held up until all ports are attached so we get a deterministic
457 * order.
458 */
459 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
460 if ((pi & (1 << i)) == 0) {
461 /* dont allocate stuff if the port isnt implemented */
462 continue;
463 }
464 error = ahci_port_alloc(sc, i);
465 }
466
467 /*
468 * Setup the interrupt vector and enable interrupts. Note that
469 * since the irq may be shared we do not set it up until we are
470 * ready to go.
471 */
472 if (error == 0) {
473 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
474 ahci_intr, sc,
475 &sc->sc_irq_handle, NULL);
476 }
477
478 if (error) {
479 device_printf(dev, "unable to install interrupt\n");
480 ahci_pci_detach(dev);
481 return (ENXIO);
482 }
483
484 /*
485 * Before marking the sc as good, which allows the interrupt
486 * subsystem to operate on the ports, wait for all the port threads
487 * to get past their initial pre-probe init. Otherwise an interrupt
488 * may try to process the port before it has been initialized.
489 */
490 for (i = 0; i < AHCI_MAX_PORTS; i++) {
491 if ((ap = sc->sc_ports[i]) != NULL) {
492 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
493 ahci_os_sleep(100);
494 }
495 }
496
497 /*
498 * Master interrupt enable, and call ahci_intr() in case we race
499 * our AHCI_F_INT_GOOD flag.
500 */
501 crit_enter();
502 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
503 sc->sc_flags |= AHCI_F_INT_GOOD;
504 crit_exit();
505 ahci_intr(sc);
506
507 /*
508 * All ports are probing in parallel. Wait for them to finish
509 * and then issue the cam attachment and bus scan serially so
510 * the 'da' assignments are deterministic.
511 */
512 for (i = 0; i < AHCI_MAX_PORTS; i++) {
513 if ((ap = sc->sc_ports[i]) != NULL) {
514 while (ap->ap_signal & AP_SIGF_INIT)
515 ahci_os_sleep(100);
516 ahci_os_lock_port(ap);
517 if (ahci_cam_attach(ap) == 0) {
518 ahci_cam_changed(ap, NULL, -1);
519 ahci_os_unlock_port(ap);
520 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
521 ahci_os_sleep(100);
522 }
523 } else {
524 ahci_os_unlock_port(ap);
525 }
526 }
527 }
528
529 return(0);
530 }
531
532 /*
533 * Device unload / detachment
534 */
535 static int
536 ahci_pci_detach(device_t dev)
537 {
538 struct ahci_softc *sc = device_get_softc(dev);
539 struct ahci_port *ap;
540 int i;
541
542 /*
543 * Disable the controller and de-register the interrupt, if any.
544 *
545 * XXX interlock last interrupt?
546 */
547 sc->sc_flags &= ~AHCI_F_INT_GOOD;
548 if (sc->sc_regs)
549 ahci_write(sc, AHCI_REG_GHC, 0);
550
551 if (sc->sc_irq_handle) {
552 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
553 sc->sc_irq_handle = NULL;
554 }
555
556 /*
557 * Free port structures and DMA memory
558 */
559 for (i = 0; i < AHCI_MAX_PORTS; i++) {
560 ap = sc->sc_ports[i];
561 if (ap) {
562 ahci_cam_detach(ap);
563 ahci_port_free(sc, i);
564 }
565 }
566
567 /*
568 * Clean up the bus space
569 */
570 if (sc->sc_irq) {
571 bus_release_resource(dev, SYS_RES_IRQ,
572 sc->sc_rid_irq, sc->sc_irq);
573 sc->sc_irq = NULL;
574 }
575 if (sc->sc_regs) {
576 bus_release_resource(dev, SYS_RES_MEMORY,
577 sc->sc_rid_regs, sc->sc_regs);
578 sc->sc_regs = NULL;
579 }
580
581 if (sc->sc_tag_rfis) {
582 bus_dma_tag_destroy(sc->sc_tag_rfis);
583 sc->sc_tag_rfis = NULL;
584 }
585 if (sc->sc_tag_cmdh) {
586 bus_dma_tag_destroy(sc->sc_tag_cmdh);
587 sc->sc_tag_cmdh = NULL;
588 }
589 if (sc->sc_tag_cmdt) {
590 bus_dma_tag_destroy(sc->sc_tag_cmdt);
591 sc->sc_tag_cmdt = NULL;
592 }
593 if (sc->sc_tag_data) {
594 bus_dma_tag_destroy(sc->sc_tag_data);
595 sc->sc_tag_data = NULL;
596 }
597
598 return (0);
599 }
Mirror of AROS' svn.