arch/arm-raspi/boot/serialdebug.c

   1 /*
   2     Copyright � 2013-2015, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <inttypes.h>
   7 #include <stdio.h>
   8 #include <stdint.h>
   9
  10 #include <hardware/bcm2708.h>
  11 #include <hardware/bcm2708_boot.h>
  12 #include <hardware/videocore.h>
  13 #include <hardware/pl011uart.h>
  14
  15 #include "serialdebug.h"
  16 #include "bootconsole.h"
  17 #include "vc_mb.h"
  18
  19 #undef ARM_PERIIOBASE
  20 #define ARM_PERIIOBASE (__arm_periiobase)
  21 extern uint32_t __arm_periiobase;
  22
  23 #define PL011_ICR_FLAGS (PL011_ICR_RXIC|PL011_ICR_TXIC|PL011_ICR_RTIC|PL011_ICR_FEIC|PL011_ICR_PEIC|PL011_ICR_BEIC|PL011_ICR_OEIC|PL011_ICR_RIMIC|PL011_ICR_CTSMIC|PL011_ICR_DSRMIC|PL011_ICR_DCDMIC)
  24
  25 #define DEF_BAUD 115200
  26
  27 #define PL011_DIVCLOCK(baud, clock)     ((clock * 4) / baud)
  28 #define PL011_BAUDINT(baud, clock)      ((PL011_DIVCLOCK(baud, clock) & 0xFFFFFFC0) >> 6)
  29 #define PL011_BAUDFRAC(baud, clock)     ((PL011_DIVCLOCK(baud, clock) & 0x0000003F) >> 0)
  30
  31 unsigned int uartclock;
  32 unsigned int uartdivint;
  33 unsigned int uartdivfrac;
  34 unsigned int uartbaud;
  35
  36 inline void waitSerOUT()
  37 {
  38     while(1)
  39     {
  40        if ((*(volatile uint32_t *)(PL011_0_BASE + PL011_FR) & PL011_FR_TXFF) == 0) break;
  41     }
  42 }
  43
  44 inline void putByte(uint8_t chr)
  45 {
  46     waitSerOUT();
  47
  48     if (chr == '\n')
  49     {
  50         *(volatile uint32_t *)(PL011_0_BASE + PL011_DR) = '\r';
  51         waitSerOUT();
  52     }
  53     *(volatile uint32_t *)(PL011_0_BASE + PL011_DR) = chr;
  54 }
  55
  56 void serInit(void)
  57 {
  58     unsigned int        uartvar;
  59
  60     volatile unsigned int *uart_msg = (unsigned int *) BOOTMEMADDR(bm_mboxmsg);
  61
  62     uartbaud = DEF_BAUD;
  63
  64     uart_msg[0] = 8 * 4;
  65     uart_msg[1] = VCTAG_REQ;
  66     uart_msg[2] = VCTAG_GETCLKRATE;
  67     uart_msg[3] = 8;
  68     uart_msg[4] = 4;
  69     uart_msg[5] = 0x000000002;                  // UART clock
  70     uart_msg[6] = 0;
  71     uart_msg[7] = 0;                            // terminate tag
  72
  73     vcmb_write(VCMB_BASE, VCMB_PROPCHAN, uart_msg);
  74     uart_msg = vcmb_read(VCMB_BASE, VCMB_PROPCHAN);
  75
  76     uartclock = uart_msg[6];
  77
  78     *(volatile uint32_t *)(PL011_0_BASE + PL011_CR) = 0;
  79
  80     uartvar = *(volatile uint32_t *)GPFSEL1;
  81     uartvar &= ~(7<<12);                        // TX on GPIO14
  82     uartvar |= 4<<12;                           // alt0
  83     uartvar &= ~(7<<15);                        // RX on GPIO15
  84     uartvar |= 4<<15;                           // alt0
  85     *(volatile uint32_t *)GPFSEL1 = uartvar;
  86
  87     /* Disable pull-ups and pull-downs on rs232 lines */
  88     *(volatile uint32_t *)GPPUD = 0;
  89
  90     for (uartvar = 0; uartvar < 150; uartvar++) asm volatile ("mov r0, r0\n");
  91
  92     *(volatile uint32_t *)GPPUDCLK0 = (1 << 14)|(1 << 15);
  93
  94     for (uartvar = 0; uartvar < 150; uartvar++) asm volatile ("mov r0, r0\n");
  95
  96     *(volatile uint32_t *)GPPUDCLK0 = 0;
  97
  98     *(volatile uint32_t *)(PL011_0_BASE + PL011_ICR) = PL011_ICR_FLAGS;
  99     uartdivint = PL011_BAUDINT(uartbaud, uartclock);
 100     *(volatile uint32_t *)(PL011_0_BASE + PL011_IBRD) = uartdivint;
 101     uartdivfrac = PL011_BAUDFRAC(uartbaud, uartclock);
 102     *(volatile uint32_t *)(PL011_0_BASE + PL011_FBRD) = uartdivfrac;
 103     *(volatile uint32_t *)(PL011_0_BASE + PL011_LCRH) = PL011_LCRH_WLEN8|PL011_LCRH_FEN;           // 8N1, Fifo enabled
 104     *(volatile uint32_t *)(PL011_0_BASE + PL011_CR) = PL011_CR_UARTEN|PL011_CR_TXE|PL011_CR_RXE;   // enable the uart, tx and rx
 105
 106     for (uartvar = 0; uartvar < 150; uartvar++) asm volatile ("mov r0, r0\n");
 107 }