workbench/devs/networks/e1000/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_HW_H_
  30 #define _E1000_HW_H_
  31
  32 #include "e1000_osdep.h"
  33 #include "e1000_regs.h"
  34 #include "e1000_defines.h"
  35
  36 struct e1000_hw;
  37
  38 #define E1000_DEV_ID_82542                    0x1000
  39 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  40 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  41 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  42 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  43 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  44 #define E1000_DEV_ID_82544GC_LOM              0x100D
  45 #define E1000_DEV_ID_82540EM                  0x100E
  46 #define E1000_DEV_ID_82540EM_LOM              0x1015
  47 #define E1000_DEV_ID_82540EP_LOM              0x1016
  48 #define E1000_DEV_ID_82540EP                  0x1017
  49 #define E1000_DEV_ID_82540EP_LP               0x101E
  50 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  51 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  52 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  53 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  54 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  55 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  56 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  57 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  58 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  59 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  60 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  61 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  62 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  63 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  64 #define E1000_DEV_ID_82541EI                  0x1013
  65 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  66 #define E1000_DEV_ID_82541ER_LOM              0x1014
  67 #define E1000_DEV_ID_82541ER                  0x1078
  68 #define E1000_DEV_ID_82541GI                  0x1076
  69 #define E1000_DEV_ID_82541GI_LF               0x107C
  70 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  71 #define E1000_DEV_ID_82547EI                  0x1019
  72 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  73 #define E1000_DEV_ID_82547GI                  0x1075
  74 #define E1000_REVISION_0 0
  75 #define E1000_REVISION_1 1
  76 #define E1000_REVISION_2 2
  77 #define E1000_REVISION_3 3
  78 #define E1000_REVISION_4 4
  79
  80 #define E1000_FUNC_0     0
  81 #define E1000_FUNC_1     1
  82
  83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  85
  86 enum e1000_mac_type {
  87         e1000_undefined = 0,
  88         e1000_82542,
  89         e1000_82543,
  90         e1000_82544,
  91         e1000_82540,
  92         e1000_82545,
  93         e1000_82545_rev_3,
  94         e1000_82546,
  95         e1000_82546_rev_3,
  96         e1000_82541,
  97         e1000_82541_rev_2,
  98         e1000_82547,
  99         e1000_82547_rev_2,
 100         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 101 };
 102
 103 enum e1000_media_type {
 104         e1000_media_type_unknown = 0,
 105         e1000_media_type_copper = 1,
 106         e1000_media_type_fiber = 2,
 107         e1000_media_type_internal_serdes = 3,
 108         e1000_num_media_types
 109 };
 110
 111 enum e1000_nvm_type {
 112         e1000_nvm_unknown = 0,
 113         e1000_nvm_none,
 114         e1000_nvm_eeprom_spi,
 115         e1000_nvm_eeprom_microwire,
 116         e1000_nvm_flash_hw,
 117         e1000_nvm_flash_sw
 118 };
 119
 120 enum e1000_nvm_override {
 121         e1000_nvm_override_none = 0,
 122         e1000_nvm_override_spi_small,
 123         e1000_nvm_override_spi_large,
 124         e1000_nvm_override_microwire_small,
 125         e1000_nvm_override_microwire_large
 126 };
 127
 128 enum e1000_phy_type {
 129         e1000_phy_unknown = 0,
 130         e1000_phy_none,
 131         e1000_phy_m88,
 132         e1000_phy_igp,
 133         e1000_phy_igp_2,
 134         e1000_phy_gg82563,
 135         e1000_phy_igp_3,
 136         e1000_phy_ife,
 137 };
 138
 139 enum e1000_bus_type {
 140         e1000_bus_type_unknown = 0,
 141         e1000_bus_type_pci,
 142         e1000_bus_type_pcix,
 143         e1000_bus_type_pci_express,
 144         e1000_bus_type_reserved
 145 };
 146
 147 enum e1000_bus_speed {
 148         e1000_bus_speed_unknown = 0,
 149         e1000_bus_speed_33,
 150         e1000_bus_speed_66,
 151         e1000_bus_speed_100,
 152         e1000_bus_speed_120,
 153         e1000_bus_speed_133,
 154         e1000_bus_speed_2500,
 155         e1000_bus_speed_5000,
 156         e1000_bus_speed_reserved
 157 };
 158
 159 enum e1000_bus_width {
 160         e1000_bus_width_unknown = 0,
 161         e1000_bus_width_pcie_x1,
 162         e1000_bus_width_pcie_x2,
 163         e1000_bus_width_pcie_x4 = 4,
 164         e1000_bus_width_pcie_x8 = 8,
 165         e1000_bus_width_32,
 166         e1000_bus_width_64,
 167         e1000_bus_width_reserved
 168 };
 169
 170 enum e1000_1000t_rx_status {
 171         e1000_1000t_rx_status_not_ok = 0,
 172         e1000_1000t_rx_status_ok,
 173         e1000_1000t_rx_status_undefined = 0xFF
 174 };
 175
 176 enum e1000_rev_polarity {
 177         e1000_rev_polarity_normal = 0,
 178         e1000_rev_polarity_reversed,
 179         e1000_rev_polarity_undefined = 0xFF
 180 };
 181
 182 enum e1000_fc_mode {
 183         e1000_fc_none = 0,
 184         e1000_fc_rx_pause,
 185         e1000_fc_tx_pause,
 186         e1000_fc_full,
 187         e1000_fc_default = 0xFF
 188 };
 189
 190 enum e1000_ffe_config {
 191         e1000_ffe_config_enabled = 0,
 192         e1000_ffe_config_active,
 193         e1000_ffe_config_blocked
 194 };
 195
 196 enum e1000_dsp_config {
 197         e1000_dsp_config_disabled = 0,
 198         e1000_dsp_config_enabled,
 199         e1000_dsp_config_activated,
 200         e1000_dsp_config_undefined = 0xFF
 201 };
 202
 203 enum e1000_ms_type {
 204         e1000_ms_hw_default = 0,
 205         e1000_ms_force_master,
 206         e1000_ms_force_slave,
 207         e1000_ms_auto
 208 };
 209
 210 enum e1000_smart_speed {
 211         e1000_smart_speed_default = 0,
 212         e1000_smart_speed_on,
 213         e1000_smart_speed_off
 214 };
 215
 216 enum e1000_serdes_link_state {
 217         e1000_serdes_link_down = 0,
 218         e1000_serdes_link_autoneg_progress,
 219         e1000_serdes_link_autoneg_complete,
 220         e1000_serdes_link_forced_up
 221 };
 222
 223 /* Receive Descriptor */
 224 struct e1000_rx_desc {
 225         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 226         __le16 length;      /* Length of data DMAed into data buffer */
 227         __le16 csum;        /* Packet checksum */
 228         u8  status;         /* Descriptor status */
 229         u8  errors;         /* Descriptor Errors */
 230         __le16 special;
 231 };
 232
 233 /* Receive Descriptor - Extended */
 234 union e1000_rx_desc_extended {
 235         struct {
 236                 __le64 buffer_addr;
 237                 __le64 reserved;
 238         } read;
 239         struct {
 240                 struct {
 241                         __le32 mrq;           /* Multiple Rx Queues */
 242                         union {
 243                                 __le32 rss;         /* RSS Hash */
 244                                 struct {
 245                                         __le16 ip_id;  /* IP id */
 246                                         __le16 csum;   /* Packet Checksum */
 247                                 } csum_ip;
 248                         } hi_dword;
 249                 } lower;
 250                 struct {
 251                         __le32 status_error;  /* ext status/error */
 252                         __le16 length;
 253                         __le16 vlan;          /* VLAN tag */
 254                 } upper;
 255         } wb;  /* writeback */
 256 };
 257
 258 #define MAX_PS_BUFFERS 4
 259 /* Receive Descriptor - Packet Split */
 260 union e1000_rx_desc_packet_split {
 261         struct {
 262                 /* one buffer for protocol header(s), three data buffers */
 263                 __le64 buffer_addr[MAX_PS_BUFFERS];
 264         } read;
 265         struct {
 266                 struct {
 267                         __le32 mrq;           /* Multiple Rx Queues */
 268                         union {
 269                                 __le32 rss;           /* RSS Hash */
 270                                 struct {
 271                                         __le16 ip_id;    /* IP id */
 272                                         __le16 csum;     /* Packet Checksum */
 273                                 } csum_ip;
 274                         } hi_dword;
 275                 } lower;
 276                 struct {
 277                         __le32 status_error;  /* ext status/error */
 278                         __le16 length0;       /* length of buffer 0 */
 279                         __le16 vlan;          /* VLAN tag */
 280                 } middle;
 281                 struct {
 282                         __le16 header_status;
 283                         __le16 length[3];     /* length of buffers 1-3 */
 284                 } upper;
 285                 __le64 reserved;
 286         } wb; /* writeback */
 287 };
 288
 289 /* Transmit Descriptor */
 290 struct e1000_tx_desc {
 291         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 292         union {
 293                 __le32 data;
 294                 struct {
 295                         __le16 length;    /* Data buffer length */
 296                         u8 cso;           /* Checksum offset */
 297                         u8 cmd;           /* Descriptor control */
 298                 } flags;
 299         } lower;
 300         union {
 301                 __le32 data;
 302                 struct {
 303                         u8 status;        /* Descriptor status */
 304                         u8 css;           /* Checksum start */
 305                         __le16 special;
 306                 } fields;
 307         } upper;
 308 };
 309
 310 /* Offload Context Descriptor */
 311 struct e1000_context_desc {
 312         union {
 313                 __le32 ip_config;
 314                 struct {
 315                         u8 ipcss;         /* IP checksum start */
 316                         u8 ipcso;         /* IP checksum offset */
 317                         __le16 ipcse;     /* IP checksum end */
 318                 } ip_fields;
 319         } lower_setup;
 320         union {
 321                 __le32 tcp_config;
 322                 struct {
 323                         u8 tucss;         /* TCP checksum start */
 324                         u8 tucso;         /* TCP checksum offset */
 325                         __le16 tucse;     /* TCP checksum end */
 326                 } tcp_fields;
 327         } upper_setup;
 328         __le32 cmd_and_length;
 329         union {
 330                 __le32 data;
 331                 struct {
 332                         u8 status;        /* Descriptor status */
 333                         u8 hdr_len;       /* Header length */
 334                         __le16 mss;       /* Maximum segment size */
 335                 } fields;
 336         } tcp_seg_setup;
 337 };
 338
 339 /* Offload data descriptor */
 340 struct e1000_data_desc {
 341         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 342         union {
 343                 __le32 data;
 344                 struct {
 345                         __le16 length;    /* Data buffer length */
 346                         u8 typ_len_ext;
 347                         u8 cmd;
 348                 } flags;
 349         } lower;
 350         union {
 351                 __le32 data;
 352                 struct {
 353                         u8 status;        /* Descriptor status */
 354                         u8 popts;         /* Packet Options */
 355                         __le16 special;
 356                 } fields;
 357         } upper;
 358 };
 359
 360 /* Statistics counters collected by the MAC */
 361 struct e1000_hw_stats {
 362         u64 crcerrs;
 363         u64 algnerrc;
 364         u64 symerrs;
 365         u64 rxerrc;
 366         u64 mpc;
 367         u64 scc;
 368         u64 ecol;
 369         u64 mcc;
 370         u64 latecol;
 371         u64 colc;
 372         u64 dc;
 373         u64 tncrs;
 374         u64 sec;
 375         u64 cexterr;
 376         u64 rlec;
 377         u64 xonrxc;
 378         u64 xontxc;
 379         u64 xoffrxc;
 380         u64 xofftxc;
 381         u64 fcruc;
 382         u64 prc64;
 383         u64 prc127;
 384         u64 prc255;
 385         u64 prc511;
 386         u64 prc1023;
 387         u64 prc1522;
 388         u64 gprc;
 389         u64 bprc;
 390         u64 mprc;
 391         u64 gptc;
 392         u64 gorc;
 393         u64 gotc;
 394         u64 rnbc;
 395         u64 ruc;
 396         u64 rfc;
 397         u64 roc;
 398         u64 rjc;
 399         u64 mgprc;
 400         u64 mgpdc;
 401         u64 mgptc;
 402         u64 tor;
 403         u64 tot;
 404         u64 tpr;
 405         u64 tpt;
 406         u64 ptc64;
 407         u64 ptc127;
 408         u64 ptc255;
 409         u64 ptc511;
 410         u64 ptc1023;
 411         u64 ptc1522;
 412         u64 mptc;
 413         u64 bptc;
 414         u64 tsctc;
 415         u64 tsctfc;
 416         u64 iac;
 417         u64 icrxptc;
 418         u64 icrxatc;
 419         u64 ictxptc;
 420         u64 ictxatc;
 421         u64 ictxqec;
 422         u64 ictxqmtc;
 423         u64 icrxdmtc;
 424         u64 icrxoc;
 425         u64 cbtmpc;
 426         u64 htdpmc;
 427         u64 cbrdpc;
 428         u64 cbrmpc;
 429         u64 rpthc;
 430         u64 hgptc;
 431         u64 htcbdpc;
 432         u64 hgorc;
 433         u64 hgotc;
 434         u64 lenerrs;
 435         u64 scvpc;
 436         u64 hrmpc;
 437         u64 doosync;
 438 };
 439
 440
 441 struct e1000_phy_stats {
 442         u32 idle_errors;
 443         u32 receive_errors;
 444 };
 445
 446 struct e1000_host_mng_dhcp_cookie {
 447         u32 signature;
 448         u8  status;
 449         u8  reserved0;
 450         u16 vlan_id;
 451         u32 reserved1;
 452         u16 reserved2;
 453         u8  reserved3;
 454         u8  checksum;
 455 };
 456
 457 /* Host Interface "Rev 1" */
 458 struct e1000_host_command_header {
 459         u8 command_id;
 460         u8 command_length;
 461         u8 command_options;
 462         u8 checksum;
 463 };
 464
 465 #define E1000_HI_MAX_DATA_LENGTH     252
 466 struct e1000_host_command_info {
 467         struct e1000_host_command_header command_header;
 468         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 469 };
 470
 471 /* Host Interface "Rev 2" */
 472 struct e1000_host_mng_command_header {
 473         u8  command_id;
 474         u8  checksum;
 475         u16 reserved1;
 476         u16 reserved2;
 477         u16 command_length;
 478 };
 479
 480 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 481 struct e1000_host_mng_command_info {
 482         struct e1000_host_mng_command_header command_header;
 483         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 484 };
 485
 486 #include "e1000_mac.h"
 487 #include "e1000_phy.h"
 488 #include "e1000_nvm.h"
 489 #include "e1000_manage.h"
 490
 491 struct e1000_mac_operations {
 492         /* Function pointers for the MAC. */
 493         s32  (*init_params)(struct e1000_hw *);
 494         s32  (*id_led_init)(struct e1000_hw *);
 495         s32  (*blink_led)(struct e1000_hw *);
 496         s32  (*check_for_link)(struct e1000_hw *);
 497         bool (*check_mng_mode)(struct e1000_hw *hw);
 498         s32  (*cleanup_led)(struct e1000_hw *);
 499         void (*clear_hw_cntrs)(struct e1000_hw *);
 500         void (*clear_vfta)(struct e1000_hw *);
 501         s32  (*get_bus_info)(struct e1000_hw *);
 502         void (*set_lan_id)(struct e1000_hw *);
 503         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 504         s32  (*led_on)(struct e1000_hw *);
 505         s32  (*led_off)(struct e1000_hw *);
 506         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 507         s32  (*reset_hw)(struct e1000_hw *);
 508         s32  (*init_hw)(struct e1000_hw *);
 509         s32  (*setup_link)(struct e1000_hw *);
 510         s32  (*setup_physical_interface)(struct e1000_hw *);
 511         s32  (*setup_led)(struct e1000_hw *);
 512         void (*write_vfta)(struct e1000_hw *, u32, u32);
 513         void (*mta_set)(struct e1000_hw *, u32);
 514         void (*config_collision_dist)(struct e1000_hw *);
 515         void (*rar_set)(struct e1000_hw *, u8*, u32);
 516         s32  (*read_mac_addr)(struct e1000_hw *);
 517         s32  (*validate_mdi_setting)(struct e1000_hw *);
 518         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 519         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 520                       struct e1000_host_mng_command_header*);
 521         s32  (*mng_enable_host_if)(struct e1000_hw *);
 522         s32  (*wait_autoneg)(struct e1000_hw *);
 523 };
 524
 525 struct e1000_phy_operations {
 526         s32  (*init_params)(struct e1000_hw *);
 527         s32  (*acquire)(struct e1000_hw *);
 528         s32  (*check_polarity)(struct e1000_hw *);
 529         s32  (*check_reset_block)(struct e1000_hw *);
 530         s32  (*commit)(struct e1000_hw *);
 531         s32  (*force_speed_duplex)(struct e1000_hw *);
 532         s32  (*get_cfg_done)(struct e1000_hw *hw);
 533         s32  (*get_cable_length)(struct e1000_hw *);
 534         s32  (*get_info)(struct e1000_hw *);
 535         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 536         void (*release)(struct e1000_hw *);
 537         s32  (*reset)(struct e1000_hw *);
 538         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 539         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 540         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 541         void (*power_up)(struct e1000_hw *);
 542         void (*power_down)(struct e1000_hw *);
 543 };
 544
 545 struct e1000_nvm_operations {
 546         s32  (*init_params)(struct e1000_hw *);
 547         s32  (*acquire)(struct e1000_hw *);
 548         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 549         void (*release)(struct e1000_hw *);
 550         void (*reload)(struct e1000_hw *);
 551         s32  (*update)(struct e1000_hw *);
 552         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 553         s32  (*validate)(struct e1000_hw *);
 554         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 555 };
 556
 557 struct e1000_mac_info {
 558         struct e1000_mac_operations ops;
 559         u8 addr[6];
 560         u8 perm_addr[6];
 561
 562         enum e1000_mac_type type;
 563
 564         u32 collision_delta;
 565         u32 ledctl_default;
 566         u32 ledctl_mode1;
 567         u32 ledctl_mode2;
 568         u32 mc_filter_type;
 569         u32 tx_packet_delta;
 570         u32 txcw;
 571
 572         u16 current_ifs_val;
 573         u16 ifs_max_val;
 574         u16 ifs_min_val;
 575         u16 ifs_ratio;
 576         u16 ifs_step_size;
 577         u16 mta_reg_count;
 578
 579         /* Maximum size of the MTA register table in all supported adapters */
 580         #define MAX_MTA_REG 128
 581         u32 mta_shadow[MAX_MTA_REG];
 582         u16 rar_entry_count;
 583
 584         u8  forced_speed_duplex;
 585
 586         bool adaptive_ifs;
 587         bool arc_subsystem_valid;
 588         bool asf_firmware_present;
 589         bool autoneg;
 590         bool autoneg_failed;
 591         bool get_link_status;
 592         bool in_ifs_mode;
 593         bool report_tx_early;
 594         enum e1000_serdes_link_state serdes_link_state;
 595         bool serdes_has_link;
 596         bool tx_pkt_filtering;
 597 };
 598
 599 struct e1000_phy_info {
 600         struct e1000_phy_operations ops;
 601         enum e1000_phy_type type;
 602
 603         enum e1000_1000t_rx_status local_rx;
 604         enum e1000_1000t_rx_status remote_rx;
 605         enum e1000_ms_type ms_type;
 606         enum e1000_ms_type original_ms_type;
 607         enum e1000_rev_polarity cable_polarity;
 608         enum e1000_smart_speed smart_speed;
 609
 610         u32 addr;
 611         u32 id;
 612         u32 reset_delay_us; /* in usec */
 613         u32 revision;
 614
 615         enum e1000_media_type media_type;
 616
 617         u16 autoneg_advertised;
 618         u16 autoneg_mask;
 619         u16 cable_length;
 620         u16 max_cable_length;
 621         u16 min_cable_length;
 622
 623         u8 mdix;
 624
 625         bool disable_polarity_correction;
 626         bool is_mdix;
 627         bool polarity_correction;
 628         bool reset_disable;
 629         bool speed_downgraded;
 630         bool autoneg_wait_to_complete;
 631 };
 632
 633 struct e1000_nvm_info {
 634         struct e1000_nvm_operations ops;
 635         enum e1000_nvm_type type;
 636         enum e1000_nvm_override override;
 637
 638         u32 flash_bank_size;
 639         u32 flash_base_addr;
 640
 641         u16 word_size;
 642         u16 delay_usec;
 643         u16 address_bits;
 644         u16 opcode_bits;
 645         u16 page_size;
 646 };
 647
 648 struct e1000_bus_info {
 649         enum e1000_bus_type type;
 650         enum e1000_bus_speed speed;
 651         enum e1000_bus_width width;
 652
 653         u16 func;
 654         u16 pci_cmd_word;
 655 };
 656
 657 struct e1000_fc_info {
 658         u32 high_water;          /* Flow control high-water mark */
 659         u32 low_water;           /* Flow control low-water mark */
 660         u16 pause_time;          /* Flow control pause timer */
 661         bool send_xon;           /* Flow control send XON */
 662         bool strict_ieee;        /* Strict IEEE mode */
 663         enum e1000_fc_mode current_mode; /* FC mode in effect */
 664         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 665 };
 666
 667 struct e1000_dev_spec_82541 {
 668         enum e1000_dsp_config dsp_config;
 669         enum e1000_ffe_config ffe_config;
 670         u16 spd_default;
 671         bool phy_init_script;
 672 };
 673
 674 struct e1000_dev_spec_82542 {
 675         bool dma_fairness;
 676 };
 677
 678 struct e1000_dev_spec_82543 {
 679         u32  tbi_compatibility;
 680         bool dma_fairness;
 681         bool init_phy_disabled;
 682 };
 683
 684 struct e1000_hw {
 685         void *back;
 686
 687         u8 __iomem *hw_addr;
 688         u8 __iomem *flash_address;
 689         unsigned long io_base;
 690
 691         struct e1000_mac_info  mac;
 692         struct e1000_fc_info   fc;
 693         struct e1000_phy_info  phy;
 694         struct e1000_nvm_info  nvm;
 695         struct e1000_bus_info  bus;
 696         struct e1000_host_mng_dhcp_cookie mng_cookie;
 697
 698         union {
 699                 struct e1000_dev_spec_82541     _82541;
 700                 struct e1000_dev_spec_82542     _82542;
 701                 struct e1000_dev_spec_82543     _82543;
 702         } dev_spec;
 703
 704         u16 device_id;
 705         u16 subsystem_vendor_id;
 706         u16 subsystem_device_id;
 707         u16 vendor_id;
 708
 709         u8  revision_id;
 710 };
 711
 712 #include "e1000_82541.h"
 713 #include "e1000_82543.h"
 714
 715 /* These functions must be implemented by drivers */
 716 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 717 void e1000_pci_set_mwi(struct e1000_hw *hw);
 718 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 719 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 720 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 721
 722 #endif