6 static inline eieio() {
7 asm volatile("eieio":::"memory");
10 static inline sync() {
11 asm volatile("sync":::"memory");
14 static inline isync() {
15 asm volatile("isync":::"memory");
18 static inline uint8_t _inb(volatile uint8_t *port
) {
19 uint8_t ret
; asm volatile("lbz%U1%X1 %0,%1; eieio":"=r"(ret
):"m"(*port
)); return ret
;
22 static inline void _outb(uint8_t val
, volatile uint8_t *port
) {
23 asm volatile("stb%U0%X0 %1,%0; eieio"::"m"(*port
),"r"(val
));
26 static inline uint16_t _inw(volatile uint16_t *port
) {
27 uint16_t ret
; asm volatile("lhz%U1%X1 %0,%1; eieio":"=r"(ret
):"m"(*port
)); return ret
;
30 static inline void _outw(uint16_t val
, volatile uint16_t *port
) {
31 asm volatile("sth%U0%X0 %1,%0; eieio"::"m"(*port
),"r"(val
));
34 static inline uint16_t _inw_be(volatile uint16_t *port
) {
38 static inline void _outw_be(uint16_t val
, volatile uint16_t *port
) {
42 static inline uint16_t _inw_le(volatile uint16_t *port
) {
43 uint16_t ret
; asm volatile("lhbrx %0,0,%1; eieio":"=r"(ret
):"r"(port
),"m"(*port
)); return ret
;
46 static inline void _outw_le(uint16_t val
, volatile uint16_t *port
) {
47 asm volatile("sthbrx %1,0,%2; eieio":"=m"(*port
):"r"(val
),"r"(port
));
51 static inline uint32_t _inl(volatile uint32_t *port
) {
52 uint32_t ret
; asm volatile("lwz%U1%X1 %0,%1; eieio":"=r"(ret
):"m"(*port
)); return ret
;
55 static inline void _outl(uint32_t val
, volatile uint32_t *port
) {
56 asm volatile("stw%U0%X0 %1,%0; eieio"::"m"(*port
),"r"(val
));
59 static inline uint32_t _inl_be(volatile uint32_t *port
) {
63 static inline void _outl_be(uint32_t val
, volatile uint32_t *port
) {
67 static inline uint32_t _inl_le(volatile uint32_t *port
) {
68 uint32_t ret
; asm volatile("lwbrx %0,0,%1; eieio":"=r"(ret
):"r"(port
),"m"(*port
)); return ret
;
71 static inline void _outl_le(uint32_t val
, volatile uint32_t *port
) {
72 asm volatile("stwbrx %1,0,%2; eieio":"=m"(*port
):"r"(val
),"r"(port
));
75 #define inb(a) _inb((volatile uint8_t *)(a))
76 #define inw(a) _inw((volatile uint16_t *)(a))
77 #define inl(a) _inl((volatile uint32_t *)(a))
78 #define inw_be(a) _inw_be((volatile uint16_t *)(a))
79 #define inl_be(a) _inl_be((volatile uint32_t *)(a))
80 #define inw_le(a) _inw_le((volatile uint16_t *)(a))
81 #define inl_le(a) _inl_le((volatile uint32_t *)(a))
83 #define outb(v,a) _outb(v,(volatile uint8_t *)(a))
84 #define outw(v,a) _outw(v,(volatile uint16_t *)(a))
85 #define outl(v,a) _outl(v,(volatile uint32_t *)(a))
86 #define outw_be(v,a) _outw_be(v,(volatile uint16_t *)(a))
87 #define outl_be(v,a) _outl_be(v,(volatile uint32_t *)(a))
88 #define outw_le(v,a) _outw_le(v,(volatile uint16_t *)(a))
89 #define outl_le(v,a) _outl_le(v,(volatile uint32_t *)(a))
91 /* This CPU has special little-endian I/O instructions */
94 /* This CPU has special MMIO instructions */
97 /* This CPU has special little-endian MMIO instructions */
98 #define HAVE_LE_MMIO_IO
100 /* All I/O on this CPU is memory-mapped */
101 #define mmio_inb(address) inb((uint8_t *)address)
102 #define mmio_inw(address) inw((uint16_t *)address)
103 #define mmio_inl(address) inl((uint32_t *)address)
105 #define mmio_outb(value, address) outb(value, (uint8_t *)address)
106 #define mmio_outw(value, address) outw(value, (uint16_t *)address)
107 #define mmio_outl(value, address) outl(value, (uint32_t *)address)
109 #define mmio_inw_le(address) inw_le((uint16_t *)address)
110 #define mmio_inl_le(address) inl_le((uint32_t *)address)
112 #define mmio_outw_le(value, address) outw_le(value, (uint16_t *)address)
113 #define mmio_outl_le(value, address) outl_le(value, (uint32_t *)address)