rom/usb/pciusbhc/xhci/pcixhci_controller.h

   1 /*
   2     Copyright © 2014, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc:
   6     Lang: English
   7 */
   8 #ifndef PCIXHCICONTROLLER_H
   9 #define PCIXHCICONTROLLER_H
  10
  11 #ifndef __packed
  12 #ifdef __GNUC__
  13 #define __packed __attribute__((__packed__))
  14 #else
  15 #define __packed
  16 #endif
  17 #endif
  18
  19 /*
  20  *----------------------------------------------------------------------------
  21  *             Includes for XHCI USB Controller
  22  *----------------------------------------------------------------------------
  23  */
  24
  25 /*
  26     XHCI_xxx's are register indexes
  27     XHCB_xxx's are bitnumbers
  28     XHCF_xxx's are flags
  29     XHCM_xxx's are bitmasks
  30     XHCV_xxx(p)'s return shifted values from p
  31 */
  32
  33 #define READMEM32(rb) AROS_LE2LONG(*((volatile ULONG *) (rb)))
  34 #define WRITEMEM32(adr, value)     *((volatile ULONG *) (adr)) = AROS_LONG2LE(value)
  35
  36 #define WRITEREG16(rb, offset, value) *((volatile UWORD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))) = AROS_WORD2LE(value)
  37 #define WRITEREG32(rb, offset, value) *((volatile ULONG *) (((UBYTE *) (rb)) + ((ULONG) (offset)))) = AROS_LONG2LE(value)
  38 #define WRITEREG64(rb, offset, value) *((volatile UQUAD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))) = AROS_QUAD2LE(value)
  39
  40 #define  READREG8(rb, offset)             (*((volatile UBYTE *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  41 #define READREG16(rb, offset) AROS_LE2WORD(*((volatile UWORD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  42 #define READREG32(rb, offset) AROS_LE2LONG(*((volatile ULONG *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  43 #define READREG64(rb, offset) AROS_LE2QUAD(*((volatile UQUAD *) (((UBYTE *) (rb)) + ((ULONG) (offset)))))
  44
  45 #define operational_readl(reg)          READREG32(unit->hc.operational_base, reg)
  46 #define operational_readq(reg)          READREG64(unit->hc.operational_base, reg)
  47 #define operational_writel(reg, value) WRITEREG32(unit->hc.operational_base, reg, value)
  48 #define operational_writeq(reg, value) WRITEREG64(unit->hc.operational_base, reg, value)
  49
  50 #define capability_readl(reg) READREG32(unit->hc.capability_base, reg)
  51 #define capability_readw(reg) READREG16(unit->hc.capability_base, reg)
  52 #define capability_readb(reg)  READREG8(unit->hc.capability_base, reg)
  53
  54 #define doorbell_readl(reg) READREG32(unit->hc.doorbell_base, reg)
  55
  56 #define runtime_readl(reg)          READREG32(unit->hc.runtime_base, reg)
  57 #define runtime_writel(reg, value) WRITEREG32(unit->hc.runtime_base, reg, value)
  58 #define runtime_writeq(reg, value) WRITEREG64(unit->hc.runtime_base, reg, value)
  59
  60 /*
  61     XHCI capability register defines
  62
  63     All Capability Registers are Read-Only (RO).
  64     The offsets for these registers are all relative to the beginning of the host controller’s MMIO address space.
  65 */
  66 #define XHCI_CAPLENGTH  0x00
  67 #define XHCI_HCIVERSION 0x02
  68 #define XHCI_HCSPARAMS1 0x04
  69 #define XHCI_HCSPARAMS2 0x08
  70 #define XHCI_HCSPARAMS3 0x0C
  71 #define XHCI_HCCPARAMS1 0x10
  72 #define XHCI_DBOFF      0x14
  73 #define XHCV_DBOFF(p)   (p&~0x3)
  74 #define XHCI_RTSOFF     0x18
  75 #define XHCV_RTSOFF(p)  (p&~0xf)
  76
  77
  78 /* XHCI_HCSPARAMS1 defines */
  79 #define XHCB_MaxSlots   0
  80 #define XHCB_MaxIntrs   8
  81 #define XHCB_MaxPorts   24
  82
  83 #define XHCM_MaxSlots (((1UL<<8)-1)<<XHCB_MaxSlots)
  84 #define XHCM_MaxIntrs (((1UL<<11)-1)<<XHCB_MaxIntrs)
  85 #define XHCM_MaxPorts (((1UL<<8)-1)<<XHCB_MaxPorts)
  86
  87 #define XHCV_MaxPorts(p)    (((p)&XHCM_MaxPorts)>>XHCB_MaxPorts)
  88 #define XHCV_MaxIntrs(p)    (((p)&XHCM_MaxIntrs)>>XHCB_MaxIntrs)
  89 #define XHCV_MaxSlots(p)    (((p)&XHCM_MaxSlots)>>XHCB_MaxSlots)
  90
  91
  92 /* XHCI_HCSPARAMS2 defines */
  93 #define XHCB_IST        0
  94 #define XHCB_ERST_Max   4
  95 #define XHCB_SPR        26
  96 #define XHCB_SPB_Max    27
  97
  98 #define XHCM_IST         (((1UL<<4)-1)<<XHCB_IST)
  99 #define XHCM_ERST_Max    (((1UL<<4)-1)<<XHCB_ERST_Max)
 100 #define XHCV_ERST_Max(p) (((p)&XHCM_ERST_Max)>>XHCB_ERST_Max)
 101 #define XHCF_SPR         (1UL<<XHCB_SPR)
 102 #define XHCM_SPB_Max     (((1UL<<5)-1)<<XHCB_SPB_Max)
 103 #define XHCV_SPB_Max(p)  (((p)&XHCM_SPB_Max)>>XHCB_SPB_Max)
 104
 105 #define XHCI_MAX_SCRATCHPADS    31
 106
 107 /* XHCI_HCSPARAMS3 defines */
 108 #define XHCB_U1DEV_LAT  0
 109 #define XHCB_U2DEV_LAT  16
 110
 111 #define XHCM_U1DEV_LAT  (((1UL<<8)-1)<<XHCB_U1DEV_LAT)
 112 #define XHCM_U2DEV_LAT  (((1UL<<16)-1)<<XHCB_U2DEV_LAT)
 113
 114
 115 /* XHCI_HCCPARAMS1 defines */
 116 #define XHCB_AC64       0
 117 #define XHCB_BNC        1
 118 #define XHCB_CSZ        2
 119 #define XHCB_PPC        3
 120 #define XHCB_PIND       4
 121 #define XHCB_LHRC       5
 122 #define XHCB_LTC        6
 123 #define XHCB_NSS        7
 124 #define XHCB_MaxPSASize 12
 125 #define XHCB_xECP       16
 126
 127 #define XHCF_AC64       (1UL<<XHCB_AC64)
 128 #define XHCF_BNC        (1UL<<XHCB_BNC)
 129 #define XHCF_CSZ        (1UL<<XHCB_CSZ)
 130 #define XHCF_PPC        (1UL<<XHCB_PPC)
 131 #define XHCF_PIND       (1UL<<XHCB_PIND)
 132 #define XHCF_LHRC       (1UL<<XHCB_LHRC)
 133 #define XHCF_LTC        (1UL<<XHCB_LTC)
 134 #define XHCF_NSS        (1UL<<XHCB_NSS)
 135 #define XHCM_MaxPSASize (((1UL<<4)-1)<<XHCB_MaxPSASize)
 136 #define XHCM_xECP       (((1UL<<16)-1)<<XHCB_xECP)
 137 #define XHCV_xECP(p)    ((((p)&XHCM_xECP)>>XHCB_xECP)<<2)
 138
 139
 140 /*
 141     XHCI runtime register defines
 142 */
 143 #define XHCI_MFINDEX    0
 144 #define XHCI_IMAN(n)    0x20+(32*n)
 145 #define XHCI_IMOD(n)    0x24+(32*n)
 146 #define XHCI_ERSTSZ(n)  0x28+(32*n)
 147 #define XHCI_ERSTBA(n)  0x30+(32*n)
 148 #define XHCI_ERDP(n)    0x38+(32*n)
 149
 150 #define XHCB_IMANIE     1
 151 #define XHCF_IMANIE     (1UL<<XHCB_IMANIE)
 152
 153
 154 /* Extended capability IDs */
 155 #define XHCB_EXT_CAPS_ID        0
 156 #define XHCB_EXT_CAPS_NEXT      8
 157 #define XHCB_EXT_CAPS_VALUE     16
 158
 159 #define XHCM_EXT_CAPS_ID        (((1UL<<8)-1)<<XHCB_EXT_CAPS_ID)
 160 #define XHCM_EXT_CAPS_NEXT      (((1UL<<8)-1)<<XHCB_EXT_CAPS_NEXT)
 161 #define XHCM_EXT_CAPS_VALUE     (((1UL<<16)-1)<<XHCB_EXT_CAPS_VALUE)
 162
 163 #define XHCV_EXT_CAPS_ID(p)     (((p)&XHCM_EXT_CAPS_ID)>>XHCB_EXT_CAPS_ID)
 164 #define XHCV_EXT_CAPS_NEXT(p)   ((((p)&XHCM_EXT_CAPS_NEXT)>>XHCB_EXT_CAPS_NEXT)<<2)
 165 #define XHCV_EXT_CAPS_VALUE(p)  (((p)&XHCM_EXT_CAPS_VALUE)>>XHCB_EXT_CAPS_VALUE)
 166
 167
 168 /* Reserved ID 0 */
 169 #define XHCI_EXT_CAPS_LEGACY    1
 170 #define XHCI_EXT_CAPS_PROTOCOL  2
 171 #define XHCI_EXT_CAPS_XPOWERMNG 3
 172 #define XHCI_EXT_CAPS_IOVIRT    4
 173 #define XHCI_EXT_CAPS_MSGINTR   5
 174 #define XHCI_EXT_CAPS_LOCALMEM  6
 175 /* Reserved IDs 7-9 */
 176 #define XHCI_EXT_CAPS_USBDEBUG  10
 177 /* Reserved IDs 11-16 */
 178 #define XHCI_EXT_CAPS_XMSGINTR  17
 179 /* Reserved IDs 18-191 */
 180 /* Vendor defined IDs 192-255 */
 181 #define XHCI_EXT_CAPS_MAX       255
 182
 183
 184 /* These are for XHCI_EXT_CAPS_LEGACY */
 185 /* USB Legacy Support Capability (USBLEGSUP) */
 186 #define XHCI_USBLEGSUP   0x00
 187 #define XHCB_BIOSOWNED   16
 188 #define XHCB_OSOWNED     24
 189 #define XHCF_BIOSOWNED  (1UL<<XHCB_BIOSOWNED)
 190 #define XHCF_OSOWNED    (1UL<<XHCB_OSOWNED)
 191
 192 /* USB Legacy Support Control/Status (USBLEGCTLSTS) */
 193 #define XHCI_USBLEGCTLSTS       0x04
 194 #define XHCB_SMI_USBE           0
 195 #define XHCB_SMI_HSEE           4
 196 #define XHCB_SMI_OSOE           13
 197 #define XHCB_SMI_PCICE          14
 198 #define XHCB_SMI_BARE           15
 199 #define XHCB_SMI_EI             16
 200 #define XHCB_SMI_HSE            20
 201 #define XHCB_SMI_OSOC           29
 202 #define XHCB_SMI_PCIC           30
 203 #define XHCB_SMI_BAR            31
 204
 205 #define XHCF_SMI_USBE           (1UL<<XHCB_SMI_USBE)
 206 #define XHCF_SMI_HSEE           (1UL<<XHCB_SMI_HSEE)
 207 #define XHCF_SMI_OSOE           (1UL<<XHCB_SMI_OSOE)
 208 #define XHCF_SMI_PCICE          (1UL<<XHCB_SMI_PCICE)
 209 #define XHCF_SMI_BARE           (1UL<<XHCB_SMI_BARE)
 210 #define XHCF_SMI_EI             (1UL<<XHCB_SMI_EI)
 211 #define XHCF_SMI_HSE            (1UL<<XHCB_SMI_HSE)
 212 #define XHCF_SMI_OSOC           (1UL<<XHCB_SMI_OSOC)
 213 #define XHCF_SMI_PCIC           (1UL<<XHCB_SMI_PCIC)
 214 #define XHCF_SMI_BAR            (1UL<<XHCB_SMI_BAR)
 215
 216
 217 /* These are for XHCI_EXT_CAPS_PROTOCOL */
 218 /* xHCI Supported Protocol Capability Field Definitions */
 219 #define XHCI_SPFD               0x00
 220 #define XHCB_SPFD_RMINOR        16
 221 #define XHCB_SPFD_RMAJOR        24
 222
 223 #define XHCM_SPFD_RMINOR        (((1UL<<8)-1)<<XHCB_SPFD_RMINOR)
 224 #define XHCM_SPFD_RMAJOR        (((1UL<<8)-1)<<XHCB_SPFD_RMAJOR)
 225
 226 #define XHCV_SPFD_RMINOR(p)    (((p)&XHCM_SPFD_RMINOR)>>XHCB_SPFD_RMINOR)
 227 #define XHCV_SPFD_RMAJOR(p)    (((p)&XHCM_SPFD_RMAJOR)>>XHCB_SPFD_RMAJOR)
 228
 229 #define XHCI_SPNAMESTRING       0x04
 230
 231 #define XHCI_SPPORT             0x08
 232 #define XHCB_SPPORT_CPO         0       /* Compatible Port Offset */
 233 #define XHCB_SPPORT_CPCNT       8       /* Compatible Port Count */
 234 #define XHCB_SPPORT_PD          16      /* Protocol Defined */
 235 #define XHCB_SPPORT_PSIC        28      /* Protocol Speed ID Count */
 236
 237 #define XHCM_SPPORT_CPO         (((1UL<<8)-1)<<XHCB_SPPORT_CPO)
 238 #define XHCM_SPPORT_CPCNT       (((1UL<<8)-1)<<XHCB_SPPORT_CPCNT)
 239 #define XHCM_SPPORT_PD          (((1UL<<12)-1)<<XHCB_SPPORT_PD)
 240 #define XHCM_SPPORT_PSIC        (((1UL<<4)-1)<<XHCB_SPPORT_PSIC)
 241
 242 #define XHCV_SPPORT_CPO(p)      (((p)&XHCM_SPPORT_CPO)>>XHCB_SPPORT_CPO)
 243 #define XHCV_SPPORT_CPCNT(p)    (((p)&XHCM_SPPORT_CPCNT)>>XHCB_SPPORT_CPCNT)
 244 #define XHCV_SPPORT_PD(p)       (((p)&XHCM_SPPORT_PD)>>XHCB_SPPORT_PD)
 245 #define XHCV_SPPORT_PSIC(p)     (((p)&XHCM_SPPORT_PSIC)>>XHCB_SPPORT_PSIC)
 246
 247 #define XHCI_SPPSI(psic) ((psic *4) + 0x10 )
 248 /* XHCI operational register defines */
 249 /* USB Command Register (USBCMD) */
 250 #define XHCI_USBCMD     0x00
 251
 252 #define XHCB_CMD_RS     0
 253 #define XHCB_CMD_HCRST  1
 254 #define XHCB_CMD_INTE   2
 255 #define XHCB_CMD_HSEE   3
 256 #define XHCB_CMD_LHCRST 7
 257 #define XHCB_CMD_CSS    8
 258 #define XHCB_CMD_CRS    9
 259 #define XHCB_CMD_EWE    10
 260 #define XHCB_CMD_EU3S   11
 261
 262 #define XHCF_CMD_RS     (1UL<<XHCB_CMD_RS)
 263 #define XHCF_CMD_HCRST  (1UL<<XHCB_CMD_HCRST)
 264 #define XHCF_CMD_INTE   (1UL<<XHCB_CMD_INTE)
 265 #define XHCF_CMD_HSEE   (1UL<<XHCB_CMD_HSEE)
 266 #define XHCF_CMD_LHCRST (1UL<<XHCB_CMD_LHCRST)
 267 #define XHCF_CMD_CSS    (1UL<<XHCB_CMD_CSS)
 268 #define XHCF_CMD_CRS    (1UL<<XHCB_CMD_CRS)
 269 #define XHCF_CMD_EWE    (1UL<<XHCB_CMD_EWE)
 270 #define XHCF_CMD_EU3S   (1UL<<XHCB_CMD_EU3S)
 271
 272 /* USB Status Register (USBSTS) */
 273 #define XHCI_USBSTS     0x04
 274 #define XHCB_STS_HCH    0
 275 #define XHCB_STS_HSE    2
 276 #define XHCB_STS_EINT   3
 277 #define XHCB_STS_PCD    4
 278 #define XHCB_STS_SSS    8
 279 #define XHCB_STS_RSS    9
 280 #define XHCB_STS_SRE    10
 281 #define XHCB_STS_CNR    11
 282 #define XHCB_STS_HCE    12
 283
 284 #define XHCF_STS_HCH    (1UL<<XHCB_STS_HCH)
 285 #define XHCF_STS_HSE    (1UL<<XHCB_STS_HSE)
 286 #define XHCF_STS_EINT   (1UL<<XHCB_STS_EINT)
 287 #define XHCF_STS_PCD    (1UL<<XHCB_STS_PCD)
 288 #define XHCF_STS_SSS    (1UL<<XHCB_STS_SSS)
 289 #define XHCF_STS_RSS    (1UL<<XHCB_STS_RSS)
 290 #define XHCF_STS_SRE    (1UL<<XHCB_STS_SRE)
 291 #define XHCF_STS_CNR    (1UL<<XHCB_STS_CNR)
 292 #define XHCF_STS_HCE    (1UL<<XHCB_STS_HCE)
 293
 294 /* Page Size Register (PAGESIZE) */
 295 #define XHCI_PAGESIZE   0x08
 296
 297 /* Device Notification Control Register (DNCTRL) */
 298 #define XHCI_DNCTRL     0x14
 299
 300 /* Command Ring Control Register (CRCR) */
 301 #define XHCI_CRCR       0x18
 302
 303 /* Device Context Base Address Array Pointer Register (DCBAAP) */
 304 #define XHCI_DCBAAP     0x30
 305
 306 /* Configure Register (CONFIG) */
 307 #define XHCI_CONFIG     0x38
 308 #define XHCB_CONFIG_MaxSlotsEn  0
 309 #define XHCM_CONFIG_MaxSlotsEn  (((1UL<<8)-1)<<XHCB_CONFIG_MaxSlotsEn)
 310
 311 /* Port Status and Control Register (PORTSC) */
 312 #define XHCI_PORTSC(port) (0x400 + (0x10 * (port-1)))
 313
 314 #define XHCB_PS_CCS     0
 315 #define XHCB_PS_PED     1
 316 #define XHCB_PS_OCA     3
 317 #define XHCB_PS_PR      4
 318 #define XHCB_PS_PLS     5
 319 #define XHCB_PS_PP      9
 320 #define XHCB_PS_SPEED   10
 321 #define XHCB_PS_PIC     14
 322 #define XHCB_PS_LWS     16
 323 #define XHCB_PS_CSC     17
 324 #define XHCB_PS_PEC     18
 325 #define XHCB_PS_WRC     19
 326 #define XHCB_PS_OCC     20
 327 #define XHCB_PS_PRC     21
 328 #define XHCB_PS_PLC     22
 329 #define XHCB_PS_CEC     23
 330 #define XHCB_PS_CAS     24
 331 #define XHCB_PS_WCE     25
 332 #define XHCB_PS_WDE     26
 333 #define XHCB_PS_WOE     27
 334 #define XHCB_PS_DR      30
 335 #define XHCB_PS_WPR     31
 336
 337 #define XHCF_PS_CCS     (1UL<<XHCB_PS_CCS)
 338 #define XHCF_PS_PED     (1UL<<XHCB_PS_PED)
 339 #define XHCF_PS_OCA     (1UL<<XHCB_PS_OCA)
 340 #define XHCF_PS_PR      (1UL<<XHCB_PS_PR)
 341 #define XHCM_PS_PLS     (((1UL<<4)-1)<<XHCB_PS_PLS)
 342 #define XHCF_PS_PP      (1UL<<XHCB_PS_PP)
 343 #define XHCM_PS_SPEED   (((1UL<<4)-1)<<XHCB_PS_SPEED)
 344 #define XHCM_PS_PIC     (((1UL<<2)-1)<<XHCB_PS_PIC)
 345 #define XHCF_PS_LWS     (1UL<<XHCB_PS_LWS)
 346 #define XHCF_PS_CSC     (1UL<<XHCB_PS_CSC)
 347 #define XHCF_PS_PEC     (1UL<<XHCB_PS_PEC)
 348 #define XHCF_PS_WRC     (1UL<<XHCB_PS_WRC)
 349 #define XHCF_PS_OCC     (1UL<<XHCB_PS_OCC)
 350 #define XHCF_PS_PRC     (1UL<<XHCB_PS_PRC)
 351 #define XHCF_PS_PLC     (1UL<<XHCB_PS_PLC)
 352 #define XHCF_PS_CEC     (1UL<<XHCB_PS_CEC)
 353 #define XHCF_PS_CAS     (1UL<<XHCB_PS_CAS)
 354 #define XHCF_PS_WCE     (1UL<<XHCB_PS_WCE)
 355 #define XHCF_PS_WDE     (1UL<<XHCB_PS_WDE)
 356 #define XHCF_PS_WOE     (1UL<<XHCB_PS_WOE)
 357 #define XHCF_PS_DR      (1UL<<XHCB_PS_DR)
 358 #define XHCF_PS_WPR     (1UL<<XHCB_PS_WPR)
 359 #define XHCV_PS_SPEED(p)    (((p)&XHCM_PS_SPEED)>>XHCB_PS_SPEED)
 360
 361 /* Event Ring Segment Table Entry */
 362 struct xhci_erste {
 363     UQUAD address;
 364     UWORD size;
 365     UWORD rsvd1;
 366         ULONG rsvd2;
 367 } __packed;
 368
 369 struct xhci_trb_template {
 370     UQUAD parameter;
 371     ULONG status;
 372     ULONG control;
 373 } __packed;
 374
 375
 376 /* TODO: define these */
 377 struct PCIXHCITransferRequestBlock {
 378         UQUAD   a;
 379         ULONG   b;
 380         ULONG   c;
 381 } __packed;
 382
 383 enum xhci_ring_type {
 384     TYPE_CTRL = 0,
 385     TYPE_ISOC,
 386     TYPE_BULK,
 387     TYPE_INTR,
 388     TYPE_STREAM,
 389     TYPE_COMMAND,
 390     TYPE_EVENT,
 391 };
 392
 393 #endif /* PCIXHCICONTROLLER_H */