2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #ifdef AH_SUPPORT_AR5210
24 #include "ah_internal.h"
26 #include "ar5210/ar5210.h"
27 #include "ar5210/ar5210reg.h"
28 #include "ar5210/ar5210phy.h"
30 #define AR_NUM_GPIO 6 /* 6 GPIO bits */
31 #define AR_GPIOD_MASK 0x2f /* 6-bit mask */
34 ar5210GetMacAddress(struct ath_hal
*ah
, uint8_t *mac
)
36 struct ath_hal_5210
*ahp
= AH5210(ah
);
38 OS_MEMCPY(mac
, ahp
->ah_macaddr
, IEEE80211_ADDR_LEN
);
42 ar5210SetMacAddress(struct ath_hal
*ah
, const uint8_t *mac
)
44 struct ath_hal_5210
*ahp
= AH5210(ah
);
46 OS_MEMCPY(ahp
->ah_macaddr
, mac
, IEEE80211_ADDR_LEN
);
51 ar5210GetBssIdMask(struct ath_hal
*ah
, uint8_t *mask
)
53 static const uint8_t ones
[IEEE80211_ADDR_LEN
] =
54 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
55 OS_MEMCPY(mask
, ones
, IEEE80211_ADDR_LEN
);
59 ar5210SetBssIdMask(struct ath_hal
*ah
, const uint8_t *mask
)
65 * Read 16 bits of data from the specified EEPROM offset.
68 ar5210EepromRead(struct ath_hal
*ah
, u_int off
, uint16_t *data
)
70 (void) OS_REG_READ(ah
, AR_EP_AIR(off
)); /* activate read op */
71 if (!ath_hal_wait(ah
, AR_EP_STA
,
72 AR_EP_STA_RDCMPLT
| AR_EP_STA_RDERR
, AR_EP_STA_RDCMPLT
)) {
73 HALDEBUG(ah
, HAL_DEBUG_ANY
, "%s: read failed for entry 0x%x\n",
74 __func__
, AR_EP_AIR(off
));
77 *data
= OS_REG_READ(ah
, AR_EP_RDATA
) & 0xffff;
82 * Return the wireless modes (a,b,g,t) supported by hardware.
84 * This value is what is actually supported by the hardware
85 * and is unaffected by regulatory/country code settings.
89 ar5210GetWirelessModes(struct ath_hal
*ah
)
91 /* XXX could enable turbo mode but can't do all rates */
96 * Called if RfKill is supported (according to EEPROM). Set the interrupt and
97 * GPIO values so the ISR and can disable RF on a switch signal
100 ar5210EnableRfKill(struct ath_hal
*ah
)
102 uint16_t rfsilent
= AH_PRIVATE(ah
)->ah_rfsilent
;
103 int select
= MS(rfsilent
, AR_EEPROM_RFSILENT_GPIO_SEL
);
104 int polarity
= MS(rfsilent
, AR_EEPROM_RFSILENT_POLARITY
);
107 * If radio disable switch connection to GPIO bit 0 is enabled
108 * program GPIO interrupt.
109 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
110 * verified that it is a later version of eeprom, it has a place for
111 * rfkill bit and it is set to 1, indicating that GPIO bit 0 hardware
112 * connection is present.
114 ar5210Gpio0SetIntr(ah
, select
, (ar5210GpioGet(ah
, select
) == polarity
));
118 * Configure GPIO Output lines
121 ar5210GpioCfgOutput(struct ath_hal
*ah
, uint32_t gpio
)
123 HALASSERT(gpio
< AR_NUM_GPIO
);
125 OS_REG_WRITE(ah
, AR_GPIOCR
,
126 (OS_REG_READ(ah
, AR_GPIOCR
) &~ AR_GPIOCR_ALL(gpio
))
127 | AR_GPIOCR_OUT1(gpio
));
133 * Configure GPIO Input lines
136 ar5210GpioCfgInput(struct ath_hal
*ah
, uint32_t gpio
)
138 HALASSERT(gpio
< AR_NUM_GPIO
);
140 OS_REG_WRITE(ah
, AR_GPIOCR
,
141 (OS_REG_READ(ah
, AR_GPIOCR
) &~ AR_GPIOCR_ALL(gpio
))
142 | AR_GPIOCR_IN(gpio
));
148 * Once configured for I/O - set output lines
151 ar5210GpioSet(struct ath_hal
*ah
, uint32_t gpio
, uint32_t val
)
155 HALASSERT(gpio
< AR_NUM_GPIO
);
157 reg
= OS_REG_READ(ah
, AR_GPIODO
);
159 reg
|= (val
&1) << gpio
;
161 OS_REG_WRITE(ah
, AR_GPIODO
, reg
);
166 * Once configured for I/O - get input lines
169 ar5210GpioGet(struct ath_hal
*ah
, uint32_t gpio
)
171 if (gpio
< AR_NUM_GPIO
) {
172 uint32_t val
= OS_REG_READ(ah
, AR_GPIODI
);
173 val
= ((val
& AR_GPIOD_MASK
) >> gpio
) & 0x1;
181 * Set the GPIO 0 Interrupt
184 ar5210Gpio0SetIntr(struct ath_hal
*ah
, u_int gpio
, uint32_t ilevel
)
186 uint32_t val
= OS_REG_READ(ah
, AR_GPIOCR
);
188 /* Clear the bits that we will modify. */
189 val
&= ~(AR_GPIOCR_INT_SEL(gpio
) | AR_GPIOCR_INT_SELH
| AR_GPIOCR_INT_ENA
|
190 AR_GPIOCR_ALL(gpio
));
192 val
|= AR_GPIOCR_INT_SEL(gpio
) | AR_GPIOCR_INT_ENA
;
194 val
|= AR_GPIOCR_INT_SELH
;
196 /* Don't need to change anything for low level interrupt. */
197 OS_REG_WRITE(ah
, AR_GPIOCR
, val
);
199 /* Change the interrupt mask. */
200 ar5210SetInterrupts(ah
, AH5210(ah
)->ah_maskReg
| HAL_INT_GPIO
);
204 * Change the LED blinking pattern to correspond to the connectivity
207 ar5210SetLedState(struct ath_hal
*ah
, HAL_LED_STATE state
)
211 val
= OS_REG_READ(ah
, AR_PCICFG
);
214 val
&= ~(AR_PCICFG_LED_PEND
| AR_PCICFG_LED_ACT
);
217 /* normal blink when connected */
218 val
&= ~AR_PCICFG_LED_PEND
;
219 val
|= AR_PCICFG_LED_ACT
;
222 val
|= AR_PCICFG_LED_PEND
;
223 val
&= ~AR_PCICFG_LED_ACT
;
226 OS_REG_WRITE(ah
, AR_PCICFG
, val
);
230 * Return 1 or 2 for the corresponding antenna that is in use
233 ar5210GetDefAntenna(struct ath_hal
*ah
)
235 uint32_t val
= OS_REG_READ(ah
, AR_STA_ID1
);
236 return (val
& AR_STA_ID1_DEFAULT_ANTENNA
? 2 : 1);
240 ar5210SetDefAntenna(struct ath_hal
*ah
, u_int antenna
)
242 uint32_t val
= OS_REG_READ(ah
, AR_STA_ID1
);
244 if (antenna
!= (val
& AR_STA_ID1_DEFAULT_ANTENNA
? 2 : 1)) {
246 * Antenna change requested, force a toggle of the default.
248 OS_REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_DEFAULT_ANTENNA
);
253 ar5210GetAntennaSwitch(struct ath_hal
*ah
)
255 return HAL_ANT_VARIABLE
;
259 ar5210SetAntennaSwitch(struct ath_hal
*ah
, HAL_ANT_SETTING settings
)
261 /* XXX not sure how to fix antenna */
262 return (settings
== HAL_ANT_VARIABLE
);
266 * Change association related fields programmed into the hardware.
267 * Writing a valid BSSID to the hardware effectively enables the hardware
268 * to synchronize its TSF to the correct beacons and receive frames coming
269 * from that BSSID. It is called by the SME JOIN operation.
272 ar5210WriteAssocid(struct ath_hal
*ah
, const uint8_t *bssid
, uint16_t assocId
)
274 struct ath_hal_5210
*ahp
= AH5210(ah
);
276 /* XXX save bssid for possible re-use on reset */
277 OS_MEMCPY(ahp
->ah_bssid
, bssid
, IEEE80211_ADDR_LEN
);
278 OS_REG_WRITE(ah
, AR_BSS_ID0
, LE_READ_4(ahp
->ah_bssid
));
279 OS_REG_WRITE(ah
, AR_BSS_ID1
, LE_READ_2(ahp
->ah_bssid
+4) |
280 ((assocId
& 0x3fff)<<AR_BSS_ID1_AID_S
));
282 OS_REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_NO_PSPOLL
);
284 OS_REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_NO_PSPOLL
);
288 * Get the current hardware tsf for stamlme.
291 ar5210GetTsf64(struct ath_hal
*ah
)
293 uint32_t low1
, low2
, u32
;
295 /* sync multi-word read */
296 low1
= OS_REG_READ(ah
, AR_TSF_L32
);
297 u32
= OS_REG_READ(ah
, AR_TSF_U32
);
298 low2
= OS_REG_READ(ah
, AR_TSF_L32
);
299 if (low2
< low1
) { /* roll over */
301 * If we are not preempted this will work. If we are
302 * then we re-reading AR_TSF_U32 does no good as the
303 * low bits will be meaningless. Likewise reading
304 * L32, U32, U32, then comparing the last two reads
305 * to check for rollover
306 * doesn't help if preempted--so we take this approach
307 * as it costs one less PCI read which can be noticeable
308 * when doing things like timestamping packets in
313 return (((uint64_t) u32
) << 32) | ((uint64_t) low2
);
317 * Get the current hardware tsf for stamlme.
320 ar5210GetTsf32(struct ath_hal
*ah
)
322 return OS_REG_READ(ah
, AR_TSF_L32
);
326 * Reset the current hardware tsf for stamlme
329 ar5210ResetTsf(struct ath_hal
*ah
)
331 uint32_t val
= OS_REG_READ(ah
, AR_BEACON
);
333 OS_REG_WRITE(ah
, AR_BEACON
, val
| AR_BEACON_RESET_TSF
);
337 * Grab a semi-random value from hardware registers - may not
341 ar5210GetRandomSeed(struct ath_hal
*ah
)
345 nf
= (OS_REG_READ(ah
, AR_PHY_BASE
+ (25 << 2)) >> 19) & 0x1ff;
347 nf
= 0 - ((nf
^ 0x1ff) + 1);
348 return (OS_REG_READ(ah
, AR_TSF_U32
) ^
349 OS_REG_READ(ah
, AR_TSF_L32
) ^ nf
);
353 * Detect if our card is present
356 ar5210DetectCardPresent(struct ath_hal
*ah
)
359 * Read the Silicon Revision register and compare that
360 * to what we read at attach time. If the same, we say
361 * a card/device is present.
363 return (AH_PRIVATE(ah
)->ah_macRev
== (OS_REG_READ(ah
, AR_SREV
) & 0xff));
367 * Update MIB Counters
370 ar5210UpdateMibCounters(struct ath_hal
*ah
, HAL_MIB_STATS
*stats
)
372 stats
->ackrcv_bad
+= OS_REG_READ(ah
, AR_ACK_FAIL
);
373 stats
->rts_bad
+= OS_REG_READ(ah
, AR_RTS_FAIL
);
374 stats
->fcs_bad
+= OS_REG_READ(ah
, AR_FCS_FAIL
);
375 stats
->rts_good
+= OS_REG_READ(ah
, AR_RTS_OK
);
376 stats
->beacons
+= OS_REG_READ(ah
, AR_BEACON_CNT
);
380 ar5210SetSifsTime(struct ath_hal
*ah
, u_int us
)
382 struct ath_hal_5210
*ahp
= AH5210(ah
);
384 if (us
> ath_hal_mac_usec(ah
, 0x7ff)) {
385 HALDEBUG(ah
, HAL_DEBUG_ANY
, "%s: bad SIFS time %u\n",
387 ahp
->ah_sifstime
= (u_int
) -1; /* restore default handling */
390 /* convert to system clocks */
391 OS_REG_RMW_FIELD(ah
, AR_IFS0
, AR_IFS0_SIFS
,
392 ath_hal_mac_clks(ah
, us
));
393 ahp
->ah_sifstime
= us
;
399 ar5210GetSifsTime(struct ath_hal
*ah
)
401 u_int clks
= OS_REG_READ(ah
, AR_IFS0
) & 0x7ff;
402 return ath_hal_mac_usec(ah
, clks
); /* convert from system clocks */
406 ar5210SetSlotTime(struct ath_hal
*ah
, u_int us
)
408 struct ath_hal_5210
*ahp
= AH5210(ah
);
410 if (us
< HAL_SLOT_TIME_9
|| us
> ath_hal_mac_usec(ah
, 0xffff)) {
411 HALDEBUG(ah
, HAL_DEBUG_ANY
, "%s: bad slot time %u\n",
413 ahp
->ah_slottime
= (u_int
) -1; /* restore default handling */
416 /* convert to system clocks */
417 OS_REG_WRITE(ah
, AR_SLOT_TIME
, ath_hal_mac_clks(ah
, us
));
418 ahp
->ah_slottime
= us
;
424 ar5210GetSlotTime(struct ath_hal
*ah
)
426 u_int clks
= OS_REG_READ(ah
, AR_SLOT_TIME
) & 0xffff;
427 return ath_hal_mac_usec(ah
, clks
); /* convert from system clocks */
431 ar5210SetAckTimeout(struct ath_hal
*ah
, u_int us
)
433 struct ath_hal_5210
*ahp
= AH5210(ah
);
435 if (us
> ath_hal_mac_usec(ah
, MS(0xffffffff, AR_TIME_OUT_ACK
))) {
436 HALDEBUG(ah
, HAL_DEBUG_ANY
, "%s: bad ack timeout %u\n",
438 ahp
->ah_acktimeout
= (u_int
) -1; /* restore default handling */
441 /* convert to system clocks */
442 OS_REG_RMW_FIELD(ah
, AR_TIME_OUT
,
443 AR_TIME_OUT_ACK
, ath_hal_mac_clks(ah
, us
));
444 ahp
->ah_acktimeout
= us
;
450 ar5210GetAckTimeout(struct ath_hal
*ah
)
452 u_int clks
= MS(OS_REG_READ(ah
, AR_TIME_OUT
), AR_TIME_OUT_ACK
);
453 return ath_hal_mac_usec(ah
, clks
); /* convert from system clocks */
457 ar5210GetAckCTSRate(struct ath_hal
*ah
)
459 return ((AH5210(ah
)->ah_staId1Defaults
& AR_STA_ID1_ACKCTS_6MB
) == 0);
463 ar5210SetAckCTSRate(struct ath_hal
*ah
, u_int high
)
465 struct ath_hal_5210
*ahp
= AH5210(ah
);
468 OS_REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_ACKCTS_6MB
);
469 ahp
->ah_staId1Defaults
&= ~AR_STA_ID1_ACKCTS_6MB
;
471 OS_REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_ACKCTS_6MB
);
472 ahp
->ah_staId1Defaults
|= AR_STA_ID1_ACKCTS_6MB
;
478 ar5210SetCTSTimeout(struct ath_hal
*ah
, u_int us
)
480 struct ath_hal_5210
*ahp
= AH5210(ah
);
482 if (us
> ath_hal_mac_usec(ah
, MS(0xffffffff, AR_TIME_OUT_CTS
))) {
483 HALDEBUG(ah
, HAL_DEBUG_ANY
, "%s: bad cts timeout %u\n",
485 ahp
->ah_ctstimeout
= (u_int
) -1; /* restore default handling */
488 /* convert to system clocks */
489 OS_REG_RMW_FIELD(ah
, AR_TIME_OUT
,
490 AR_TIME_OUT_CTS
, ath_hal_mac_clks(ah
, us
));
491 ahp
->ah_ctstimeout
= us
;
497 ar5210GetCTSTimeout(struct ath_hal
*ah
)
499 u_int clks
= MS(OS_REG_READ(ah
, AR_TIME_OUT
), AR_TIME_OUT_CTS
);
500 return ath_hal_mac_usec(ah
, clks
); /* convert from system clocks */
504 ar5210SetDecompMask(struct ath_hal
*ah
, uint16_t keyidx
, int en
)
511 ar5210SetCoverageClass(struct ath_hal
*ah
, uint8_t coverageclass
, int now
)
516 * Control Adaptive Noise Immunity Parameters
519 ar5210AniControl(struct ath_hal
*ah
, HAL_ANI_CMD cmd
, int param
)
525 ar5210AniPoll(struct ath_hal
*ah
, const HAL_NODE_STATS
*stats
, HAL_CHANNEL
*chan
)
530 ar5210MibEvent(struct ath_hal
*ah
, const HAL_NODE_STATS
*stats
)
534 #define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC)
537 ar5210GetCapability(struct ath_hal
*ah
, HAL_CAPABILITY_TYPE type
,
538 uint32_t capability
, uint32_t *result
)
542 case HAL_CAP_CIPHER
: /* cipher handled in hardware */
543 return (capability
== HAL_CIPHER_WEP
? HAL_OK
: HAL_ENOTSUPP
);
545 return ath_hal_getcapability(ah
, type
, capability
, result
);
550 ar5210SetCapability(struct ath_hal
*ah
, HAL_CAPABILITY_TYPE type
,
551 uint32_t capability
, uint32_t setting
, HAL_STATUS
*status
)
555 case HAL_CAP_DIAG
: /* hardware diagnostic support */
557 * NB: could split this up into virtual capabilities,
558 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
559 * seems worth the additional complexity.
562 AH_PRIVATE(ah
)->ah_diagreg
= setting
;
564 AH_PRIVATE(ah
)->ah_diagreg
= setting
& 0x6; /* ACK+CTS */
566 OS_REG_WRITE(ah
, AR_DIAG_SW
, AH_PRIVATE(ah
)->ah_diagreg
);
568 case HAL_CAP_RXORN_FATAL
: /* HAL_INT_RXORN treated as fatal */
569 return AH_FALSE
; /* NB: disallow */
571 return ath_hal_setcapability(ah
, type
, capability
,
577 ar5210GetDiagState(struct ath_hal
*ah
, int request
,
578 const void *args
, uint32_t argsize
,
579 void **result
, uint32_t *resultsize
)
581 #ifdef AH_PRIVATE_DIAG
586 case HAL_DIAG_EEPROM
:
589 case HAL_DIAG_EEREAD
:
590 if (argsize
!= sizeof(uint16_t))
592 pcicfg
= OS_REG_READ(ah
, AR_PCICFG
);
593 OS_REG_WRITE(ah
, AR_PCICFG
, pcicfg
| AR_PCICFG_EEPROMSEL
);
594 ok
= ath_hal_eepromRead(ah
, *(const uint16_t *)args
, *result
);
595 OS_REG_WRITE(ah
, AR_PCICFG
, pcicfg
);
597 *resultsize
= sizeof(uint16_t);
601 return ath_hal_getdiagstate(ah
, request
,
602 args
, argsize
, result
, resultsize
);
604 #endif /* AH_SUPPORT_AR5210 */