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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / e1000 / e1000_82540.c
blob8911835b590f64d9f88e0e78680b72dc2a59b26f
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82540EM Gigabit Ethernet Controller
31 * 82540EP Gigabit Ethernet Controller
32 * 82545EM Gigabit Ethernet Controller (Copper)
33 * 82545EM Gigabit Ethernet Controller (Fiber)
34 * 82545GM Gigabit Ethernet Controller
35 * 82546EB Gigabit Ethernet Controller (Copper)
36 * 82546EB Gigabit Ethernet Controller (Fiber)
37 * 82546GB Gigabit Ethernet Controller
38 */
39
40 #include "e1000_api.h"
41
42 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
45 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
46 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
47 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
48 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
49 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
50 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
51 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
52 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
53 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
54
55 /**
56 * e1000_init_phy_params_82540 - Init PHY func ptrs.
57 * @hw: pointer to the HW structure
58 **/
59 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
60 {
61 struct e1000_phy_info *phy = &hw->phy;
62 s32 ret_val = E1000_SUCCESS;
63
64 phy->addr = 1;
65 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
66 phy->reset_delay_us = 10000;
67 phy->type = e1000_phy_m88;
68
69 /* Function Pointers */
70 phy->ops.check_polarity = e1000_check_polarity_m88;
71 phy->ops.commit = e1000_phy_sw_reset_generic;
72 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
73 phy->ops.get_cable_length = e1000_get_cable_length_m88;
74 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
75 phy->ops.read_reg = e1000_read_phy_reg_m88;
76 phy->ops.reset = e1000_phy_hw_reset_generic;
77 phy->ops.write_reg = e1000_write_phy_reg_m88;
78 phy->ops.get_info = e1000_get_phy_info_m88;
79 phy->ops.power_up = e1000_power_up_phy_copper;
80 phy->ops.power_down = e1000_power_down_phy_copper_82540;
81
82 ret_val = e1000_get_phy_id(hw);
83 if (ret_val)
84 goto out;
85
86 /* Verify phy id */
87 switch (hw->mac.type) {
88 case e1000_82540:
89 case e1000_82545:
90 case e1000_82545_rev_3:
91 case e1000_82546:
92 case e1000_82546_rev_3:
93 if (phy->id == M88E1011_I_PHY_ID)
94 break;
95 /* Fall Through */
96 default:
97 ret_val = -E1000_ERR_PHY;
98 goto out;
99 break;
100 }
101
102 out:
103 return ret_val;
104 }
105
106 /**
107 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
108 * @hw: pointer to the HW structure
109 **/
110 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
111 {
112 struct e1000_nvm_info *nvm = &hw->nvm;
113 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
114
115 DEBUGFUNC("e1000_init_nvm_params_82540");
116
117 nvm->type = e1000_nvm_eeprom_microwire;
118 nvm->delay_usec = 50;
119 nvm->opcode_bits = 3;
120 switch (nvm->override) {
121 case e1000_nvm_override_microwire_large:
122 nvm->address_bits = 8;
123 nvm->word_size = 256;
124 break;
125 case e1000_nvm_override_microwire_small:
126 nvm->address_bits = 6;
127 nvm->word_size = 64;
128 break;
129 default:
130 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
131 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
132 break;
133 }
134
135 /* Function Pointers */
136 nvm->ops.acquire = e1000_acquire_nvm_generic;
137 nvm->ops.read = e1000_read_nvm_microwire;
138 nvm->ops.release = e1000_release_nvm_generic;
139 nvm->ops.update = e1000_update_nvm_checksum_generic;
140 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
141 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
142 nvm->ops.write = e1000_write_nvm_microwire;
143
144 return E1000_SUCCESS;
145 }
146
147 /**
148 * e1000_init_mac_params_82540 - Init MAC func ptrs.
149 * @hw: pointer to the HW structure
150 **/
151 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
152 {
153 struct e1000_mac_info *mac = &hw->mac;
154 s32 ret_val = E1000_SUCCESS;
155
156 DEBUGFUNC("e1000_init_mac_params_82540");
157
158 /* Set media type */
159 switch (hw->device_id) {
160 case E1000_DEV_ID_82545EM_FIBER:
161 case E1000_DEV_ID_82545GM_FIBER:
162 case E1000_DEV_ID_82546EB_FIBER:
163 case E1000_DEV_ID_82546GB_FIBER:
164 hw->phy.media_type = e1000_media_type_fiber;
165 break;
166 case E1000_DEV_ID_82545GM_SERDES:
167 case E1000_DEV_ID_82546GB_SERDES:
168 hw->phy.media_type = e1000_media_type_internal_serdes;
169 break;
170 default:
171 hw->phy.media_type = e1000_media_type_copper;
172 break;
173 }
174
175 /* Set mta register count */
176 mac->mta_reg_count = 128;
177 /* Set rar entry count */
178 mac->rar_entry_count = E1000_RAR_ENTRIES;
179
180 /* Function pointers */
181
182 /* bus type/speed/width */
183 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
184 /* function id */
185 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
186 /* reset */
187 mac->ops.reset_hw = e1000_reset_hw_82540;
188 /* hw initialization */
189 mac->ops.init_hw = e1000_init_hw_82540;
190 /* link setup */
191 mac->ops.setup_link = e1000_setup_link_generic;
192 /* physical interface setup */
193 mac->ops.setup_physical_interface =
194 (hw->phy.media_type == e1000_media_type_copper)
195 ? e1000_setup_copper_link_82540
196 : e1000_setup_fiber_serdes_link_82540;
197 /* check for link */
198 switch (hw->phy.media_type) {
199 case e1000_media_type_copper:
200 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
201 break;
202 case e1000_media_type_fiber:
203 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
204 break;
205 case e1000_media_type_internal_serdes:
206 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
207 break;
208 default:
209 ret_val = -E1000_ERR_CONFIG;
210 goto out;
211 break;
212 }
213 /* link info */
214 mac->ops.get_link_up_info =
215 (hw->phy.media_type == e1000_media_type_copper)
216 ? e1000_get_speed_and_duplex_copper_generic
217 : e1000_get_speed_and_duplex_fiber_serdes_generic;
218 /* multicast address update */
219 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
220 /* writing VFTA */
221 mac->ops.write_vfta = e1000_write_vfta_generic;
222 /* clearing VFTA */
223 mac->ops.clear_vfta = e1000_clear_vfta_generic;
224 /* setting MTA */
225 mac->ops.mta_set = e1000_mta_set_generic;
226 /* ID LED init */
227 mac->ops.id_led_init = e1000_id_led_init_generic;
228 /* setup LED */
229 mac->ops.setup_led = e1000_setup_led_generic;
230 /* cleanup LED */
231 mac->ops.cleanup_led = e1000_cleanup_led_generic;
232 /* turn on/off LED */
233 mac->ops.led_on = e1000_led_on_generic;
234 mac->ops.led_off = e1000_led_off_generic;
235 /* clear hardware counters */
236 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
237
238 out:
239 return ret_val;
240 }
241
242 /**
243 * e1000_init_function_pointers_82540 - Init func ptrs.
244 * @hw: pointer to the HW structure
245 *
246 * Called to initialize all function pointers and parameters.
247 **/
248 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
249 {
250 DEBUGFUNC("e1000_init_function_pointers_82540");
251
252 hw->mac.ops.init_params = e1000_init_mac_params_82540;
253 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
254 hw->phy.ops.init_params = e1000_init_phy_params_82540;
255 }
256
257 /**
258 * e1000_reset_hw_82540 - Reset hardware
259 * @hw: pointer to the HW structure
260 *
261 * This resets the hardware into a known state.
262 **/
263 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
264 {
265 u32 ctrl, manc;
266 s32 ret_val = E1000_SUCCESS;
267
268 DEBUGFUNC("e1000_reset_hw_82540");
269
270 DEBUGOUT("Masking off all interrupts\n");
271 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
272
273 E1000_WRITE_REG(hw, E1000_RCTL, 0);
274 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
275 E1000_WRITE_FLUSH(hw);
276
277 /*
278 * Delay to allow any outstanding PCI transactions to complete
279 * before resetting the device.
280 */
281 msec_delay(10);
282
283 ctrl = E1000_READ_REG(hw, E1000_CTRL);
284
285 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
286 switch (hw->mac.type) {
287 case e1000_82545_rev_3:
288 case e1000_82546_rev_3:
289 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
290 break;
291 default:
292 /*
293 * These controllers can't ack the 64-bit write when
294 * issuing the reset, so we use IO-mapping as a
295 * workaround to issue the reset.
296 */
297 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
298 break;
299 }
300
301 /* Wait for EEPROM reload */
302 msec_delay(5);
303
304 /* Disable HW ARPs on ASF enabled adapters */
305 manc = E1000_READ_REG(hw, E1000_MANC);
306 manc &= ~E1000_MANC_ARP_EN;
307 E1000_WRITE_REG(hw, E1000_MANC, manc);
308
309 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
310 E1000_READ_REG(hw, E1000_ICR);
311
312 return ret_val;
313 }
314
315 /**
316 * e1000_init_hw_82540 - Initialize hardware
317 * @hw: pointer to the HW structure
318 *
319 * This inits the hardware readying it for operation.
320 **/
321 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
322 {
323 struct e1000_mac_info *mac = &hw->mac;
324 u32 txdctl, ctrl_ext;
325 s32 ret_val = E1000_SUCCESS;
326 u16 i;
327
328 DEBUGFUNC("e1000_init_hw_82540");
329
330 /* Initialize identification LED */
331 ret_val = mac->ops.id_led_init(hw);
332 if (ret_val) {
333 DEBUGOUT("Error initializing identification LED\n");
334 /* This is not fatal and we should not stop init due to this */
335 }
336
337 /* Disabling VLAN filtering */
338 DEBUGOUT("Initializing the IEEE VLAN\n");
339 if (mac->type < e1000_82545_rev_3)
340 E1000_WRITE_REG(hw, E1000_VET, 0);
341
342 mac->ops.clear_vfta(hw);
343
344 /* Setup the receive address. */
345 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
346
347 /* Zero out the Multicast HASH table */
348 DEBUGOUT("Zeroing the MTA\n");
349 for (i = 0; i < mac->mta_reg_count; i++) {
350 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
351 /*
352 * Avoid back to back register writes by adding the register
353 * read (flush). This is to protect against some strange
354 * bridge configurations that may issue Memory Write Block
355 * (MWB) to our register space. The *_rev_3 hardware at
356 * least doesn't respond correctly to every other dword in an
357 * MWB to our register space.
358 */
359 E1000_WRITE_FLUSH(hw);
360 }
361
362 if (mac->type < e1000_82545_rev_3)
363 e1000_pcix_mmrbc_workaround_generic(hw);
364
365 /* Setup link and flow control */
366 ret_val = mac->ops.setup_link(hw);
367
368 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
369 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
370 E1000_TXDCTL_FULL_TX_DESC_WB;
371 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
372
373 /*
374 * Clear all of the statistics registers (clear on read). It is
375 * important that we do this after we have tried to establish link
376 * because the symbol error count will increment wildly if there
377 * is no link.
378 */
379 e1000_clear_hw_cntrs_82540(hw);
380
381 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
382 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
383 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
384 /*
385 * Relaxed ordering must be disabled to avoid a parity
386 * error crash in a PCI slot.
387 */
388 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
389 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
390 }
391
392 return ret_val;
393 }
394
395 /**
396 * e1000_setup_copper_link_82540 - Configure copper link settings
397 * @hw: pointer to the HW structure
398 *
399 * Calls the appropriate function to configure the link for auto-neg or forced
400 * speed and duplex. Then we check for link, once link is established calls
401 * to configure collision distance and flow control are called. If link is
402 * not established, we return -E1000_ERR_PHY (-2).
403 **/
404 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
405 {
406 u32 ctrl;
407 s32 ret_val = E1000_SUCCESS;
408 u16 data;
409
410 DEBUGFUNC("e1000_setup_copper_link_82540");
411
412 ctrl = E1000_READ_REG(hw, E1000_CTRL);
413 ctrl |= E1000_CTRL_SLU;
414 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
415 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
416
417 ret_val = e1000_set_phy_mode_82540(hw);
418 if (ret_val)
419 goto out;
420
421 if (hw->mac.type == e1000_82545_rev_3 ||
422 hw->mac.type == e1000_82546_rev_3) {
423 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
424 if (ret_val)
425 goto out;
426 data |= 0x00000008;
427 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
428 if (ret_val)
429 goto out;
430 }
431
432 ret_val = e1000_copper_link_setup_m88(hw);
433 if (ret_val)
434 goto out;
435
436 ret_val = e1000_setup_copper_link_generic(hw);
437
438 out:
439 return ret_val;
440 }
441
442 /**
443 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
444 * @hw: pointer to the HW structure
445 *
446 * Set the output amplitude to the value in the EEPROM and adjust the VCO
447 * speed to improve Bit Error Rate (BER) performance. Configures collision
448 * distance and flow control for fiber and serdes links. Upon successful
449 * setup, poll for link.
450 **/
451 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
452 {
453 struct e1000_mac_info *mac = &hw->mac;
454 s32 ret_val = E1000_SUCCESS;
455
456 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
457
458 switch (mac->type) {
459 case e1000_82545_rev_3:
460 case e1000_82546_rev_3:
461 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
462 /*
463 * If we're on serdes media, adjust the output
464 * amplitude to value set in the EEPROM.
465 */
466 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
467 if (ret_val)
468 goto out;
469 }
470 /* Adjust VCO speed to improve BER performance */
471 ret_val = e1000_set_vco_speed_82540(hw);
472 if (ret_val)
473 goto out;
474 default:
475 break;
476 }
477
478 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
479
480 out:
481 return ret_val;
482 }
483
484 /**
485 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
486 * @hw: pointer to the HW structure
487 *
488 * Adjust the SERDES output amplitude based on the EEPROM settings.
489 **/
490 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
491 {
492 s32 ret_val = E1000_SUCCESS;
493 u16 nvm_data;
494
495 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
496
497 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
498 if (ret_val)
499 goto out;
500
501 if (nvm_data != NVM_RESERVED_WORD) {
502 /* Adjust serdes output amplitude only. */
503 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
504 ret_val = hw->phy.ops.write_reg(hw,
505 M88E1000_PHY_EXT_CTRL,
506 nvm_data);
507 if (ret_val)
508 goto out;
509 }
510
511 out:
512 return ret_val;
513 }
514
515 /**
516 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
517 * @hw: pointer to the HW structure
518 *
519 * Set the VCO speed to improve Bit Error Rate (BER) performance.
520 **/
521 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
522 {
523 s32 ret_val = E1000_SUCCESS;
524 u16 default_page = 0;
525 u16 phy_data;
526
527 DEBUGFUNC("e1000_set_vco_speed_82540");
528
529 /* Set PHY register 30, page 5, bit 8 to 0 */
530
531 ret_val = hw->phy.ops.read_reg(hw,
532 M88E1000_PHY_PAGE_SELECT,
533 &default_page);
534 if (ret_val)
535 goto out;
536
537 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
538 if (ret_val)
539 goto out;
540
541 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
542 if (ret_val)
543 goto out;
544
545 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
546 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
547 if (ret_val)
548 goto out;
549
550 /* Set PHY register 30, page 4, bit 11 to 1 */
551
552 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
553 if (ret_val)
554 goto out;
555
556 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
557 if (ret_val)
558 goto out;
559
560 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
561 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
562 if (ret_val)
563 goto out;
564
565 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
566 default_page);
567
568 out:
569 return ret_val;
570 }
571
572 /**
573 * e1000_set_phy_mode_82540 - Set PHY to class A mode
574 * @hw: pointer to the HW structure
575 *
576 * Sets the PHY to class A mode and assumes the following operations will
577 * follow to enable the new class mode:
578 * 1. Do a PHY soft reset.
579 * 2. Restart auto-negotiation or force link.
580 **/
581 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
582 {
583 struct e1000_phy_info *phy = &hw->phy;
584 s32 ret_val = E1000_SUCCESS;
585 u16 nvm_data;
586
587 DEBUGFUNC("e1000_set_phy_mode_82540");
588
589 if (hw->mac.type != e1000_82545_rev_3)
590 goto out;
591
592 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
593 if (ret_val) {
594 ret_val = -E1000_ERR_PHY;
595 goto out;
596 }
597
598 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
599 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
600 0x000B);
601 if (ret_val) {
602 ret_val = -E1000_ERR_PHY;
603 goto out;
604 }
605 ret_val = hw->phy.ops.write_reg(hw,
606 M88E1000_PHY_GEN_CONTROL,
607 0x8104);
608 if (ret_val) {
609 ret_val = -E1000_ERR_PHY;
610 goto out;
611 }
612
613 phy->reset_disable = false;
614 }
615
616 out:
617 return ret_val;
618 }
619
620 /**
621 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
622 * @hw: pointer to the HW structure
623 *
624 * In the case of a PHY power down to save power, or to turn off link during a
625 * driver unload, or wake on lan is not enabled, remove the link.
626 **/
627 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
628 {
629 /* If the management interface is not enabled, then power down */
630 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
631 e1000_power_down_phy_copper(hw);
632
633 return;
634 }
635
636 /**
637 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
638 * @hw: pointer to the HW structure
639 *
640 * Clears the hardware counters by reading the counter registers.
641 **/
642 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
643 {
644 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
645
646 e1000_clear_hw_cntrs_base_generic(hw);
647
648 E1000_READ_REG(hw, E1000_PRC64);
649 E1000_READ_REG(hw, E1000_PRC127);
650 E1000_READ_REG(hw, E1000_PRC255);
651 E1000_READ_REG(hw, E1000_PRC511);
652 E1000_READ_REG(hw, E1000_PRC1023);
653 E1000_READ_REG(hw, E1000_PRC1522);
654 E1000_READ_REG(hw, E1000_PTC64);
655 E1000_READ_REG(hw, E1000_PTC127);
656 E1000_READ_REG(hw, E1000_PTC255);
657 E1000_READ_REG(hw, E1000_PTC511);
658 E1000_READ_REG(hw, E1000_PTC1023);
659 E1000_READ_REG(hw, E1000_PTC1522);
660
661 E1000_READ_REG(hw, E1000_ALGNERRC);
662 E1000_READ_REG(hw, E1000_RXERRC);
663 E1000_READ_REG(hw, E1000_TNCRS);
664 E1000_READ_REG(hw, E1000_CEXTERR);
665 E1000_READ_REG(hw, E1000_TSCTC);
666 E1000_READ_REG(hw, E1000_TSCTFC);
667
668 E1000_READ_REG(hw, E1000_MGTPRC);
669 E1000_READ_REG(hw, E1000_MGTPDC);
670 E1000_READ_REG(hw, E1000_MGTPTC);
671 }
672
Mirror of AROS' svn.