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Check for SYS/GL during library init. Reason is that
[AROS.git] / workbench / devs / networks / e1000 / e1000_82541.c
blobf05eecf8b6f1e259d29c44c0204ddc02468f5610
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82541EI Gigabit Ethernet Controller
31 * 82541ER Gigabit Ethernet Controller
32 * 82541GI Gigabit Ethernet Controller
33 * 82541PI Gigabit Ethernet Controller
34 * 82547EI Gigabit Ethernet Controller
35 * 82547GI Gigabit Ethernet Controller
36 */
37
38 #include "e1000_api.h"
39
40 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
41 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
42 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
43 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
44 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
45 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
46 u16 *duplex);
47 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
48 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
49 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
50 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
51 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
52 bool active);
53 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
54 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
55 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
56 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
57 bool link_up);
58 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
60
61 static const u16 e1000_igp_cable_length_table[] =
62 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
63 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
64 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
65 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
66 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
67 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
68 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
69 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
70 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
71 (sizeof(e1000_igp_cable_length_table) / \
72 sizeof(e1000_igp_cable_length_table[0]))
73
74 /**
75 * e1000_init_phy_params_82541 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
77 **/
78 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
79 {
80 struct e1000_phy_info *phy = &hw->phy;
81 s32 ret_val = E1000_SUCCESS;
82
83 DEBUGFUNC("e1000_init_phy_params_82541");
84
85 phy->addr = 1;
86 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
87 phy->reset_delay_us = 10000;
88 phy->type = e1000_phy_igp;
89
90 /* Function Pointers */
91 phy->ops.check_polarity = e1000_check_polarity_igp;
92 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
93 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
94 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
95 phy->ops.get_info = e1000_get_phy_info_igp;
96 phy->ops.read_reg = e1000_read_phy_reg_igp;
97 phy->ops.reset = e1000_phy_hw_reset_82541;
98 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
99 phy->ops.write_reg = e1000_write_phy_reg_igp;
100 phy->ops.power_up = e1000_power_up_phy_copper;
101 phy->ops.power_down = e1000_power_down_phy_copper_82541;
102
103 ret_val = e1000_get_phy_id(hw);
104 if (ret_val)
105 goto out;
106
107 /* Verify phy id */
108 if (phy->id != IGP01E1000_I_PHY_ID) {
109 ret_val = -E1000_ERR_PHY;
110 goto out;
111 }
112
113 out:
114 return ret_val;
115 }
116
117 /**
118 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
119 * @hw: pointer to the HW structure
120 **/
121 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
122 {
123 struct e1000_nvm_info *nvm = &hw->nvm;
124 s32 ret_val = E1000_SUCCESS;
125 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
126 u16 size;
127
128 DEBUGFUNC("e1000_init_nvm_params_82541");
129
130 switch (nvm->override) {
131 case e1000_nvm_override_spi_large:
132 nvm->type = e1000_nvm_eeprom_spi;
133 eecd |= E1000_EECD_ADDR_BITS;
134 break;
135 case e1000_nvm_override_spi_small:
136 nvm->type = e1000_nvm_eeprom_spi;
137 eecd &= ~E1000_EECD_ADDR_BITS;
138 break;
139 case e1000_nvm_override_microwire_large:
140 nvm->type = e1000_nvm_eeprom_microwire;
141 eecd |= E1000_EECD_SIZE;
142 break;
143 case e1000_nvm_override_microwire_small:
144 nvm->type = e1000_nvm_eeprom_microwire;
145 eecd &= ~E1000_EECD_SIZE;
146 break;
147 default:
148 nvm->type = eecd & E1000_EECD_TYPE
149 ? e1000_nvm_eeprom_spi
150 : e1000_nvm_eeprom_microwire;
151 break;
152 }
153
154 if (nvm->type == e1000_nvm_eeprom_spi) {
155 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
156 ? 16 : 8;
157 nvm->delay_usec = 1;
158 nvm->opcode_bits = 8;
159 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
160 ? 32 : 8;
161
162 /* Function Pointers */
163 nvm->ops.acquire = e1000_acquire_nvm_generic;
164 nvm->ops.read = e1000_read_nvm_spi;
165 nvm->ops.release = e1000_release_nvm_generic;
166 nvm->ops.update = e1000_update_nvm_checksum_generic;
167 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
168 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
169 nvm->ops.write = e1000_write_nvm_spi;
170
171 /*
172 * nvm->word_size must be discovered after the pointers
173 * are set so we can verify the size from the nvm image
174 * itself. Temporarily set it to a dummy value so the
175 * read will work.
176 */
177 nvm->word_size = 64;
178 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
179 if (ret_val)
180 goto out;
181 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
182 /*
183 * if size != 0, it can be added to a constant and become
184 * the left-shift value to set the word_size. Otherwise,
185 * word_size stays at 64.
186 */
187 if (size) {
188 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
189 nvm->word_size = 1 << size;
190 }
191 } else {
192 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
193 ? 8 : 6;
194 nvm->delay_usec = 50;
195 nvm->opcode_bits = 3;
196 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
197 ? 256 : 64;
198
199 /* Function Pointers */
200 nvm->ops.acquire = e1000_acquire_nvm_generic;
201 nvm->ops.read = e1000_read_nvm_microwire;
202 nvm->ops.release = e1000_release_nvm_generic;
203 nvm->ops.update = e1000_update_nvm_checksum_generic;
204 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
205 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
206 nvm->ops.write = e1000_write_nvm_microwire;
207 }
208
209 out:
210 return ret_val;
211 }
212
213 /**
214 * e1000_init_mac_params_82541 - Init MAC func ptrs.
215 * @hw: pointer to the HW structure
216 **/
217 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
218 {
219 struct e1000_mac_info *mac = &hw->mac;
220
221 DEBUGFUNC("e1000_init_mac_params_82541");
222
223 /* Set media type */
224 hw->phy.media_type = e1000_media_type_copper;
225 /* Set mta register count */
226 mac->mta_reg_count = 128;
227 /* Set rar entry count */
228 mac->rar_entry_count = E1000_RAR_ENTRIES;
229 /* Set if part includes ASF firmware */
230 mac->asf_firmware_present = true;
231
232 /* Function Pointers */
233
234 /* bus type/speed/width */
235 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
236 /* function id */
237 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
238 /* reset */
239 mac->ops.reset_hw = e1000_reset_hw_82541;
240 /* hw initialization */
241 mac->ops.init_hw = e1000_init_hw_82541;
242 /* link setup */
243 mac->ops.setup_link = e1000_setup_link_generic;
244 /* physical interface link setup */
245 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
246 /* check for link */
247 mac->ops.check_for_link = e1000_check_for_link_82541;
248 /* link info */
249 mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
250 /* multicast address update */
251 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
252 /* writing VFTA */
253 mac->ops.write_vfta = e1000_write_vfta_generic;
254 /* clearing VFTA */
255 mac->ops.clear_vfta = e1000_clear_vfta_generic;
256 /* setting MTA */
257 mac->ops.mta_set = e1000_mta_set_generic;
258 /* ID LED init */
259 mac->ops.id_led_init = e1000_id_led_init_generic;
260 /* setup LED */
261 mac->ops.setup_led = e1000_setup_led_82541;
262 /* cleanup LED */
263 mac->ops.cleanup_led = e1000_cleanup_led_82541;
264 /* turn on/off LED */
265 mac->ops.led_on = e1000_led_on_generic;
266 mac->ops.led_off = e1000_led_off_generic;
267 /* clear hardware counters */
268 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
269
270 return E1000_SUCCESS;
271 }
272
273 /**
274 * e1000_init_function_pointers_82541 - Init func ptrs.
275 * @hw: pointer to the HW structure
276 *
277 * Called to initialize all function pointers and parameters.
278 **/
279 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
280 {
281 DEBUGFUNC("e1000_init_function_pointers_82541");
282
283 hw->mac.ops.init_params = e1000_init_mac_params_82541;
284 hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
285 hw->phy.ops.init_params = e1000_init_phy_params_82541;
286 }
287
288 /**
289 * e1000_reset_hw_82541 - Reset hardware
290 * @hw: pointer to the HW structure
291 *
292 * This resets the hardware into a known state.
293 **/
294 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
295 {
296 u32 ledctl, ctrl, manc;
297
298 DEBUGFUNC("e1000_reset_hw_82541");
299
300 DEBUGOUT("Masking off all interrupts\n");
301 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
302
303 E1000_WRITE_REG(hw, E1000_RCTL, 0);
304 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
305 E1000_WRITE_FLUSH(hw);
306
307 /*
308 * Delay to allow any outstanding PCI transactions to complete
309 * before resetting the device.
310 */
311 msec_delay(10);
312
313 ctrl = E1000_READ_REG(hw, E1000_CTRL);
314
315 /* Must reset the Phy before resetting the MAC */
316 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
317 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
318 msec_delay(5);
319 }
320
321 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
322 switch (hw->mac.type) {
323 case e1000_82541:
324 case e1000_82541_rev_2:
325 /*
326 * These controllers can't ack the 64-bit write when
327 * issuing the reset, so we use IO-mapping as a
328 * workaround to issue the reset.
329 */
330 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
331 break;
332 default:
333 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
334 break;
335 }
336
337 /* Wait for NVM reload */
338 msec_delay(20);
339
340 /* Disable HW ARPs on ASF enabled adapters */
341 manc = E1000_READ_REG(hw, E1000_MANC);
342 manc &= ~E1000_MANC_ARP_EN;
343 E1000_WRITE_REG(hw, E1000_MANC, manc);
344
345 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
346 e1000_phy_init_script_82541(hw);
347
348 /* Configure activity LED after Phy reset */
349 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
350 ledctl &= IGP_ACTIVITY_LED_MASK;
351 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
352 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
353 }
354
355 /* Once again, mask the interrupts */
356 DEBUGOUT("Masking off all interrupts\n");
357 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
358
359 /* Clear any pending interrupt events. */
360 E1000_READ_REG(hw, E1000_ICR);
361
362 return E1000_SUCCESS;
363 }
364
365 /**
366 * e1000_init_hw_82541 - Initialize hardware
367 * @hw: pointer to the HW structure
368 *
369 * This inits the hardware readying it for operation.
370 **/
371 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
372 {
373 struct e1000_mac_info *mac = &hw->mac;
374 u32 i, txdctl;
375 s32 ret_val;
376
377 DEBUGFUNC("e1000_init_hw_82541");
378
379 /* Initialize identification LED */
380 ret_val = mac->ops.id_led_init(hw);
381 if (ret_val) {
382 DEBUGOUT("Error initializing identification LED\n");
383 /* This is not fatal and we should not stop init due to this */
384 }
385
386 /* Disabling VLAN filtering */
387 DEBUGOUT("Initializing the IEEE VLAN\n");
388 mac->ops.clear_vfta(hw);
389
390 /* Setup the receive address. */
391 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
392
393 /* Zero out the Multicast HASH table */
394 DEBUGOUT("Zeroing the MTA\n");
395 for (i = 0; i < mac->mta_reg_count; i++) {
396 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
397 /*
398 * Avoid back to back register writes by adding the register
399 * read (flush). This is to protect against some strange
400 * bridge configurations that may issue Memory Write Block
401 * (MWB) to our register space.
402 */
403 E1000_WRITE_FLUSH(hw);
404 }
405
406 /* Setup link and flow control */
407 ret_val = mac->ops.setup_link(hw);
408
409 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
410 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
411 E1000_TXDCTL_FULL_TX_DESC_WB;
412 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
413
414 /*
415 * Clear all of the statistics registers (clear on read). It is
416 * important that we do this after we have tried to establish link
417 * because the symbol error count will increment wildly if there
418 * is no link.
419 */
420 e1000_clear_hw_cntrs_82541(hw);
421
422 return ret_val;
423 }
424
425 /**
426 * e1000_get_link_up_info_82541 - Report speed and duplex
427 * @hw: pointer to the HW structure
428 * @speed: pointer to speed buffer
429 * @duplex: pointer to duplex buffer
430 *
431 * Retrieve the current speed and duplex configuration.
432 **/
433 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
434 u16 *duplex)
435 {
436 struct e1000_phy_info *phy = &hw->phy;
437 s32 ret_val;
438 u16 data;
439
440 DEBUGFUNC("e1000_get_link_up_info_82541");
441
442 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
443 if (ret_val)
444 goto out;
445
446 if (!phy->speed_downgraded)
447 goto out;
448
449 /*
450 * IGP01 PHY may advertise full duplex operation after speed
451 * downgrade even if it is operating at half duplex.
452 * Here we set the duplex settings to match the duplex in the
453 * link partner's capabilities.
454 */
455 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
456 if (ret_val)
457 goto out;
458
459 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
460 *duplex = HALF_DUPLEX;
461 } else {
462 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
463 if (ret_val)
464 goto out;
465
466 if (*speed == SPEED_100) {
467 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
468 *duplex = HALF_DUPLEX;
469 } else if (*speed == SPEED_10) {
470 if (!(data & NWAY_LPAR_10T_FD_CAPS))
471 *duplex = HALF_DUPLEX;
472 }
473 }
474
475 out:
476 return ret_val;
477 }
478
479 /**
480 * e1000_phy_hw_reset_82541 - PHY hardware reset
481 * @hw: pointer to the HW structure
482 *
483 * Verify the reset block is not blocking us from resetting. Acquire
484 * semaphore (if necessary) and read/set/write the device control reset
485 * bit in the PHY. Wait the appropriate delay time for the device to
486 * reset and release the semaphore (if necessary).
487 **/
488 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
489 {
490 s32 ret_val;
491 u32 ledctl;
492
493 DEBUGFUNC("e1000_phy_hw_reset_82541");
494
495 ret_val = e1000_phy_hw_reset_generic(hw);
496 if (ret_val)
497 goto out;
498
499 e1000_phy_init_script_82541(hw);
500
501 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
502 /* Configure activity LED after PHY reset */
503 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
504 ledctl &= IGP_ACTIVITY_LED_MASK;
505 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
506 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
507 }
508
509 out:
510 return ret_val;
511 }
512
513 /**
514 * e1000_setup_copper_link_82541 - Configure copper link settings
515 * @hw: pointer to the HW structure
516 *
517 * Calls the appropriate function to configure the link for auto-neg or forced
518 * speed and duplex. Then we check for link, once link is established calls
519 * to configure collision distance and flow control are called. If link is
520 * not established, we return -E1000_ERR_PHY (-2).
521 **/
522 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
523 {
524 struct e1000_phy_info *phy = &hw->phy;
525 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
526 s32 ret_val;
527 u32 ctrl, ledctl;
528
529 DEBUGFUNC("e1000_setup_copper_link_82541");
530
531 ctrl = E1000_READ_REG(hw, E1000_CTRL);
532 ctrl |= E1000_CTRL_SLU;
533 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
534 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
535
536 hw->phy.reset_disable = false;
537
538 /* Earlier revs of the IGP phy require us to force MDI. */
539 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
540 dev_spec->dsp_config = e1000_dsp_config_disabled;
541 phy->mdix = 1;
542 } else {
543 dev_spec->dsp_config = e1000_dsp_config_enabled;
544 }
545
546 ret_val = e1000_copper_link_setup_igp(hw);
547 if (ret_val)
548 goto out;
549
550 if (hw->mac.autoneg) {
551 if (dev_spec->ffe_config == e1000_ffe_config_active)
552 dev_spec->ffe_config = e1000_ffe_config_enabled;
553 }
554
555 /* Configure activity LED after Phy reset */
556 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
557 ledctl &= IGP_ACTIVITY_LED_MASK;
558 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
559 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
560
561 ret_val = e1000_setup_copper_link_generic(hw);
562
563 out:
564 return ret_val;
565 }
566
567 /**
568 * e1000_check_for_link_82541 - Check/Store link connection
569 * @hw: pointer to the HW structure
570 *
571 * This checks the link condition of the adapter and stores the
572 * results in the hw->mac structure.
573 **/
574 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
575 {
576 struct e1000_mac_info *mac = &hw->mac;
577 s32 ret_val;
578 bool link;
579
580 DEBUGFUNC("e1000_check_for_link_82541");
581
582 /*
583 * We only want to go out to the PHY registers to see if Auto-Neg
584 * has completed and/or if our link status has changed. The
585 * get_link_status flag is set upon receiving a Link Status
586 * Change or Rx Sequence Error interrupt.
587 */
588 if (!mac->get_link_status) {
589 ret_val = E1000_SUCCESS;
590 goto out;
591 }
592
593 /*
594 * First we want to see if the MII Status Register reports
595 * link. If so, then we want to get the current speed/duplex
596 * of the PHY.
597 */
598 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
599 if (ret_val)
600 goto out;
601
602 if (!link) {
603 ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
604 goto out; /* No link detected */
605 }
606
607 mac->get_link_status = false;
608
609 /*
610 * Check if there was DownShift, must be checked
611 * immediately after link-up
612 */
613 e1000_check_downshift_generic(hw);
614
615 /*
616 * If we are forcing speed/duplex, then we simply return since
617 * we have already determined whether we have link or not.
618 */
619 if (!mac->autoneg) {
620 ret_val = -E1000_ERR_CONFIG;
621 goto out;
622 }
623
624 ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
625
626 /*
627 * Auto-Neg is enabled. Auto Speed Detection takes care
628 * of MAC speed/duplex configuration. So we only need to
629 * configure Collision Distance in the MAC.
630 */
631 e1000_config_collision_dist_generic(hw);
632
633 /*
634 * Configure Flow Control now that Auto-Neg has completed.
635 * First, we need to restore the desired flow control
636 * settings because we may have had to re-autoneg with a
637 * different link partner.
638 */
639 ret_val = e1000_config_fc_after_link_up_generic(hw);
640 if (ret_val) {
641 DEBUGOUT("Error configuring flow control\n");
642 }
643
644 out:
645 return ret_val;
646 }
647
648 /**
649 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
650 * @hw: pointer to the HW structure
651 * @link_up: boolean flag for link up status
652 *
653 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
654 * at any other case.
655 *
656 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
657 * gigabit link is achieved to improve link quality.
658 **/
659 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
660 bool link_up)
661 {
662 struct e1000_phy_info *phy = &hw->phy;
663 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
664 s32 ret_val;
665 u32 idle_errs = 0;
666 u16 phy_data, phy_saved_data, speed, duplex, i;
667 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
668 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
669 {IGP01E1000_PHY_AGC_PARAM_A,
670 IGP01E1000_PHY_AGC_PARAM_B,
671 IGP01E1000_PHY_AGC_PARAM_C,
672 IGP01E1000_PHY_AGC_PARAM_D};
673
674 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
675
676 if (link_up) {
677 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
678 if (ret_val) {
679 DEBUGOUT("Error getting link speed and duplex\n");
680 goto out;
681 }
682
683 if (speed != SPEED_1000) {
684 ret_val = E1000_SUCCESS;
685 goto out;
686 }
687
688 ret_val = phy->ops.get_cable_length(hw);
689 if (ret_val)
690 goto out;
691
692 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
693 phy->min_cable_length >= 50) {
694
695 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
696 ret_val = phy->ops.read_reg(hw,
697 dsp_reg_array[i],
698 &phy_data);
699 if (ret_val)
700 goto out;
701
702 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
703
704 ret_val = phy->ops.write_reg(hw,
705 dsp_reg_array[i],
706 phy_data);
707 if (ret_val)
708 goto out;
709 }
710 dev_spec->dsp_config = e1000_dsp_config_activated;
711 }
712
713 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
714 (phy->min_cable_length >= 50)) {
715 ret_val = E1000_SUCCESS;
716 goto out;
717 }
718
719 /* clear previous idle error counts */
720 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
721 if (ret_val)
722 goto out;
723
724 for (i = 0; i < ffe_idle_err_timeout; i++) {
725 usec_delay(1000);
726 ret_val = phy->ops.read_reg(hw,
727 PHY_1000T_STATUS,
728 &phy_data);
729 if (ret_val)
730 goto out;
731
732 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
733 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
734 dev_spec->ffe_config = e1000_ffe_config_active;
735
736 ret_val = phy->ops.write_reg(hw,
737 IGP01E1000_PHY_DSP_FFE,
738 IGP01E1000_PHY_DSP_FFE_CM_CP);
739 if (ret_val)
740 goto out;
741 break;
742 }
743
744 if (idle_errs)
745 ffe_idle_err_timeout =
746 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
747 }
748 } else {
749 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
750 /*
751 * Save off the current value of register 0x2F5B
752 * to be restored at the end of the routines.
753 */
754 ret_val = phy->ops.read_reg(hw,
755 0x2F5B,
756 &phy_saved_data);
757 if (ret_val)
758 goto out;
759
760 /* Disable the PHY transmitter */
761 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
762 if (ret_val)
763 goto out;
764
765 msec_delay_irq(20);
766
767 ret_val = phy->ops.write_reg(hw,
768 0x0000,
769 IGP01E1000_IEEE_FORCE_GIG);
770 if (ret_val)
771 goto out;
772 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
773 ret_val = phy->ops.read_reg(hw,
774 dsp_reg_array[i],
775 &phy_data);
776 if (ret_val)
777 goto out;
778
779 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
780 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
781
782 ret_val = phy->ops.write_reg(hw,
783 dsp_reg_array[i],
784 phy_data);
785 if (ret_val)
786 goto out;
787 }
788
789 ret_val = phy->ops.write_reg(hw,
790 0x0000,
791 IGP01E1000_IEEE_RESTART_AUTONEG);
792 if (ret_val)
793 goto out;
794
795 msec_delay_irq(20);
796
797 /* Now enable the transmitter */
798 ret_val = phy->ops.write_reg(hw,
799 0x2F5B,
800 phy_saved_data);
801 if (ret_val)
802 goto out;
803
804 dev_spec->dsp_config = e1000_dsp_config_enabled;
805 }
806
807 if (dev_spec->ffe_config != e1000_ffe_config_active) {
808 ret_val = E1000_SUCCESS;
809 goto out;
810 }
811
812 /*
813 * Save off the current value of register 0x2F5B
814 * to be restored at the end of the routines.
815 */
816 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
817 if (ret_val)
818 goto out;
819
820 /* Disable the PHY transmitter */
821 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
822 if (ret_val)
823 goto out;
824
825 msec_delay_irq(20);
826
827 ret_val = phy->ops.write_reg(hw,
828 0x0000,
829 IGP01E1000_IEEE_FORCE_GIG);
830 if (ret_val)
831 goto out;
832
833 ret_val = phy->ops.write_reg(hw,
834 IGP01E1000_PHY_DSP_FFE,
835 IGP01E1000_PHY_DSP_FFE_DEFAULT);
836 if (ret_val)
837 goto out;
838
839 ret_val = phy->ops.write_reg(hw,
840 0x0000,
841 IGP01E1000_IEEE_RESTART_AUTONEG);
842 if (ret_val)
843 goto out;
844
845 msec_delay_irq(20);
846
847 /* Now enable the transmitter */
848 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
849
850 if (ret_val)
851 goto out;
852
853 dev_spec->ffe_config = e1000_ffe_config_enabled;
854 }
855
856 out:
857 return ret_val;
858 }
859
860 /**
861 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
862 * @hw: pointer to the HW structure
863 *
864 * The automatic gain control (agc) normalizes the amplitude of the
865 * received signal, adjusting for the attenuation produced by the
866 * cable. By reading the AGC registers, which represent the
867 * combination of coarse and fine gain value, the value can be put
868 * into a lookup table to obtain the approximate cable length
869 * for each channel.
870 **/
871 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
872 {
873 struct e1000_phy_info *phy = &hw->phy;
874 s32 ret_val = E1000_SUCCESS;
875 u16 i, data;
876 u16 cur_agc_value, agc_value = 0;
877 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
878 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
879 {IGP01E1000_PHY_AGC_A,
880 IGP01E1000_PHY_AGC_B,
881 IGP01E1000_PHY_AGC_C,
882 IGP01E1000_PHY_AGC_D};
883
884 DEBUGFUNC("e1000_get_cable_length_igp_82541");
885
886 /* Read the AGC registers for all channels */
887 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
888 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
889 if (ret_val)
890 goto out;
891
892 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
893
894 /* Bounds checking */
895 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
896 (cur_agc_value == 0)) {
897 ret_val = -E1000_ERR_PHY;
898 goto out;
899 }
900
901 agc_value += cur_agc_value;
902
903 if (min_agc_value > cur_agc_value)
904 min_agc_value = cur_agc_value;
905 }
906
907 /* Remove the minimal AGC result for length < 50m */
908 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
909 agc_value -= min_agc_value;
910 /* Average the three remaining channels for the length. */
911 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
912 } else {
913 /* Average the channels for the length. */
914 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
915 }
916
917 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
918 IGP01E1000_AGC_RANGE)
919 ? (e1000_igp_cable_length_table[agc_value] -
920 IGP01E1000_AGC_RANGE)
921 : 0;
922 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
923 IGP01E1000_AGC_RANGE;
924
925 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
926
927 out:
928 return ret_val;
929 }
930
931 /**
932 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
933 * @hw: pointer to the HW structure
934 * @active: boolean used to enable/disable lplu
935 *
936 * Success returns 0, Failure returns 1
937 *
938 * The low power link up (lplu) state is set to the power management level D3
939 * and SmartSpeed is disabled when active is true, else clear lplu for D3
940 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
941 * is used during Dx states where the power conservation is most important.
942 * During driver activity, SmartSpeed should be enabled so performance is
943 * maintained.
944 **/
945 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
946 {
947 struct e1000_phy_info *phy = &hw->phy;
948 s32 ret_val;
949 u16 data;
950
951 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
952
953 switch (hw->mac.type) {
954 case e1000_82541_rev_2:
955 case e1000_82547_rev_2:
956 break;
957 default:
958 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
959 goto out;
960 break;
961 }
962
963 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
964 if (ret_val)
965 goto out;
966
967 if (!active) {
968 data &= ~IGP01E1000_GMII_FLEX_SPD;
969 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
970 if (ret_val)
971 goto out;
972
973 /*
974 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
975 * during Dx states where the power conservation is most
976 * important. During driver activity we should enable
977 * SmartSpeed, so performance is maintained.
978 */
979 if (phy->smart_speed == e1000_smart_speed_on) {
980 ret_val = phy->ops.read_reg(hw,
981 IGP01E1000_PHY_PORT_CONFIG,
982 &data);
983 if (ret_val)
984 goto out;
985
986 data |= IGP01E1000_PSCFR_SMART_SPEED;
987 ret_val = phy->ops.write_reg(hw,
988 IGP01E1000_PHY_PORT_CONFIG,
989 data);
990 if (ret_val)
991 goto out;
992 } else if (phy->smart_speed == e1000_smart_speed_off) {
993 ret_val = phy->ops.read_reg(hw,
994 IGP01E1000_PHY_PORT_CONFIG,
995 &data);
996 if (ret_val)
997 goto out;
998
999 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1000 ret_val = phy->ops.write_reg(hw,
1001 IGP01E1000_PHY_PORT_CONFIG,
1002 data);
1003 if (ret_val)
1004 goto out;
1005 }
1006 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1007 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1008 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1009 data |= IGP01E1000_GMII_FLEX_SPD;
1010 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1011 if (ret_val)
1012 goto out;
1013
1014 /* When LPLU is enabled, we should disable SmartSpeed */
1015 ret_val = phy->ops.read_reg(hw,
1016 IGP01E1000_PHY_PORT_CONFIG,
1017 &data);
1018 if (ret_val)
1019 goto out;
1020
1021 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1022 ret_val = phy->ops.write_reg(hw,
1023 IGP01E1000_PHY_PORT_CONFIG,
1024 data);
1025 }
1026
1027 out:
1028 return ret_val;
1029 }
1030
1031 /**
1032 * e1000_setup_led_82541 - Configures SW controllable LED
1033 * @hw: pointer to the HW structure
1034 *
1035 * This prepares the SW controllable LED for use and saves the current state
1036 * of the LED so it can be later restored.
1037 **/
1038 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1039 {
1040 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1041 s32 ret_val;
1042
1043 DEBUGFUNC("e1000_setup_led_82541");
1044
1045 ret_val = hw->phy.ops.read_reg(hw,
1046 IGP01E1000_GMII_FIFO,
1047 &dev_spec->spd_default);
1048 if (ret_val)
1049 goto out;
1050
1051 ret_val = hw->phy.ops.write_reg(hw,
1052 IGP01E1000_GMII_FIFO,
1053 (u16)(dev_spec->spd_default &
1054 ~IGP01E1000_GMII_SPD));
1055 if (ret_val)
1056 goto out;
1057
1058 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1059
1060 out:
1061 return ret_val;
1062 }
1063
1064 /**
1065 * e1000_cleanup_led_82541 - Set LED config to default operation
1066 * @hw: pointer to the HW structure
1067 *
1068 * Remove the current LED configuration and set the LED configuration
1069 * to the default value, saved from the EEPROM.
1070 **/
1071 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1072 {
1073 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1074 s32 ret_val;
1075
1076 DEBUGFUNC("e1000_cleanup_led_82541");
1077
1078 ret_val = hw->phy.ops.write_reg(hw,
1079 IGP01E1000_GMII_FIFO,
1080 dev_spec->spd_default);
1081 if (ret_val)
1082 goto out;
1083
1084 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1085
1086 out:
1087 return ret_val;
1088 }
1089
1090 /**
1091 * e1000_phy_init_script_82541 - Initialize GbE PHY
1092 * @hw: pointer to the HW structure
1093 *
1094 * Initializes the IGP PHY.
1095 **/
1096 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1097 {
1098 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1099 u32 ret_val;
1100 u16 phy_saved_data;
1101
1102 DEBUGFUNC("e1000_phy_init_script_82541");
1103
1104 if (!dev_spec->phy_init_script) {
1105 ret_val = E1000_SUCCESS;
1106 goto out;
1107 }
1108
1109 /* Delay after phy reset to enable NVM configuration to load */
1110 msec_delay(20);
1111
1112 /*
1113 * Save off the current value of register 0x2F5B to be restored at
1114 * the end of this routine.
1115 */
1116 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1117
1118 /* Disabled the PHY transmitter */
1119 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1120
1121 msec_delay(20);
1122
1123 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1124
1125 msec_delay(5);
1126
1127 switch (hw->mac.type) {
1128 case e1000_82541:
1129 case e1000_82547:
1130 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1131
1132 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1133
1134 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1135
1136 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1137
1138 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1139
1140 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1141
1142 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1143
1144 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1145
1146 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1147 break;
1148 case e1000_82541_rev_2:
1149 case e1000_82547_rev_2:
1150 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1151 break;
1152 default:
1153 break;
1154 }
1155
1156 hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1157
1158 msec_delay(20);
1159
1160 /* Now enable the transmitter */
1161 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1162
1163 if (hw->mac.type == e1000_82547) {
1164 u16 fused, fine, coarse;
1165
1166 /* Move to analog registers page */
1167 hw->phy.ops.read_reg(hw,
1168 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1169 &fused);
1170
1171 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1172 hw->phy.ops.read_reg(hw,
1173 IGP01E1000_ANALOG_FUSE_STATUS,
1174 &fused);
1175
1176 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1177 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1178
1179 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1180 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1181 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1182 } else if (coarse ==
1183 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1184 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1185
1186 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1187 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1188 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1189
1190 hw->phy.ops.write_reg(hw,
1191 IGP01E1000_ANALOG_FUSE_CONTROL,
1192 fused);
1193 hw->phy.ops.write_reg(hw,
1194 IGP01E1000_ANALOG_FUSE_BYPASS,
1195 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1196 }
1197 }
1198
1199 out:
1200 return ret_val;
1201 }
1202
1203 /**
1204 * e1000_init_script_state_82541 - Enable/Disable PHY init script
1205 * @hw: pointer to the HW structure
1206 * @state: boolean value used to enable/disable PHY init script
1207 *
1208 * Allows the driver to enable/disable the PHY init script, if the PHY is an
1209 * IGP PHY.
1210 **/
1211 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1212 {
1213 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1214
1215 DEBUGFUNC("e1000_init_script_state_82541");
1216
1217 if (hw->phy.type != e1000_phy_igp) {
1218 DEBUGOUT("Initialization script not necessary.\n");
1219 goto out;
1220 }
1221
1222 dev_spec->phy_init_script = state;
1223
1224 out:
1225 return;
1226 }
1227
1228 /**
1229 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1230 * @hw: pointer to the HW structure
1231 *
1232 * In the case of a PHY power down to save power, or to turn off link during a
1233 * driver unload, or wake on lan is not enabled, remove the link.
1234 **/
1235 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1236 {
1237 /* If the management interface is not enabled, then power down */
1238 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1239 e1000_power_down_phy_copper(hw);
1240
1241 return;
1242 }
1243
1244 /**
1245 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1246 * @hw: pointer to the HW structure
1247 *
1248 * Clears the hardware counters by reading the counter registers.
1249 **/
1250 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1251 {
1252 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1253
1254 e1000_clear_hw_cntrs_base_generic(hw);
1255
1256 E1000_READ_REG(hw, E1000_PRC64);
1257 E1000_READ_REG(hw, E1000_PRC127);
1258 E1000_READ_REG(hw, E1000_PRC255);
1259 E1000_READ_REG(hw, E1000_PRC511);
1260 E1000_READ_REG(hw, E1000_PRC1023);
1261 E1000_READ_REG(hw, E1000_PRC1522);
1262 E1000_READ_REG(hw, E1000_PTC64);
1263 E1000_READ_REG(hw, E1000_PTC127);
1264 E1000_READ_REG(hw, E1000_PTC255);
1265 E1000_READ_REG(hw, E1000_PTC511);
1266 E1000_READ_REG(hw, E1000_PTC1023);
1267 E1000_READ_REG(hw, E1000_PTC1522);
1268
1269 E1000_READ_REG(hw, E1000_ALGNERRC);
1270 E1000_READ_REG(hw, E1000_RXERRC);
1271 E1000_READ_REG(hw, E1000_TNCRS);
1272 E1000_READ_REG(hw, E1000_CEXTERR);
1273 E1000_READ_REG(hw, E1000_TSCTC);
1274 E1000_READ_REG(hw, E1000_TSCTFC);
1275
1276 E1000_READ_REG(hw, E1000_MGTPRC);
1277 E1000_READ_REG(hw, E1000_MGTPDC);
1278 E1000_READ_REG(hw, E1000_MGTPTC);
1279 }
Mirror of AROS' svn.