1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include "e1000_api.h"
31 static void e1000_reload_nvm_generic(struct e1000_hw
*hw
);
34 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
35 * @hw: pointer to the HW structure
37 * Setups up the function pointers to no-op functions
39 void e1000_init_nvm_ops_generic(struct e1000_hw
*hw
)
41 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
42 DEBUGFUNC("e1000_init_nvm_ops_generic");
44 /* Initialize function pointers */
45 nvm
->ops
.init_params
= e1000_null_ops_generic
;
46 nvm
->ops
.acquire
= e1000_null_ops_generic
;
47 nvm
->ops
.read
= e1000_null_read_nvm
;
48 nvm
->ops
.release
= e1000_null_nvm_generic
;
49 nvm
->ops
.reload
= e1000_reload_nvm_generic
;
50 nvm
->ops
.update
= e1000_null_ops_generic
;
51 nvm
->ops
.valid_led_default
= e1000_null_led_default
;
52 nvm
->ops
.validate
= e1000_null_ops_generic
;
53 nvm
->ops
.write
= e1000_null_write_nvm
;
57 * e1000_null_nvm_read - No-op function, return 0
58 * @hw: pointer to the HW structure
60 s32
e1000_null_read_nvm(struct e1000_hw
*hw
, u16 a
, u16 b
, u16
*c
)
62 DEBUGFUNC("e1000_null_read_nvm");
67 * e1000_null_nvm_generic - No-op function, return void
68 * @hw: pointer to the HW structure
70 void e1000_null_nvm_generic(struct e1000_hw
*hw
)
72 DEBUGFUNC("e1000_null_nvm_generic");
77 * e1000_null_led_default - No-op function, return 0
78 * @hw: pointer to the HW structure
80 s32
e1000_null_led_default(struct e1000_hw
*hw
, u16
*data
)
82 DEBUGFUNC("e1000_null_led_default");
87 * e1000_null_write_nvm - No-op function, return 0
88 * @hw: pointer to the HW structure
90 s32
e1000_null_write_nvm(struct e1000_hw
*hw
, u16 a
, u16 b
, u16
*c
)
92 DEBUGFUNC("e1000_null_write_nvm");
97 * e1000_raise_eec_clk - Raise EEPROM clock
98 * @hw: pointer to the HW structure
99 * @eecd: pointer to the EEPROM
101 * Enable/Raise the EEPROM clock bit.
103 static void e1000_raise_eec_clk(struct e1000_hw
*hw
, u32
*eecd
)
105 *eecd
= *eecd
| E1000_EECD_SK
;
106 E1000_WRITE_REG(hw
, E1000_EECD
, *eecd
);
107 E1000_WRITE_FLUSH(hw
);
108 usec_delay(hw
->nvm
.delay_usec
);
112 * e1000_lower_eec_clk - Lower EEPROM clock
113 * @hw: pointer to the HW structure
114 * @eecd: pointer to the EEPROM
116 * Clear/Lower the EEPROM clock bit.
118 static void e1000_lower_eec_clk(struct e1000_hw
*hw
, u32
*eecd
)
120 *eecd
= *eecd
& ~E1000_EECD_SK
;
121 E1000_WRITE_REG(hw
, E1000_EECD
, *eecd
);
122 E1000_WRITE_FLUSH(hw
);
123 usec_delay(hw
->nvm
.delay_usec
);
127 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
128 * @hw: pointer to the HW structure
129 * @data: data to send to the EEPROM
130 * @count: number of bits to shift out
132 * We need to shift 'count' bits out to the EEPROM. So, the value in the
133 * "data" parameter will be shifted out to the EEPROM one bit at a time.
134 * In order to do this, "data" must be broken down into bits.
136 static void e1000_shift_out_eec_bits(struct e1000_hw
*hw
, u16 data
, u16 count
)
138 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
139 u32 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
142 DEBUGFUNC("e1000_shift_out_eec_bits");
144 mask
= 0x01 << (count
- 1);
145 if (nvm
->type
== e1000_nvm_eeprom_microwire
)
146 eecd
&= ~E1000_EECD_DO
;
148 if (nvm
->type
== e1000_nvm_eeprom_spi
)
149 eecd
|= E1000_EECD_DO
;
152 eecd
&= ~E1000_EECD_DI
;
155 eecd
|= E1000_EECD_DI
;
157 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
158 E1000_WRITE_FLUSH(hw
);
160 usec_delay(nvm
->delay_usec
);
162 e1000_raise_eec_clk(hw
, &eecd
);
163 e1000_lower_eec_clk(hw
, &eecd
);
168 eecd
&= ~E1000_EECD_DI
;
169 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
173 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
174 * @hw: pointer to the HW structure
175 * @count: number of bits to shift in
177 * In order to read a register from the EEPROM, we need to shift 'count' bits
178 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
179 * the EEPROM (setting the SK bit), and then reading the value of the data out
180 * "DO" bit. During this "shifting in" process the data in "DI" bit should
183 static u16
e1000_shift_in_eec_bits(struct e1000_hw
*hw
, u16 count
)
189 DEBUGFUNC("e1000_shift_in_eec_bits");
191 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
193 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
196 for (i
= 0; i
< count
; i
++) {
198 e1000_raise_eec_clk(hw
, &eecd
);
200 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
202 eecd
&= ~E1000_EECD_DI
;
203 if (eecd
& E1000_EECD_DO
)
206 e1000_lower_eec_clk(hw
, &eecd
);
213 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
214 * @hw: pointer to the HW structure
215 * @ee_reg: EEPROM flag for polling
217 * Polls the EEPROM status bit for either read or write completion based
218 * upon the value of 'ee_reg'.
220 s32
e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int ee_reg
)
222 u32 attempts
= 100000;
224 s32 ret_val
= -E1000_ERR_NVM
;
226 DEBUGFUNC("e1000_poll_eerd_eewr_done");
228 for (i
= 0; i
< attempts
; i
++) {
229 if (ee_reg
== E1000_NVM_POLL_READ
)
230 reg
= E1000_READ_REG(hw
, E1000_EERD
);
232 reg
= E1000_READ_REG(hw
, E1000_EEWR
);
234 if (reg
& E1000_NVM_RW_REG_DONE
) {
235 ret_val
= E1000_SUCCESS
;
246 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
247 * @hw: pointer to the HW structure
249 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
250 * Return successful if access grant bit set, else clear the request for
251 * EEPROM access and return -E1000_ERR_NVM (-1).
253 s32
e1000_acquire_nvm_generic(struct e1000_hw
*hw
)
255 u32 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
256 s32 timeout
= E1000_NVM_GRANT_ATTEMPTS
;
257 s32 ret_val
= E1000_SUCCESS
;
259 DEBUGFUNC("e1000_acquire_nvm_generic");
261 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
| E1000_EECD_REQ
);
262 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
265 if (eecd
& E1000_EECD_GNT
)
268 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
273 eecd
&= ~E1000_EECD_REQ
;
274 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
275 DEBUGOUT("Could not acquire NVM grant\n");
276 ret_val
= -E1000_ERR_NVM
;
283 * e1000_standby_nvm - Return EEPROM to standby state
284 * @hw: pointer to the HW structure
286 * Return the EEPROM to a standby state.
288 static void e1000_standby_nvm(struct e1000_hw
*hw
)
290 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
291 u32 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
293 DEBUGFUNC("e1000_standby_nvm");
295 if (nvm
->type
== e1000_nvm_eeprom_microwire
) {
296 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
297 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
298 E1000_WRITE_FLUSH(hw
);
299 usec_delay(nvm
->delay_usec
);
301 e1000_raise_eec_clk(hw
, &eecd
);
304 eecd
|= E1000_EECD_CS
;
305 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
306 E1000_WRITE_FLUSH(hw
);
307 usec_delay(nvm
->delay_usec
);
309 e1000_lower_eec_clk(hw
, &eecd
);
311 if (nvm
->type
== e1000_nvm_eeprom_spi
) {
312 /* Toggle CS to flush commands */
313 eecd
|= E1000_EECD_CS
;
314 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
315 E1000_WRITE_FLUSH(hw
);
316 usec_delay(nvm
->delay_usec
);
317 eecd
&= ~E1000_EECD_CS
;
318 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
319 E1000_WRITE_FLUSH(hw
);
320 usec_delay(nvm
->delay_usec
);
325 * e1000_stop_nvm - Terminate EEPROM command
326 * @hw: pointer to the HW structure
328 * Terminates the current command by inverting the EEPROM's chip select pin.
330 void e1000_stop_nvm(struct e1000_hw
*hw
)
334 DEBUGFUNC("e1000_stop_nvm");
336 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
337 if (hw
->nvm
.type
== e1000_nvm_eeprom_spi
) {
339 eecd
|= E1000_EECD_CS
;
340 e1000_lower_eec_clk(hw
, &eecd
);
341 } else if (hw
->nvm
.type
== e1000_nvm_eeprom_microwire
) {
342 /* CS on Microwire is active-high */
343 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_DI
);
344 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
345 e1000_raise_eec_clk(hw
, &eecd
);
346 e1000_lower_eec_clk(hw
, &eecd
);
351 * e1000_release_nvm_generic - Release exclusive access to EEPROM
352 * @hw: pointer to the HW structure
354 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
356 void e1000_release_nvm_generic(struct e1000_hw
*hw
)
360 DEBUGFUNC("e1000_release_nvm_generic");
364 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
365 eecd
&= ~E1000_EECD_REQ
;
366 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
370 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
371 * @hw: pointer to the HW structure
373 * Setups the EEPROM for reading and writing.
375 static s32
e1000_ready_nvm_eeprom(struct e1000_hw
*hw
)
377 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
378 u32 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
379 s32 ret_val
= E1000_SUCCESS
;
383 DEBUGFUNC("e1000_ready_nvm_eeprom");
385 if (nvm
->type
== e1000_nvm_eeprom_microwire
) {
386 /* Clear SK and DI */
387 eecd
&= ~(E1000_EECD_DI
| E1000_EECD_SK
);
388 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
390 eecd
|= E1000_EECD_CS
;
391 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
393 if (nvm
->type
== e1000_nvm_eeprom_spi
) {
394 /* Clear SK and CS */
395 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
396 E1000_WRITE_REG(hw
, E1000_EECD
, eecd
);
398 timeout
= NVM_MAX_RETRY_SPI
;
401 * Read "Status Register" repeatedly until the LSB is cleared.
402 * The EEPROM will signal that the command has been completed
403 * by clearing bit 0 of the internal status register. If it's
404 * not cleared within 'timeout', then error out.
407 e1000_shift_out_eec_bits(hw
, NVM_RDSR_OPCODE_SPI
,
408 hw
->nvm
.opcode_bits
);
409 spi_stat_reg
= (u8
)e1000_shift_in_eec_bits(hw
, 8);
410 if (!(spi_stat_reg
& NVM_STATUS_RDY_SPI
))
414 e1000_standby_nvm(hw
);
419 DEBUGOUT("SPI NVM Status error\n");
420 ret_val
= -E1000_ERR_NVM
;
430 * e1000_read_nvm_spi - Read EEPROM's using SPI
431 * @hw: pointer to the HW structure
432 * @offset: offset of word in the EEPROM to read
433 * @words: number of words to read
434 * @data: word read from the EEPROM
436 * Reads a 16 bit word from the EEPROM.
438 s32
e1000_read_nvm_spi(struct e1000_hw
*hw
, u16 offset
, u16 words
, u16
*data
)
440 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
444 u8 read_opcode
= NVM_READ_OPCODE_SPI
;
446 DEBUGFUNC("e1000_read_nvm_spi");
449 * A check for invalid values: offset too large, too many words,
450 * and not enough words.
452 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
454 DEBUGOUT("nvm parameter(s) out of bounds\n");
455 ret_val
= -E1000_ERR_NVM
;
459 ret_val
= nvm
->ops
.acquire(hw
);
463 ret_val
= e1000_ready_nvm_eeprom(hw
);
467 e1000_standby_nvm(hw
);
469 if ((nvm
->address_bits
== 8) && (offset
>= 128))
470 read_opcode
|= NVM_A8_OPCODE_SPI
;
472 /* Send the READ command (opcode + addr) */
473 e1000_shift_out_eec_bits(hw
, read_opcode
, nvm
->opcode_bits
);
474 e1000_shift_out_eec_bits(hw
, (u16
)(offset
*2), nvm
->address_bits
);
477 * Read the data. SPI NVMs increment the address with each byte
478 * read and will roll over if reading beyond the end. This allows
479 * us to read the whole NVM from any offset
481 for (i
= 0; i
< words
; i
++) {
482 word_in
= e1000_shift_in_eec_bits(hw
, 16);
483 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
487 nvm
->ops
.release(hw
);
494 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
495 * @hw: pointer to the HW structure
496 * @offset: offset of word in the EEPROM to read
497 * @words: number of words to read
498 * @data: word read from the EEPROM
500 * Reads a 16 bit word from the EEPROM.
502 s32
e1000_read_nvm_microwire(struct e1000_hw
*hw
, u16 offset
, u16 words
,
505 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
508 u8 read_opcode
= NVM_READ_OPCODE_MICROWIRE
;
510 DEBUGFUNC("e1000_read_nvm_microwire");
513 * A check for invalid values: offset too large, too many words,
514 * and not enough words.
516 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
518 DEBUGOUT("nvm parameter(s) out of bounds\n");
519 ret_val
= -E1000_ERR_NVM
;
523 ret_val
= nvm
->ops
.acquire(hw
);
527 ret_val
= e1000_ready_nvm_eeprom(hw
);
531 for (i
= 0; i
< words
; i
++) {
532 /* Send the READ command (opcode + addr) */
533 e1000_shift_out_eec_bits(hw
, read_opcode
, nvm
->opcode_bits
);
534 e1000_shift_out_eec_bits(hw
, (u16
)(offset
+ i
),
538 * Read the data. For microwire, each word requires the
539 * overhead of setup and tear-down.
541 data
[i
] = e1000_shift_in_eec_bits(hw
, 16);
542 e1000_standby_nvm(hw
);
546 nvm
->ops
.release(hw
);
553 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
554 * @hw: pointer to the HW structure
555 * @offset: offset of word in the EEPROM to read
556 * @words: number of words to read
557 * @data: word read from the EEPROM
559 * Reads a 16 bit word from the EEPROM using the EERD register.
561 s32
e1000_read_nvm_eerd(struct e1000_hw
*hw
, u16 offset
, u16 words
, u16
*data
)
563 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
565 s32 ret_val
= E1000_SUCCESS
;
567 DEBUGFUNC("e1000_read_nvm_eerd");
570 * A check for invalid values: offset too large, too many words,
571 * too many words for the offset, and not enough words.
573 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
575 DEBUGOUT("nvm parameter(s) out of bounds\n");
576 ret_val
= -E1000_ERR_NVM
;
580 for (i
= 0; i
< words
; i
++) {
581 eerd
= ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) +
582 E1000_NVM_RW_REG_START
;
584 E1000_WRITE_REG(hw
, E1000_EERD
, eerd
);
585 ret_val
= e1000_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_READ
);
589 data
[i
] = (E1000_READ_REG(hw
, E1000_EERD
) >>
590 E1000_NVM_RW_REG_DATA
);
598 * e1000_write_nvm_spi - Write to EEPROM using SPI
599 * @hw: pointer to the HW structure
600 * @offset: offset within the EEPROM to be written to
601 * @words: number of words to write
602 * @data: 16 bit word(s) to be written to the EEPROM
604 * Writes data to EEPROM at offset using SPI interface.
606 * If e1000_update_nvm_checksum is not called after this function , the
607 * EEPROM will most likely contain an invalid checksum.
609 s32
e1000_write_nvm_spi(struct e1000_hw
*hw
, u16 offset
, u16 words
, u16
*data
)
611 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
615 DEBUGFUNC("e1000_write_nvm_spi");
618 * A check for invalid values: offset too large, too many words,
619 * and not enough words.
621 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
623 DEBUGOUT("nvm parameter(s) out of bounds\n");
624 ret_val
= -E1000_ERR_NVM
;
628 ret_val
= nvm
->ops
.acquire(hw
);
632 while (widx
< words
) {
633 u8 write_opcode
= NVM_WRITE_OPCODE_SPI
;
635 ret_val
= e1000_ready_nvm_eeprom(hw
);
639 e1000_standby_nvm(hw
);
641 /* Send the WRITE ENABLE command (8 bit opcode) */
642 e1000_shift_out_eec_bits(hw
, NVM_WREN_OPCODE_SPI
,
645 e1000_standby_nvm(hw
);
648 * Some SPI eeproms use the 8th address bit embedded in the
651 if ((nvm
->address_bits
== 8) && (offset
>= 128))
652 write_opcode
|= NVM_A8_OPCODE_SPI
;
654 /* Send the Write command (8-bit opcode + addr) */
655 e1000_shift_out_eec_bits(hw
, write_opcode
, nvm
->opcode_bits
);
656 e1000_shift_out_eec_bits(hw
, (u16
)((offset
+ widx
) * 2),
659 /* Loop to allow for up to whole page write of eeprom */
660 while (widx
< words
) {
661 u16 word_out
= data
[widx
];
662 word_out
= (word_out
>> 8) | (word_out
<< 8);
663 e1000_shift_out_eec_bits(hw
, word_out
, 16);
666 if ((((offset
+ widx
) * 2) % nvm
->page_size
) == 0) {
667 e1000_standby_nvm(hw
);
675 nvm
->ops
.release(hw
);
682 * e1000_write_nvm_microwire - Writes EEPROM using microwire
683 * @hw: pointer to the HW structure
684 * @offset: offset within the EEPROM to be written to
685 * @words: number of words to write
686 * @data: 16 bit word(s) to be written to the EEPROM
688 * Writes data to EEPROM at offset using microwire interface.
690 * If e1000_update_nvm_checksum is not called after this function , the
691 * EEPROM will most likely contain an invalid checksum.
693 s32
e1000_write_nvm_microwire(struct e1000_hw
*hw
, u16 offset
, u16 words
,
696 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
699 u16 words_written
= 0;
702 DEBUGFUNC("e1000_write_nvm_microwire");
705 * A check for invalid values: offset too large, too many words,
706 * and not enough words.
708 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
710 DEBUGOUT("nvm parameter(s) out of bounds\n");
711 ret_val
= -E1000_ERR_NVM
;
715 ret_val
= nvm
->ops
.acquire(hw
);
719 ret_val
= e1000_ready_nvm_eeprom(hw
);
723 e1000_shift_out_eec_bits(hw
, NVM_EWEN_OPCODE_MICROWIRE
,
724 (u16
)(nvm
->opcode_bits
+ 2));
726 e1000_shift_out_eec_bits(hw
, 0, (u16
)(nvm
->address_bits
- 2));
728 e1000_standby_nvm(hw
);
730 while (words_written
< words
) {
731 e1000_shift_out_eec_bits(hw
, NVM_WRITE_OPCODE_MICROWIRE
,
734 e1000_shift_out_eec_bits(hw
, (u16
)(offset
+ words_written
),
737 e1000_shift_out_eec_bits(hw
, data
[words_written
], 16);
739 e1000_standby_nvm(hw
);
741 for (widx
= 0; widx
< 200; widx
++) {
742 eecd
= E1000_READ_REG(hw
, E1000_EECD
);
743 if (eecd
& E1000_EECD_DO
)
749 DEBUGOUT("NVM Write did not complete\n");
750 ret_val
= -E1000_ERR_NVM
;
754 e1000_standby_nvm(hw
);
759 e1000_shift_out_eec_bits(hw
, NVM_EWDS_OPCODE_MICROWIRE
,
760 (u16
)(nvm
->opcode_bits
+ 2));
762 e1000_shift_out_eec_bits(hw
, 0, (u16
)(nvm
->address_bits
- 2));
765 nvm
->ops
.release(hw
);
772 * e1000_read_pba_num_generic - Read device part number
773 * @hw: pointer to the HW structure
774 * @pba_num: pointer to device part number
776 * Reads the product board assembly (PBA) number from the EEPROM and stores
777 * the value in pba_num.
779 s32
e1000_read_pba_num_generic(struct e1000_hw
*hw
, u32
*pba_num
)
784 DEBUGFUNC("e1000_read_pba_num_generic");
786 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_PBA_OFFSET_0
, 1, &nvm_data
);
788 DEBUGOUT("NVM Read Error\n");
791 *pba_num
= (u32
)(nvm_data
<< 16);
793 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_PBA_OFFSET_1
, 1, &nvm_data
);
795 DEBUGOUT("NVM Read Error\n");
798 *pba_num
|= nvm_data
;
805 * e1000_read_mac_addr_generic - Read device MAC address
806 * @hw: pointer to the HW structure
808 * Reads the device MAC address from the EEPROM and stores the value.
809 * Since devices with two ports use the same EEPROM, we increment the
810 * last bit in the MAC address for the second port.
812 s32
e1000_read_mac_addr_generic(struct e1000_hw
*hw
)
818 rar_high
= E1000_READ_REG(hw
, E1000_RAH(0));
819 rar_low
= E1000_READ_REG(hw
, E1000_RAL(0));
821 for (i
= 0; i
< E1000_RAL_MAC_ADDR_LEN
; i
++)
822 hw
->mac
.perm_addr
[i
] = (u8
)(rar_low
>> (i
*8));
824 for (i
= 0; i
< E1000_RAH_MAC_ADDR_LEN
; i
++)
825 hw
->mac
.perm_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
827 for (i
= 0; i
< ETH_ADDR_LEN
; i
++)
828 hw
->mac
.addr
[i
] = hw
->mac
.perm_addr
[i
];
830 return E1000_SUCCESS
;
834 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
835 * @hw: pointer to the HW structure
837 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
838 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
840 s32
e1000_validate_nvm_checksum_generic(struct e1000_hw
*hw
)
842 s32 ret_val
= E1000_SUCCESS
;
846 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
848 for (i
= 0; i
< (NVM_CHECKSUM_REG
+ 1); i
++) {
849 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
851 DEBUGOUT("NVM Read Error\n");
854 checksum
+= nvm_data
;
857 if (checksum
!= (u16
) NVM_SUM
) {
858 DEBUGOUT("NVM Checksum Invalid\n");
859 ret_val
= -E1000_ERR_NVM
;
868 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
869 * @hw: pointer to the HW structure
871 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
872 * up to the checksum. Then calculates the EEPROM checksum and writes the
873 * value to the EEPROM.
875 s32
e1000_update_nvm_checksum_generic(struct e1000_hw
*hw
)
881 DEBUGFUNC("e1000_update_nvm_checksum");
883 for (i
= 0; i
< NVM_CHECKSUM_REG
; i
++) {
884 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
886 DEBUGOUT("NVM Read Error while updating checksum.\n");
889 checksum
+= nvm_data
;
891 checksum
= (u16
) NVM_SUM
- checksum
;
892 ret_val
= hw
->nvm
.ops
.write(hw
, NVM_CHECKSUM_REG
, 1, &checksum
);
894 DEBUGOUT("NVM Write Error while updating checksum.\n");
901 * e1000_reload_nvm_generic - Reloads EEPROM
902 * @hw: pointer to the HW structure
904 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
905 * extended control register.
907 static void e1000_reload_nvm_generic(struct e1000_hw
*hw
)
911 DEBUGFUNC("e1000_reload_nvm_generic");
914 ctrl_ext
= E1000_READ_REG(hw
, E1000_CTRL_EXT
);
915 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
916 E1000_WRITE_REG(hw
, E1000_CTRL_EXT
, ctrl_ext
);
917 E1000_WRITE_FLUSH(hw
);