workbench/devs/networks/rtl8169/rtl8168_hw.c

   1 #include "rtl8168_hw.h"
   2
   3 void rtl8168cp_hw_phy_config(struct net_device *unit)
   4 {
   5         struct phy_reg phy_reg_init[] =
   6         {
   7                 { 0x1f, 0x0000 },
   8                 { 0x1d, 0x0f00 },
   9                 { 0x1f, 0x0002 },
  10                 { 0x0c, 0x1ec8 },
  11                 { 0x1f, 0x0000 }
  12         };
  13
  14         rtl_phy_write(unit, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  15 }
  16
  17 void rtl8168c_hw_phy_config(struct net_device *unit)
  18 {
  19         struct phy_reg phy_reg_init[] =
  20         {
  21                 { 0x1f, 0x0001 },
  22                 { 0x12, 0x2300 },
  23                 { 0x1f, 0x0002 },
  24                 { 0x00, 0x88d4 },
  25                 { 0x01, 0x82b1 },
  26                 { 0x03, 0x7002 },
  27                 { 0x08, 0x9e30 },
  28                 { 0x09, 0x01f0 },
  29                 { 0x0a, 0x5500 },
  30                 { 0x0c, 0x00c8 },
  31                 { 0x1f, 0x0003 },
  32                 { 0x12, 0xc096 },
  33                 { 0x16, 0x000a },
  34                 { 0x1f, 0x0000 }
  35         };
  36
  37         rtl_phy_write(unit, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  38 }
  39
  40 void rtl8168cx_hw_phy_config(struct net_device *unit)
  41 {
  42         struct phy_reg phy_reg_init[] =
  43         {
  44                 { 0x1f, 0x0000 },
  45                 { 0x12, 0x2300 },
  46                 { 0x1f, 0x0003 },
  47                 { 0x16, 0x0f0a },
  48                 { 0x1f, 0x0000 },
  49                 { 0x1f, 0x0002 },
  50                 { 0x0c, 0x7eb8 },
  51                 { 0x1f, 0x0000 }
  52         };
  53
  54         rtl_phy_write(unit, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  55 }
  56
  57 void rtl_hw_start_8168(struct net_device *unit)
  58 {
  59     struct rtl8169_priv *np = get_pcnpriv(unit);
  60     APTR base = get_hwbase(unit);
  61         UBYTE ctl;
  62
  63         RTL_W8(base + Cfg9346, Cfg9346_Unlock);
  64
  65         RTL_W8(base + EarlyTxThres, EarlyTxThld);
  66
  67         rtl_set_rx_max_size(unit);
  68
  69         rtl_set_rx_tx_config_registers(unit);
  70
  71         np->cp_cmd |= RTL_R16(base + CPlusCmd) | PktCntrDisable | INTT_1;
  72
  73         RTL_W16(base + CPlusCmd, np->cp_cmd);
  74
  75         /* Tx performance tweak. */
  76     ctl = HIDD_PCIDevice_ReadConfigByte(unit->rtl8169u_PCIDevice, 0x69);
  77         ctl = (ctl & ~0x70) | 0x50;
  78     HIDD_PCIDevice_WriteConfigByte(unit->rtl8169u_PCIDevice, 0x69, ctl);
  79
  80         RTL_W16(base + IntrMitigate, 0x5151);
  81
  82         rtl_set_rx_tx_desc_registers(unit);
  83
  84         RTL_W8(base + Cfg9346, Cfg9346_Lock);
  85
  86         RTL_R8(base + IntrMask);
  87
  88         RTL_W32(base + RxMissed, 0);
  89
  90         rtl_set_rx_mode(unit);
  91
  92         RTL_W8(base + ChipCmd, CmdTxEnb | CmdRxEnb);
  93
  94         RTL_W16(base + MultiIntr, RTL_R16(base + MultiIntr) & 0xF000);
  95
  96     /* Work around for RxFIFO overflow. */
  97         if (np->mcfg == RTL_GIGA_MAC_VER_11)
  98         {
  99                 np->intr_event |= RxFIFOOver | PCSTimeout;
 100                 np->intr_event &= ~RxOverflow;
 101         }
 102     RTL_W16(base + IntrMask, np->intr_event);
 103 }