fpga/hi_simulate.v

   1 //-----------------------------------------------------------------------------
   2 // Pretend to be an ISO 14443 tag. We will do this by alternately short-
   3 // circuiting and open-circuiting the antenna coil, with the tri-state
   4 // pins.
   5 //
   6 // We communicate over the SSP, as a bitstream (i.e., might as well be
   7 // unframed, though we still generate the word sync signal). The output
   8 // (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
   9 // -> ARM) is us using the A/D as a fancy comparator; this is with
  10 // (software-added) hysteresis, to undo the high-pass filter.
  11 //
  12 // At this point only Type A is implemented. This means that we are using a
  13 // bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
  14 // things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
  15 //
  16 // Jonathan Westhues, October 2006
  17 //-----------------------------------------------------------------------------
  18
  19 module hi_simulate(
  20     ck_1356meg,
  21     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
  22     adc_d, adc_clk,
  23     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  24     dbg,
  25     mod_type
  26 );
  27     input ck_1356meg;
  28     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  29     input [7:0] adc_d;
  30     output adc_clk;
  31     input ssp_dout;
  32     output ssp_frame, ssp_din, ssp_clk;
  33     output dbg;
  34     input [3:0] mod_type;
  35
  36 // Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
  37 // always be low.
  38 assign pwr_hi = 1'b0;        // HF antenna connected to GND
  39 assign pwr_lo = 1'b0;        // LF antenna connected to GND
  40
  41 // This one is all LF, so doesn't matter
  42 assign pwr_oe2 = 1'b0;
  43
  44 assign adc_clk = ck_1356meg;
  45 assign dbg = ssp_frame;
  46
  47 // The comparator with hysteresis on the output from the peak detector.
  48 reg after_hysteresis;
  49 reg [11:0] has_been_low_for;
  50
  51 always @(negedge adc_clk)
  52 begin
  53     if (& adc_d[7:5]) after_hysteresis <= 1'b1;           // if (adc_d >= 224)
  54     else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0;   // if (adc_d <= 31)
  55
  56     if (adc_d >= 224)
  57     begin
  58         has_been_low_for <= 12'd0;
  59     end
  60     else
  61     begin
  62         if (has_been_low_for == 12'd4095)
  63         begin
  64             has_been_low_for <= 12'd0;
  65             after_hysteresis <= 1'b1;
  66         end
  67         else
  68         begin
  69             has_been_low_for <= has_been_low_for + 1;
  70         end
  71     end
  72 end
  73
  74
  75 // Divide 13.56 MHz to produce various frequencies for SSP_CLK
  76 // and modulation.
  77 reg [8:0] ssp_clk_divider;
  78
  79 always @(negedge adc_clk)
  80     ssp_clk_divider <= (ssp_clk_divider + 1);
  81
  82 reg ssp_clk;
  83
  84 always @(negedge adc_clk)
  85 begin
  86     if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
  87       // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
  88       ssp_clk <= ~ssp_clk_divider[7];
  89     else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
  90       // Get next bit at 212kHz
  91       ssp_clk <= ~ssp_clk_divider[5];
  92     else
  93       // Get next bit at 424kHz
  94       ssp_clk <= ~ssp_clk_divider[4];
  95 end
  96
  97
  98 // Produce the byte framing signal; the phase of this signal
  99 // is arbitrary, because it's just a bit stream in this module.
 100 reg ssp_frame;
 101 always @(negedge adc_clk)
 102 begin
 103     if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
 104     begin
 105         if (ssp_clk_divider[8:5] == 4'd1)
 106             ssp_frame <= 1'b1;
 107         if (ssp_clk_divider[8:5] == 4'd5)
 108             ssp_frame <= 1'b0;
 109     end
 110     else
 111     begin
 112         if (ssp_clk_divider[7:4] == 4'd1)
 113             ssp_frame <= 1'b1;
 114         if (ssp_clk_divider[7:4] == 4'd5)
 115             ssp_frame <= 1'b0;
 116     end
 117 end
 118
 119
 120 // Synchronize up the after-hysteresis signal, to produce DIN.
 121 reg ssp_din;
 122 always @(posedge ssp_clk)
 123     ssp_din = after_hysteresis;
 124
 125 // Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
 126 reg modulating_carrier;
 127 always @(*)
 128     if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
 129         modulating_carrier <= 1'b0;                          // no modulation
 130     else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
 131         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
 132     else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
 133         modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
 134     else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
 135         modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
 136     else
 137         modulating_carrier <= 1'b0;                           // yet unused
 138
 139
 140
 141 // Load modulation. Toggle only one of these, since we are already producing much deeper
 142 // modulation than a real tag would.
 143 assign pwr_oe1 = 1'b0;                  // 33 Ohms Load
 144 assign pwr_oe4 = modulating_carrier;    // 33 Ohms Load
 145 // This one is always on, so that we can watch the carrier.
 146 assign pwr_oe3 = 1'b0;                  // 10k Load
 147
 148 endmodule