src/main/drivers/dma.h

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #pragma once
  22
  23 #include "drivers/resource.h"
  24
  25 #define CACHE_LINE_SIZE 32
  26 #define CACHE_LINE_MASK (CACHE_LINE_SIZE - 1)
  27
  28 // dmaResource_t is a opaque data type which represents a single DMA engine,
  29 // called and implemented differently in different families of STM32s.
  30 // The opaque data type provides uniform handling of the engine in source code.
  31 // The engines are referenced by dmaResource_t through out the Betaflight code,
  32 // and then converted back to DMA_ARCH_TYPE which is a native type for
  33 // the particular MCU type when calling library functions.
  34
  35 typedef struct dmaResource_s dmaResource_t;
  36
  37 #if defined(STM32F4) || defined(STM32F7)
  38 #define DMA_ARCH_TYPE DMA_Stream_TypeDef
  39 #elif defined(STM32H7)
  40 // H7 has stream based DMA and channel based BDMA, but we ignore BDMA (for now).
  41 #define DMA_ARCH_TYPE DMA_Stream_TypeDef
  42 #else
  43 #define DMA_ARCH_TYPE DMA_Channel_TypeDef
  44 #endif
  45
  46 struct dmaChannelDescriptor_s;
  47 typedef void (*dmaCallbackHandlerFuncPtr)(struct dmaChannelDescriptor_s *channelDescriptor);
  48
  49 typedef struct dmaChannelDescriptor_s {
  50     DMA_TypeDef*                dma;
  51     dmaResource_t               *ref;
  52 #if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
  53     uint8_t                     stream;
  54 #endif
  55     uint32_t                    channel;
  56     dmaCallbackHandlerFuncPtr   irqHandlerCallback;
  57     uint8_t                     flagsShift;
  58     IRQn_Type                   irqN;
  59     uint32_t                    userParam;
  60     resourceOwner_t             owner;
  61     uint8_t                     resourceIndex;
  62     uint32_t                    completeFlag;
  63 } dmaChannelDescriptor_t;
  64
  65 #if defined(STM32F7)
  66 //#define HAL_CLEANINVALIDATECACHE(addr, size) (SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
  67 //#define HAL_CLEANCACHE(addr, size) (SCB_CleanDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
  68
  69 #endif
  70
  71 #define DMA_IDENTIFIER_TO_INDEX(x) ((x) - 1)
  72
  73 #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
  74
  75 typedef enum {
  76     DMA_NONE = 0,
  77     DMA1_ST0_HANDLER = 1,
  78     DMA1_ST1_HANDLER,
  79     DMA1_ST2_HANDLER,
  80     DMA1_ST3_HANDLER,
  81     DMA1_ST4_HANDLER,
  82     DMA1_ST5_HANDLER,
  83     DMA1_ST6_HANDLER,
  84     DMA1_ST7_HANDLER,
  85     DMA2_ST0_HANDLER,
  86     DMA2_ST1_HANDLER,
  87     DMA2_ST2_HANDLER,
  88     DMA2_ST3_HANDLER,
  89     DMA2_ST4_HANDLER,
  90     DMA2_ST5_HANDLER,
  91     DMA2_ST6_HANDLER,
  92     DMA2_ST7_HANDLER,
  93     DMA_LAST_HANDLER = DMA2_ST7_HANDLER
  94 } dmaIdentifier_e;
  95
  96 #define DMA_DEVICE_NO(x)    ((((x)-1) / 8) + 1)
  97 #define DMA_DEVICE_INDEX(x) ((((x)-1) % 8))
  98 #define DMA_OUTPUT_INDEX    0
  99 #define DMA_OUTPUT_STRING   "DMA%d Stream %d:"
 100 #define DMA_INPUT_STRING    "DMA%d_ST%d"
 101
 102 #define DEFINE_DMA_CHANNEL(d, s, f) { \
 103     .dma = d, \
 104     .ref = (dmaResource_t *)d ## _Stream ## s, \
 105     .stream = s, \
 106     .irqHandlerCallback = NULL, \
 107     .flagsShift = f, \
 108     .irqN = d ## _Stream ## s ## _IRQn, \
 109     .userParam = 0, \
 110     .owner.owner = 0, \
 111     .owner.resourceIndex = 0 \
 112     }
 113
 114 #define DEFINE_DMA_IRQ_HANDLER(d, s, i) FAST_IRQ_HANDLER void DMA ## d ## _Stream ## s ## _IRQHandler(void) {\
 115                                                                 const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \
 116                                                                 dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \
 117                                                                 if (handler) \
 118                                                                     handler(&dmaDescriptors[index]); \
 119                                                             }
 120
 121 #define DMA_CLEAR_FLAG(d, flag) if (d->flagsShift > 31) d->dma->HIFCR = (flag << (d->flagsShift - 32)); else d->dma->LIFCR = (flag << d->flagsShift)
 122 #define DMA_GET_FLAG_STATUS(d, flag) (d->flagsShift > 31 ? d->dma->HISR & (flag << (d->flagsShift - 32)): d->dma->LISR & (flag << d->flagsShift))
 123
 124
 125 #define DMA_IT_TCIF         ((uint32_t)0x00000020)
 126 #define DMA_IT_HTIF         ((uint32_t)0x00000010)
 127 #define DMA_IT_TEIF         ((uint32_t)0x00000008)
 128 #define DMA_IT_DMEIF        ((uint32_t)0x00000004)
 129 #define DMA_IT_FEIF         ((uint32_t)0x00000001)
 130
 131 #else
 132
 133 #if defined(STM32G4)
 134
 135 typedef enum {
 136     DMA_NONE = 0,
 137     DMA1_CH1_HANDLER = 1,
 138     DMA1_CH2_HANDLER,
 139     DMA1_CH3_HANDLER,
 140     DMA1_CH4_HANDLER,
 141     DMA1_CH5_HANDLER,
 142     DMA1_CH6_HANDLER,
 143     DMA1_CH7_HANDLER,
 144     DMA1_CH8_HANDLER,
 145     DMA2_CH1_HANDLER,
 146     DMA2_CH2_HANDLER,
 147     DMA2_CH3_HANDLER,
 148     DMA2_CH4_HANDLER,
 149     DMA2_CH5_HANDLER,
 150     DMA2_CH6_HANDLER,
 151     DMA2_CH7_HANDLER,
 152     DMA2_CH8_HANDLER,
 153     DMA_LAST_HANDLER = DMA2_CH8_HANDLER
 154 } dmaIdentifier_e;
 155
 156 #define DMA_DEVICE_NO(x)    ((((x)-1) / 8) + 1)
 157 #define DMA_DEVICE_INDEX(x) ((((x)-1) % 8) + 1)
 158
 159 uint32_t dmaGetChannel(const uint8_t channel);
 160
 161 #else // !STM32G4
 162
 163 typedef enum {
 164     DMA_NONE = 0,
 165     DMA1_CH1_HANDLER = 1,
 166     DMA1_CH2_HANDLER,
 167     DMA1_CH3_HANDLER,
 168     DMA1_CH4_HANDLER,
 169     DMA1_CH5_HANDLER,
 170     DMA1_CH6_HANDLER,
 171     DMA1_CH7_HANDLER,
 172 #if defined(STM32F3) || defined(STM32F10X_CL)
 173     DMA2_CH1_HANDLER,
 174     DMA2_CH2_HANDLER,
 175     DMA2_CH3_HANDLER,
 176     DMA2_CH4_HANDLER,
 177     DMA2_CH5_HANDLER,
 178     DMA_LAST_HANDLER = DMA2_CH5_HANDLER
 179 #else
 180     DMA_LAST_HANDLER = DMA1_CH7_HANDLER
 181 #endif
 182 } dmaIdentifier_e;
 183
 184 #define DMA_DEVICE_NO(x)    ((((x)-1) / 7) + 1)
 185 #define DMA_DEVICE_INDEX(x) ((((x)-1) % 7) + 1)
 186
 187 #endif // STM32G4
 188
 189 #define DMA_OUTPUT_INDEX    0
 190 #define DMA_OUTPUT_STRING   "DMA%d Channel %d:"
 191 #define DMA_INPUT_STRING    "DMA%d_CH%d"
 192
 193 #define DEFINE_DMA_CHANNEL(d, c, f) { \
 194     .dma = d, \
 195     .ref = (dmaResource_t *)d ## _Channel ## c, \
 196     .irqHandlerCallback = NULL, \
 197     .flagsShift = f, \
 198     .irqN = d ## _Channel ## c ## _IRQn, \
 199     .userParam = 0, \
 200     .owner.owner = 0, \
 201     .owner.resourceIndex = 0 \
 202     }
 203
 204 #if defined(USE_CCM_CODE) && defined(STM32F3)
 205 #define DMA_HANDLER_CODE CCM_CODE
 206 #else
 207 #define DMA_HANDLER_CODE
 208 #endif
 209
 210 #define DEFINE_DMA_IRQ_HANDLER(d, c, i) DMA_HANDLER_CODE void DMA ## d ## _Channel ## c ## _IRQHandler(void) {\
 211                                                                         const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \
 212                                                                         dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \
 213                                                                         if (handler) \
 214                                                                             handler(&dmaDescriptors[index]); \
 215                                                                     }
 216
 217 #define DMA_CLEAR_FLAG(d, flag) d->dma->IFCR = (flag << d->flagsShift)
 218 #define DMA_GET_FLAG_STATUS(d, flag) (d->dma->ISR & (flag << d->flagsShift))
 219
 220 #define DMA_IT_TCIF         ((uint32_t)0x00000002)
 221 #define DMA_IT_HTIF         ((uint32_t)0x00000004)
 222 #define DMA_IT_TEIF         ((uint32_t)0x00000008)
 223
 224 #endif
 225
 226 // Macros to avoid direct register and register bit access
 227
 228 #if defined(STM32F4) || defined(STM32F7)
 229 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CR & DMA_SxCR_EN)
 230 #define REG_NDTR NDTR
 231 #elif defined(STM32H7)
 232 // For H7, we have to differenciate DMA1/2 and BDMA for access to the control register.
 233 // HAL library has a macro for this, but it is extremely inefficient in that it compares
 234 // the address against all possible values.
 235 // Here, we just compare the address against regions of memory.
 236 #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
 237 // For H7A3, if it's lower than CD_AHB2PERIPH_BASE, then it's DMA1/2 and it's stream based.
 238 // If not, it's BDMA and it's channel based.
 239 #define IS_DMA_ENABLED(reg) \
 240     ((uint32_t)(reg) < CD_AHB2PERIPH_BASE) ? \
 241         (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \
 242         (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN)
 243 #else
 244 // For H743 and H750, if it's not in D3 peripheral area, then it's DMA1/2 and it's stream based.
 245 // If not, it's BDMA and it's channel based.
 246 #define IS_DMA_ENABLED(reg) \
 247     ((uint32_t)(reg) < D3_AHB1PERIPH_BASE) ? \
 248         (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \
 249         (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN)
 250 #endif
 251 #elif defined(STM32G4)
 252 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN)
 253 // Missing __HAL_DMA_SET_COUNTER in FW library V1.0.0
 254 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNDTR = (uint16_t)(__COUNTER__))
 255 #else
 256 #if defined(STM32F1)
 257 #define DMA_CCR_EN 1 // Not defined anywhere ...
 258 #endif
 259 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN)
 260 #define DMAx_SetMemoryAddress(reg, address) ((DMA_ARCH_TYPE *)(reg))->CMAR = (uint32_t)&s->port.txBuffer[s->port.txBufferTail]
 261 #endif
 262
 263 dmaIdentifier_e dmaAllocate(dmaIdentifier_e identifier, resourceOwner_e owner, uint8_t resourceIndex);
 264 void dmaEnable(dmaIdentifier_e identifier);
 265 void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam);
 266
 267 dmaIdentifier_e dmaGetIdentifier(const dmaResource_t* channel);
 268 const resourceOwner_t *dmaGetOwner(dmaIdentifier_e identifier);
 269 dmaChannelDescriptor_t* dmaGetDescriptorByIdentifier(const dmaIdentifier_e identifier);
 270 uint32_t dmaGetChannel(const uint8_t channel);
 271
 272 //
 273 // Wrapper macros to cast dmaResource_t back into DMA_ARCH_TYPE
 274 //
 275
 276 #ifdef USE_HAL_DRIVER
 277
 278 // We actually need these LL case only
 279
 280 #define xLL_EX_DMA_DeInit(dmaResource) LL_EX_DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource))
 281 #define xLL_EX_DMA_Init(dmaResource, initstruct) LL_EX_DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initstruct)
 282 #define xLL_EX_DMA_DisableResource(dmaResource) LL_EX_DMA_DisableResource((DMA_ARCH_TYPE *)(dmaResource))
 283 #define xLL_EX_DMA_EnableResource(dmaResource) LL_EX_DMA_EnableResource((DMA_ARCH_TYPE *)(dmaResource))
 284 #define xLL_EX_DMA_GetDataLength(dmaResource) LL_EX_DMA_GetDataLength((DMA_ARCH_TYPE *)(dmaResource))
 285 #define xLL_EX_DMA_SetDataLength(dmaResource, length) LL_EX_DMA_SetDataLength((DMA_ARCH_TYPE *)(dmaResource), length)
 286 #define xLL_EX_DMA_EnableIT_TC(dmaResource) LL_EX_DMA_EnableIT_TC((DMA_ARCH_TYPE *)(dmaResource))
 287
 288 #else
 289
 290 #define xDMA_Init(dmaResource, initStruct) DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initStruct)
 291 #define xDMA_DeInit(dmaResource) DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource))
 292 #define xDMA_Cmd(dmaResource, newState) DMA_Cmd((DMA_ARCH_TYPE *)(dmaResource), newState)
 293 #define xDMA_ITConfig(dmaResource, flags, newState) DMA_ITConfig((DMA_ARCH_TYPE *)(dmaResource), flags, newState)
 294 #define xDMA_GetCurrDataCounter(dmaResource) DMA_GetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource))
 295 #define xDMA_SetCurrDataCounter(dmaResource, count) DMA_SetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource), count)
 296 #define xDMA_GetFlagStatus(dmaResource, flags) DMA_GetFlagStatus((DMA_ARCH_TYPE *)(dmaResource), flags)
 297 #define xDMA_ClearFlag(dmaResource, flags) DMA_ClearFlag((DMA_ARCH_TYPE *)(dmaResource), flags)
 298 #define xDMA_MemoryTargetConfig(dmaResource, address, target) DMA_MemoryTargetConfig((DMA_ARCH_TYPE *)(dmaResource), address, target)
 299
 300 #endif