lib/main/CMSIS/Core/Include/cmsis_armcc.h

   1 /**************************************************************************//**
   2  * @file     cmsis_armcc.h
   3  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
   4  * @version  V5.0.4
   5  * @date     10. January 2018
   6  ******************************************************************************/
   7 /*
   8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
   9  *
  10  * SPDX-License-Identifier: Apache-2.0
  11  *
  12  * Licensed under the Apache License, Version 2.0 (the License); you may
  13  * not use this file except in compliance with the License.
  14  * You may obtain a copy of the License at
  15  *
  16  * www.apache.org/licenses/LICENSE-2.0
  17  *
  18  * Unless required by applicable law or agreed to in writing, software
  19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21  * See the License for the specific language governing permissions and
  22  * limitations under the License.
  23  */
  24
  25 #ifndef __CMSIS_ARMCC_H
  26 #define __CMSIS_ARMCC_H
  27
  28
  29 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
  30   #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
  31 #endif
  32
  33 /* CMSIS compiler control architecture macros */
  34 #if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
  35      (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
  36   #define __ARM_ARCH_6M__           1
  37 #endif
  38
  39 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
  40   #define __ARM_ARCH_7M__           1
  41 #endif
  42
  43 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
  44   #define __ARM_ARCH_7EM__          1
  45 #endif
  46
  47   /* __ARM_ARCH_8M_BASE__  not applicable */
  48   /* __ARM_ARCH_8M_MAIN__  not applicable */
  49
  50
  51 /* CMSIS compiler specific defines */
  52 #ifndef   __ASM
  53   #define __ASM                                  __asm
  54 #endif
  55 #ifndef   __INLINE
  56   #define __INLINE                               __inline
  57 #endif
  58 #ifndef   __STATIC_INLINE
  59   #define __STATIC_INLINE                        static __inline
  60 #endif
  61 #ifndef   __STATIC_FORCEINLINE
  62   #define __STATIC_FORCEINLINE                   static __forceinline
  63 #endif
  64 #ifndef   __NO_RETURN
  65   #define __NO_RETURN                            __declspec(noreturn)
  66 #endif
  67 #ifndef   __USED
  68   #define __USED                                 __attribute__((used))
  69 #endif
  70 #ifndef   __WEAK
  71   #define __WEAK                                 __attribute__((weak))
  72 #endif
  73 #ifndef   __PACKED
  74   #define __PACKED                               __attribute__((packed))
  75 #endif
  76 #ifndef   __PACKED_STRUCT
  77   #define __PACKED_STRUCT                        __packed struct
  78 #endif
  79 #ifndef   __PACKED_UNION
  80   #define __PACKED_UNION                         __packed union
  81 #endif
  82 #ifndef   __UNALIGNED_UINT32        /* deprecated */
  83   #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
  84 #endif
  85 #ifndef   __UNALIGNED_UINT16_WRITE
  86   #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
  87 #endif
  88 #ifndef   __UNALIGNED_UINT16_READ
  89   #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
  90 #endif
  91 #ifndef   __UNALIGNED_UINT32_WRITE
  92   #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
  93 #endif
  94 #ifndef   __UNALIGNED_UINT32_READ
  95   #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
  96 #endif
  97 #ifndef   __ALIGNED
  98   #define __ALIGNED(x)                           __attribute__((aligned(x)))
  99 #endif
 100 #ifndef   __RESTRICT
 101   #define __RESTRICT                             __restrict
 102 #endif
 103
 104 /* ###########################  Core Function Access  ########################### */
 105 /** \ingroup  CMSIS_Core_FunctionInterface
 106     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 107   @{
 108  */
 109
 110 /**
 111   \brief   Enable IRQ Interrupts
 112   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
 113            Can only be executed in Privileged modes.
 114  */
 115 /* intrinsic void __enable_irq();     */
 116
 117
 118 /**
 119   \brief   Disable IRQ Interrupts
 120   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
 121            Can only be executed in Privileged modes.
 122  */
 123 /* intrinsic void __disable_irq();    */
 124
 125 /**
 126   \brief   Get Control Register
 127   \details Returns the content of the Control Register.
 128   \return               Control Register value
 129  */
 130 __STATIC_INLINE uint32_t __get_CONTROL(void)
 131 {
 132   register uint32_t __regControl         __ASM("control");
 133   return(__regControl);
 134 }
 135
 136
 137 /**
 138   \brief   Set Control Register
 139   \details Writes the given value to the Control Register.
 140   \param [in]    control  Control Register value to set
 141  */
 142 __STATIC_INLINE void __set_CONTROL(uint32_t control)
 143 {
 144   register uint32_t __regControl         __ASM("control");
 145   __regControl = control;
 146 }
 147
 148
 149 /**
 150   \brief   Get IPSR Register
 151   \details Returns the content of the IPSR Register.
 152   \return               IPSR Register value
 153  */
 154 __STATIC_INLINE uint32_t __get_IPSR(void)
 155 {
 156   register uint32_t __regIPSR          __ASM("ipsr");
 157   return(__regIPSR);
 158 }
 159
 160
 161 /**
 162   \brief   Get APSR Register
 163   \details Returns the content of the APSR Register.
 164   \return               APSR Register value
 165  */
 166 __STATIC_INLINE uint32_t __get_APSR(void)
 167 {
 168   register uint32_t __regAPSR          __ASM("apsr");
 169   return(__regAPSR);
 170 }
 171
 172
 173 /**
 174   \brief   Get xPSR Register
 175   \details Returns the content of the xPSR Register.
 176   \return               xPSR Register value
 177  */
 178 __STATIC_INLINE uint32_t __get_xPSR(void)
 179 {
 180   register uint32_t __regXPSR          __ASM("xpsr");
 181   return(__regXPSR);
 182 }
 183
 184
 185 /**
 186   \brief   Get Process Stack Pointer
 187   \details Returns the current value of the Process Stack Pointer (PSP).
 188   \return               PSP Register value
 189  */
 190 __STATIC_INLINE uint32_t __get_PSP(void)
 191 {
 192   register uint32_t __regProcessStackPointer  __ASM("psp");
 193   return(__regProcessStackPointer);
 194 }
 195
 196
 197 /**
 198   \brief   Set Process Stack Pointer
 199   \details Assigns the given value to the Process Stack Pointer (PSP).
 200   \param [in]    topOfProcStack  Process Stack Pointer value to set
 201  */
 202 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 203 {
 204   register uint32_t __regProcessStackPointer  __ASM("psp");
 205   __regProcessStackPointer = topOfProcStack;
 206 }
 207
 208
 209 /**
 210   \brief   Get Main Stack Pointer
 211   \details Returns the current value of the Main Stack Pointer (MSP).
 212   \return               MSP Register value
 213  */
 214 __STATIC_INLINE uint32_t __get_MSP(void)
 215 {
 216   register uint32_t __regMainStackPointer     __ASM("msp");
 217   return(__regMainStackPointer);
 218 }
 219
 220
 221 /**
 222   \brief   Set Main Stack Pointer
 223   \details Assigns the given value to the Main Stack Pointer (MSP).
 224   \param [in]    topOfMainStack  Main Stack Pointer value to set
 225  */
 226 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 227 {
 228   register uint32_t __regMainStackPointer     __ASM("msp");
 229   __regMainStackPointer = topOfMainStack;
 230 }
 231
 232
 233 /**
 234   \brief   Get Priority Mask
 235   \details Returns the current state of the priority mask bit from the Priority Mask Register.
 236   \return               Priority Mask value
 237  */
 238 __STATIC_INLINE uint32_t __get_PRIMASK(void)
 239 {
 240   register uint32_t __regPriMask         __ASM("primask");
 241   return(__regPriMask);
 242 }
 243
 244
 245 /**
 246   \brief   Set Priority Mask
 247   \details Assigns the given value to the Priority Mask Register.
 248   \param [in]    priMask  Priority Mask
 249  */
 250 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 251 {
 252   register uint32_t __regPriMask         __ASM("primask");
 253   __regPriMask = (priMask);
 254 }
 255
 256
 257 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
 258      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 259
 260 /**
 261   \brief   Enable FIQ
 262   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
 263            Can only be executed in Privileged modes.
 264  */
 265 #define __enable_fault_irq                __enable_fiq
 266
 267
 268 /**
 269   \brief   Disable FIQ
 270   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
 271            Can only be executed in Privileged modes.
 272  */
 273 #define __disable_fault_irq               __disable_fiq
 274
 275
 276 /**
 277   \brief   Get Base Priority
 278   \details Returns the current value of the Base Priority register.
 279   \return               Base Priority register value
 280  */
 281 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
 282 {
 283   register uint32_t __regBasePri         __ASM("basepri");
 284   return(__regBasePri);
 285 }
 286
 287
 288 /**
 289   \brief   Set Base Priority
 290   \details Assigns the given value to the Base Priority register.
 291   \param [in]    basePri  Base Priority value to set
 292  */
 293 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 294 {
 295   register uint32_t __regBasePri         __ASM("basepri");
 296   __regBasePri = (basePri & 0xFFU);
 297 }
 298
 299
 300 /**
 301   \brief   Set Base Priority with condition
 302   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
 303            or the new value increases the BASEPRI priority level.
 304   \param [in]    basePri  Base Priority value to set
 305  */
 306 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
 307 {
 308   register uint32_t __regBasePriMax      __ASM("basepri_max");
 309   __regBasePriMax = (basePri & 0xFFU);
 310 }
 311
 312
 313 /**
 314   \brief   Get Fault Mask
 315   \details Returns the current value of the Fault Mask register.
 316   \return               Fault Mask register value
 317  */
 318 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 319 {
 320   register uint32_t __regFaultMask       __ASM("faultmask");
 321   return(__regFaultMask);
 322 }
 323
 324
 325 /**
 326   \brief   Set Fault Mask
 327   \details Assigns the given value to the Fault Mask register.
 328   \param [in]    faultMask  Fault Mask value to set
 329  */
 330 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 331 {
 332   register uint32_t __regFaultMask       __ASM("faultmask");
 333   __regFaultMask = (faultMask & (uint32_t)1U);
 334 }
 335
 336 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
 337            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 338
 339
 340 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 341
 342 /**
 343   \brief   Get FPSCR
 344   \details Returns the current value of the Floating Point Status/Control register.
 345   \return               Floating Point Status/Control register value
 346  */
 347 __STATIC_INLINE uint32_t __get_FPSCR(void)
 348 {
 349 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 350      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 351   register uint32_t __regfpscr         __ASM("fpscr");
 352   return(__regfpscr);
 353 #else
 354    return(0U);
 355 #endif
 356 }
 357
 358
 359 /**
 360   \brief   Set FPSCR
 361   \details Assigns the given value to the Floating Point Status/Control register.
 362   \param [in]    fpscr  Floating Point Status/Control value to set
 363  */
 364 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 365 {
 366 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 367      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 368   register uint32_t __regfpscr         __ASM("fpscr");
 369   __regfpscr = (fpscr);
 370 #else
 371   (void)fpscr;
 372 #endif
 373 }
 374
 375 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 376
 377
 378
 379 /*@} end of CMSIS_Core_RegAccFunctions */
 380
 381
 382 /* ##########################  Core Instruction Access  ######################### */
 383 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 384   Access to dedicated instructions
 385   @{
 386 */
 387
 388 /**
 389   \brief   No Operation
 390   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 391  */
 392 #define __NOP                             __nop
 393
 394
 395 /**
 396   \brief   Wait For Interrupt
 397   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
 398  */
 399 #define __WFI                             __wfi
 400
 401
 402 /**
 403   \brief   Wait For Event
 404   \details Wait For Event is a hint instruction that permits the processor to enter
 405            a low-power state until one of a number of events occurs.
 406  */
 407 #define __WFE                             __wfe
 408
 409
 410 /**
 411   \brief   Send Event
 412   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 413  */
 414 #define __SEV                             __sev
 415
 416
 417 /**
 418   \brief   Instruction Synchronization Barrier
 419   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 420            so that all instructions following the ISB are fetched from cache or memory,
 421            after the instruction has been completed.
 422  */
 423 #define __ISB() do {\
 424                    __schedule_barrier();\
 425                    __isb(0xF);\
 426                    __schedule_barrier();\
 427                 } while (0U)
 428
 429 /**
 430   \brief   Data Synchronization Barrier
 431   \details Acts as a special kind of Data Memory Barrier.
 432            It completes when all explicit memory accesses before this instruction complete.
 433  */
 434 #define __DSB() do {\
 435                    __schedule_barrier();\
 436                    __dsb(0xF);\
 437                    __schedule_barrier();\
 438                 } while (0U)
 439
 440 /**
 441   \brief   Data Memory Barrier
 442   \details Ensures the apparent order of the explicit memory operations before
 443            and after the instruction, without ensuring their completion.
 444  */
 445 #define __DMB() do {\
 446                    __schedule_barrier();\
 447                    __dmb(0xF);\
 448                    __schedule_barrier();\
 449                 } while (0U)
 450
 451
 452 /**
 453   \brief   Reverse byte order (32 bit)
 454   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
 455   \param [in]    value  Value to reverse
 456   \return               Reversed value
 457  */
 458 #define __REV                             __rev
 459
 460
 461 /**
 462   \brief   Reverse byte order (16 bit)
 463   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
 464   \param [in]    value  Value to reverse
 465   \return               Reversed value
 466  */
 467 #ifndef __NO_EMBEDDED_ASM
 468 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 469 {
 470   rev16 r0, r0
 471   bx lr
 472 }
 473 #endif
 474
 475
 476 /**
 477   \brief   Reverse byte order (16 bit)
 478   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
 479   \param [in]    value  Value to reverse
 480   \return               Reversed value
 481  */
 482 #ifndef __NO_EMBEDDED_ASM
 483 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
 484 {
 485   revsh r0, r0
 486   bx lr
 487 }
 488 #endif
 489
 490
 491 /**
 492   \brief   Rotate Right in unsigned value (32 bit)
 493   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
 494   \param [in]    op1  Value to rotate
 495   \param [in]    op2  Number of Bits to rotate
 496   \return               Rotated value
 497  */
 498 #define __ROR                             __ror
 499
 500
 501 /**
 502   \brief   Breakpoint
 503   \details Causes the processor to enter Debug state.
 504            Debug tools can use this to investigate system state when the instruction at a particular address is reached.
 505   \param [in]    value  is ignored by the processor.
 506                  If required, a debugger can use it to store additional information about the breakpoint.
 507  */
 508 #define __BKPT(value)                       __breakpoint(value)
 509
 510
 511 /**
 512   \brief   Reverse bit order of value
 513   \details Reverses the bit order of the given value.
 514   \param [in]    value  Value to reverse
 515   \return               Reversed value
 516  */
 517 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
 518      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 519   #define __RBIT                          __rbit
 520 #else
 521 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 522 {
 523   uint32_t result;
 524   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 525
 526   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 527   for (value >>= 1U; value != 0U; value >>= 1U)
 528   {
 529     result <<= 1U;
 530     result |= value & 1U;
 531     s--;
 532   }
 533   result <<= s;                        /* shift when v's highest bits are zero */
 534   return result;
 535 }
 536 #endif
 537
 538
 539 /**
 540   \brief   Count leading zeros
 541   \details Counts the number of leading zeros of a data value.
 542   \param [in]  value  Value to count the leading zeros
 543   \return             number of leading zeros in value
 544  */
 545 #define __CLZ                             __clz
 546
 547
 548 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
 549      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 550
 551 /**
 552   \brief   LDR Exclusive (8 bit)
 553   \details Executes a exclusive LDR instruction for 8 bit value.
 554   \param [in]    ptr  Pointer to data
 555   \return             value of type uint8_t at (*ptr)
 556  */
 557 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
 558   #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
 559 #else
 560   #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
 561 #endif
 562
 563
 564 /**
 565   \brief   LDR Exclusive (16 bit)
 566   \details Executes a exclusive LDR instruction for 16 bit values.
 567   \param [in]    ptr  Pointer to data
 568   \return        value of type uint16_t at (*ptr)
 569  */
 570 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
 571   #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
 572 #else
 573   #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
 574 #endif
 575
 576
 577 /**
 578   \brief   LDR Exclusive (32 bit)
 579   \details Executes a exclusive LDR instruction for 32 bit values.
 580   \param [in]    ptr  Pointer to data
 581   \return        value of type uint32_t at (*ptr)
 582  */
 583 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
 584   #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
 585 #else
 586   #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
 587 #endif
 588
 589
 590 /**
 591   \brief   STR Exclusive (8 bit)
 592   \details Executes a exclusive STR instruction for 8 bit values.
 593   \param [in]  value  Value to store
 594   \param [in]    ptr  Pointer to location
 595   \return          0  Function succeeded
 596   \return          1  Function failed
 597  */
 598 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
 599   #define __STREXB(value, ptr)                                                 __strex(value, ptr)
 600 #else
 601   #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 602 #endif
 603
 604
 605 /**
 606   \brief   STR Exclusive (16 bit)
 607   \details Executes a exclusive STR instruction for 16 bit values.
 608   \param [in]  value  Value to store
 609   \param [in]    ptr  Pointer to location
 610   \return          0  Function succeeded
 611   \return          1  Function failed
 612  */
 613 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
 614   #define __STREXH(value, ptr)                                                 __strex(value, ptr)
 615 #else
 616   #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 617 #endif
 618
 619
 620 /**
 621   \brief   STR Exclusive (32 bit)
 622   \details Executes a exclusive STR instruction for 32 bit values.
 623   \param [in]  value  Value to store
 624   \param [in]    ptr  Pointer to location
 625   \return          0  Function succeeded
 626   \return          1  Function failed
 627  */
 628 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
 629   #define __STREXW(value, ptr)                                                 __strex(value, ptr)
 630 #else
 631   #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 632 #endif
 633
 634
 635 /**
 636   \brief   Remove the exclusive lock
 637   \details Removes the exclusive lock which is created by LDREX.
 638  */
 639 #define __CLREX                           __clrex
 640
 641
 642 /**
 643   \brief   Signed Saturate
 644   \details Saturates a signed value.
 645   \param [in]  value  Value to be saturated
 646   \param [in]    sat  Bit position to saturate to (1..32)
 647   \return             Saturated value
 648  */
 649 #define __SSAT                            __ssat
 650
 651
 652 /**
 653   \brief   Unsigned Saturate
 654   \details Saturates an unsigned value.
 655   \param [in]  value  Value to be saturated
 656   \param [in]    sat  Bit position to saturate to (0..31)
 657   \return             Saturated value
 658  */
 659 #define __USAT                            __usat
 660
 661
 662 /**
 663   \brief   Rotate Right with Extend (32 bit)
 664   \details Moves each bit of a bitstring right by one bit.
 665            The carry input is shifted in at the left end of the bitstring.
 666   \param [in]    value  Value to rotate
 667   \return               Rotated value
 668  */
 669 #ifndef __NO_EMBEDDED_ASM
 670 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
 671 {
 672   rrx r0, r0
 673   bx lr
 674 }
 675 #endif
 676
 677
 678 /**
 679   \brief   LDRT Unprivileged (8 bit)
 680   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 681   \param [in]    ptr  Pointer to data
 682   \return             value of type uint8_t at (*ptr)
 683  */
 684 #define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
 685
 686
 687 /**
 688   \brief   LDRT Unprivileged (16 bit)
 689   \details Executes a Unprivileged LDRT instruction for 16 bit values.
 690   \param [in]    ptr  Pointer to data
 691   \return        value of type uint16_t at (*ptr)
 692  */
 693 #define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
 694
 695
 696 /**
 697   \brief   LDRT Unprivileged (32 bit)
 698   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 699   \param [in]    ptr  Pointer to data
 700   \return        value of type uint32_t at (*ptr)
 701  */
 702 #define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
 703
 704
 705 /**
 706   \brief   STRT Unprivileged (8 bit)
 707   \details Executes a Unprivileged STRT instruction for 8 bit values.
 708   \param [in]  value  Value to store
 709   \param [in]    ptr  Pointer to location
 710  */
 711 #define __STRBT(value, ptr)               __strt(value, ptr)
 712
 713
 714 /**
 715   \brief   STRT Unprivileged (16 bit)
 716   \details Executes a Unprivileged STRT instruction for 16 bit values.
 717   \param [in]  value  Value to store
 718   \param [in]    ptr  Pointer to location
 719  */
 720 #define __STRHT(value, ptr)               __strt(value, ptr)
 721
 722
 723 /**
 724   \brief   STRT Unprivileged (32 bit)
 725   \details Executes a Unprivileged STRT instruction for 32 bit values.
 726   \param [in]  value  Value to store
 727   \param [in]    ptr  Pointer to location
 728  */
 729 #define __STRT(value, ptr)                __strt(value, ptr)
 730
 731 #else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
 732            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 733
 734 /**
 735   \brief   Signed Saturate
 736   \details Saturates a signed value.
 737   \param [in]  value  Value to be saturated
 738   \param [in]    sat  Bit position to saturate to (1..32)
 739   \return             Saturated value
 740  */
 741 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
 742 {
 743   if ((sat >= 1U) && (sat <= 32U))
 744   {
 745     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 746     const int32_t min = -1 - max ;
 747     if (val > max)
 748     {
 749       return max;
 750     }
 751     else if (val < min)
 752     {
 753       return min;
 754     }
 755   }
 756   return val;
 757 }
 758
 759 /**
 760   \brief   Unsigned Saturate
 761   \details Saturates an unsigned value.
 762   \param [in]  value  Value to be saturated
 763   \param [in]    sat  Bit position to saturate to (0..31)
 764   \return             Saturated value
 765  */
 766 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
 767 {
 768   if (sat <= 31U)
 769   {
 770     const uint32_t max = ((1U << sat) - 1U);
 771     if (val > (int32_t)max)
 772     {
 773       return max;
 774     }
 775     else if (val < 0)
 776     {
 777       return 0U;
 778     }
 779   }
 780   return (uint32_t)val;
 781 }
 782
 783 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
 784            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 785
 786 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 787
 788
 789 /* ###################  Compiler specific Intrinsics  ########################### */
 790 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
 791   Access to dedicated SIMD instructions
 792   @{
 793 */
 794
 795 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 796
 797 #define __SADD8                           __sadd8
 798 #define __QADD8                           __qadd8
 799 #define __SHADD8                          __shadd8
 800 #define __UADD8                           __uadd8
 801 #define __UQADD8                          __uqadd8
 802 #define __UHADD8                          __uhadd8
 803 #define __SSUB8                           __ssub8
 804 #define __QSUB8                           __qsub8
 805 #define __SHSUB8                          __shsub8
 806 #define __USUB8                           __usub8
 807 #define __UQSUB8                          __uqsub8
 808 #define __UHSUB8                          __uhsub8
 809 #define __SADD16                          __sadd16
 810 #define __QADD16                          __qadd16
 811 #define __SHADD16                         __shadd16
 812 #define __UADD16                          __uadd16
 813 #define __UQADD16                         __uqadd16
 814 #define __UHADD16                         __uhadd16
 815 #define __SSUB16                          __ssub16
 816 #define __QSUB16                          __qsub16
 817 #define __SHSUB16                         __shsub16
 818 #define __USUB16                          __usub16
 819 #define __UQSUB16                         __uqsub16
 820 #define __UHSUB16                         __uhsub16
 821 #define __SASX                            __sasx
 822 #define __QASX                            __qasx
 823 #define __SHASX                           __shasx
 824 #define __UASX                            __uasx
 825 #define __UQASX                           __uqasx
 826 #define __UHASX                           __uhasx
 827 #define __SSAX                            __ssax
 828 #define __QSAX                            __qsax
 829 #define __SHSAX                           __shsax
 830 #define __USAX                            __usax
 831 #define __UQSAX                           __uqsax
 832 #define __UHSAX                           __uhsax
 833 #define __USAD8                           __usad8
 834 #define __USADA8                          __usada8
 835 #define __SSAT16                          __ssat16
 836 #define __USAT16                          __usat16
 837 #define __UXTB16                          __uxtb16
 838 #define __UXTAB16                         __uxtab16
 839 #define __SXTB16                          __sxtb16
 840 #define __SXTAB16                         __sxtab16
 841 #define __SMUAD                           __smuad
 842 #define __SMUADX                          __smuadx
 843 #define __SMLAD                           __smlad
 844 #define __SMLADX                          __smladx
 845 #define __SMLALD                          __smlald
 846 #define __SMLALDX                         __smlaldx
 847 #define __SMUSD                           __smusd
 848 #define __SMUSDX                          __smusdx
 849 #define __SMLSD                           __smlsd
 850 #define __SMLSDX                          __smlsdx
 851 #define __SMLSLD                          __smlsld
 852 #define __SMLSLDX                         __smlsldx
 853 #define __SEL                             __sel
 854 #define __QADD                            __qadd
 855 #define __QSUB                            __qsub
 856
 857 #define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
 858                                            ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
 859
 860 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
 861                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
 862
 863 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
 864                                                       ((int64_t)(ARG3) << 32U)     ) >> 32U))
 865
 866 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 867 /*@} end of group CMSIS_SIMD_intrinsics */
 868
 869
 870 #endif /* __CMSIS_ARMCC_H */