lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   Header file of NAND HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_NAND_H
  40 #define __STM32F4xx_HAL_NAND_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
  48   #include "stm32f4xx_ll_fsmc.h"
  49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
  50
  51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
  52     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
  53   #include "stm32f4xx_ll_fmc.h"
  54 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
  55           STM32F479xx */
  56
  57 /** @addtogroup STM32F4xx_HAL_Driver
  58   * @{
  59   */
  60
  61 /** @addtogroup NAND
  62   * @{
  63   */
  64
  65 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
  66     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
  67     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
  68
  69 /* Exported typedef ----------------------------------------------------------*/
  70 /* Exported types ------------------------------------------------------------*/
  71 /** @defgroup NAND_Exported_Types NAND Exported Types
  72   * @{
  73   */
  74
  75 /**
  76   * @brief  HAL NAND State structures definition
  77   */
  78 typedef enum
  79 {
  80   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  81   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  82   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  83   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  84 }HAL_NAND_StateTypeDef;
  85
  86 /**
  87   * @brief  NAND Memory electronic signature Structure definition
  88   */
  89 typedef struct
  90 {
  91   /*<! NAND memory electronic signature maker and device IDs */
  92
  93   uint8_t Maker_Id;
  94
  95   uint8_t Device_Id;
  96
  97   uint8_t Third_Id;
  98
  99   uint8_t Fourth_Id;
 100 }NAND_IDTypeDef;
 101
 102 /**
 103   * @brief  NAND Memory address Structure definition
 104   */
 105 typedef struct
 106 {
 107   uint16_t Page;   /*!< NAND memory Page address    */
 108
 109   uint16_t Plane;   /*!< NAND memory Plane address  */
 110
 111   uint16_t Block;  /*!< NAND memory Block address   */
 112
 113 }NAND_AddressTypeDef;
 114
 115 /**
 116   * @brief  NAND Memory info Structure definition
 117   */
 118 typedef struct
 119 {
 120   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
 121                                               for 8 bits adressing or words for 16 bits addressing             */
 122
 123   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
 124                                               for 8 bits adressing or words for 16 bits addressing             */
 125
 126   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
 127
 128   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
 129
 130   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 131
 132   uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks               */
 133
 134   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 135                                               parameter is mandatory for some NAND parts after the read
 136                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 137                                               Example: Toshiba THTH58BYG3S0HBAI6.
 138                                               This parameter could be ENABLE or DISABLE
 139                                               Please check the Read Mode sequnece in the NAND device datasheet */
 140 }NAND_DeviceConfigTypeDef;
 141
 142 /**
 143   * @brief  NAND handle Structure definition
 144   */
 145 typedef struct
 146 {
 147   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
 148
 149   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 150
 151   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 152
 153   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 154
 155   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 156
 157 }NAND_HandleTypeDef;
 158 /**
 159   * @}
 160   */
 161
 162 /* Exported constants --------------------------------------------------------*/
 163 /* Exported macros ------------------------------------------------------------*/
 164 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 165  * @{
 166  */
 167
 168 /** @brief Reset NAND handle state
 169   * @param  __HANDLE__: specifies the NAND handle.
 170   * @retval None
 171   */
 172 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 173
 174 /**
 175   * @}
 176   */
 177
 178 /* Exported functions --------------------------------------------------------*/
 179 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 180   * @{
 181   */
 182
 183 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 184   * @{
 185   */
 186
 187 /* Initialization/de-initialization functions  ********************************/
 188 /* Initialization/de-initialization functions  ********************************/
 189 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 190 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 191
 192 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 193
 194 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 195
 196 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 197 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 198 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 199 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 200
 201 /**
 202   * @}
 203   */
 204
 205 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 206   * @{
 207   */
 208
 209 /* IO operation functions  ****************************************************/
 210 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 211
 212 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 213 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 214 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 215 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 216
 217 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 218 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 219 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 220 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 221
 222 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 223
 224 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 225 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 226
 227 /**
 228   * @}
 229   */
 230
 231 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 232   * @{
 233   */
 234
 235 /* NAND Control functions  ****************************************************/
 236 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 237 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 238 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 239
 240 /**
 241   * @}
 242   */
 243
 244 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
 245   * @{
 246   */
 247 /* NAND State functions *******************************************************/
 248 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 249 /**
 250   * @}
 251   */
 252
 253 /**
 254   * @}
 255   */
 256
 257 /* Private types -------------------------------------------------------------*/
 258 /* Private variables ---------------------------------------------------------*/
 259 /* Private constants ---------------------------------------------------------*/
 260 /** @defgroup NAND_Private_Constants NAND Private Constants
 261   * @{
 262   */
 263 #define NAND_DEVICE1               0x70000000U
 264 #define NAND_DEVICE2               0x80000000U
 265 #define NAND_WRITE_TIMEOUT         0x01000000U
 266
 267 #define CMD_AREA                   ((uint32_t)(1U<<16U))  /* A16 = CLE high */
 268 #define ADDR_AREA                  ((uint32_t)(1U<<17U))  /* A17 = ALE high */
 269
 270 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
 271 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
 272 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
 273 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
 274
 275 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
 276 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
 277 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
 278 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
 279 #define NAND_CMD_READID            ((uint8_t)0x90)
 280 #define NAND_CMD_STATUS            ((uint8_t)0x70)
 281 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
 282 #define NAND_CMD_RESET             ((uint8_t)0xFF)
 283
 284 /* NAND memory status */
 285 #define NAND_VALID_ADDRESS         0x00000100U
 286 #define NAND_INVALID_ADDRESS       0x00000200U
 287 #define NAND_TIMEOUT_ERROR         0x00000400U
 288 #define NAND_BUSY                  0x00000000U
 289 #define NAND_ERROR                 0x00000001U
 290 #define NAND_READY                 0x00000040U
 291 /**
 292   * @}
 293   */
 294
 295 /* Private macros ------------------------------------------------------------*/
 296 /** @defgroup NAND_Private_Macros NAND Private Macros
 297   * @{
 298   */
 299
 300 /**
 301   * @brief  NAND memory address computation.
 302   * @param  __ADDRESS__: NAND memory address.
 303   * @param  __HANDLE__: NAND handle.
 304   * @retval NAND Raw address value
 305   */
 306 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 307                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 308
 309 /**
 310   * @brief  NAND memory Column address computation.
 311   * @param  __HANDLE__: NAND handle.
 312   * @retval NAND Raw address value
 313   */
 314 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 315
 316 /**
 317   * @brief  NAND memory address cycling.
 318   * @param  __ADDRESS__: NAND memory address.
 319   * @retval NAND address cycling value.
 320   */
 321 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 322 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 323 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 324 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 325
 326 /**
 327   * @brief  NAND memory Columns cycling.
 328   * @param  __ADDRESS__: NAND memory address.
 329   * @retval NAND Column address cycling value.
 330   */
 331 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
 332 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 333
 334 /**
 335   * @}
 336   */
 337 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
 338           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
 339           STM32F446xx || STM32F469xx || STM32F479xx */
 340
 341 /**
 342   * @}
 343   */
 344 /**
 345   * @}
 346   */
 347
 348 /**
 349   * @}
 350   */
 351
 352 #ifdef __cplusplus
 353 }
 354 #endif
 355
 356 #endif /* __STM32F4xx_HAL_NAND_H */
 357
 358 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/