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FIX: Flash page size check is STM (or clone) specific (#14130)
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_dma.h
blob4a0181741b63fedbce27e497f92e83a93d39537e
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of DMA LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_DMA_H
40 #define __STM32F4xx_LL_DMA_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx.h"
48
49 /** @addtogroup STM32F4xx_LL_Driver
50 * @{
51 */
52
53 #if defined (DMA1) || defined (DMA2)
54
55 /** @defgroup DMA_LL DMA
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
62 * @{
63 */
64 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
65 static const uint8_t STREAM_OFFSET_TAB[] =
66 {
67 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
68 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
70 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
72 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
73 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
74 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
75 };
76
77 /**
78 * @}
79 */
80
81 /* Private constants ---------------------------------------------------------*/
82 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
83 * @{
84 */
85 /**
86 * @}
87 */
88
89
90 /* Private macros ------------------------------------------------------------*/
91 /* Exported types ------------------------------------------------------------*/
92 #if defined(USE_FULL_LL_DRIVER)
93 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
94 * @{
95 */
96 typedef struct
97 {
98 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
99 or as Source base address in case of memory to memory transfer direction.
100
101 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
102
103 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
104 or as Destination base address in case of memory to memory transfer direction.
105
106 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
107
108 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
109 from memory to memory or from peripheral to memory.
110 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
111
112 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
113
114 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
115 This parameter can be a value of @ref DMA_LL_EC_MODE
116 @note The circular buffer mode cannot be used if the memory to memory
117 data transfer direction is configured on the selected Stream
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
120
121 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
122 is incremented or not.
123 This parameter can be a value of @ref DMA_LL_EC_PERIPH
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
126
127 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
128 is incremented or not.
129 This parameter can be a value of @ref DMA_LL_EC_MEMORY
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
132
133 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
134 in case of memory to memory transfer direction.
135 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
136
137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
138
139 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
140 in case of memory to memory transfer direction.
141 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
142
143 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
144
145 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
146 The data unit is equal to the source buffer configuration set in PeripheralSize
147 or MemorySize parameters depending in the transfer direction.
148 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
149
150 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
151
152 uint32_t Channel; /*!< Specifies the peripheral channel.
153 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
154
155 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
156
157 uint32_t Priority; /*!< Specifies the channel priority level.
158 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
159
160 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
161
162 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
163 This parameter can be a value of @ref DMA_LL_FIFOMODE
164 @note The Direct mode (FIFO mode disabled) cannot be used if the
165 memory-to-memory data transfer is configured on the selected stream
166
167 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
168
169 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
170 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
171
172 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
173
174 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
175 It specifies the amount of data to be transferred in a single non interruptible
176 transaction.
177 This parameter can be a value of @ref DMA_LL_EC_MBURST
178 @note The burst mode is possible only if the address Increment mode is enabled.
179
180 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
181
182 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
183 It specifies the amount of data to be transferred in a single non interruptible
184 transaction.
185 This parameter can be a value of @ref DMA_LL_EC_PBURST
186 @note The burst mode is possible only if the address Increment mode is enabled.
187
188 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
189
190 } LL_DMA_InitTypeDef;
191 /**
192 * @}
193 */
194 #endif /*USE_FULL_LL_DRIVER*/
195 /* Exported constants --------------------------------------------------------*/
196 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
197 * @{
198 */
199
200 /** @defgroup DMA_LL_EC_STREAM STREAM
201 * @{
202 */
203 #define LL_DMA_STREAM_0 0x00000000U
204 #define LL_DMA_STREAM_1 0x00000001U
205 #define LL_DMA_STREAM_2 0x00000002U
206 #define LL_DMA_STREAM_3 0x00000003U
207 #define LL_DMA_STREAM_4 0x00000004U
208 #define LL_DMA_STREAM_5 0x00000005U
209 #define LL_DMA_STREAM_6 0x00000006U
210 #define LL_DMA_STREAM_7 0x00000007U
211 #define LL_DMA_STREAM_ALL 0xFFFF0000U
212 /**
213 * @}
214 */
215
216 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
217 * @{
218 */
219 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
220 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
221 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
222 /**
223 * @}
224 */
225
226 /** @defgroup DMA_LL_EC_MODE MODE
227 * @{
228 */
229 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
230 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
231 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
232 /**
233 * @}
234 */
235
236 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
237 * @{
238 */
239 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
240 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
241 /**
242 * @}
243 */
244
245 /** @defgroup DMA_LL_EC_PERIPH PERIPH
246 * @{
247 */
248 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
249 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
250 /**
251 * @}
252 */
253
254 /** @defgroup DMA_LL_EC_MEMORY MEMORY
255 * @{
256 */
257 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
258 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
259 /**
260 * @}
261 */
262
263 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
264 * @{
265 */
266 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
267 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
268 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
269 /**
270 * @}
271 */
272
273 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
274 * @{
275 */
276 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
277 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
278 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
279 /**
280 * @}
281 */
282
283 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
284 * @{
285 */
286 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
287 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
288 /**
289 * @}
290 */
291
292 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
293 * @{
294 */
295 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
296 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
297 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
298 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
299 /**
300 * @}
301 */
302
303 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
304 * @{
305 */
306 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
307 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
308 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
309 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
310 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
311 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
312 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
313 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
314 /**
315 * @}
316 */
317
318 /** @defgroup DMA_LL_EC_MBURST MBURST
319 * @{
320 */
321 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
322 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
323 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
324 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
325 /**
326 * @}
327 */
328
329 /** @defgroup DMA_LL_EC_PBURST PBURST
330 * @{
331 */
332 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
333 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
334 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
335 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
336 /**
337 * @}
338 */
339
340 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
341 * @{
342 */
343 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
344 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
345 /**
346 * @}
347 */
348
349 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
350 * @{
351 */
352 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
353 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
354 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
355 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
356 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
357 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
358 /**
359 * @}
360 */
361
362 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
363 * @{
364 */
365 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
366 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
367 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
368 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
369 /**
370 * @}
371 */
372
373 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
374 * @{
375 */
376 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
377 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
378 /**
379 * @}
380 */
381
382 /**
383 * @}
384 */
385
386 /* Exported macro ------------------------------------------------------------*/
387 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
388 * @{
389 */
390
391 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
392 * @{
393 */
394 /**
395 * @brief Write a value in DMA register
396 * @param __INSTANCE__ DMA Instance
397 * @param __REG__ Register to be written
398 * @param __VALUE__ Value to be written in the register
399 * @retval None
400 */
401 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
402
403 /**
404 * @brief Read a value in DMA register
405 * @param __INSTANCE__ DMA Instance
406 * @param __REG__ Register to be read
407 * @retval Register value
408 */
409 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
410 /**
411 * @}
412 */
413
414 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
415 * @{
416 */
417 /**
418 * @brief Convert DMAx_Streamy into DMAx
419 * @param __STREAM_INSTANCE__ DMAx_Streamy
420 * @retval DMAx
421 */
422 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
423 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
424
425 /**
426 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
427 * @param __STREAM_INSTANCE__ DMAx_Streamy
428 * @retval LL_DMA_CHANNEL_y
429 */
430 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
431 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
437 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
438 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
439 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
440 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
441 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
442 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
443 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
444 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
445 LL_DMA_STREAM_7)
446
447 /**
448 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
449 * @param __DMA_INSTANCE__ DMAx
450 * @param __STREAM__ LL_DMA_STREAM_y
451 * @retval DMAx_Streamy
452 */
453 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
454 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
467 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
469 DMA2_Stream7)
470
471 /**
472 * @}
473 */
474
475 /**
476 * @}
477 */
478
479
480 /* Exported functions --------------------------------------------------------*/
481 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
482 * @{
483 */
484
485 /** @defgroup DMA_LL_EF_Configuration Configuration
486 * @{
487 */
488 /**
489 * @brief Enable DMA stream.
490 * @rmtoll CR EN LL_DMA_EnableStream
491 * @param DMAx DMAx Instance
492 * @param Stream This parameter can be one of the following values:
493 * @arg @ref LL_DMA_STREAM_0
494 * @arg @ref LL_DMA_STREAM_1
495 * @arg @ref LL_DMA_STREAM_2
496 * @arg @ref LL_DMA_STREAM_3
497 * @arg @ref LL_DMA_STREAM_4
498 * @arg @ref LL_DMA_STREAM_5
499 * @arg @ref LL_DMA_STREAM_6
500 * @arg @ref LL_DMA_STREAM_7
501 * @retval None
502 */
503 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
504 {
505 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
506 }
507
508 /**
509 * @brief Disable DMA stream.
510 * @rmtoll CR EN LL_DMA_DisableStream
511 * @param DMAx DMAx Instance
512 * @param Stream This parameter can be one of the following values:
513 * @arg @ref LL_DMA_STREAM_0
514 * @arg @ref LL_DMA_STREAM_1
515 * @arg @ref LL_DMA_STREAM_2
516 * @arg @ref LL_DMA_STREAM_3
517 * @arg @ref LL_DMA_STREAM_4
518 * @arg @ref LL_DMA_STREAM_5
519 * @arg @ref LL_DMA_STREAM_6
520 * @arg @ref LL_DMA_STREAM_7
521 * @retval None
522 */
523 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
524 {
525 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
526 }
527
528 /**
529 * @brief Check if DMA stream is enabled or disabled.
530 * @rmtoll CR EN LL_DMA_IsEnabledStream
531 * @param DMAx DMAx Instance
532 * @param Stream This parameter can be one of the following values:
533 * @arg @ref LL_DMA_STREAM_0
534 * @arg @ref LL_DMA_STREAM_1
535 * @arg @ref LL_DMA_STREAM_2
536 * @arg @ref LL_DMA_STREAM_3
537 * @arg @ref LL_DMA_STREAM_4
538 * @arg @ref LL_DMA_STREAM_5
539 * @arg @ref LL_DMA_STREAM_6
540 * @arg @ref LL_DMA_STREAM_7
541 * @retval State of bit (1 or 0).
542 */
543 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
544 {
545 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
546 }
547
548 /**
549 * @brief Configure all parameters linked to DMA transfer.
550 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
551 * CR CIRC LL_DMA_ConfigTransfer\n
552 * CR PINC LL_DMA_ConfigTransfer\n
553 * CR MINC LL_DMA_ConfigTransfer\n
554 * CR PSIZE LL_DMA_ConfigTransfer\n
555 * CR MSIZE LL_DMA_ConfigTransfer\n
556 * CR PL LL_DMA_ConfigTransfer\n
557 * CR PFCTRL LL_DMA_ConfigTransfer
558 * @param DMAx DMAx Instance
559 * @param Stream This parameter can be one of the following values:
560 * @arg @ref LL_DMA_STREAM_0
561 * @arg @ref LL_DMA_STREAM_1
562 * @arg @ref LL_DMA_STREAM_2
563 * @arg @ref LL_DMA_STREAM_3
564 * @arg @ref LL_DMA_STREAM_4
565 * @arg @ref LL_DMA_STREAM_5
566 * @arg @ref LL_DMA_STREAM_6
567 * @arg @ref LL_DMA_STREAM_7
568 * @param Configuration This parameter must be a combination of all the following values:
569 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
570 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
571 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
572 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
573 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
574 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
575 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
576 *@retval None
577 */
578 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
579 {
580 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
581 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
582 Configuration);
583 }
584
585 /**
586 * @brief Set Data transfer direction (read from peripheral or from memory).
587 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
588 * @param DMAx DMAx Instance
589 * @param Stream This parameter can be one of the following values:
590 * @arg @ref LL_DMA_STREAM_0
591 * @arg @ref LL_DMA_STREAM_1
592 * @arg @ref LL_DMA_STREAM_2
593 * @arg @ref LL_DMA_STREAM_3
594 * @arg @ref LL_DMA_STREAM_4
595 * @arg @ref LL_DMA_STREAM_5
596 * @arg @ref LL_DMA_STREAM_6
597 * @arg @ref LL_DMA_STREAM_7
598 * @param Direction This parameter can be one of the following values:
599 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
600 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
601 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
602 * @retval None
603 */
604 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
605 {
606 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
607 }
608
609 /**
610 * @brief Get Data transfer direction (read from peripheral or from memory).
611 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
612 * @param DMAx DMAx Instance
613 * @param Stream This parameter can be one of the following values:
614 * @arg @ref LL_DMA_STREAM_0
615 * @arg @ref LL_DMA_STREAM_1
616 * @arg @ref LL_DMA_STREAM_2
617 * @arg @ref LL_DMA_STREAM_3
618 * @arg @ref LL_DMA_STREAM_4
619 * @arg @ref LL_DMA_STREAM_5
620 * @arg @ref LL_DMA_STREAM_6
621 * @arg @ref LL_DMA_STREAM_7
622 * @retval Returned value can be one of the following values:
623 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
624 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
625 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
626 */
627 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
628 {
629 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
630 }
631
632 /**
633 * @brief Set DMA mode normal, circular or peripheral flow control.
634 * @rmtoll CR CIRC LL_DMA_SetMode\n
635 * CR PFCTRL LL_DMA_SetMode
636 * @param DMAx DMAx Instance
637 * @param Stream This parameter can be one of the following values:
638 * @arg @ref LL_DMA_STREAM_0
639 * @arg @ref LL_DMA_STREAM_1
640 * @arg @ref LL_DMA_STREAM_2
641 * @arg @ref LL_DMA_STREAM_3
642 * @arg @ref LL_DMA_STREAM_4
643 * @arg @ref LL_DMA_STREAM_5
644 * @arg @ref LL_DMA_STREAM_6
645 * @arg @ref LL_DMA_STREAM_7
646 * @param Mode This parameter can be one of the following values:
647 * @arg @ref LL_DMA_MODE_NORMAL
648 * @arg @ref LL_DMA_MODE_CIRCULAR
649 * @arg @ref LL_DMA_MODE_PFCTRL
650 * @retval None
651 */
652 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
653 {
654 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
655 }
656
657 /**
658 * @brief Get DMA mode normal, circular or peripheral flow control.
659 * @rmtoll CR CIRC LL_DMA_GetMode\n
660 * CR PFCTRL LL_DMA_GetMode
661 * @param DMAx DMAx Instance
662 * @param Stream This parameter can be one of the following values:
663 * @arg @ref LL_DMA_STREAM_0
664 * @arg @ref LL_DMA_STREAM_1
665 * @arg @ref LL_DMA_STREAM_2
666 * @arg @ref LL_DMA_STREAM_3
667 * @arg @ref LL_DMA_STREAM_4
668 * @arg @ref LL_DMA_STREAM_5
669 * @arg @ref LL_DMA_STREAM_6
670 * @arg @ref LL_DMA_STREAM_7
671 * @retval Returned value can be one of the following values:
672 * @arg @ref LL_DMA_MODE_NORMAL
673 * @arg @ref LL_DMA_MODE_CIRCULAR
674 * @arg @ref LL_DMA_MODE_PFCTRL
675 */
676 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
677 {
678 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
679 }
680
681 /**
682 * @brief Set Peripheral increment mode.
683 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
684 * @param DMAx DMAx Instance
685 * @param Stream This parameter can be one of the following values:
686 * @arg @ref LL_DMA_STREAM_0
687 * @arg @ref LL_DMA_STREAM_1
688 * @arg @ref LL_DMA_STREAM_2
689 * @arg @ref LL_DMA_STREAM_3
690 * @arg @ref LL_DMA_STREAM_4
691 * @arg @ref LL_DMA_STREAM_5
692 * @arg @ref LL_DMA_STREAM_6
693 * @arg @ref LL_DMA_STREAM_7
694 * @param IncrementMode This parameter can be one of the following values:
695 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
696 * @arg @ref LL_DMA_PERIPH_INCREMENT
697 * @retval None
698 */
699 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
700 {
701 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
702 }
703
704 /**
705 * @brief Get Peripheral increment mode.
706 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
707 * @param DMAx DMAx Instance
708 * @param Stream This parameter can be one of the following values:
709 * @arg @ref LL_DMA_STREAM_0
710 * @arg @ref LL_DMA_STREAM_1
711 * @arg @ref LL_DMA_STREAM_2
712 * @arg @ref LL_DMA_STREAM_3
713 * @arg @ref LL_DMA_STREAM_4
714 * @arg @ref LL_DMA_STREAM_5
715 * @arg @ref LL_DMA_STREAM_6
716 * @arg @ref LL_DMA_STREAM_7
717 * @retval Returned value can be one of the following values:
718 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
719 * @arg @ref LL_DMA_PERIPH_INCREMENT
720 */
721 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
722 {
723 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
724 }
725
726 /**
727 * @brief Set Memory increment mode.
728 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
729 * @param DMAx DMAx Instance
730 * @param Stream This parameter can be one of the following values:
731 * @arg @ref LL_DMA_STREAM_0
732 * @arg @ref LL_DMA_STREAM_1
733 * @arg @ref LL_DMA_STREAM_2
734 * @arg @ref LL_DMA_STREAM_3
735 * @arg @ref LL_DMA_STREAM_4
736 * @arg @ref LL_DMA_STREAM_5
737 * @arg @ref LL_DMA_STREAM_6
738 * @arg @ref LL_DMA_STREAM_7
739 * @param IncrementMode This parameter can be one of the following values:
740 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
741 * @arg @ref LL_DMA_MEMORY_INCREMENT
742 * @retval None
743 */
744 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
745 {
746 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
747 }
748
749 /**
750 * @brief Get Memory increment mode.
751 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
752 * @param DMAx DMAx Instance
753 * @param Stream This parameter can be one of the following values:
754 * @arg @ref LL_DMA_STREAM_0
755 * @arg @ref LL_DMA_STREAM_1
756 * @arg @ref LL_DMA_STREAM_2
757 * @arg @ref LL_DMA_STREAM_3
758 * @arg @ref LL_DMA_STREAM_4
759 * @arg @ref LL_DMA_STREAM_5
760 * @arg @ref LL_DMA_STREAM_6
761 * @arg @ref LL_DMA_STREAM_7
762 * @retval Returned value can be one of the following values:
763 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
764 * @arg @ref LL_DMA_MEMORY_INCREMENT
765 */
766 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
767 {
768 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
769 }
770
771 /**
772 * @brief Set Peripheral size.
773 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
774 * @param DMAx DMAx Instance
775 * @param Stream This parameter can be one of the following values:
776 * @arg @ref LL_DMA_STREAM_0
777 * @arg @ref LL_DMA_STREAM_1
778 * @arg @ref LL_DMA_STREAM_2
779 * @arg @ref LL_DMA_STREAM_3
780 * @arg @ref LL_DMA_STREAM_4
781 * @arg @ref LL_DMA_STREAM_5
782 * @arg @ref LL_DMA_STREAM_6
783 * @arg @ref LL_DMA_STREAM_7
784 * @param Size This parameter can be one of the following values:
785 * @arg @ref LL_DMA_PDATAALIGN_BYTE
786 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
787 * @arg @ref LL_DMA_PDATAALIGN_WORD
788 * @retval None
789 */
790 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
791 {
792 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
793 }
794
795 /**
796 * @brief Get Peripheral size.
797 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
798 * @param DMAx DMAx Instance
799 * @param Stream This parameter can be one of the following values:
800 * @arg @ref LL_DMA_STREAM_0
801 * @arg @ref LL_DMA_STREAM_1
802 * @arg @ref LL_DMA_STREAM_2
803 * @arg @ref LL_DMA_STREAM_3
804 * @arg @ref LL_DMA_STREAM_4
805 * @arg @ref LL_DMA_STREAM_5
806 * @arg @ref LL_DMA_STREAM_6
807 * @arg @ref LL_DMA_STREAM_7
808 * @retval Returned value can be one of the following values:
809 * @arg @ref LL_DMA_PDATAALIGN_BYTE
810 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
811 * @arg @ref LL_DMA_PDATAALIGN_WORD
812 */
813 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
814 {
815 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
816 }
817
818 /**
819 * @brief Set Memory size.
820 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
821 * @param DMAx DMAx Instance
822 * @param Stream This parameter can be one of the following values:
823 * @arg @ref LL_DMA_STREAM_0
824 * @arg @ref LL_DMA_STREAM_1
825 * @arg @ref LL_DMA_STREAM_2
826 * @arg @ref LL_DMA_STREAM_3
827 * @arg @ref LL_DMA_STREAM_4
828 * @arg @ref LL_DMA_STREAM_5
829 * @arg @ref LL_DMA_STREAM_6
830 * @arg @ref LL_DMA_STREAM_7
831 * @param Size This parameter can be one of the following values:
832 * @arg @ref LL_DMA_MDATAALIGN_BYTE
833 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
834 * @arg @ref LL_DMA_MDATAALIGN_WORD
835 * @retval None
836 */
837 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
838 {
839 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
840 }
841
842 /**
843 * @brief Get Memory size.
844 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
845 * @param DMAx DMAx Instance
846 * @param Stream This parameter can be one of the following values:
847 * @arg @ref LL_DMA_STREAM_0
848 * @arg @ref LL_DMA_STREAM_1
849 * @arg @ref LL_DMA_STREAM_2
850 * @arg @ref LL_DMA_STREAM_3
851 * @arg @ref LL_DMA_STREAM_4
852 * @arg @ref LL_DMA_STREAM_5
853 * @arg @ref LL_DMA_STREAM_6
854 * @arg @ref LL_DMA_STREAM_7
855 * @retval Returned value can be one of the following values:
856 * @arg @ref LL_DMA_MDATAALIGN_BYTE
857 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
858 * @arg @ref LL_DMA_MDATAALIGN_WORD
859 */
860 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
861 {
862 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
863 }
864
865 /**
866 * @brief Set Peripheral increment offset size.
867 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
868 * @param DMAx DMAx Instance
869 * @param Stream This parameter can be one of the following values:
870 * @arg @ref LL_DMA_STREAM_0
871 * @arg @ref LL_DMA_STREAM_1
872 * @arg @ref LL_DMA_STREAM_2
873 * @arg @ref LL_DMA_STREAM_3
874 * @arg @ref LL_DMA_STREAM_4
875 * @arg @ref LL_DMA_STREAM_5
876 * @arg @ref LL_DMA_STREAM_6
877 * @arg @ref LL_DMA_STREAM_7
878 * @param OffsetSize This parameter can be one of the following values:
879 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
880 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
881 * @retval None
882 */
883 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
884 {
885 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
886 }
887
888 /**
889 * @brief Get Peripheral increment offset size.
890 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
891 * @param DMAx DMAx Instance
892 * @param Stream This parameter can be one of the following values:
893 * @arg @ref LL_DMA_STREAM_0
894 * @arg @ref LL_DMA_STREAM_1
895 * @arg @ref LL_DMA_STREAM_2
896 * @arg @ref LL_DMA_STREAM_3
897 * @arg @ref LL_DMA_STREAM_4
898 * @arg @ref LL_DMA_STREAM_5
899 * @arg @ref LL_DMA_STREAM_6
900 * @arg @ref LL_DMA_STREAM_7
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
903 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
904 */
905 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
906 {
907 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
908 }
909
910 /**
911 * @brief Set Stream priority level.
912 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
913 * @param DMAx DMAx Instance
914 * @param Stream This parameter can be one of the following values:
915 * @arg @ref LL_DMA_STREAM_0
916 * @arg @ref LL_DMA_STREAM_1
917 * @arg @ref LL_DMA_STREAM_2
918 * @arg @ref LL_DMA_STREAM_3
919 * @arg @ref LL_DMA_STREAM_4
920 * @arg @ref LL_DMA_STREAM_5
921 * @arg @ref LL_DMA_STREAM_6
922 * @arg @ref LL_DMA_STREAM_7
923 * @param Priority This parameter can be one of the following values:
924 * @arg @ref LL_DMA_PRIORITY_LOW
925 * @arg @ref LL_DMA_PRIORITY_MEDIUM
926 * @arg @ref LL_DMA_PRIORITY_HIGH
927 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
928 * @retval None
929 */
930 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
931 {
932 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
933 }
934
935 /**
936 * @brief Get Stream priority level.
937 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
938 * @param DMAx DMAx Instance
939 * @param Stream This parameter can be one of the following values:
940 * @arg @ref LL_DMA_STREAM_0
941 * @arg @ref LL_DMA_STREAM_1
942 * @arg @ref LL_DMA_STREAM_2
943 * @arg @ref LL_DMA_STREAM_3
944 * @arg @ref LL_DMA_STREAM_4
945 * @arg @ref LL_DMA_STREAM_5
946 * @arg @ref LL_DMA_STREAM_6
947 * @arg @ref LL_DMA_STREAM_7
948 * @retval Returned value can be one of the following values:
949 * @arg @ref LL_DMA_PRIORITY_LOW
950 * @arg @ref LL_DMA_PRIORITY_MEDIUM
951 * @arg @ref LL_DMA_PRIORITY_HIGH
952 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
953 */
954 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
955 {
956 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
957 }
958
959 /**
960 * @brief Set Number of data to transfer.
961 * @rmtoll NDTR NDT LL_DMA_SetDataLength
962 * @note This action has no effect if
963 * stream is enabled.
964 * @param DMAx DMAx Instance
965 * @param Stream This parameter can be one of the following values:
966 * @arg @ref LL_DMA_STREAM_0
967 * @arg @ref LL_DMA_STREAM_1
968 * @arg @ref LL_DMA_STREAM_2
969 * @arg @ref LL_DMA_STREAM_3
970 * @arg @ref LL_DMA_STREAM_4
971 * @arg @ref LL_DMA_STREAM_5
972 * @arg @ref LL_DMA_STREAM_6
973 * @arg @ref LL_DMA_STREAM_7
974 * @param NbData Between 0 to 0xFFFFFFFF
975 * @retval None
976 */
977 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
978 {
979 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
980 }
981
982 /**
983 * @brief Get Number of data to transfer.
984 * @rmtoll NDTR NDT LL_DMA_GetDataLength
985 * @note Once the stream is enabled, the return value indicate the
986 * remaining bytes to be transmitted.
987 * @param DMAx DMAx Instance
988 * @param Stream This parameter can be one of the following values:
989 * @arg @ref LL_DMA_STREAM_0
990 * @arg @ref LL_DMA_STREAM_1
991 * @arg @ref LL_DMA_STREAM_2
992 * @arg @ref LL_DMA_STREAM_3
993 * @arg @ref LL_DMA_STREAM_4
994 * @arg @ref LL_DMA_STREAM_5
995 * @arg @ref LL_DMA_STREAM_6
996 * @arg @ref LL_DMA_STREAM_7
997 * @retval Between 0 to 0xFFFFFFFF
998 */
999 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
1000 {
1001 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
1002 }
1003
1004 /**
1005 * @brief Select Channel number associated to the Stream.
1006 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
1007 * @param DMAx DMAx Instance
1008 * @param Stream This parameter can be one of the following values:
1009 * @arg @ref LL_DMA_STREAM_0
1010 * @arg @ref LL_DMA_STREAM_1
1011 * @arg @ref LL_DMA_STREAM_2
1012 * @arg @ref LL_DMA_STREAM_3
1013 * @arg @ref LL_DMA_STREAM_4
1014 * @arg @ref LL_DMA_STREAM_5
1015 * @arg @ref LL_DMA_STREAM_6
1016 * @arg @ref LL_DMA_STREAM_7
1017 * @param Channel This parameter can be one of the following values:
1018 * @arg @ref LL_DMA_CHANNEL_0
1019 * @arg @ref LL_DMA_CHANNEL_1
1020 * @arg @ref LL_DMA_CHANNEL_2
1021 * @arg @ref LL_DMA_CHANNEL_3
1022 * @arg @ref LL_DMA_CHANNEL_4
1023 * @arg @ref LL_DMA_CHANNEL_5
1024 * @arg @ref LL_DMA_CHANNEL_6
1025 * @arg @ref LL_DMA_CHANNEL_7
1026 * @retval None
1027 */
1028 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1029 {
1030 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1031 }
1032
1033 /**
1034 * @brief Get the Channel number associated to the Stream.
1035 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1036 * @param DMAx DMAx Instance
1037 * @param Stream This parameter can be one of the following values:
1038 * @arg @ref LL_DMA_STREAM_0
1039 * @arg @ref LL_DMA_STREAM_1
1040 * @arg @ref LL_DMA_STREAM_2
1041 * @arg @ref LL_DMA_STREAM_3
1042 * @arg @ref LL_DMA_STREAM_4
1043 * @arg @ref LL_DMA_STREAM_5
1044 * @arg @ref LL_DMA_STREAM_6
1045 * @arg @ref LL_DMA_STREAM_7
1046 * @retval Returned value can be one of the following values:
1047 * @arg @ref LL_DMA_CHANNEL_0
1048 * @arg @ref LL_DMA_CHANNEL_1
1049 * @arg @ref LL_DMA_CHANNEL_2
1050 * @arg @ref LL_DMA_CHANNEL_3
1051 * @arg @ref LL_DMA_CHANNEL_4
1052 * @arg @ref LL_DMA_CHANNEL_5
1053 * @arg @ref LL_DMA_CHANNEL_6
1054 * @arg @ref LL_DMA_CHANNEL_7
1055 */
1056 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1057 {
1058 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1059 }
1060
1061 /**
1062 * @brief Set Memory burst transfer configuration.
1063 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1064 * @param DMAx DMAx Instance
1065 * @param Stream This parameter can be one of the following values:
1066 * @arg @ref LL_DMA_STREAM_0
1067 * @arg @ref LL_DMA_STREAM_1
1068 * @arg @ref LL_DMA_STREAM_2
1069 * @arg @ref LL_DMA_STREAM_3
1070 * @arg @ref LL_DMA_STREAM_4
1071 * @arg @ref LL_DMA_STREAM_5
1072 * @arg @ref LL_DMA_STREAM_6
1073 * @arg @ref LL_DMA_STREAM_7
1074 * @param Mburst This parameter can be one of the following values:
1075 * @arg @ref LL_DMA_MBURST_SINGLE
1076 * @arg @ref LL_DMA_MBURST_INC4
1077 * @arg @ref LL_DMA_MBURST_INC8
1078 * @arg @ref LL_DMA_MBURST_INC16
1079 * @retval None
1080 */
1081 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1082 {
1083 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1084 }
1085
1086 /**
1087 * @brief Get Memory burst transfer configuration.
1088 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1089 * @param DMAx DMAx Instance
1090 * @param Stream This parameter can be one of the following values:
1091 * @arg @ref LL_DMA_STREAM_0
1092 * @arg @ref LL_DMA_STREAM_1
1093 * @arg @ref LL_DMA_STREAM_2
1094 * @arg @ref LL_DMA_STREAM_3
1095 * @arg @ref LL_DMA_STREAM_4
1096 * @arg @ref LL_DMA_STREAM_5
1097 * @arg @ref LL_DMA_STREAM_6
1098 * @arg @ref LL_DMA_STREAM_7
1099 * @retval Returned value can be one of the following values:
1100 * @arg @ref LL_DMA_MBURST_SINGLE
1101 * @arg @ref LL_DMA_MBURST_INC4
1102 * @arg @ref LL_DMA_MBURST_INC8
1103 * @arg @ref LL_DMA_MBURST_INC16
1104 */
1105 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1106 {
1107 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1108 }
1109
1110 /**
1111 * @brief Set Peripheral burst transfer configuration.
1112 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1113 * @param DMAx DMAx Instance
1114 * @param Stream This parameter can be one of the following values:
1115 * @arg @ref LL_DMA_STREAM_0
1116 * @arg @ref LL_DMA_STREAM_1
1117 * @arg @ref LL_DMA_STREAM_2
1118 * @arg @ref LL_DMA_STREAM_3
1119 * @arg @ref LL_DMA_STREAM_4
1120 * @arg @ref LL_DMA_STREAM_5
1121 * @arg @ref LL_DMA_STREAM_6
1122 * @arg @ref LL_DMA_STREAM_7
1123 * @param Pburst This parameter can be one of the following values:
1124 * @arg @ref LL_DMA_PBURST_SINGLE
1125 * @arg @ref LL_DMA_PBURST_INC4
1126 * @arg @ref LL_DMA_PBURST_INC8
1127 * @arg @ref LL_DMA_PBURST_INC16
1128 * @retval None
1129 */
1130 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1131 {
1132 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1133 }
1134
1135 /**
1136 * @brief Get Peripheral burst transfer configuration.
1137 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1138 * @param DMAx DMAx Instance
1139 * @param Stream This parameter can be one of the following values:
1140 * @arg @ref LL_DMA_STREAM_0
1141 * @arg @ref LL_DMA_STREAM_1
1142 * @arg @ref LL_DMA_STREAM_2
1143 * @arg @ref LL_DMA_STREAM_3
1144 * @arg @ref LL_DMA_STREAM_4
1145 * @arg @ref LL_DMA_STREAM_5
1146 * @arg @ref LL_DMA_STREAM_6
1147 * @arg @ref LL_DMA_STREAM_7
1148 * @retval Returned value can be one of the following values:
1149 * @arg @ref LL_DMA_PBURST_SINGLE
1150 * @arg @ref LL_DMA_PBURST_INC4
1151 * @arg @ref LL_DMA_PBURST_INC8
1152 * @arg @ref LL_DMA_PBURST_INC16
1153 */
1154 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1155 {
1156 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1157 }
1158
1159 /**
1160 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1161 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1162 * @param DMAx DMAx Instance
1163 * @param Stream This parameter can be one of the following values:
1164 * @arg @ref LL_DMA_STREAM_0
1165 * @arg @ref LL_DMA_STREAM_1
1166 * @arg @ref LL_DMA_STREAM_2
1167 * @arg @ref LL_DMA_STREAM_3
1168 * @arg @ref LL_DMA_STREAM_4
1169 * @arg @ref LL_DMA_STREAM_5
1170 * @arg @ref LL_DMA_STREAM_6
1171 * @arg @ref LL_DMA_STREAM_7
1172 * @param CurrentMemory This parameter can be one of the following values:
1173 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1174 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1175 * @retval None
1176 */
1177 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1178 {
1179 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1180 }
1181
1182 /**
1183 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1184 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1185 * @param DMAx DMAx Instance
1186 * @param Stream This parameter can be one of the following values:
1187 * @arg @ref LL_DMA_STREAM_0
1188 * @arg @ref LL_DMA_STREAM_1
1189 * @arg @ref LL_DMA_STREAM_2
1190 * @arg @ref LL_DMA_STREAM_3
1191 * @arg @ref LL_DMA_STREAM_4
1192 * @arg @ref LL_DMA_STREAM_5
1193 * @arg @ref LL_DMA_STREAM_6
1194 * @arg @ref LL_DMA_STREAM_7
1195 * @retval Returned value can be one of the following values:
1196 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1197 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1198 */
1199 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1200 {
1201 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1202 }
1203
1204 /**
1205 * @brief Enable the double buffer mode.
1206 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1207 * @param DMAx DMAx Instance
1208 * @param Stream This parameter can be one of the following values:
1209 * @arg @ref LL_DMA_STREAM_0
1210 * @arg @ref LL_DMA_STREAM_1
1211 * @arg @ref LL_DMA_STREAM_2
1212 * @arg @ref LL_DMA_STREAM_3
1213 * @arg @ref LL_DMA_STREAM_4
1214 * @arg @ref LL_DMA_STREAM_5
1215 * @arg @ref LL_DMA_STREAM_6
1216 * @arg @ref LL_DMA_STREAM_7
1217 * @retval None
1218 */
1219 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1220 {
1221 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1222 }
1223
1224 /**
1225 * @brief Disable the double buffer mode.
1226 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1227 * @param DMAx DMAx Instance
1228 * @param Stream This parameter can be one of the following values:
1229 * @arg @ref LL_DMA_STREAM_0
1230 * @arg @ref LL_DMA_STREAM_1
1231 * @arg @ref LL_DMA_STREAM_2
1232 * @arg @ref LL_DMA_STREAM_3
1233 * @arg @ref LL_DMA_STREAM_4
1234 * @arg @ref LL_DMA_STREAM_5
1235 * @arg @ref LL_DMA_STREAM_6
1236 * @arg @ref LL_DMA_STREAM_7
1237 * @retval None
1238 */
1239 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1240 {
1241 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1242 }
1243
1244 /**
1245 * @brief Get FIFO status.
1246 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1247 * @param DMAx DMAx Instance
1248 * @param Stream This parameter can be one of the following values:
1249 * @arg @ref LL_DMA_STREAM_0
1250 * @arg @ref LL_DMA_STREAM_1
1251 * @arg @ref LL_DMA_STREAM_2
1252 * @arg @ref LL_DMA_STREAM_3
1253 * @arg @ref LL_DMA_STREAM_4
1254 * @arg @ref LL_DMA_STREAM_5
1255 * @arg @ref LL_DMA_STREAM_6
1256 * @arg @ref LL_DMA_STREAM_7
1257 * @retval Returned value can be one of the following values:
1258 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1259 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1260 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1261 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1262 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1263 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1264 */
1265 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1266 {
1267 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1268 }
1269
1270 /**
1271 * @brief Disable Fifo mode.
1272 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1273 * @param DMAx DMAx Instance
1274 * @param Stream This parameter can be one of the following values:
1275 * @arg @ref LL_DMA_STREAM_0
1276 * @arg @ref LL_DMA_STREAM_1
1277 * @arg @ref LL_DMA_STREAM_2
1278 * @arg @ref LL_DMA_STREAM_3
1279 * @arg @ref LL_DMA_STREAM_4
1280 * @arg @ref LL_DMA_STREAM_5
1281 * @arg @ref LL_DMA_STREAM_6
1282 * @arg @ref LL_DMA_STREAM_7
1283 * @retval None
1284 */
1285 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1286 {
1287 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1288 }
1289
1290 /**
1291 * @brief Enable Fifo mode.
1292 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1293 * @param DMAx DMAx Instance
1294 * @param Stream This parameter can be one of the following values:
1295 * @arg @ref LL_DMA_STREAM_0
1296 * @arg @ref LL_DMA_STREAM_1
1297 * @arg @ref LL_DMA_STREAM_2
1298 * @arg @ref LL_DMA_STREAM_3
1299 * @arg @ref LL_DMA_STREAM_4
1300 * @arg @ref LL_DMA_STREAM_5
1301 * @arg @ref LL_DMA_STREAM_6
1302 * @arg @ref LL_DMA_STREAM_7
1303 * @retval None
1304 */
1305 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1306 {
1307 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1308 }
1309
1310 /**
1311 * @brief Select FIFO threshold.
1312 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1313 * @param DMAx DMAx Instance
1314 * @param Stream This parameter can be one of the following values:
1315 * @arg @ref LL_DMA_STREAM_0
1316 * @arg @ref LL_DMA_STREAM_1
1317 * @arg @ref LL_DMA_STREAM_2
1318 * @arg @ref LL_DMA_STREAM_3
1319 * @arg @ref LL_DMA_STREAM_4
1320 * @arg @ref LL_DMA_STREAM_5
1321 * @arg @ref LL_DMA_STREAM_6
1322 * @arg @ref LL_DMA_STREAM_7
1323 * @param Threshold This parameter can be one of the following values:
1324 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1325 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1326 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1327 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1328 * @retval None
1329 */
1330 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1331 {
1332 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1333 }
1334
1335 /**
1336 * @brief Get FIFO threshold.
1337 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1338 * @param DMAx DMAx Instance
1339 * @param Stream This parameter can be one of the following values:
1340 * @arg @ref LL_DMA_STREAM_0
1341 * @arg @ref LL_DMA_STREAM_1
1342 * @arg @ref LL_DMA_STREAM_2
1343 * @arg @ref LL_DMA_STREAM_3
1344 * @arg @ref LL_DMA_STREAM_4
1345 * @arg @ref LL_DMA_STREAM_5
1346 * @arg @ref LL_DMA_STREAM_6
1347 * @arg @ref LL_DMA_STREAM_7
1348 * @retval Returned value can be one of the following values:
1349 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1350 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1351 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1352 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1353 */
1354 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1355 {
1356 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1357 }
1358
1359 /**
1360 * @brief Configure the FIFO .
1361 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1362 * FCR DMDIS LL_DMA_ConfigFifo
1363 * @param DMAx DMAx Instance
1364 * @param Stream This parameter can be one of the following values:
1365 * @arg @ref LL_DMA_STREAM_0
1366 * @arg @ref LL_DMA_STREAM_1
1367 * @arg @ref LL_DMA_STREAM_2
1368 * @arg @ref LL_DMA_STREAM_3
1369 * @arg @ref LL_DMA_STREAM_4
1370 * @arg @ref LL_DMA_STREAM_5
1371 * @arg @ref LL_DMA_STREAM_6
1372 * @arg @ref LL_DMA_STREAM_7
1373 * @param FifoMode This parameter can be one of the following values:
1374 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1375 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1376 * @param FifoThreshold This parameter can be one of the following values:
1377 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1378 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1379 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1380 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1381 * @retval None
1382 */
1383 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1384 {
1385 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1386 }
1387
1388 /**
1389 * @brief Configure the Source and Destination addresses.
1390 * @note This API must not be called when the DMA stream is enabled.
1391 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1392 * PAR PA LL_DMA_ConfigAddresses
1393 * @param DMAx DMAx Instance
1394 * @param Stream This parameter can be one of the following values:
1395 * @arg @ref LL_DMA_STREAM_0
1396 * @arg @ref LL_DMA_STREAM_1
1397 * @arg @ref LL_DMA_STREAM_2
1398 * @arg @ref LL_DMA_STREAM_3
1399 * @arg @ref LL_DMA_STREAM_4
1400 * @arg @ref LL_DMA_STREAM_5
1401 * @arg @ref LL_DMA_STREAM_6
1402 * @arg @ref LL_DMA_STREAM_7
1403 * @param SrcAddress Between 0 to 0xFFFFFFFF
1404 * @param DstAddress Between 0 to 0xFFFFFFFF
1405 * @param Direction This parameter can be one of the following values:
1406 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1407 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1408 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1409 * @retval None
1410 */
1411 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1412 {
1413 /* Direction Memory to Periph */
1414 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1415 {
1416 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1417 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1418 }
1419 /* Direction Periph to Memory and Memory to Memory */
1420 else
1421 {
1422 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1423 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1424 }
1425 }
1426
1427 /**
1428 * @brief Set the Memory address.
1429 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1430 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1431 * @note This API must not be called when the DMA channel is enabled.
1432 * @param DMAx DMAx Instance
1433 * @param Stream This parameter can be one of the following values:
1434 * @arg @ref LL_DMA_STREAM_0
1435 * @arg @ref LL_DMA_STREAM_1
1436 * @arg @ref LL_DMA_STREAM_2
1437 * @arg @ref LL_DMA_STREAM_3
1438 * @arg @ref LL_DMA_STREAM_4
1439 * @arg @ref LL_DMA_STREAM_5
1440 * @arg @ref LL_DMA_STREAM_6
1441 * @arg @ref LL_DMA_STREAM_7
1442 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1443 * @retval None
1444 */
1445 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1446 {
1447 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1448 }
1449
1450 /**
1451 * @brief Set the Peripheral address.
1452 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1453 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1454 * @note This API must not be called when the DMA channel is enabled.
1455 * @param DMAx DMAx Instance
1456 * @param Stream This parameter can be one of the following values:
1457 * @arg @ref LL_DMA_STREAM_0
1458 * @arg @ref LL_DMA_STREAM_1
1459 * @arg @ref LL_DMA_STREAM_2
1460 * @arg @ref LL_DMA_STREAM_3
1461 * @arg @ref LL_DMA_STREAM_4
1462 * @arg @ref LL_DMA_STREAM_5
1463 * @arg @ref LL_DMA_STREAM_6
1464 * @arg @ref LL_DMA_STREAM_7
1465 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1466 * @retval None
1467 */
1468 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1469 {
1470 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1471 }
1472
1473 /**
1474 * @brief Get the Memory address.
1475 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1476 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1477 * @param DMAx DMAx Instance
1478 * @param Stream This parameter can be one of the following values:
1479 * @arg @ref LL_DMA_STREAM_0
1480 * @arg @ref LL_DMA_STREAM_1
1481 * @arg @ref LL_DMA_STREAM_2
1482 * @arg @ref LL_DMA_STREAM_3
1483 * @arg @ref LL_DMA_STREAM_4
1484 * @arg @ref LL_DMA_STREAM_5
1485 * @arg @ref LL_DMA_STREAM_6
1486 * @arg @ref LL_DMA_STREAM_7
1487 * @retval Between 0 to 0xFFFFFFFF
1488 */
1489 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1490 {
1491 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1492 }
1493
1494 /**
1495 * @brief Get the Peripheral address.
1496 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1497 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1498 * @param DMAx DMAx Instance
1499 * @param Stream This parameter can be one of the following values:
1500 * @arg @ref LL_DMA_STREAM_0
1501 * @arg @ref LL_DMA_STREAM_1
1502 * @arg @ref LL_DMA_STREAM_2
1503 * @arg @ref LL_DMA_STREAM_3
1504 * @arg @ref LL_DMA_STREAM_4
1505 * @arg @ref LL_DMA_STREAM_5
1506 * @arg @ref LL_DMA_STREAM_6
1507 * @arg @ref LL_DMA_STREAM_7
1508 * @retval Between 0 to 0xFFFFFFFF
1509 */
1510 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1511 {
1512 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1513 }
1514
1515 /**
1516 * @brief Set the Memory to Memory Source address.
1517 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1518 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1519 * @note This API must not be called when the DMA channel is enabled.
1520 * @param DMAx DMAx Instance
1521 * @param Stream This parameter can be one of the following values:
1522 * @arg @ref LL_DMA_STREAM_0
1523 * @arg @ref LL_DMA_STREAM_1
1524 * @arg @ref LL_DMA_STREAM_2
1525 * @arg @ref LL_DMA_STREAM_3
1526 * @arg @ref LL_DMA_STREAM_4
1527 * @arg @ref LL_DMA_STREAM_5
1528 * @arg @ref LL_DMA_STREAM_6
1529 * @arg @ref LL_DMA_STREAM_7
1530 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1531 * @retval None
1532 */
1533 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1534 {
1535 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1536 }
1537
1538 /**
1539 * @brief Set the Memory to Memory Destination address.
1540 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1541 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1542 * @note This API must not be called when the DMA channel is enabled.
1543 * @param DMAx DMAx Instance
1544 * @param Stream This parameter can be one of the following values:
1545 * @arg @ref LL_DMA_STREAM_0
1546 * @arg @ref LL_DMA_STREAM_1
1547 * @arg @ref LL_DMA_STREAM_2
1548 * @arg @ref LL_DMA_STREAM_3
1549 * @arg @ref LL_DMA_STREAM_4
1550 * @arg @ref LL_DMA_STREAM_5
1551 * @arg @ref LL_DMA_STREAM_6
1552 * @arg @ref LL_DMA_STREAM_7
1553 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1554 * @retval None
1555 */
1556 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1557 {
1558 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1559 }
1560
1561 /**
1562 * @brief Get the Memory to Memory Source address.
1563 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1564 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1565 * @param DMAx DMAx Instance
1566 * @param Stream This parameter can be one of the following values:
1567 * @arg @ref LL_DMA_STREAM_0
1568 * @arg @ref LL_DMA_STREAM_1
1569 * @arg @ref LL_DMA_STREAM_2
1570 * @arg @ref LL_DMA_STREAM_3
1571 * @arg @ref LL_DMA_STREAM_4
1572 * @arg @ref LL_DMA_STREAM_5
1573 * @arg @ref LL_DMA_STREAM_6
1574 * @arg @ref LL_DMA_STREAM_7
1575 * @retval Between 0 to 0xFFFFFFFF
1576 */
1577 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1578 {
1579 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1580 }
1581
1582 /**
1583 * @brief Get the Memory to Memory Destination address.
1584 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1585 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1586 * @param DMAx DMAx Instance
1587 * @param Stream This parameter can be one of the following values:
1588 * @arg @ref LL_DMA_STREAM_0
1589 * @arg @ref LL_DMA_STREAM_1
1590 * @arg @ref LL_DMA_STREAM_2
1591 * @arg @ref LL_DMA_STREAM_3
1592 * @arg @ref LL_DMA_STREAM_4
1593 * @arg @ref LL_DMA_STREAM_5
1594 * @arg @ref LL_DMA_STREAM_6
1595 * @arg @ref LL_DMA_STREAM_7
1596 * @retval Between 0 to 0xFFFFFFFF
1597 */
1598 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1599 {
1600 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1601 }
1602
1603 /**
1604 * @brief Set Memory 1 address (used in case of Double buffer mode).
1605 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1606 * @param DMAx DMAx Instance
1607 * @param Stream This parameter can be one of the following values:
1608 * @arg @ref LL_DMA_STREAM_0
1609 * @arg @ref LL_DMA_STREAM_1
1610 * @arg @ref LL_DMA_STREAM_2
1611 * @arg @ref LL_DMA_STREAM_3
1612 * @arg @ref LL_DMA_STREAM_4
1613 * @arg @ref LL_DMA_STREAM_5
1614 * @arg @ref LL_DMA_STREAM_6
1615 * @arg @ref LL_DMA_STREAM_7
1616 * @param Address Between 0 to 0xFFFFFFFF
1617 * @retval None
1618 */
1619 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1620 {
1621 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1622 }
1623
1624 /**
1625 * @brief Get Memory 1 address (used in case of Double buffer mode).
1626 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1627 * @param DMAx DMAx Instance
1628 * @param Stream This parameter can be one of the following values:
1629 * @arg @ref LL_DMA_STREAM_0
1630 * @arg @ref LL_DMA_STREAM_1
1631 * @arg @ref LL_DMA_STREAM_2
1632 * @arg @ref LL_DMA_STREAM_3
1633 * @arg @ref LL_DMA_STREAM_4
1634 * @arg @ref LL_DMA_STREAM_5
1635 * @arg @ref LL_DMA_STREAM_6
1636 * @arg @ref LL_DMA_STREAM_7
1637 * @retval Between 0 to 0xFFFFFFFF
1638 */
1639 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1640 {
1641 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1642 }
1643
1644 /**
1645 * @}
1646 */
1647
1648 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1649 * @{
1650 */
1651
1652 /**
1653 * @brief Get Stream 0 half transfer flag.
1654 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1655 * @param DMAx DMAx Instance
1656 * @retval State of bit (1 or 0).
1657 */
1658 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1659 {
1660 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1661 }
1662
1663 /**
1664 * @brief Get Stream 1 half transfer flag.
1665 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1666 * @param DMAx DMAx Instance
1667 * @retval State of bit (1 or 0).
1668 */
1669 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1670 {
1671 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1672 }
1673
1674 /**
1675 * @brief Get Stream 2 half transfer flag.
1676 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1677 * @param DMAx DMAx Instance
1678 * @retval State of bit (1 or 0).
1679 */
1680 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1681 {
1682 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1683 }
1684
1685 /**
1686 * @brief Get Stream 3 half transfer flag.
1687 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1688 * @param DMAx DMAx Instance
1689 * @retval State of bit (1 or 0).
1690 */
1691 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1692 {
1693 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1694 }
1695
1696 /**
1697 * @brief Get Stream 4 half transfer flag.
1698 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1699 * @param DMAx DMAx Instance
1700 * @retval State of bit (1 or 0).
1701 */
1702 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1703 {
1704 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1705 }
1706
1707 /**
1708 * @brief Get Stream 5 half transfer flag.
1709 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1710 * @param DMAx DMAx Instance
1711 * @retval State of bit (1 or 0).
1712 */
1713 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1714 {
1715 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1716 }
1717
1718 /**
1719 * @brief Get Stream 6 half transfer flag.
1720 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1721 * @param DMAx DMAx Instance
1722 * @retval State of bit (1 or 0).
1723 */
1724 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1725 {
1726 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1727 }
1728
1729 /**
1730 * @brief Get Stream 7 half transfer flag.
1731 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1732 * @param DMAx DMAx Instance
1733 * @retval State of bit (1 or 0).
1734 */
1735 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1736 {
1737 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1738 }
1739
1740 /**
1741 * @brief Get Stream 0 transfer complete flag.
1742 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1743 * @param DMAx DMAx Instance
1744 * @retval State of bit (1 or 0).
1745 */
1746 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1747 {
1748 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1749 }
1750
1751 /**
1752 * @brief Get Stream 1 transfer complete flag.
1753 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1754 * @param DMAx DMAx Instance
1755 * @retval State of bit (1 or 0).
1756 */
1757 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1758 {
1759 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1760 }
1761
1762 /**
1763 * @brief Get Stream 2 transfer complete flag.
1764 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1765 * @param DMAx DMAx Instance
1766 * @retval State of bit (1 or 0).
1767 */
1768 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1769 {
1770 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1771 }
1772
1773 /**
1774 * @brief Get Stream 3 transfer complete flag.
1775 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1776 * @param DMAx DMAx Instance
1777 * @retval State of bit (1 or 0).
1778 */
1779 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1780 {
1781 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1782 }
1783
1784 /**
1785 * @brief Get Stream 4 transfer complete flag.
1786 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1787 * @param DMAx DMAx Instance
1788 * @retval State of bit (1 or 0).
1789 */
1790 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1791 {
1792 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1793 }
1794
1795 /**
1796 * @brief Get Stream 5 transfer complete flag.
1797 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1798 * @param DMAx DMAx Instance
1799 * @retval State of bit (1 or 0).
1800 */
1801 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1802 {
1803 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1804 }
1805
1806 /**
1807 * @brief Get Stream 6 transfer complete flag.
1808 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1809 * @param DMAx DMAx Instance
1810 * @retval State of bit (1 or 0).
1811 */
1812 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1813 {
1814 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1815 }
1816
1817 /**
1818 * @brief Get Stream 7 transfer complete flag.
1819 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1820 * @param DMAx DMAx Instance
1821 * @retval State of bit (1 or 0).
1822 */
1823 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1824 {
1825 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1826 }
1827
1828 /**
1829 * @brief Get Stream 0 transfer error flag.
1830 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1831 * @param DMAx DMAx Instance
1832 * @retval State of bit (1 or 0).
1833 */
1834 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1835 {
1836 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1837 }
1838
1839 /**
1840 * @brief Get Stream 1 transfer error flag.
1841 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1842 * @param DMAx DMAx Instance
1843 * @retval State of bit (1 or 0).
1844 */
1845 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1846 {
1847 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1848 }
1849
1850 /**
1851 * @brief Get Stream 2 transfer error flag.
1852 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1853 * @param DMAx DMAx Instance
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1857 {
1858 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1859 }
1860
1861 /**
1862 * @brief Get Stream 3 transfer error flag.
1863 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1864 * @param DMAx DMAx Instance
1865 * @retval State of bit (1 or 0).
1866 */
1867 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1868 {
1869 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1870 }
1871
1872 /**
1873 * @brief Get Stream 4 transfer error flag.
1874 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1875 * @param DMAx DMAx Instance
1876 * @retval State of bit (1 or 0).
1877 */
1878 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1879 {
1880 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1881 }
1882
1883 /**
1884 * @brief Get Stream 5 transfer error flag.
1885 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1886 * @param DMAx DMAx Instance
1887 * @retval State of bit (1 or 0).
1888 */
1889 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1890 {
1891 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1892 }
1893
1894 /**
1895 * @brief Get Stream 6 transfer error flag.
1896 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1897 * @param DMAx DMAx Instance
1898 * @retval State of bit (1 or 0).
1899 */
1900 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1901 {
1902 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1903 }
1904
1905 /**
1906 * @brief Get Stream 7 transfer error flag.
1907 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1908 * @param DMAx DMAx Instance
1909 * @retval State of bit (1 or 0).
1910 */
1911 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1912 {
1913 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1914 }
1915
1916 /**
1917 * @brief Get Stream 0 direct mode error flag.
1918 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1919 * @param DMAx DMAx Instance
1920 * @retval State of bit (1 or 0).
1921 */
1922 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1923 {
1924 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1925 }
1926
1927 /**
1928 * @brief Get Stream 1 direct mode error flag.
1929 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1930 * @param DMAx DMAx Instance
1931 * @retval State of bit (1 or 0).
1932 */
1933 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1934 {
1935 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1936 }
1937
1938 /**
1939 * @brief Get Stream 2 direct mode error flag.
1940 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1941 * @param DMAx DMAx Instance
1942 * @retval State of bit (1 or 0).
1943 */
1944 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1945 {
1946 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1947 }
1948
1949 /**
1950 * @brief Get Stream 3 direct mode error flag.
1951 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1952 * @param DMAx DMAx Instance
1953 * @retval State of bit (1 or 0).
1954 */
1955 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1956 {
1957 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1958 }
1959
1960 /**
1961 * @brief Get Stream 4 direct mode error flag.
1962 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1963 * @param DMAx DMAx Instance
1964 * @retval State of bit (1 or 0).
1965 */
1966 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1967 {
1968 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1969 }
1970
1971 /**
1972 * @brief Get Stream 5 direct mode error flag.
1973 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1974 * @param DMAx DMAx Instance
1975 * @retval State of bit (1 or 0).
1976 */
1977 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1978 {
1979 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1980 }
1981
1982 /**
1983 * @brief Get Stream 6 direct mode error flag.
1984 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
1985 * @param DMAx DMAx Instance
1986 * @retval State of bit (1 or 0).
1987 */
1988 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
1989 {
1990 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
1991 }
1992
1993 /**
1994 * @brief Get Stream 7 direct mode error flag.
1995 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
1996 * @param DMAx DMAx Instance
1997 * @retval State of bit (1 or 0).
1998 */
1999 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
2000 {
2001 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
2002 }
2003
2004 /**
2005 * @brief Get Stream 0 FIFO error flag.
2006 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2007 * @param DMAx DMAx Instance
2008 * @retval State of bit (1 or 0).
2009 */
2010 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2011 {
2012 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
2013 }
2014
2015 /**
2016 * @brief Get Stream 1 FIFO error flag.
2017 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2018 * @param DMAx DMAx Instance
2019 * @retval State of bit (1 or 0).
2020 */
2021 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2022 {
2023 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2024 }
2025
2026 /**
2027 * @brief Get Stream 2 FIFO error flag.
2028 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2029 * @param DMAx DMAx Instance
2030 * @retval State of bit (1 or 0).
2031 */
2032 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2033 {
2034 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2035 }
2036
2037 /**
2038 * @brief Get Stream 3 FIFO error flag.
2039 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2040 * @param DMAx DMAx Instance
2041 * @retval State of bit (1 or 0).
2042 */
2043 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2044 {
2045 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2046 }
2047
2048 /**
2049 * @brief Get Stream 4 FIFO error flag.
2050 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2051 * @param DMAx DMAx Instance
2052 * @retval State of bit (1 or 0).
2053 */
2054 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2055 {
2056 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2057 }
2058
2059 /**
2060 * @brief Get Stream 5 FIFO error flag.
2061 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2062 * @param DMAx DMAx Instance
2063 * @retval State of bit (1 or 0).
2064 */
2065 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2066 {
2067 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2068 }
2069
2070 /**
2071 * @brief Get Stream 6 FIFO error flag.
2072 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2073 * @param DMAx DMAx Instance
2074 * @retval State of bit (1 or 0).
2075 */
2076 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2077 {
2078 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2079 }
2080
2081 /**
2082 * @brief Get Stream 7 FIFO error flag.
2083 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2084 * @param DMAx DMAx Instance
2085 * @retval State of bit (1 or 0).
2086 */
2087 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2088 {
2089 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2090 }
2091
2092 /**
2093 * @brief Clear Stream 0 half transfer flag.
2094 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2095 * @param DMAx DMAx Instance
2096 * @retval None
2097 */
2098 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2099 {
2100 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2101 }
2102
2103 /**
2104 * @brief Clear Stream 1 half transfer flag.
2105 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2106 * @param DMAx DMAx Instance
2107 * @retval None
2108 */
2109 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2110 {
2111 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2112 }
2113
2114 /**
2115 * @brief Clear Stream 2 half transfer flag.
2116 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2117 * @param DMAx DMAx Instance
2118 * @retval None
2119 */
2120 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2121 {
2122 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2123 }
2124
2125 /**
2126 * @brief Clear Stream 3 half transfer flag.
2127 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2128 * @param DMAx DMAx Instance
2129 * @retval None
2130 */
2131 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2132 {
2133 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2134 }
2135
2136 /**
2137 * @brief Clear Stream 4 half transfer flag.
2138 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2139 * @param DMAx DMAx Instance
2140 * @retval None
2141 */
2142 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2143 {
2144 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2145 }
2146
2147 /**
2148 * @brief Clear Stream 5 half transfer flag.
2149 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2150 * @param DMAx DMAx Instance
2151 * @retval None
2152 */
2153 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2154 {
2155 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2156 }
2157
2158 /**
2159 * @brief Clear Stream 6 half transfer flag.
2160 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2161 * @param DMAx DMAx Instance
2162 * @retval None
2163 */
2164 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2165 {
2166 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2167 }
2168
2169 /**
2170 * @brief Clear Stream 7 half transfer flag.
2171 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2172 * @param DMAx DMAx Instance
2173 * @retval None
2174 */
2175 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2176 {
2177 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2178 }
2179
2180 /**
2181 * @brief Clear Stream 0 transfer complete flag.
2182 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2183 * @param DMAx DMAx Instance
2184 * @retval None
2185 */
2186 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2187 {
2188 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2189 }
2190
2191 /**
2192 * @brief Clear Stream 1 transfer complete flag.
2193 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2194 * @param DMAx DMAx Instance
2195 * @retval None
2196 */
2197 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2198 {
2199 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2200 }
2201
2202 /**
2203 * @brief Clear Stream 2 transfer complete flag.
2204 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2205 * @param DMAx DMAx Instance
2206 * @retval None
2207 */
2208 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2209 {
2210 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2211 }
2212
2213 /**
2214 * @brief Clear Stream 3 transfer complete flag.
2215 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2216 * @param DMAx DMAx Instance
2217 * @retval None
2218 */
2219 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2220 {
2221 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2222 }
2223
2224 /**
2225 * @brief Clear Stream 4 transfer complete flag.
2226 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2227 * @param DMAx DMAx Instance
2228 * @retval None
2229 */
2230 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2231 {
2232 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2233 }
2234
2235 /**
2236 * @brief Clear Stream 5 transfer complete flag.
2237 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2238 * @param DMAx DMAx Instance
2239 * @retval None
2240 */
2241 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2242 {
2243 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2244 }
2245
2246 /**
2247 * @brief Clear Stream 6 transfer complete flag.
2248 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2249 * @param DMAx DMAx Instance
2250 * @retval None
2251 */
2252 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2253 {
2254 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2255 }
2256
2257 /**
2258 * @brief Clear Stream 7 transfer complete flag.
2259 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2260 * @param DMAx DMAx Instance
2261 * @retval None
2262 */
2263 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2264 {
2265 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2266 }
2267
2268 /**
2269 * @brief Clear Stream 0 transfer error flag.
2270 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2271 * @param DMAx DMAx Instance
2272 * @retval None
2273 */
2274 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2275 {
2276 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2277 }
2278
2279 /**
2280 * @brief Clear Stream 1 transfer error flag.
2281 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2282 * @param DMAx DMAx Instance
2283 * @retval None
2284 */
2285 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2286 {
2287 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2288 }
2289
2290 /**
2291 * @brief Clear Stream 2 transfer error flag.
2292 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2293 * @param DMAx DMAx Instance
2294 * @retval None
2295 */
2296 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2297 {
2298 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2299 }
2300
2301 /**
2302 * @brief Clear Stream 3 transfer error flag.
2303 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2304 * @param DMAx DMAx Instance
2305 * @retval None
2306 */
2307 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2308 {
2309 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2310 }
2311
2312 /**
2313 * @brief Clear Stream 4 transfer error flag.
2314 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2315 * @param DMAx DMAx Instance
2316 * @retval None
2317 */
2318 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2319 {
2320 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2321 }
2322
2323 /**
2324 * @brief Clear Stream 5 transfer error flag.
2325 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2326 * @param DMAx DMAx Instance
2327 * @retval None
2328 */
2329 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2330 {
2331 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2332 }
2333
2334 /**
2335 * @brief Clear Stream 6 transfer error flag.
2336 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2337 * @param DMAx DMAx Instance
2338 * @retval None
2339 */
2340 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2341 {
2342 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2343 }
2344
2345 /**
2346 * @brief Clear Stream 7 transfer error flag.
2347 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2348 * @param DMAx DMAx Instance
2349 * @retval None
2350 */
2351 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2352 {
2353 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2354 }
2355
2356 /**
2357 * @brief Clear Stream 0 direct mode error flag.
2358 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2359 * @param DMAx DMAx Instance
2360 * @retval None
2361 */
2362 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2363 {
2364 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2365 }
2366
2367 /**
2368 * @brief Clear Stream 1 direct mode error flag.
2369 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2370 * @param DMAx DMAx Instance
2371 * @retval None
2372 */
2373 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2374 {
2375 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2376 }
2377
2378 /**
2379 * @brief Clear Stream 2 direct mode error flag.
2380 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2381 * @param DMAx DMAx Instance
2382 * @retval None
2383 */
2384 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2385 {
2386 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2387 }
2388
2389 /**
2390 * @brief Clear Stream 3 direct mode error flag.
2391 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2392 * @param DMAx DMAx Instance
2393 * @retval None
2394 */
2395 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2396 {
2397 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2398 }
2399
2400 /**
2401 * @brief Clear Stream 4 direct mode error flag.
2402 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2403 * @param DMAx DMAx Instance
2404 * @retval None
2405 */
2406 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2407 {
2408 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2409 }
2410
2411 /**
2412 * @brief Clear Stream 5 direct mode error flag.
2413 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2414 * @param DMAx DMAx Instance
2415 * @retval None
2416 */
2417 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2418 {
2419 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2420 }
2421
2422 /**
2423 * @brief Clear Stream 6 direct mode error flag.
2424 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2425 * @param DMAx DMAx Instance
2426 * @retval None
2427 */
2428 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2429 {
2430 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2431 }
2432
2433 /**
2434 * @brief Clear Stream 7 direct mode error flag.
2435 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2436 * @param DMAx DMAx Instance
2437 * @retval None
2438 */
2439 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2440 {
2441 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2442 }
2443
2444 /**
2445 * @brief Clear Stream 0 FIFO error flag.
2446 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2447 * @param DMAx DMAx Instance
2448 * @retval None
2449 */
2450 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2451 {
2452 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2453 }
2454
2455 /**
2456 * @brief Clear Stream 1 FIFO error flag.
2457 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2458 * @param DMAx DMAx Instance
2459 * @retval None
2460 */
2461 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2462 {
2463 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2464 }
2465
2466 /**
2467 * @brief Clear Stream 2 FIFO error flag.
2468 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2469 * @param DMAx DMAx Instance
2470 * @retval None
2471 */
2472 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2473 {
2474 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2475 }
2476
2477 /**
2478 * @brief Clear Stream 3 FIFO error flag.
2479 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2480 * @param DMAx DMAx Instance
2481 * @retval None
2482 */
2483 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2484 {
2485 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2486 }
2487
2488 /**
2489 * @brief Clear Stream 4 FIFO error flag.
2490 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2491 * @param DMAx DMAx Instance
2492 * @retval None
2493 */
2494 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2495 {
2496 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2497 }
2498
2499 /**
2500 * @brief Clear Stream 5 FIFO error flag.
2501 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2502 * @param DMAx DMAx Instance
2503 * @retval None
2504 */
2505 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2506 {
2507 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2508 }
2509
2510 /**
2511 * @brief Clear Stream 6 FIFO error flag.
2512 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2513 * @param DMAx DMAx Instance
2514 * @retval None
2515 */
2516 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2517 {
2518 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2519 }
2520
2521 /**
2522 * @brief Clear Stream 7 FIFO error flag.
2523 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2524 * @param DMAx DMAx Instance
2525 * @retval None
2526 */
2527 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2528 {
2529 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2530 }
2531
2532 /**
2533 * @}
2534 */
2535
2536 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2537 * @{
2538 */
2539
2540 /**
2541 * @brief Enable Half transfer interrupt.
2542 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2543 * @param DMAx DMAx Instance
2544 * @param Stream This parameter can be one of the following values:
2545 * @arg @ref LL_DMA_STREAM_0
2546 * @arg @ref LL_DMA_STREAM_1
2547 * @arg @ref LL_DMA_STREAM_2
2548 * @arg @ref LL_DMA_STREAM_3
2549 * @arg @ref LL_DMA_STREAM_4
2550 * @arg @ref LL_DMA_STREAM_5
2551 * @arg @ref LL_DMA_STREAM_6
2552 * @arg @ref LL_DMA_STREAM_7
2553 * @retval None
2554 */
2555 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2556 {
2557 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2558 }
2559
2560 /**
2561 * @brief Enable Transfer error interrupt.
2562 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2563 * @param DMAx DMAx Instance
2564 * @param Stream This parameter can be one of the following values:
2565 * @arg @ref LL_DMA_STREAM_0
2566 * @arg @ref LL_DMA_STREAM_1
2567 * @arg @ref LL_DMA_STREAM_2
2568 * @arg @ref LL_DMA_STREAM_3
2569 * @arg @ref LL_DMA_STREAM_4
2570 * @arg @ref LL_DMA_STREAM_5
2571 * @arg @ref LL_DMA_STREAM_6
2572 * @arg @ref LL_DMA_STREAM_7
2573 * @retval None
2574 */
2575 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2576 {
2577 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2578 }
2579
2580 /**
2581 * @brief Enable Transfer complete interrupt.
2582 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2583 * @param DMAx DMAx Instance
2584 * @param Stream This parameter can be one of the following values:
2585 * @arg @ref LL_DMA_STREAM_0
2586 * @arg @ref LL_DMA_STREAM_1
2587 * @arg @ref LL_DMA_STREAM_2
2588 * @arg @ref LL_DMA_STREAM_3
2589 * @arg @ref LL_DMA_STREAM_4
2590 * @arg @ref LL_DMA_STREAM_5
2591 * @arg @ref LL_DMA_STREAM_6
2592 * @arg @ref LL_DMA_STREAM_7
2593 * @retval None
2594 */
2595 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2596 {
2597 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2598 }
2599
2600 /**
2601 * @brief Enable Direct mode error interrupt.
2602 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2603 * @param DMAx DMAx Instance
2604 * @param Stream This parameter can be one of the following values:
2605 * @arg @ref LL_DMA_STREAM_0
2606 * @arg @ref LL_DMA_STREAM_1
2607 * @arg @ref LL_DMA_STREAM_2
2608 * @arg @ref LL_DMA_STREAM_3
2609 * @arg @ref LL_DMA_STREAM_4
2610 * @arg @ref LL_DMA_STREAM_5
2611 * @arg @ref LL_DMA_STREAM_6
2612 * @arg @ref LL_DMA_STREAM_7
2613 * @retval None
2614 */
2615 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2616 {
2617 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2618 }
2619
2620 /**
2621 * @brief Enable FIFO error interrupt.
2622 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2623 * @param DMAx DMAx Instance
2624 * @param Stream This parameter can be one of the following values:
2625 * @arg @ref LL_DMA_STREAM_0
2626 * @arg @ref LL_DMA_STREAM_1
2627 * @arg @ref LL_DMA_STREAM_2
2628 * @arg @ref LL_DMA_STREAM_3
2629 * @arg @ref LL_DMA_STREAM_4
2630 * @arg @ref LL_DMA_STREAM_5
2631 * @arg @ref LL_DMA_STREAM_6
2632 * @arg @ref LL_DMA_STREAM_7
2633 * @retval None
2634 */
2635 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2636 {
2637 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2638 }
2639
2640 /**
2641 * @brief Disable Half transfer interrupt.
2642 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2643 * @param DMAx DMAx Instance
2644 * @param Stream This parameter can be one of the following values:
2645 * @arg @ref LL_DMA_STREAM_0
2646 * @arg @ref LL_DMA_STREAM_1
2647 * @arg @ref LL_DMA_STREAM_2
2648 * @arg @ref LL_DMA_STREAM_3
2649 * @arg @ref LL_DMA_STREAM_4
2650 * @arg @ref LL_DMA_STREAM_5
2651 * @arg @ref LL_DMA_STREAM_6
2652 * @arg @ref LL_DMA_STREAM_7
2653 * @retval None
2654 */
2655 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2656 {
2657 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2658 }
2659
2660 /**
2661 * @brief Disable Transfer error interrupt.
2662 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2663 * @param DMAx DMAx Instance
2664 * @param Stream This parameter can be one of the following values:
2665 * @arg @ref LL_DMA_STREAM_0
2666 * @arg @ref LL_DMA_STREAM_1
2667 * @arg @ref LL_DMA_STREAM_2
2668 * @arg @ref LL_DMA_STREAM_3
2669 * @arg @ref LL_DMA_STREAM_4
2670 * @arg @ref LL_DMA_STREAM_5
2671 * @arg @ref LL_DMA_STREAM_6
2672 * @arg @ref LL_DMA_STREAM_7
2673 * @retval None
2674 */
2675 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2676 {
2677 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2678 }
2679
2680 /**
2681 * @brief Disable Transfer complete interrupt.
2682 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2683 * @param DMAx DMAx Instance
2684 * @param Stream This parameter can be one of the following values:
2685 * @arg @ref LL_DMA_STREAM_0
2686 * @arg @ref LL_DMA_STREAM_1
2687 * @arg @ref LL_DMA_STREAM_2
2688 * @arg @ref LL_DMA_STREAM_3
2689 * @arg @ref LL_DMA_STREAM_4
2690 * @arg @ref LL_DMA_STREAM_5
2691 * @arg @ref LL_DMA_STREAM_6
2692 * @arg @ref LL_DMA_STREAM_7
2693 * @retval None
2694 */
2695 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2696 {
2697 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2698 }
2699
2700 /**
2701 * @brief Disable Direct mode error interrupt.
2702 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2703 * @param DMAx DMAx Instance
2704 * @param Stream This parameter can be one of the following values:
2705 * @arg @ref LL_DMA_STREAM_0
2706 * @arg @ref LL_DMA_STREAM_1
2707 * @arg @ref LL_DMA_STREAM_2
2708 * @arg @ref LL_DMA_STREAM_3
2709 * @arg @ref LL_DMA_STREAM_4
2710 * @arg @ref LL_DMA_STREAM_5
2711 * @arg @ref LL_DMA_STREAM_6
2712 * @arg @ref LL_DMA_STREAM_7
2713 * @retval None
2714 */
2715 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2716 {
2717 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2718 }
2719
2720 /**
2721 * @brief Disable FIFO error interrupt.
2722 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2723 * @param DMAx DMAx Instance
2724 * @param Stream This parameter can be one of the following values:
2725 * @arg @ref LL_DMA_STREAM_0
2726 * @arg @ref LL_DMA_STREAM_1
2727 * @arg @ref LL_DMA_STREAM_2
2728 * @arg @ref LL_DMA_STREAM_3
2729 * @arg @ref LL_DMA_STREAM_4
2730 * @arg @ref LL_DMA_STREAM_5
2731 * @arg @ref LL_DMA_STREAM_6
2732 * @arg @ref LL_DMA_STREAM_7
2733 * @retval None
2734 */
2735 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2736 {
2737 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2738 }
2739
2740 /**
2741 * @brief Check if Half transfer interrup is enabled.
2742 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2743 * @param DMAx DMAx Instance
2744 * @param Stream This parameter can be one of the following values:
2745 * @arg @ref LL_DMA_STREAM_0
2746 * @arg @ref LL_DMA_STREAM_1
2747 * @arg @ref LL_DMA_STREAM_2
2748 * @arg @ref LL_DMA_STREAM_3
2749 * @arg @ref LL_DMA_STREAM_4
2750 * @arg @ref LL_DMA_STREAM_5
2751 * @arg @ref LL_DMA_STREAM_6
2752 * @arg @ref LL_DMA_STREAM_7
2753 * @retval State of bit (1 or 0).
2754 */
2755 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2756 {
2757 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2758 }
2759
2760 /**
2761 * @brief Check if Transfer error nterrup is enabled.
2762 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2763 * @param DMAx DMAx Instance
2764 * @param Stream This parameter can be one of the following values:
2765 * @arg @ref LL_DMA_STREAM_0
2766 * @arg @ref LL_DMA_STREAM_1
2767 * @arg @ref LL_DMA_STREAM_2
2768 * @arg @ref LL_DMA_STREAM_3
2769 * @arg @ref LL_DMA_STREAM_4
2770 * @arg @ref LL_DMA_STREAM_5
2771 * @arg @ref LL_DMA_STREAM_6
2772 * @arg @ref LL_DMA_STREAM_7
2773 * @retval State of bit (1 or 0).
2774 */
2775 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2776 {
2777 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2778 }
2779
2780 /**
2781 * @brief Check if Transfer complete interrup is enabled.
2782 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2783 * @param DMAx DMAx Instance
2784 * @param Stream This parameter can be one of the following values:
2785 * @arg @ref LL_DMA_STREAM_0
2786 * @arg @ref LL_DMA_STREAM_1
2787 * @arg @ref LL_DMA_STREAM_2
2788 * @arg @ref LL_DMA_STREAM_3
2789 * @arg @ref LL_DMA_STREAM_4
2790 * @arg @ref LL_DMA_STREAM_5
2791 * @arg @ref LL_DMA_STREAM_6
2792 * @arg @ref LL_DMA_STREAM_7
2793 * @retval State of bit (1 or 0).
2794 */
2795 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2796 {
2797 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2798 }
2799
2800 /**
2801 * @brief Check if Direct mode error interrupt is enabled.
2802 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2803 * @param DMAx DMAx Instance
2804 * @param Stream This parameter can be one of the following values:
2805 * @arg @ref LL_DMA_STREAM_0
2806 * @arg @ref LL_DMA_STREAM_1
2807 * @arg @ref LL_DMA_STREAM_2
2808 * @arg @ref LL_DMA_STREAM_3
2809 * @arg @ref LL_DMA_STREAM_4
2810 * @arg @ref LL_DMA_STREAM_5
2811 * @arg @ref LL_DMA_STREAM_6
2812 * @arg @ref LL_DMA_STREAM_7
2813 * @retval State of bit (1 or 0).
2814 */
2815 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2816 {
2817 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2818 }
2819
2820 /**
2821 * @brief Check if FIFO error interrup is enabled.
2822 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2823 * @param DMAx DMAx Instance
2824 * @param Stream This parameter can be one of the following values:
2825 * @arg @ref LL_DMA_STREAM_0
2826 * @arg @ref LL_DMA_STREAM_1
2827 * @arg @ref LL_DMA_STREAM_2
2828 * @arg @ref LL_DMA_STREAM_3
2829 * @arg @ref LL_DMA_STREAM_4
2830 * @arg @ref LL_DMA_STREAM_5
2831 * @arg @ref LL_DMA_STREAM_6
2832 * @arg @ref LL_DMA_STREAM_7
2833 * @retval State of bit (1 or 0).
2834 */
2835 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2836 {
2837 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2838 }
2839
2840 /**
2841 * @}
2842 */
2843
2844 #if defined(USE_FULL_LL_DRIVER)
2845 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2846 * @{
2847 */
2848
2849 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2850 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2851 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2852
2853 /**
2854 * @}
2855 */
2856 #endif /* USE_FULL_LL_DRIVER */
2857
2858 /**
2859 * @}
2860 */
2861
2862 /**
2863 * @}
2864 */
2865
2866 #endif /* DMA1 || DMA2 */
2867
2868 /**
2869 * @}
2870 */
2871
2872 #ifdef __cplusplus
2873 }
2874 #endif
2875
2876 #endif /* __STM32F4xx_LL_DMA_H */
2877
2878 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/