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FIX: Flash page size check is STM (or clone) specific (#14130)
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Src / stm32f4xx_hal_tim.c
blobea68dd1fa761050cf7c9bbcdc6202965338919df
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_tim.c
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
11 * + Time Base Start
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
34 @verbatim
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
43 (++) Input Capture
44 (++) Output Compare
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
47
48 ##### How to use this driver #####
49 ==============================================================================
50 [..]
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
59
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
64 __GPIOx_CLK_ENABLE();
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
66
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
70 any start function.
71
72 (#) Configure the TIM in the desired functioning mode using one of the
73 initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
78 PWM signal.
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
80 external signal.
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
82 in One Pulse Mode.
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
84
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
92
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
96
97 @endverbatim
98 ******************************************************************************
99 * @attention
100 *
101 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
102 *
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
113 *
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
124 *
125 ******************************************************************************
126 */
127
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f4xx_hal.h"
130
131 /** @addtogroup STM32F4xx_HAL_Driver
132 * @{
133 */
134
135 /** @defgroup TIM TIM
136 * @brief TIM HAL module driver
137 * @{
138 */
139
140 #ifdef HAL_TIM_MODULE_ENABLED
141
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /** @addtogroup TIM_Private_Functions
147 * @{
148 */
149 /* Private function prototypes -----------------------------------------------*/
150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
153
154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
156 uint32_t TIM_ICFilter);
157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
159 uint32_t TIM_ICFilter);
160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
161 uint32_t TIM_ICFilter);
162
163 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
164 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
165
166 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
170 TIM_SlaveConfigTypeDef * sSlaveConfig);
171 /**
172 * @}
173 */
174
175 /* Exported functions --------------------------------------------------------*/
176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
177 * @{
178 */
179
180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
181 * @brief Time Base functions
182 *
183 @verbatim
184 ==============================================================================
185 ##### Time Base functions #####
186 ==============================================================================
187 [..]
188 This section provides functions allowing to:
189 (+) Initialize and configure the TIM base.
190 (+) De-initialize the TIM base.
191 (+) Start the Time Base.
192 (+) Stop the Time Base.
193 (+) Start the Time Base and enable interrupt.
194 (+) Stop the Time Base and disable interrupt.
195 (+) Start the Time Base and enable DMA transfer.
196 (+) Stop the Time Base and disable DMA transfer.
197
198 @endverbatim
199 * @{
200 */
201 /**
202 * @brief Initializes the TIM Time base Unit according to the specified
203 * parameters in the TIM_HandleTypeDef and create the associated handle.
204 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
205 * the configuration information for TIM module.
206 * @retval HAL status
207 */
208 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
209 {
210 /* Check the TIM handle allocation */
211 if(htim == NULL)
212 {
213 return HAL_ERROR;
214 }
215
216 /* Check the parameters */
217 assert_param(IS_TIM_INSTANCE(htim->Instance));
218 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
219 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
220
221 if(htim->State == HAL_TIM_STATE_RESET)
222 {
223 /* Allocate lock resource and initialize it */
224 htim->Lock = HAL_UNLOCKED;
225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
226 HAL_TIM_Base_MspInit(htim);
227 }
228
229 /* Set the TIM state */
230 htim->State= HAL_TIM_STATE_BUSY;
231
232 /* Set the Time Base configuration */
233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
234
235 /* Initialize the TIM state*/
236 htim->State= HAL_TIM_STATE_READY;
237
238 return HAL_OK;
239 }
240
241 /**
242 * @brief DeInitializes the TIM Base peripheral
243 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
244 * the configuration information for TIM module.
245 * @retval HAL status
246 */
247 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
248 {
249 /* Check the parameters */
250 assert_param(IS_TIM_INSTANCE(htim->Instance));
251
252 htim->State = HAL_TIM_STATE_BUSY;
253
254 /* Disable the TIM Peripheral Clock */
255 __HAL_TIM_DISABLE(htim);
256
257 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
258 HAL_TIM_Base_MspDeInit(htim);
259
260 /* Change TIM state */
261 htim->State = HAL_TIM_STATE_RESET;
262
263 /* Release Lock */
264 __HAL_UNLOCK(htim);
265
266 return HAL_OK;
267 }
268
269 /**
270 * @brief Initializes the TIM Base MSP.
271 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
272 * the configuration information for TIM module.
273 * @retval None
274 */
275 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
276 {
277 /* Prevent unused argument(s) compilation warning */
278 UNUSED(htim);
279 /* NOTE : This function Should not be modified, when the callback is needed,
280 the HAL_TIM_Base_MspInit could be implemented in the user file
281 */
282 }
283
284 /**
285 * @brief DeInitializes TIM Base MSP.
286 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
287 * the configuration information for TIM module.
288 * @retval None
289 */
290 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
291 {
292 /* Prevent unused argument(s) compilation warning */
293 UNUSED(htim);
294 /* NOTE : This function Should not be modified, when the callback is needed,
295 the HAL_TIM_Base_MspDeInit could be implemented in the user file
296 */
297 }
298
299 /**
300 * @brief Starts the TIM Base generation.
301 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
302 * the configuration information for TIM module.
303 * @retval HAL status
304 */
305 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
306 {
307 /* Check the parameters */
308 assert_param(IS_TIM_INSTANCE(htim->Instance));
309
310 /* Set the TIM state */
311 htim->State= HAL_TIM_STATE_BUSY;
312
313 /* Enable the Peripheral */
314 __HAL_TIM_ENABLE(htim);
315
316 /* Change the TIM state*/
317 htim->State= HAL_TIM_STATE_READY;
318
319 /* Return function status */
320 return HAL_OK;
321 }
322
323 /**
324 * @brief Stops the TIM Base generation.
325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
326 * the configuration information for TIM module.
327 * @retval HAL status
328 */
329 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
330 {
331 /* Check the parameters */
332 assert_param(IS_TIM_INSTANCE(htim->Instance));
333
334 /* Set the TIM state */
335 htim->State= HAL_TIM_STATE_BUSY;
336
337 /* Disable the Peripheral */
338 __HAL_TIM_DISABLE(htim);
339
340 /* Change the TIM state*/
341 htim->State= HAL_TIM_STATE_READY;
342
343 /* Return function status */
344 return HAL_OK;
345 }
346
347 /**
348 * @brief Starts the TIM Base generation in interrupt mode.
349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
350 * the configuration information for TIM module.
351 * @retval HAL status
352 */
353 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
354 {
355 /* Check the parameters */
356 assert_param(IS_TIM_INSTANCE(htim->Instance));
357
358 /* Enable the TIM Update interrupt */
359 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
360
361 /* Enable the Peripheral */
362 __HAL_TIM_ENABLE(htim);
363
364 /* Return function status */
365 return HAL_OK;
366 }
367
368 /**
369 * @brief Stops the TIM Base generation in interrupt mode.
370 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
371 * the configuration information for TIM module.
372 * @retval HAL status
373 */
374 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
375 {
376 /* Check the parameters */
377 assert_param(IS_TIM_INSTANCE(htim->Instance));
378 /* Disable the TIM Update interrupt */
379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
380
381 /* Disable the Peripheral */
382 __HAL_TIM_DISABLE(htim);
383
384 /* Return function status */
385 return HAL_OK;
386 }
387
388 /**
389 * @brief Starts the TIM Base generation in DMA mode.
390 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
391 * the configuration information for TIM module.
392 * @param pData: The source Buffer address.
393 * @param Length: The length of data to be transferred from memory to peripheral.
394 * @retval HAL status
395 */
396 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
397 {
398 /* Check the parameters */
399 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
400
401 if((htim->State == HAL_TIM_STATE_BUSY))
402 {
403 return HAL_BUSY;
404 }
405 else if((htim->State == HAL_TIM_STATE_READY))
406 {
407 if((pData == 0U) && (Length > 0))
408 {
409 return HAL_ERROR;
410 }
411 else
412 {
413 htim->State = HAL_TIM_STATE_BUSY;
414 }
415 }
416 /* Set the DMA Period elapsed callback */
417 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
418
419 /* Set the DMA error callback */
420 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
421
422 /* Enable the DMA Stream */
423 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
424
425 /* Enable the TIM Update DMA request */
426 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
427
428 /* Enable the Peripheral */
429 __HAL_TIM_ENABLE(htim);
430
431 /* Return function status */
432 return HAL_OK;
433 }
434
435 /**
436 * @brief Stops the TIM Base generation in DMA mode.
437 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
438 * the configuration information for TIM module.
439 * @retval HAL status
440 */
441 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
442 {
443 /* Check the parameters */
444 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
445
446 /* Disable the TIM Update DMA request */
447 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
448
449 /* Disable the Peripheral */
450 __HAL_TIM_DISABLE(htim);
451
452 /* Change the htim state */
453 htim->State = HAL_TIM_STATE_READY;
454
455 /* Return function status */
456 return HAL_OK;
457 }
458 /**
459 * @}
460 */
461
462 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
463 * @brief Time Output Compare functions
464 *
465 @verbatim
466 ==============================================================================
467 ##### Time Output Compare functions #####
468 ==============================================================================
469 [..]
470 This section provides functions allowing to:
471 (+) Initialize and configure the TIM Output Compare.
472 (+) De-initialize the TIM Output Compare.
473 (+) Start the Time Output Compare.
474 (+) Stop the Time Output Compare.
475 (+) Start the Time Output Compare and enable interrupt.
476 (+) Stop the Time Output Compare and disable interrupt.
477 (+) Start the Time Output Compare and enable DMA transfer.
478 (+) Stop the Time Output Compare and disable DMA transfer.
479
480 @endverbatim
481 * @{
482 */
483 /**
484 * @brief Initializes the TIM Output Compare according to the specified
485 * parameters in the TIM_HandleTypeDef and create the associated handle.
486 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
487 * the configuration information for TIM module.
488 * @retval HAL status
489 */
490 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
491 {
492 /* Check the TIM handle allocation */
493 if(htim == NULL)
494 {
495 return HAL_ERROR;
496 }
497
498 /* Check the parameters */
499 assert_param(IS_TIM_INSTANCE(htim->Instance));
500 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
501 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
502
503 if(htim->State == HAL_TIM_STATE_RESET)
504 {
505 /* Allocate lock resource and initialize it */
506 htim->Lock = HAL_UNLOCKED;
507 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
508 HAL_TIM_OC_MspInit(htim);
509 }
510
511 /* Set the TIM state */
512 htim->State= HAL_TIM_STATE_BUSY;
513
514 /* Init the base time for the Output Compare */
515 TIM_Base_SetConfig(htim->Instance, &htim->Init);
516
517 /* Initialize the TIM state*/
518 htim->State= HAL_TIM_STATE_READY;
519
520 return HAL_OK;
521 }
522
523 /**
524 * @brief DeInitializes the TIM peripheral
525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
526 * the configuration information for TIM module.
527 * @retval HAL status
528 */
529 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
530 {
531 /* Check the parameters */
532 assert_param(IS_TIM_INSTANCE(htim->Instance));
533
534 htim->State = HAL_TIM_STATE_BUSY;
535
536 /* Disable the TIM Peripheral Clock */
537 __HAL_TIM_DISABLE(htim);
538
539 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
540 HAL_TIM_OC_MspDeInit(htim);
541
542 /* Change TIM state */
543 htim->State = HAL_TIM_STATE_RESET;
544
545 /* Release Lock */
546 __HAL_UNLOCK(htim);
547
548 return HAL_OK;
549 }
550
551 /**
552 * @brief Initializes the TIM Output Compare MSP.
553 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
554 * the configuration information for TIM module.
555 * @retval None
556 */
557 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
558 {
559 /* Prevent unused argument(s) compilation warning */
560 UNUSED(htim);
561 /* NOTE : This function Should not be modified, when the callback is needed,
562 the HAL_TIM_OC_MspInit could be implemented in the user file
563 */
564 }
565
566 /**
567 * @brief DeInitializes TIM Output Compare MSP.
568 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
569 * the configuration information for TIM module.
570 * @retval None
571 */
572 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
573 {
574 /* Prevent unused argument(s) compilation warning */
575 UNUSED(htim);
576 /* NOTE : This function Should not be modified, when the callback is needed,
577 the HAL_TIM_OC_MspDeInit could be implemented in the user file
578 */
579 }
580
581 /**
582 * @brief Starts the TIM Output Compare signal generation.
583 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
584 * the configuration information for TIM module.
585 * @param Channel: TIM Channel to be enabled.
586 * This parameter can be one of the following values:
587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
591 * @retval HAL status
592 */
593 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
594 {
595 /* Check the parameters */
596 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
597
598 /* Enable the Output compare channel */
599 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
600
601 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
602 {
603 /* Enable the main output */
604 __HAL_TIM_MOE_ENABLE(htim);
605 }
606
607 /* Enable the Peripheral */
608 __HAL_TIM_ENABLE(htim);
609
610 /* Return function status */
611 return HAL_OK;
612 }
613
614 /**
615 * @brief Stops the TIM Output Compare signal generation.
616 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
617 * the configuration information for TIM module.
618 * @param Channel: TIM Channel to be disabled.
619 * This parameter can be one of the following values:
620 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
621 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
622 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
623 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
624 * @retval HAL status
625 */
626 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
627 {
628 /* Check the parameters */
629 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
630
631 /* Disable the Output compare channel */
632 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
633
634 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
635 {
636 /* Disable the Main Output */
637 __HAL_TIM_MOE_DISABLE(htim);
638 }
639
640 /* Disable the Peripheral */
641 __HAL_TIM_DISABLE(htim);
642
643 /* Return function status */
644 return HAL_OK;
645 }
646
647 /**
648 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
649 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
650 * the configuration information for TIM module.
651 * @param Channel: TIM Channel to be enabled.
652 * This parameter can be one of the following values:
653 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
654 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
655 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
656 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
657 * @retval HAL status
658 */
659 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
660 {
661 /* Check the parameters */
662 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
663
664 switch (Channel)
665 {
666 case TIM_CHANNEL_1:
667 {
668 /* Enable the TIM Capture/Compare 1 interrupt */
669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
670 }
671 break;
672
673 case TIM_CHANNEL_2:
674 {
675 /* Enable the TIM Capture/Compare 2 interrupt */
676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
677 }
678 break;
679
680 case TIM_CHANNEL_3:
681 {
682 /* Enable the TIM Capture/Compare 3 interrupt */
683 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
684 }
685 break;
686
687 case TIM_CHANNEL_4:
688 {
689 /* Enable the TIM Capture/Compare 4 interrupt */
690 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
691 }
692 break;
693
694 default:
695 break;
696 }
697
698 /* Enable the Output compare channel */
699 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
700
701 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
702 {
703 /* Enable the main output */
704 __HAL_TIM_MOE_ENABLE(htim);
705 }
706
707 /* Enable the Peripheral */
708 __HAL_TIM_ENABLE(htim);
709
710 /* Return function status */
711 return HAL_OK;
712 }
713
714 /**
715 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
716 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
717 * the configuration information for TIM module.
718 * @param Channel: TIM Channel to be disabled.
719 * This parameter can be one of the following values:
720 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
721 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
722 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
723 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
724 * @retval HAL status
725 */
726 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
727 {
728 /* Check the parameters */
729 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
730
731 switch (Channel)
732 {
733 case TIM_CHANNEL_1:
734 {
735 /* Disable the TIM Capture/Compare 1 interrupt */
736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
737 }
738 break;
739
740 case TIM_CHANNEL_2:
741 {
742 /* Disable the TIM Capture/Compare 2 interrupt */
743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
744 }
745 break;
746
747 case TIM_CHANNEL_3:
748 {
749 /* Disable the TIM Capture/Compare 3 interrupt */
750 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
751 }
752 break;
753
754 case TIM_CHANNEL_4:
755 {
756 /* Disable the TIM Capture/Compare 4 interrupt */
757 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
758 }
759 break;
760
761 default:
762 break;
763 }
764
765 /* Disable the Output compare channel */
766 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
767
768 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
769 {
770 /* Disable the Main Output */
771 __HAL_TIM_MOE_DISABLE(htim);
772 }
773
774 /* Disable the Peripheral */
775 __HAL_TIM_DISABLE(htim);
776
777 /* Return function status */
778 return HAL_OK;
779 }
780
781 /**
782 * @brief Starts the TIM Output Compare signal generation in DMA mode.
783 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
784 * the configuration information for TIM module.
785 * @param Channel: TIM Channel to be enabled.
786 * This parameter can be one of the following values:
787 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
788 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
789 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
790 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
791 * @param pData: The source Buffer address.
792 * @param Length: The length of data to be transferred from memory to TIM peripheral
793 * @retval HAL status
794 */
795 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
796 {
797 /* Check the parameters */
798 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
799
800 if((htim->State == HAL_TIM_STATE_BUSY))
801 {
802 return HAL_BUSY;
803 }
804 else if((htim->State == HAL_TIM_STATE_READY))
805 {
806 if(((uint32_t)pData == 0U) && (Length > 0))
807 {
808 return HAL_ERROR;
809 }
810 else
811 {
812 htim->State = HAL_TIM_STATE_BUSY;
813 }
814 }
815 switch (Channel)
816 {
817 case TIM_CHANNEL_1:
818 {
819 /* Set the DMA Period elapsed callback */
820 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
821
822 /* Set the DMA error callback */
823 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
824
825 /* Enable the DMA Stream */
826 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
827
828 /* Enable the TIM Capture/Compare 1 DMA request */
829 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
830 }
831 break;
832
833 case TIM_CHANNEL_2:
834 {
835 /* Set the DMA Period elapsed callback */
836 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
837
838 /* Set the DMA error callback */
839 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
840
841 /* Enable the DMA Stream */
842 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
843
844 /* Enable the TIM Capture/Compare 2 DMA request */
845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
846 }
847 break;
848
849 case TIM_CHANNEL_3:
850 {
851 /* Set the DMA Period elapsed callback */
852 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
853
854 /* Set the DMA error callback */
855 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
856
857 /* Enable the DMA Stream */
858 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
859
860 /* Enable the TIM Capture/Compare 3 DMA request */
861 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
862 }
863 break;
864
865 case TIM_CHANNEL_4:
866 {
867 /* Set the DMA Period elapsed callback */
868 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
869
870 /* Set the DMA error callback */
871 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
872
873 /* Enable the DMA Stream */
874 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
875
876 /* Enable the TIM Capture/Compare 4 DMA request */
877 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
878 }
879 break;
880
881 default:
882 break;
883 }
884
885 /* Enable the Output compare channel */
886 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
887
888 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
889 {
890 /* Enable the main output */
891 __HAL_TIM_MOE_ENABLE(htim);
892 }
893
894 /* Enable the Peripheral */
895 __HAL_TIM_ENABLE(htim);
896
897 /* Return function status */
898 return HAL_OK;
899 }
900
901 /**
902 * @brief Stops the TIM Output Compare signal generation in DMA mode.
903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
904 * the configuration information for TIM module.
905 * @param Channel: TIM Channel to be disabled.
906 * This parameter can be one of the following values:
907 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
908 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
909 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
910 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
911 * @retval HAL status
912 */
913 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
914 {
915 /* Check the parameters */
916 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
917
918 switch (Channel)
919 {
920 case TIM_CHANNEL_1:
921 {
922 /* Disable the TIM Capture/Compare 1 DMA request */
923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
924 }
925 break;
926
927 case TIM_CHANNEL_2:
928 {
929 /* Disable the TIM Capture/Compare 2 DMA request */
930 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
931 }
932 break;
933
934 case TIM_CHANNEL_3:
935 {
936 /* Disable the TIM Capture/Compare 3 DMA request */
937 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
938 }
939 break;
940
941 case TIM_CHANNEL_4:
942 {
943 /* Disable the TIM Capture/Compare 4 interrupt */
944 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
945 }
946 break;
947
948 default:
949 break;
950 }
951
952 /* Disable the Output compare channel */
953 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
954
955 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
956 {
957 /* Disable the Main Output */
958 __HAL_TIM_MOE_DISABLE(htim);
959 }
960
961 /* Disable the Peripheral */
962 __HAL_TIM_DISABLE(htim);
963
964 /* Change the htim state */
965 htim->State = HAL_TIM_STATE_READY;
966
967 /* Return function status */
968 return HAL_OK;
969 }
970 /**
971 * @}
972 */
973
974 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
975 * @brief Time PWM functions
976 *
977 @verbatim
978 ==============================================================================
979 ##### Time PWM functions #####
980 ==============================================================================
981 [..]
982 This section provides functions allowing to:
983 (+) Initialize and configure the TIM OPWM.
984 (+) De-initialize the TIM PWM.
985 (+) Start the Time PWM.
986 (+) Stop the Time PWM.
987 (+) Start the Time PWM and enable interrupt.
988 (+) Stop the Time PWM and disable interrupt.
989 (+) Start the Time PWM and enable DMA transfer.
990 (+) Stop the Time PWM and disable DMA transfer.
991
992 @endverbatim
993 * @{
994 */
995 /**
996 * @brief Initializes the TIM PWM Time Base according to the specified
997 * parameters in the TIM_HandleTypeDef and create the associated handle.
998 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
999 * the configuration information for TIM module.
1000 * @retval HAL status
1001 */
1002 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1003 {
1004 /* Check the TIM handle allocation */
1005 if(htim == NULL)
1006 {
1007 return HAL_ERROR;
1008 }
1009
1010 /* Check the parameters */
1011 assert_param(IS_TIM_INSTANCE(htim->Instance));
1012 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1013 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1014
1015 if(htim->State == HAL_TIM_STATE_RESET)
1016 {
1017 /* Allocate lock resource and initialize it */
1018 htim->Lock = HAL_UNLOCKED;
1019 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1020 HAL_TIM_PWM_MspInit(htim);
1021 }
1022
1023 /* Set the TIM state */
1024 htim->State= HAL_TIM_STATE_BUSY;
1025
1026 /* Init the base time for the PWM */
1027 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1028
1029 /* Initialize the TIM state*/
1030 htim->State= HAL_TIM_STATE_READY;
1031
1032 return HAL_OK;
1033 }
1034
1035 /**
1036 * @brief DeInitializes the TIM peripheral
1037 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1038 * the configuration information for TIM module.
1039 * @retval HAL status
1040 */
1041 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1042 {
1043 /* Check the parameters */
1044 assert_param(IS_TIM_INSTANCE(htim->Instance));
1045
1046 htim->State = HAL_TIM_STATE_BUSY;
1047
1048 /* Disable the TIM Peripheral Clock */
1049 __HAL_TIM_DISABLE(htim);
1050
1051 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1052 HAL_TIM_PWM_MspDeInit(htim);
1053
1054 /* Change TIM state */
1055 htim->State = HAL_TIM_STATE_RESET;
1056
1057 /* Release Lock */
1058 __HAL_UNLOCK(htim);
1059
1060 return HAL_OK;
1061 }
1062
1063 /**
1064 * @brief Initializes the TIM PWM MSP.
1065 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1066 * the configuration information for TIM module.
1067 * @retval None
1068 */
1069 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1070 {
1071 /* Prevent unused argument(s) compilation warning */
1072 UNUSED(htim);
1073 /* NOTE : This function Should not be modified, when the callback is needed,
1074 the HAL_TIM_PWM_MspInit could be implemented in the user file
1075 */
1076 }
1077
1078 /**
1079 * @brief DeInitializes TIM PWM MSP.
1080 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1081 * the configuration information for TIM module.
1082 * @retval None
1083 */
1084 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1085 {
1086 /* Prevent unused argument(s) compilation warning */
1087 UNUSED(htim);
1088 /* NOTE : This function Should not be modified, when the callback is needed,
1089 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1090 */
1091 }
1092
1093 /**
1094 * @brief Starts the PWM signal generation.
1095 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1096 * the configuration information for TIM module.
1097 * @param Channel: TIM Channels to be enabled.
1098 * This parameter can be one of the following values:
1099 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1100 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1101 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1102 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1103 * @retval HAL status
1104 */
1105 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1106 {
1107 /* Check the parameters */
1108 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1109
1110 /* Enable the Capture compare channel */
1111 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1112
1113 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1114 {
1115 /* Enable the main output */
1116 __HAL_TIM_MOE_ENABLE(htim);
1117 }
1118
1119 /* Enable the Peripheral */
1120 __HAL_TIM_ENABLE(htim);
1121
1122 /* Return function status */
1123 return HAL_OK;
1124 }
1125
1126 /**
1127 * @brief Stops the PWM signal generation.
1128 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1129 * the configuration information for TIM module.
1130 * @param Channel: TIM Channels to be disabled.
1131 * This parameter can be one of the following values:
1132 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1133 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1134 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1135 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1136 * @retval HAL status
1137 */
1138 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1139 {
1140 /* Check the parameters */
1141 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1142
1143 /* Disable the Capture compare channel */
1144 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1145
1146 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1147 {
1148 /* Disable the Main Output */
1149 __HAL_TIM_MOE_DISABLE(htim);
1150 }
1151
1152 /* Disable the Peripheral */
1153 __HAL_TIM_DISABLE(htim);
1154
1155 /* Change the htim state */
1156 htim->State = HAL_TIM_STATE_READY;
1157
1158 /* Return function status */
1159 return HAL_OK;
1160 }
1161
1162 /**
1163 * @brief Starts the PWM signal generation in interrupt mode.
1164 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1165 * the configuration information for TIM module.
1166 * @param Channel: TIM Channel to be enabled.
1167 * This parameter can be one of the following values:
1168 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1169 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1170 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1171 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1172 * @retval HAL status
1173 */
1174 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1175 {
1176 /* Check the parameters */
1177 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1178
1179 switch (Channel)
1180 {
1181 case TIM_CHANNEL_1:
1182 {
1183 /* Enable the TIM Capture/Compare 1 interrupt */
1184 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1185 }
1186 break;
1187
1188 case TIM_CHANNEL_2:
1189 {
1190 /* Enable the TIM Capture/Compare 2 interrupt */
1191 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1192 }
1193 break;
1194
1195 case TIM_CHANNEL_3:
1196 {
1197 /* Enable the TIM Capture/Compare 3 interrupt */
1198 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1199 }
1200 break;
1201
1202 case TIM_CHANNEL_4:
1203 {
1204 /* Enable the TIM Capture/Compare 4 interrupt */
1205 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1206 }
1207 break;
1208
1209 default:
1210 break;
1211 }
1212
1213 /* Enable the Capture compare channel */
1214 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1215
1216 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1217 {
1218 /* Enable the main output */
1219 __HAL_TIM_MOE_ENABLE(htim);
1220 }
1221
1222 /* Enable the Peripheral */
1223 __HAL_TIM_ENABLE(htim);
1224
1225 /* Return function status */
1226 return HAL_OK;
1227 }
1228
1229 /**
1230 * @brief Stops the PWM signal generation in interrupt mode.
1231 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1232 * the configuration information for TIM module.
1233 * @param Channel: TIM Channels to be disabled.
1234 * This parameter can be one of the following values:
1235 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1236 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1237 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1238 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1239 * @retval HAL status
1240 */
1241 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1242 {
1243 /* Check the parameters */
1244 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1245
1246 switch (Channel)
1247 {
1248 case TIM_CHANNEL_1:
1249 {
1250 /* Disable the TIM Capture/Compare 1 interrupt */
1251 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1252 }
1253 break;
1254
1255 case TIM_CHANNEL_2:
1256 {
1257 /* Disable the TIM Capture/Compare 2 interrupt */
1258 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1259 }
1260 break;
1261
1262 case TIM_CHANNEL_3:
1263 {
1264 /* Disable the TIM Capture/Compare 3 interrupt */
1265 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1266 }
1267 break;
1268
1269 case TIM_CHANNEL_4:
1270 {
1271 /* Disable the TIM Capture/Compare 4 interrupt */
1272 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1273 }
1274 break;
1275
1276 default:
1277 break;
1278 }
1279
1280 /* Disable the Capture compare channel */
1281 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1282
1283 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1284 {
1285 /* Disable the Main Output */
1286 __HAL_TIM_MOE_DISABLE(htim);
1287 }
1288
1289 /* Disable the Peripheral */
1290 __HAL_TIM_DISABLE(htim);
1291
1292 /* Return function status */
1293 return HAL_OK;
1294 }
1295
1296 /**
1297 * @brief Starts the TIM PWM signal generation in DMA mode.
1298 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1299 * the configuration information for TIM module.
1300 * @param Channel: TIM Channels to be enabled.
1301 * This parameter can be one of the following values:
1302 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1303 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1304 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1305 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1306 * @param pData: The source Buffer address.
1307 * @param Length: The length of data to be transferred from memory to TIM peripheral
1308 * @retval HAL status
1309 */
1310 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1311 {
1312 /* Check the parameters */
1313 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1314
1315 if((htim->State == HAL_TIM_STATE_BUSY))
1316 {
1317 return HAL_BUSY;
1318 }
1319 else if((htim->State == HAL_TIM_STATE_READY))
1320 {
1321 if(((uint32_t)pData == 0U) && (Length > 0))
1322 {
1323 return HAL_ERROR;
1324 }
1325 else
1326 {
1327 htim->State = HAL_TIM_STATE_BUSY;
1328 }
1329 }
1330 switch (Channel)
1331 {
1332 case TIM_CHANNEL_1:
1333 {
1334 /* Set the DMA Period elapsed callback */
1335 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1336
1337 /* Set the DMA error callback */
1338 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1339
1340 /* Enable the DMA Stream */
1341 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1342
1343 /* Enable the TIM Capture/Compare 1 DMA request */
1344 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1345 }
1346 break;
1347
1348 case TIM_CHANNEL_2:
1349 {
1350 /* Set the DMA Period elapsed callback */
1351 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1352
1353 /* Set the DMA error callback */
1354 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1355
1356 /* Enable the DMA Stream */
1357 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1358
1359 /* Enable the TIM Capture/Compare 2 DMA request */
1360 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1361 }
1362 break;
1363
1364 case TIM_CHANNEL_3:
1365 {
1366 /* Set the DMA Period elapsed callback */
1367 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1368
1369 /* Set the DMA error callback */
1370 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1371
1372 /* Enable the DMA Stream */
1373 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1374
1375 /* Enable the TIM Output Capture/Compare 3 request */
1376 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1377 }
1378 break;
1379
1380 case TIM_CHANNEL_4:
1381 {
1382 /* Set the DMA Period elapsed callback */
1383 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1384
1385 /* Set the DMA error callback */
1386 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1387
1388 /* Enable the DMA Stream */
1389 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1390
1391 /* Enable the TIM Capture/Compare 4 DMA request */
1392 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1393 }
1394 break;
1395
1396 default:
1397 break;
1398 }
1399
1400 /* Enable the Capture compare channel */
1401 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1402
1403 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1404 {
1405 /* Enable the main output */
1406 __HAL_TIM_MOE_ENABLE(htim);
1407 }
1408
1409 /* Enable the Peripheral */
1410 __HAL_TIM_ENABLE(htim);
1411
1412 /* Return function status */
1413 return HAL_OK;
1414 }
1415
1416 /**
1417 * @brief Stops the TIM PWM signal generation in DMA mode.
1418 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1419 * the configuration information for TIM module.
1420 * @param Channel: TIM Channels to be disabled.
1421 * This parameter can be one of the following values:
1422 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1423 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1424 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1425 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1426 * @retval HAL status
1427 */
1428 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1429 {
1430 /* Check the parameters */
1431 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1432
1433 switch (Channel)
1434 {
1435 case TIM_CHANNEL_1:
1436 {
1437 /* Disable the TIM Capture/Compare 1 DMA request */
1438 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1439 }
1440 break;
1441
1442 case TIM_CHANNEL_2:
1443 {
1444 /* Disable the TIM Capture/Compare 2 DMA request */
1445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1446 }
1447 break;
1448
1449 case TIM_CHANNEL_3:
1450 {
1451 /* Disable the TIM Capture/Compare 3 DMA request */
1452 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1453 }
1454 break;
1455
1456 case TIM_CHANNEL_4:
1457 {
1458 /* Disable the TIM Capture/Compare 4 interrupt */
1459 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1460 }
1461 break;
1462
1463 default:
1464 break;
1465 }
1466
1467 /* Disable the Capture compare channel */
1468 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1469
1470 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
1471 {
1472 /* Disable the Main Output */
1473 __HAL_TIM_MOE_DISABLE(htim);
1474 }
1475
1476 /* Disable the Peripheral */
1477 __HAL_TIM_DISABLE(htim);
1478
1479 /* Change the htim state */
1480 htim->State = HAL_TIM_STATE_READY;
1481
1482 /* Return function status */
1483 return HAL_OK;
1484 }
1485 /**
1486 * @}
1487 */
1488
1489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1490 * @brief Time Input Capture functions
1491 *
1492 @verbatim
1493 ==============================================================================
1494 ##### Time Input Capture functions #####
1495 ==============================================================================
1496 [..]
1497 This section provides functions allowing to:
1498 (+) Initialize and configure the TIM Input Capture.
1499 (+) De-initialize the TIM Input Capture.
1500 (+) Start the Time Input Capture.
1501 (+) Stop the Time Input Capture.
1502 (+) Start the Time Input Capture and enable interrupt.
1503 (+) Stop the Time Input Capture and disable interrupt.
1504 (+) Start the Time Input Capture and enable DMA transfer.
1505 (+) Stop the Time Input Capture and disable DMA transfer.
1506
1507 @endverbatim
1508 * @{
1509 */
1510 /**
1511 * @brief Initializes the TIM Input Capture Time base according to the specified
1512 * parameters in the TIM_HandleTypeDef and create the associated handle.
1513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1514 * the configuration information for TIM module.
1515 * @retval HAL status
1516 */
1517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1518 {
1519 /* Check the TIM handle allocation */
1520 if(htim == NULL)
1521 {
1522 return HAL_ERROR;
1523 }
1524
1525 /* Check the parameters */
1526 assert_param(IS_TIM_INSTANCE(htim->Instance));
1527 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1528 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1529
1530 if(htim->State == HAL_TIM_STATE_RESET)
1531 {
1532 /* Allocate lock resource and initialize it */
1533 htim->Lock = HAL_UNLOCKED;
1534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1535 HAL_TIM_IC_MspInit(htim);
1536 }
1537
1538 /* Set the TIM state */
1539 htim->State= HAL_TIM_STATE_BUSY;
1540
1541 /* Init the base time for the input capture */
1542 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1543
1544 /* Initialize the TIM state*/
1545 htim->State= HAL_TIM_STATE_READY;
1546
1547 return HAL_OK;
1548 }
1549
1550 /**
1551 * @brief DeInitializes the TIM peripheral
1552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1553 * the configuration information for TIM module.
1554 * @retval HAL status
1555 */
1556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1557 {
1558 /* Check the parameters */
1559 assert_param(IS_TIM_INSTANCE(htim->Instance));
1560
1561 htim->State = HAL_TIM_STATE_BUSY;
1562
1563 /* Disable the TIM Peripheral Clock */
1564 __HAL_TIM_DISABLE(htim);
1565
1566 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1567 HAL_TIM_IC_MspDeInit(htim);
1568
1569 /* Change TIM state */
1570 htim->State = HAL_TIM_STATE_RESET;
1571
1572 /* Release Lock */
1573 __HAL_UNLOCK(htim);
1574
1575 return HAL_OK;
1576 }
1577
1578 /**
1579 * @brief Initializes the TIM INput Capture MSP.
1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1581 * the configuration information for TIM module.
1582 * @retval None
1583 */
1584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1585 {
1586 /* Prevent unused argument(s) compilation warning */
1587 UNUSED(htim);
1588 /* NOTE : This function Should not be modified, when the callback is needed,
1589 the HAL_TIM_IC_MspInit could be implemented in the user file
1590 */
1591 }
1592
1593 /**
1594 * @brief DeInitializes TIM Input Capture MSP.
1595 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1596 * the configuration information for TIM module.
1597 * @retval None
1598 */
1599 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1600 {
1601 /* Prevent unused argument(s) compilation warning */
1602 UNUSED(htim);
1603 /* NOTE : This function Should not be modified, when the callback is needed,
1604 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1605 */
1606 }
1607
1608 /**
1609 * @brief Starts the TIM Input Capture measurement.
1610 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1611 * the configuration information for TIM module.
1612 * @param Channel: TIM Channels to be enabled.
1613 * This parameter can be one of the following values:
1614 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1615 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1616 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1617 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1618 * @retval HAL status
1619 */
1620 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1621 {
1622 /* Check the parameters */
1623 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1624
1625 /* Enable the Input Capture channel */
1626 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1627
1628 /* Enable the Peripheral */
1629 __HAL_TIM_ENABLE(htim);
1630
1631 /* Return function status */
1632 return HAL_OK;
1633 }
1634
1635 /**
1636 * @brief Stops the TIM Input Capture measurement.
1637 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1638 * the configuration information for TIM module.
1639 * @param Channel: TIM Channels to be disabled.
1640 * This parameter can be one of the following values:
1641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1645 * @retval HAL status
1646 */
1647 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1648 {
1649 /* Check the parameters */
1650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1651
1652 /* Disable the Input Capture channel */
1653 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1654
1655 /* Disable the Peripheral */
1656 __HAL_TIM_DISABLE(htim);
1657
1658 /* Return function status */
1659 return HAL_OK;
1660 }
1661
1662 /**
1663 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1664 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1665 * the configuration information for TIM module.
1666 * @param Channel: TIM Channels to be enabled.
1667 * This parameter can be one of the following values:
1668 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1669 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1670 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1671 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1672 * @retval HAL status
1673 */
1674 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1675 {
1676 /* Check the parameters */
1677 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1678
1679 switch (Channel)
1680 {
1681 case TIM_CHANNEL_1:
1682 {
1683 /* Enable the TIM Capture/Compare 1 interrupt */
1684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1685 }
1686 break;
1687
1688 case TIM_CHANNEL_2:
1689 {
1690 /* Enable the TIM Capture/Compare 2 interrupt */
1691 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1692 }
1693 break;
1694
1695 case TIM_CHANNEL_3:
1696 {
1697 /* Enable the TIM Capture/Compare 3 interrupt */
1698 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1699 }
1700 break;
1701
1702 case TIM_CHANNEL_4:
1703 {
1704 /* Enable the TIM Capture/Compare 4 interrupt */
1705 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1706 }
1707 break;
1708
1709 default:
1710 break;
1711 }
1712 /* Enable the Input Capture channel */
1713 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1714
1715 /* Enable the Peripheral */
1716 __HAL_TIM_ENABLE(htim);
1717
1718 /* Return function status */
1719 return HAL_OK;
1720 }
1721
1722 /**
1723 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1724 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1725 * the configuration information for TIM module.
1726 * @param Channel: TIM Channels to be disabled.
1727 * This parameter can be one of the following values:
1728 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1729 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1730 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1731 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1732 * @retval HAL status
1733 */
1734 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1735 {
1736 /* Check the parameters */
1737 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1738
1739 switch (Channel)
1740 {
1741 case TIM_CHANNEL_1:
1742 {
1743 /* Disable the TIM Capture/Compare 1 interrupt */
1744 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1745 }
1746 break;
1747
1748 case TIM_CHANNEL_2:
1749 {
1750 /* Disable the TIM Capture/Compare 2 interrupt */
1751 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1752 }
1753 break;
1754
1755 case TIM_CHANNEL_3:
1756 {
1757 /* Disable the TIM Capture/Compare 3 interrupt */
1758 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1759 }
1760 break;
1761
1762 case TIM_CHANNEL_4:
1763 {
1764 /* Disable the TIM Capture/Compare 4 interrupt */
1765 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1766 }
1767 break;
1768
1769 default:
1770 break;
1771 }
1772
1773 /* Disable the Input Capture channel */
1774 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1775
1776 /* Disable the Peripheral */
1777 __HAL_TIM_DISABLE(htim);
1778
1779 /* Return function status */
1780 return HAL_OK;
1781 }
1782
1783 /**
1784 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1785 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1786 * the configuration information for TIM module.
1787 * @param Channel: TIM Channels to be enabled.
1788 * This parameter can be one of the following values:
1789 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1790 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1791 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1792 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1793 * @param pData: The destination Buffer address.
1794 * @param Length: The length of data to be transferred from TIM peripheral to memory.
1795 * @retval HAL status
1796 */
1797 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1798 {
1799 /* Check the parameters */
1800 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1801 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1802
1803 if((htim->State == HAL_TIM_STATE_BUSY))
1804 {
1805 return HAL_BUSY;
1806 }
1807 else if((htim->State == HAL_TIM_STATE_READY))
1808 {
1809 if((pData == 0U) && (Length > 0))
1810 {
1811 return HAL_ERROR;
1812 }
1813 else
1814 {
1815 htim->State = HAL_TIM_STATE_BUSY;
1816 }
1817 }
1818
1819 switch (Channel)
1820 {
1821 case TIM_CHANNEL_1:
1822 {
1823 /* Set the DMA Period elapsed callback */
1824 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
1825
1826 /* Set the DMA error callback */
1827 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1828
1829 /* Enable the DMA Stream */
1830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1831
1832 /* Enable the TIM Capture/Compare 1 DMA request */
1833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1834 }
1835 break;
1836
1837 case TIM_CHANNEL_2:
1838 {
1839 /* Set the DMA Period elapsed callback */
1840 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
1841
1842 /* Set the DMA error callback */
1843 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1844
1845 /* Enable the DMA Stream */
1846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1847
1848 /* Enable the TIM Capture/Compare 2 DMA request */
1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1850 }
1851 break;
1852
1853 case TIM_CHANNEL_3:
1854 {
1855 /* Set the DMA Period elapsed callback */
1856 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
1857
1858 /* Set the DMA error callback */
1859 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1860
1861 /* Enable the DMA Stream */
1862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1863
1864 /* Enable the TIM Capture/Compare 3 DMA request */
1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1866 }
1867 break;
1868
1869 case TIM_CHANNEL_4:
1870 {
1871 /* Set the DMA Period elapsed callback */
1872 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
1873
1874 /* Set the DMA error callback */
1875 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1876
1877 /* Enable the DMA Stream */
1878 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1879
1880 /* Enable the TIM Capture/Compare 4 DMA request */
1881 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1882 }
1883 break;
1884
1885 default:
1886 break;
1887 }
1888
1889 /* Enable the Input Capture channel */
1890 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1891
1892 /* Enable the Peripheral */
1893 __HAL_TIM_ENABLE(htim);
1894
1895 /* Return function status */
1896 return HAL_OK;
1897 }
1898
1899 /**
1900 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1901 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1902 * the configuration information for TIM module.
1903 * @param Channel: TIM Channels to be disabled.
1904 * This parameter can be one of the following values:
1905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1909 * @retval HAL status
1910 */
1911 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1912 {
1913 /* Check the parameters */
1914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1915 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1916
1917 switch (Channel)
1918 {
1919 case TIM_CHANNEL_1:
1920 {
1921 /* Disable the TIM Capture/Compare 1 DMA request */
1922 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1923 }
1924 break;
1925
1926 case TIM_CHANNEL_2:
1927 {
1928 /* Disable the TIM Capture/Compare 2 DMA request */
1929 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1930 }
1931 break;
1932
1933 case TIM_CHANNEL_3:
1934 {
1935 /* Disable the TIM Capture/Compare 3 DMA request */
1936 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1937 }
1938 break;
1939
1940 case TIM_CHANNEL_4:
1941 {
1942 /* Disable the TIM Capture/Compare 4 DMA request */
1943 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1944 }
1945 break;
1946
1947 default:
1948 break;
1949 }
1950
1951 /* Disable the Input Capture channel */
1952 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1953
1954 /* Disable the Peripheral */
1955 __HAL_TIM_DISABLE(htim);
1956
1957 /* Change the htim state */
1958 htim->State = HAL_TIM_STATE_READY;
1959
1960 /* Return function status */
1961 return HAL_OK;
1962 }
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1968 * @brief Time One Pulse functions
1969 *
1970 @verbatim
1971 ==============================================================================
1972 ##### Time One Pulse functions #####
1973 ==============================================================================
1974 [..]
1975 This section provides functions allowing to:
1976 (+) Initialize and configure the TIM One Pulse.
1977 (+) De-initialize the TIM One Pulse.
1978 (+) Start the Time One Pulse.
1979 (+) Stop the Time One Pulse.
1980 (+) Start the Time One Pulse and enable interrupt.
1981 (+) Stop the Time One Pulse and disable interrupt.
1982 (+) Start the Time One Pulse and enable DMA transfer.
1983 (+) Stop the Time One Pulse and disable DMA transfer.
1984
1985 @endverbatim
1986 * @{
1987 */
1988 /**
1989 * @brief Initializes the TIM One Pulse Time Base according to the specified
1990 * parameters in the TIM_HandleTypeDef and create the associated handle.
1991 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
1992 * the configuration information for TIM module.
1993 * @param OnePulseMode: Select the One pulse mode.
1994 * This parameter can be one of the following values:
1995 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1996 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
1997 * @retval HAL status
1998 */
1999 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2000 {
2001 /* Check the TIM handle allocation */
2002 if(htim == NULL)
2003 {
2004 return HAL_ERROR;
2005 }
2006
2007 /* Check the parameters */
2008 assert_param(IS_TIM_INSTANCE(htim->Instance));
2009 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2010 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2011 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2012
2013 if(htim->State == HAL_TIM_STATE_RESET)
2014 {
2015 /* Allocate lock resource and initialize it */
2016 htim->Lock = HAL_UNLOCKED;
2017 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2018 HAL_TIM_OnePulse_MspInit(htim);
2019 }
2020
2021 /* Set the TIM state */
2022 htim->State= HAL_TIM_STATE_BUSY;
2023
2024 /* Configure the Time base in the One Pulse Mode */
2025 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2026
2027 /* Reset the OPM Bit */
2028 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2029
2030 /* Configure the OPM Mode */
2031 htim->Instance->CR1 |= OnePulseMode;
2032
2033 /* Initialize the TIM state*/
2034 htim->State= HAL_TIM_STATE_READY;
2035
2036 return HAL_OK;
2037 }
2038
2039 /**
2040 * @brief DeInitializes the TIM One Pulse
2041 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2042 * the configuration information for TIM module.
2043 * @retval HAL status
2044 */
2045 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2046 {
2047 /* Check the parameters */
2048 assert_param(IS_TIM_INSTANCE(htim->Instance));
2049
2050 htim->State = HAL_TIM_STATE_BUSY;
2051
2052 /* Disable the TIM Peripheral Clock */
2053 __HAL_TIM_DISABLE(htim);
2054
2055 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2056 HAL_TIM_OnePulse_MspDeInit(htim);
2057
2058 /* Change TIM state */
2059 htim->State = HAL_TIM_STATE_RESET;
2060
2061 /* Release Lock */
2062 __HAL_UNLOCK(htim);
2063
2064 return HAL_OK;
2065 }
2066
2067 /**
2068 * @brief Initializes the TIM One Pulse MSP.
2069 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2070 * the configuration information for TIM module.
2071 * @retval None
2072 */
2073 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2074 {
2075 /* Prevent unused argument(s) compilation warning */
2076 UNUSED(htim);
2077 /* NOTE : This function Should not be modified, when the callback is needed,
2078 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2079 */
2080 }
2081
2082 /**
2083 * @brief DeInitializes TIM One Pulse MSP.
2084 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2085 * the configuration information for TIM module.
2086 * @retval None
2087 */
2088 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2089 {
2090 /* Prevent unused argument(s) compilation warning */
2091 UNUSED(htim);
2092 /* NOTE : This function Should not be modified, when the callback is needed,
2093 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2094 */
2095 }
2096
2097 /**
2098 * @brief Starts the TIM One Pulse signal generation.
2099 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2100 * the configuration information for TIM module.
2101 * @param OutputChannel : TIM Channels to be enabled.
2102 * This parameter can be one of the following values:
2103 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2104 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2105 * @retval HAL status
2106 */
2107 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2108 {
2109 /* Prevent unused argument(s) compilation warning */
2110 UNUSED(OutputChannel);
2111
2112 /* Enable the Capture compare and the Input Capture channels
2113 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2114 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2115 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2116 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2117
2118 No need to enable the counter, it's enabled automatically by hardware
2119 (the counter starts in response to a stimulus and generate a pulse */
2120
2121 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2122 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2123
2124 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2125 {
2126 /* Enable the main output */
2127 __HAL_TIM_MOE_ENABLE(htim);
2128 }
2129
2130 /* Return function status */
2131 return HAL_OK;
2132 }
2133
2134 /**
2135 * @brief Stops the TIM One Pulse signal generation.
2136 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2137 * the configuration information for TIM module.
2138 * @param OutputChannel : TIM Channels to be disable.
2139 * This parameter can be one of the following values:
2140 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2141 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2142 * @retval HAL status
2143 */
2144 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2145 {
2146 /* Prevent unused argument(s) compilation warning */
2147 UNUSED(OutputChannel);
2148
2149 /* Disable the Capture compare and the Input Capture channels
2150 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2151 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2152 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2153 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2154
2155 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2156 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2157
2158 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2159 {
2160 /* Disable the Main Output */
2161 __HAL_TIM_MOE_DISABLE(htim);
2162 }
2163
2164 /* Disable the Peripheral */
2165 __HAL_TIM_DISABLE(htim);
2166
2167 /* Return function status */
2168 return HAL_OK;
2169 }
2170
2171 /**
2172 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2173 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2174 * the configuration information for TIM module.
2175 * @param OutputChannel : TIM Channels to be enabled.
2176 * This parameter can be one of the following values:
2177 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2178 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2179 * @retval HAL status
2180 */
2181 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2182 {
2183 /* Enable the Capture compare and the Input Capture channels
2184 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2185 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2186 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2187 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2188
2189 No need to enable the counter, it's enabled automatically by hardware
2190 (the counter starts in response to a stimulus and generate a pulse */
2191
2192 /* Prevent unused argument(s) compilation warning */
2193 UNUSED(OutputChannel);
2194
2195 /* Enable the TIM Capture/Compare 1 interrupt */
2196 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2197
2198 /* Enable the TIM Capture/Compare 2 interrupt */
2199 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2200
2201 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2202 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2203
2204 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2205 {
2206 /* Enable the main output */
2207 __HAL_TIM_MOE_ENABLE(htim);
2208 }
2209
2210 /* Return function status */
2211 return HAL_OK;
2212 }
2213
2214 /**
2215 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2216 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2217 * the configuration information for TIM module.
2218 * @param OutputChannel : TIM Channels to be enabled.
2219 * This parameter can be one of the following values:
2220 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2221 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2222 * @retval HAL status
2223 */
2224 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2225 {
2226 /* Prevent unused argument(s) compilation warning */
2227 UNUSED(OutputChannel);
2228
2229 /* Disable the TIM Capture/Compare 1 interrupt */
2230 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2231
2232 /* Disable the TIM Capture/Compare 2 interrupt */
2233 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2234
2235 /* Disable the Capture compare and the Input Capture channels
2236 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2237 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2238 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2239 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2240 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2241 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2242
2243 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
2244 {
2245 /* Disable the Main Output */
2246 __HAL_TIM_MOE_DISABLE(htim);
2247 }
2248
2249 /* Disable the Peripheral */
2250 __HAL_TIM_DISABLE(htim);
2251
2252 /* Return function status */
2253 return HAL_OK;
2254 }
2255 /**
2256 * @}
2257 */
2258
2259 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2260 * @brief Time Encoder functions
2261 *
2262 @verbatim
2263 ==============================================================================
2264 ##### Time Encoder functions #####
2265 ==============================================================================
2266 [..]
2267 This section provides functions allowing to:
2268 (+) Initialize and configure the TIM Encoder.
2269 (+) De-initialize the TIM Encoder.
2270 (+) Start the Time Encoder.
2271 (+) Stop the Time Encoder.
2272 (+) Start the Time Encoder and enable interrupt.
2273 (+) Stop the Time Encoder and disable interrupt.
2274 (+) Start the Time Encoder and enable DMA transfer.
2275 (+) Stop the Time Encoder and disable DMA transfer.
2276
2277 @endverbatim
2278 * @{
2279 */
2280 /**
2281 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2282 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2283 * the configuration information for TIM module.
2284 * @param sConfig: TIM Encoder Interface configuration structure
2285 * @retval HAL status
2286 */
2287 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2288 {
2289 uint32_t tmpsmcr = 0U;
2290 uint32_t tmpccmr1 = 0U;
2291 uint32_t tmpccer = 0U;
2292
2293 /* Check the TIM handle allocation */
2294 if(htim == NULL)
2295 {
2296 return HAL_ERROR;
2297 }
2298
2299 /* Check the parameters */
2300 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2301 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2302 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2303 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2304 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2305 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2306 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2307 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2308 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2309 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2310
2311 if(htim->State == HAL_TIM_STATE_RESET)
2312 {
2313 /* Allocate lock resource and initialize it */
2314 htim->Lock = HAL_UNLOCKED;
2315 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2316 HAL_TIM_Encoder_MspInit(htim);
2317 }
2318
2319 /* Set the TIM state */
2320 htim->State= HAL_TIM_STATE_BUSY;
2321
2322 /* Reset the SMS bits */
2323 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2324
2325 /* Configure the Time base in the Encoder Mode */
2326 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2327
2328 /* Get the TIMx SMCR register value */
2329 tmpsmcr = htim->Instance->SMCR;
2330
2331 /* Get the TIMx CCMR1 register value */
2332 tmpccmr1 = htim->Instance->CCMR1;
2333
2334 /* Get the TIMx CCER register value */
2335 tmpccer = htim->Instance->CCER;
2336
2337 /* Set the encoder Mode */
2338 tmpsmcr |= sConfig->EncoderMode;
2339
2340 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2341 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2342 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2343
2344 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2345 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2346 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2347 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2348 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2349
2350 /* Set the TI1 and the TI2 Polarities */
2351 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2352 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2353 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2354
2355 /* Write to TIMx SMCR */
2356 htim->Instance->SMCR = tmpsmcr;
2357
2358 /* Write to TIMx CCMR1 */
2359 htim->Instance->CCMR1 = tmpccmr1;
2360
2361 /* Write to TIMx CCER */
2362 htim->Instance->CCER = tmpccer;
2363
2364 /* Initialize the TIM state*/
2365 htim->State= HAL_TIM_STATE_READY;
2366
2367 return HAL_OK;
2368 }
2369
2370 /**
2371 * @brief DeInitializes the TIM Encoder interface
2372 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2373 * the configuration information for TIM module.
2374 * @retval HAL status
2375 */
2376 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2377 {
2378 /* Check the parameters */
2379 assert_param(IS_TIM_INSTANCE(htim->Instance));
2380
2381 htim->State = HAL_TIM_STATE_BUSY;
2382
2383 /* Disable the TIM Peripheral Clock */
2384 __HAL_TIM_DISABLE(htim);
2385
2386 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2387 HAL_TIM_Encoder_MspDeInit(htim);
2388
2389 /* Change TIM state */
2390 htim->State = HAL_TIM_STATE_RESET;
2391
2392 /* Release Lock */
2393 __HAL_UNLOCK(htim);
2394
2395 return HAL_OK;
2396 }
2397
2398 /**
2399 * @brief Initializes the TIM Encoder Interface MSP.
2400 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2401 * the configuration information for TIM module.
2402 * @retval None
2403 */
2404 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2405 {
2406 /* Prevent unused argument(s) compilation warning */
2407 UNUSED(htim);
2408 /* NOTE : This function Should not be modified, when the callback is needed,
2409 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2410 */
2411 }
2412
2413 /**
2414 * @brief DeInitializes TIM Encoder Interface MSP.
2415 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2416 * the configuration information for TIM module.
2417 * @retval None
2418 */
2419 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2420 {
2421 /* Prevent unused argument(s) compilation warning */
2422 UNUSED(htim);
2423 /* NOTE : This function Should not be modified, when the callback is needed,
2424 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2425 */
2426 }
2427
2428 /**
2429 * @brief Starts the TIM Encoder Interface.
2430 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2431 * the configuration information for TIM module.
2432 * @param Channel: TIM Channels to be enabled.
2433 * This parameter can be one of the following values:
2434 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2435 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2436 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2437 * @retval HAL status
2438 */
2439 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2440 {
2441 /* Check the parameters */
2442 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2443
2444 /* Enable the encoder interface channels */
2445 switch (Channel)
2446 {
2447 case TIM_CHANNEL_1:
2448 {
2449 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2450 break;
2451 }
2452 case TIM_CHANNEL_2:
2453 {
2454 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2455 break;
2456 }
2457 default :
2458 {
2459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2460 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2461 break;
2462 }
2463 }
2464 /* Enable the Peripheral */
2465 __HAL_TIM_ENABLE(htim);
2466
2467 /* Return function status */
2468 return HAL_OK;
2469 }
2470
2471 /**
2472 * @brief Stops the TIM Encoder Interface.
2473 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2474 * the configuration information for TIM module.
2475 * @param Channel: TIM Channels to be disabled.
2476 * This parameter can be one of the following values:
2477 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2478 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2479 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2480 * @retval HAL status
2481 */
2482 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2483 {
2484 /* Check the parameters */
2485 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2486
2487 /* Disable the Input Capture channels 1 and 2
2488 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2489 switch (Channel)
2490 {
2491 case TIM_CHANNEL_1:
2492 {
2493 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2494 break;
2495 }
2496 case TIM_CHANNEL_2:
2497 {
2498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2499 break;
2500 }
2501 default :
2502 {
2503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2504 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2505 break;
2506 }
2507 }
2508 /* Disable the Peripheral */
2509 __HAL_TIM_DISABLE(htim);
2510
2511 /* Return function status */
2512 return HAL_OK;
2513 }
2514
2515 /**
2516 * @brief Starts the TIM Encoder Interface in interrupt mode.
2517 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2518 * the configuration information for TIM module.
2519 * @param Channel: TIM Channels to be enabled.
2520 * This parameter can be one of the following values:
2521 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2522 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2523 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2524 * @retval HAL status
2525 */
2526 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2527 {
2528 /* Check the parameters */
2529 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2530
2531 /* Enable the encoder interface channels */
2532 /* Enable the capture compare Interrupts 1 and/or 2 */
2533 switch (Channel)
2534 {
2535 case TIM_CHANNEL_1:
2536 {
2537 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2538 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2539 break;
2540 }
2541 case TIM_CHANNEL_2:
2542 {
2543 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2544 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2545 break;
2546 }
2547 default :
2548 {
2549 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2550 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2551 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2552 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2553 break;
2554 }
2555 }
2556
2557 /* Enable the Peripheral */
2558 __HAL_TIM_ENABLE(htim);
2559
2560 /* Return function status */
2561 return HAL_OK;
2562 }
2563
2564 /**
2565 * @brief Stops the TIM Encoder Interface in interrupt mode.
2566 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2567 * the configuration information for TIM module.
2568 * @param Channel: TIM Channels to be disabled.
2569 * This parameter can be one of the following values:
2570 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2571 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2572 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2573 * @retval HAL status
2574 */
2575 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2576 {
2577 /* Check the parameters */
2578 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2579
2580 /* Disable the Input Capture channels 1 and 2
2581 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2582 if(Channel == TIM_CHANNEL_1)
2583 {
2584 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2585
2586 /* Disable the capture compare Interrupts 1 */
2587 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2588 }
2589 else if(Channel == TIM_CHANNEL_2)
2590 {
2591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2592
2593 /* Disable the capture compare Interrupts 2 */
2594 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2595 }
2596 else
2597 {
2598 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2599 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2600
2601 /* Disable the capture compare Interrupts 1 and 2 */
2602 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2603 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2604 }
2605
2606 /* Disable the Peripheral */
2607 __HAL_TIM_DISABLE(htim);
2608
2609 /* Change the htim state */
2610 htim->State = HAL_TIM_STATE_READY;
2611
2612 /* Return function status */
2613 return HAL_OK;
2614 }
2615
2616 /**
2617 * @brief Starts the TIM Encoder Interface in DMA mode.
2618 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2619 * the configuration information for TIM module.
2620 * @param Channel: TIM Channels to be enabled.
2621 * This parameter can be one of the following values:
2622 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2623 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2624 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2625 * @param pData1: The destination Buffer address for IC1.
2626 * @param pData2: The destination Buffer address for IC2.
2627 * @param Length: The length of data to be transferred from TIM peripheral to memory.
2628 * @retval HAL status
2629 */
2630 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2631 {
2632 /* Check the parameters */
2633 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2634
2635 if((htim->State == HAL_TIM_STATE_BUSY))
2636 {
2637 return HAL_BUSY;
2638 }
2639 else if((htim->State == HAL_TIM_STATE_READY))
2640 {
2641 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
2642 {
2643 return HAL_ERROR;
2644 }
2645 else
2646 {
2647 htim->State = HAL_TIM_STATE_BUSY;
2648 }
2649 }
2650
2651 switch (Channel)
2652 {
2653 case TIM_CHANNEL_1:
2654 {
2655 /* Set the DMA Period elapsed callback */
2656 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2657
2658 /* Set the DMA error callback */
2659 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2660
2661 /* Enable the DMA Stream */
2662 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2663
2664 /* Enable the TIM Input Capture DMA request */
2665 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2666
2667 /* Enable the Peripheral */
2668 __HAL_TIM_ENABLE(htim);
2669
2670 /* Enable the Capture compare channel */
2671 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2672 }
2673 break;
2674
2675 case TIM_CHANNEL_2:
2676 {
2677 /* Set the DMA Period elapsed callback */
2678 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2679
2680 /* Set the DMA error callback */
2681 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2682 /* Enable the DMA Stream */
2683 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2684
2685 /* Enable the TIM Input Capture DMA request */
2686 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2687
2688 /* Enable the Peripheral */
2689 __HAL_TIM_ENABLE(htim);
2690
2691 /* Enable the Capture compare channel */
2692 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2693 }
2694 break;
2695
2696 case TIM_CHANNEL_ALL:
2697 {
2698 /* Set the DMA Period elapsed callback */
2699 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2700
2701 /* Set the DMA error callback */
2702 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2703
2704 /* Enable the DMA Stream */
2705 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2706
2707 /* Set the DMA Period elapsed callback */
2708 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2709
2710 /* Set the DMA error callback */
2711 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2712
2713 /* Enable the DMA Stream */
2714 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2715
2716 /* Enable the Peripheral */
2717 __HAL_TIM_ENABLE(htim);
2718
2719 /* Enable the Capture compare channel */
2720 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2722
2723 /* Enable the TIM Input Capture DMA request */
2724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2725 /* Enable the TIM Input Capture DMA request */
2726 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2727 }
2728 break;
2729
2730 default:
2731 break;
2732 }
2733 /* Return function status */
2734 return HAL_OK;
2735 }
2736
2737 /**
2738 * @brief Stops the TIM Encoder Interface in DMA mode.
2739 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2740 * the configuration information for TIM module.
2741 * @param Channel: TIM Channels to be enabled.
2742 * This parameter can be one of the following values:
2743 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2744 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2745 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2746 * @retval HAL status
2747 */
2748 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2749 {
2750 /* Check the parameters */
2751 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2752
2753 /* Disable the Input Capture channels 1 and 2
2754 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2755 if(Channel == TIM_CHANNEL_1)
2756 {
2757 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2758
2759 /* Disable the capture compare DMA Request 1 */
2760 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2761 }
2762 else if(Channel == TIM_CHANNEL_2)
2763 {
2764 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2765
2766 /* Disable the capture compare DMA Request 2 */
2767 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2768 }
2769 else
2770 {
2771 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2772 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2773
2774 /* Disable the capture compare DMA Request 1 and 2 */
2775 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2776 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2777 }
2778
2779 /* Disable the Peripheral */
2780 __HAL_TIM_DISABLE(htim);
2781
2782 /* Change the htim state */
2783 htim->State = HAL_TIM_STATE_READY;
2784
2785 /* Return function status */
2786 return HAL_OK;
2787 }
2788 /**
2789 * @}
2790 */
2791
2792 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2793 * @brief IRQ handler management
2794 *
2795 @verbatim
2796 ==============================================================================
2797 ##### IRQ handler management #####
2798 ==============================================================================
2799 [..]
2800 This section provides Timer IRQ handler function.
2801
2802 @endverbatim
2803 * @{
2804 */
2805 /**
2806 * @brief This function handles TIM interrupts requests.
2807 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2808 * the configuration information for TIM module.
2809 * @retval None
2810 */
2811 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2812 {
2813 /* Capture compare 1 event */
2814 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2815 {
2816 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
2817 {
2818 {
2819 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2820 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2821
2822 /* Input capture event */
2823 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
2824 {
2825 HAL_TIM_IC_CaptureCallback(htim);
2826 }
2827 /* Output compare event */
2828 else
2829 {
2830 HAL_TIM_OC_DelayElapsedCallback(htim);
2831 HAL_TIM_PWM_PulseFinishedCallback(htim);
2832 }
2833 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2834 }
2835 }
2836 }
2837 /* Capture compare 2 event */
2838 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2839 {
2840 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
2841 {
2842 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2844 /* Input capture event */
2845 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
2846 {
2847 HAL_TIM_IC_CaptureCallback(htim);
2848 }
2849 /* Output compare event */
2850 else
2851 {
2852 HAL_TIM_OC_DelayElapsedCallback(htim);
2853 HAL_TIM_PWM_PulseFinishedCallback(htim);
2854 }
2855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2856 }
2857 }
2858 /* Capture compare 3 event */
2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2860 {
2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
2862 {
2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2865 /* Input capture event */
2866 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
2867 {
2868 HAL_TIM_IC_CaptureCallback(htim);
2869 }
2870 /* Output compare event */
2871 else
2872 {
2873 HAL_TIM_OC_DelayElapsedCallback(htim);
2874 HAL_TIM_PWM_PulseFinishedCallback(htim);
2875 }
2876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2877 }
2878 }
2879 /* Capture compare 4 event */
2880 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2881 {
2882 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
2883 {
2884 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2885 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2886 /* Input capture event */
2887 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
2888 {
2889 HAL_TIM_IC_CaptureCallback(htim);
2890 }
2891 /* Output compare event */
2892 else
2893 {
2894 HAL_TIM_OC_DelayElapsedCallback(htim);
2895 HAL_TIM_PWM_PulseFinishedCallback(htim);
2896 }
2897 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2898 }
2899 }
2900 /* TIM Update event */
2901 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2902 {
2903 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
2904 {
2905 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2906 HAL_TIM_PeriodElapsedCallback(htim);
2907 }
2908 }
2909 /* TIM Break input event */
2910 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
2911 {
2912 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
2913 {
2914 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
2915 HAL_TIMEx_BreakCallback(htim);
2916 }
2917 }
2918 /* TIM Trigger detection event */
2919 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2920 {
2921 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
2922 {
2923 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2924 HAL_TIM_TriggerCallback(htim);
2925 }
2926 }
2927 /* TIM commutation event */
2928 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
2929 {
2930 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
2931 {
2932 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
2933 HAL_TIMEx_CommutationCallback(htim);
2934 }
2935 }
2936 }
2937 /**
2938 * @}
2939 */
2940
2941 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2942 * @brief Peripheral Control functions
2943 *
2944 @verbatim
2945 ==============================================================================
2946 ##### Peripheral Control functions #####
2947 ==============================================================================
2948 [..]
2949 This section provides functions allowing to:
2950 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2951 (+) Configure External Clock source.
2952 (+) Configure Complementary channels, break features and dead time.
2953 (+) Configure Master and the Slave synchronization.
2954 (+) Configure the DMA Burst Mode.
2955
2956 @endverbatim
2957 * @{
2958 */
2959
2960 /**
2961 * @brief Initializes the TIM Output Compare Channels according to the specified
2962 * parameters in the TIM_OC_InitTypeDef.
2963 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
2964 * the configuration information for TIM module.
2965 * @param sConfig: TIM Output Compare configuration structure
2966 * @param Channel: TIM Channels to be enabled.
2967 * This parameter can be one of the following values:
2968 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2969 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2970 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2971 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2972 * @retval HAL status
2973 */
2974 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2975 {
2976 /* Check the parameters */
2977 assert_param(IS_TIM_CHANNELS(Channel));
2978 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2979 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2980
2981 /* Check input state */
2982 __HAL_LOCK(htim);
2983
2984 htim->State = HAL_TIM_STATE_BUSY;
2985
2986 switch (Channel)
2987 {
2988 case TIM_CHANNEL_1:
2989 {
2990 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2991 /* Configure the TIM Channel 1 in Output Compare */
2992 TIM_OC1_SetConfig(htim->Instance, sConfig);
2993 }
2994 break;
2995
2996 case TIM_CHANNEL_2:
2997 {
2998 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2999 /* Configure the TIM Channel 2 in Output Compare */
3000 TIM_OC2_SetConfig(htim->Instance, sConfig);
3001 }
3002 break;
3003
3004 case TIM_CHANNEL_3:
3005 {
3006 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3007 /* Configure the TIM Channel 3 in Output Compare */
3008 TIM_OC3_SetConfig(htim->Instance, sConfig);
3009 }
3010 break;
3011
3012 case TIM_CHANNEL_4:
3013 {
3014 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3015 /* Configure the TIM Channel 4 in Output Compare */
3016 TIM_OC4_SetConfig(htim->Instance, sConfig);
3017 }
3018 break;
3019
3020 default:
3021 break;
3022 }
3023 htim->State = HAL_TIM_STATE_READY;
3024
3025 __HAL_UNLOCK(htim);
3026
3027 return HAL_OK;
3028 }
3029
3030 /**
3031 * @brief Initializes the TIM Input Capture Channels according to the specified
3032 * parameters in the TIM_IC_InitTypeDef.
3033 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3034 * the configuration information for TIM module.
3035 * @param sConfig: TIM Input Capture configuration structure
3036 * @param Channel: TIM Channels to be enabled.
3037 * This parameter can be one of the following values:
3038 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3039 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3040 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3041 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3042 * @retval HAL status
3043 */
3044 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
3045 {
3046 /* Check the parameters */
3047 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3048 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3049 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3050 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3051 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3052
3053 __HAL_LOCK(htim);
3054
3055 htim->State = HAL_TIM_STATE_BUSY;
3056
3057 if (Channel == TIM_CHANNEL_1)
3058 {
3059 /* TI1 Configuration */
3060 TIM_TI1_SetConfig(htim->Instance,
3061 sConfig->ICPolarity,
3062 sConfig->ICSelection,
3063 sConfig->ICFilter);
3064
3065 /* Reset the IC1PSC Bits */
3066 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3067
3068 /* Set the IC1PSC value */
3069 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3070 }
3071 else if (Channel == TIM_CHANNEL_2)
3072 {
3073 /* TI2 Configuration */
3074 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3075
3076 TIM_TI2_SetConfig(htim->Instance,
3077 sConfig->ICPolarity,
3078 sConfig->ICSelection,
3079 sConfig->ICFilter);
3080
3081 /* Reset the IC2PSC Bits */
3082 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3083
3084 /* Set the IC2PSC value */
3085 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3086 }
3087 else if (Channel == TIM_CHANNEL_3)
3088 {
3089 /* TI3 Configuration */
3090 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3091
3092 TIM_TI3_SetConfig(htim->Instance,
3093 sConfig->ICPolarity,
3094 sConfig->ICSelection,
3095 sConfig->ICFilter);
3096
3097 /* Reset the IC3PSC Bits */
3098 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3099
3100 /* Set the IC3PSC value */
3101 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3102 }
3103 else
3104 {
3105 /* TI4 Configuration */
3106 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3107
3108 TIM_TI4_SetConfig(htim->Instance,
3109 sConfig->ICPolarity,
3110 sConfig->ICSelection,
3111 sConfig->ICFilter);
3112
3113 /* Reset the IC4PSC Bits */
3114 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3115
3116 /* Set the IC4PSC value */
3117 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3118 }
3119
3120 htim->State = HAL_TIM_STATE_READY;
3121
3122 __HAL_UNLOCK(htim);
3123
3124 return HAL_OK;
3125 }
3126
3127 /**
3128 * @brief Initializes the TIM PWM channels according to the specified
3129 * parameters in the TIM_OC_InitTypeDef.
3130 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3131 * the configuration information for TIM module.
3132 * @param sConfig: TIM PWM configuration structure
3133 * @param Channel: TIM Channels to be enabled.
3134 * This parameter can be one of the following values:
3135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3139 * @retval HAL status
3140 */
3141 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
3142 {
3143 __HAL_LOCK(htim);
3144
3145 /* Check the parameters */
3146 assert_param(IS_TIM_CHANNELS(Channel));
3147 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3148 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3149 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3150
3151 htim->State = HAL_TIM_STATE_BUSY;
3152
3153 switch (Channel)
3154 {
3155 case TIM_CHANNEL_1:
3156 {
3157 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3158 /* Configure the Channel 1 in PWM mode */
3159 TIM_OC1_SetConfig(htim->Instance, sConfig);
3160
3161 /* Set the Preload enable bit for channel1 */
3162 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3163
3164 /* Configure the Output Fast mode */
3165 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3166 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3167 }
3168 break;
3169
3170 case TIM_CHANNEL_2:
3171 {
3172 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3173 /* Configure the Channel 2 in PWM mode */
3174 TIM_OC2_SetConfig(htim->Instance, sConfig);
3175
3176 /* Set the Preload enable bit for channel2 */
3177 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3178
3179 /* Configure the Output Fast mode */
3180 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3181 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3182 }
3183 break;
3184
3185 case TIM_CHANNEL_3:
3186 {
3187 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3188 /* Configure the Channel 3 in PWM mode */
3189 TIM_OC3_SetConfig(htim->Instance, sConfig);
3190
3191 /* Set the Preload enable bit for channel3 */
3192 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3193
3194 /* Configure the Output Fast mode */
3195 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3196 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3197 }
3198 break;
3199
3200 case TIM_CHANNEL_4:
3201 {
3202 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3203 /* Configure the Channel 4 in PWM mode */
3204 TIM_OC4_SetConfig(htim->Instance, sConfig);
3205
3206 /* Set the Preload enable bit for channel4 */
3207 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3208
3209 /* Configure the Output Fast mode */
3210 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3211 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3212 }
3213 break;
3214
3215 default:
3216 break;
3217 }
3218
3219 htim->State = HAL_TIM_STATE_READY;
3220
3221 __HAL_UNLOCK(htim);
3222
3223 return HAL_OK;
3224 }
3225
3226 /**
3227 * @brief Initializes the TIM One Pulse Channels according to the specified
3228 * parameters in the TIM_OnePulse_InitTypeDef.
3229 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3230 * the configuration information for TIM module.
3231 * @param sConfig: TIM One Pulse configuration structure
3232 * @param OutputChannel: TIM Channels to be enabled.
3233 * This parameter can be one of the following values:
3234 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3235 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3236 * @param InputChannel: TIM Channels to be enabled.
3237 * This parameter can be one of the following values:
3238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3240 * @retval HAL status
3241 */
3242 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3243 {
3244 TIM_OC_InitTypeDef temp1;
3245
3246 /* Check the parameters */
3247 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3248 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3249
3250 if(OutputChannel != InputChannel)
3251 {
3252 __HAL_LOCK(htim);
3253
3254 htim->State = HAL_TIM_STATE_BUSY;
3255
3256 /* Extract the Output compare configuration from sConfig structure */
3257 temp1.OCMode = sConfig->OCMode;
3258 temp1.Pulse = sConfig->Pulse;
3259 temp1.OCPolarity = sConfig->OCPolarity;
3260 temp1.OCNPolarity = sConfig->OCNPolarity;
3261 temp1.OCIdleState = sConfig->OCIdleState;
3262 temp1.OCNIdleState = sConfig->OCNIdleState;
3263
3264 switch (OutputChannel)
3265 {
3266 case TIM_CHANNEL_1:
3267 {
3268 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3269
3270 TIM_OC1_SetConfig(htim->Instance, &temp1);
3271 }
3272 break;
3273 case TIM_CHANNEL_2:
3274 {
3275 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3276
3277 TIM_OC2_SetConfig(htim->Instance, &temp1);
3278 }
3279 break;
3280 default:
3281 break;
3282 }
3283 switch (InputChannel)
3284 {
3285 case TIM_CHANNEL_1:
3286 {
3287 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3288
3289 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3290 sConfig->ICSelection, sConfig->ICFilter);
3291
3292 /* Reset the IC1PSC Bits */
3293 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3294
3295 /* Select the Trigger source */
3296 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3297 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3298
3299 /* Select the Slave Mode */
3300 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3301 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3302 }
3303 break;
3304 case TIM_CHANNEL_2:
3305 {
3306 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3307
3308 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3309 sConfig->ICSelection, sConfig->ICFilter);
3310
3311 /* Reset the IC2PSC Bits */
3312 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3313
3314 /* Select the Trigger source */
3315 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3316 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3317
3318 /* Select the Slave Mode */
3319 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3320 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3321 }
3322 break;
3323
3324 default:
3325 break;
3326 }
3327
3328 htim->State = HAL_TIM_STATE_READY;
3329
3330 __HAL_UNLOCK(htim);
3331
3332 return HAL_OK;
3333 }
3334 else
3335 {
3336 return HAL_ERROR;
3337 }
3338 }
3339
3340 /**
3341 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3342 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3343 * the configuration information for TIM module.
3344 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
3345 * This parameters can be on of the following values:
3346 * @arg TIM_DMABASE_CR1
3347 * @arg TIM_DMABASE_CR2
3348 * @arg TIM_DMABASE_SMCR
3349 * @arg TIM_DMABASE_DIER
3350 * @arg TIM_DMABASE_SR
3351 * @arg TIM_DMABASE_EGR
3352 * @arg TIM_DMABASE_CCMR1
3353 * @arg TIM_DMABASE_CCMR2
3354 * @arg TIM_DMABASE_CCER
3355 * @arg TIM_DMABASE_CNT
3356 * @arg TIM_DMABASE_PSC
3357 * @arg TIM_DMABASE_ARR
3358 * @arg TIM_DMABASE_RCR
3359 * @arg TIM_DMABASE_CCR1
3360 * @arg TIM_DMABASE_CCR2
3361 * @arg TIM_DMABASE_CCR3
3362 * @arg TIM_DMABASE_CCR4
3363 * @arg TIM_DMABASE_BDTR
3364 * @arg TIM_DMABASE_DCR
3365 * @param BurstRequestSrc: TIM DMA Request sources.
3366 * This parameters can be on of the following values:
3367 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3368 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3369 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3370 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3371 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3372 * @arg TIM_DMA_COM: TIM Commutation DMA source
3373 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3374 * @param BurstBuffer: The Buffer address.
3375 * @param BurstLength: DMA Burst length. This parameter can be one value
3376 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3377 * @retval HAL status
3378 */
3379 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3380 uint32_t* BurstBuffer, uint32_t BurstLength)
3381 {
3382 /* Check the parameters */
3383 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3384 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3385 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3386 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3387
3388 if((htim->State == HAL_TIM_STATE_BUSY))
3389 {
3390 return HAL_BUSY;
3391 }
3392 else if((htim->State == HAL_TIM_STATE_READY))
3393 {
3394 if((BurstBuffer == 0U) && (BurstLength > 0U))
3395 {
3396 return HAL_ERROR;
3397 }
3398 else
3399 {
3400 htim->State = HAL_TIM_STATE_BUSY;
3401 }
3402 }
3403 switch(BurstRequestSrc)
3404 {
3405 case TIM_DMA_UPDATE:
3406 {
3407 /* Set the DMA Period elapsed callback */
3408 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3409
3410 /* Set the DMA error callback */
3411 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3412
3413 /* Enable the DMA Stream */
3414 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3415 }
3416 break;
3417 case TIM_DMA_CC1:
3418 {
3419 /* Set the DMA Period elapsed callback */
3420 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3421
3422 /* Set the DMA error callback */
3423 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3424
3425 /* Enable the DMA Stream */
3426 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3427 }
3428 break;
3429 case TIM_DMA_CC2:
3430 {
3431 /* Set the DMA Period elapsed callback */
3432 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3433
3434 /* Set the DMA error callback */
3435 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3436
3437 /* Enable the DMA Stream */
3438 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3439 }
3440 break;
3441 case TIM_DMA_CC3:
3442 {
3443 /* Set the DMA Period elapsed callback */
3444 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3445
3446 /* Set the DMA error callback */
3447 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3448
3449 /* Enable the DMA Stream */
3450 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3451 }
3452 break;
3453 case TIM_DMA_CC4:
3454 {
3455 /* Set the DMA Period elapsed callback */
3456 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3457
3458 /* Set the DMA error callback */
3459 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3460
3461 /* Enable the DMA Stream */
3462 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3463 }
3464 break;
3465 case TIM_DMA_COM:
3466 {
3467 /* Set the DMA Period elapsed callback */
3468 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3469
3470 /* Set the DMA error callback */
3471 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3472
3473 /* Enable the DMA Stream */
3474 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3475 }
3476 break;
3477 case TIM_DMA_TRIGGER:
3478 {
3479 /* Set the DMA Period elapsed callback */
3480 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3481
3482 /* Set the DMA error callback */
3483 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3484
3485 /* Enable the DMA Stream */
3486 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3487 }
3488 break;
3489 default:
3490 break;
3491 }
3492 /* configure the DMA Burst Mode */
3493 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3494
3495 /* Enable the TIM DMA Request */
3496 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3497
3498 htim->State = HAL_TIM_STATE_READY;
3499
3500 /* Return function status */
3501 return HAL_OK;
3502 }
3503
3504 /**
3505 * @brief Stops the TIM DMA Burst mode
3506 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3507 * the configuration information for TIM module.
3508 * @param BurstRequestSrc: TIM DMA Request sources to disable
3509 * @retval HAL status
3510 */
3511 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3512 {
3513 /* Check the parameters */
3514 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3515
3516 /* Abort the DMA transfer (at least disable the DMA channel) */
3517 switch(BurstRequestSrc)
3518 {
3519 case TIM_DMA_UPDATE:
3520 {
3521 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3522 }
3523 break;
3524 case TIM_DMA_CC1:
3525 {
3526 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3527 }
3528 break;
3529 case TIM_DMA_CC2:
3530 {
3531 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3532 }
3533 break;
3534 case TIM_DMA_CC3:
3535 {
3536 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3537 }
3538 break;
3539 case TIM_DMA_CC4:
3540 {
3541 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3542 }
3543 break;
3544 case TIM_DMA_COM:
3545 {
3546 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3547 }
3548 break;
3549 case TIM_DMA_TRIGGER:
3550 {
3551 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3552 }
3553 break;
3554 default:
3555 break;
3556 }
3557
3558 /* Disable the TIM Update DMA request */
3559 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3560
3561 /* Return function status */
3562 return HAL_OK;
3563 }
3564
3565 /**
3566 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3567 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3568 * the configuration information for TIM module.
3569 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
3570 * This parameters can be on of the following values:
3571 * @arg TIM_DMABASE_CR1
3572 * @arg TIM_DMABASE_CR2
3573 * @arg TIM_DMABASE_SMCR
3574 * @arg TIM_DMABASE_DIER
3575 * @arg TIM_DMABASE_SR
3576 * @arg TIM_DMABASE_EGR
3577 * @arg TIM_DMABASE_CCMR1
3578 * @arg TIM_DMABASE_CCMR2
3579 * @arg TIM_DMABASE_CCER
3580 * @arg TIM_DMABASE_CNT
3581 * @arg TIM_DMABASE_PSC
3582 * @arg TIM_DMABASE_ARR
3583 * @arg TIM_DMABASE_RCR
3584 * @arg TIM_DMABASE_CCR1
3585 * @arg TIM_DMABASE_CCR2
3586 * @arg TIM_DMABASE_CCR3
3587 * @arg TIM_DMABASE_CCR4
3588 * @arg TIM_DMABASE_BDTR
3589 * @arg TIM_DMABASE_DCR
3590 * @param BurstRequestSrc: TIM DMA Request sources.
3591 * This parameters can be on of the following values:
3592 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3593 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3594 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3595 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3596 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3597 * @arg TIM_DMA_COM: TIM Commutation DMA source
3598 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3599 * @param BurstBuffer: The Buffer address.
3600 * @param BurstLength: DMA Burst length. This parameter can be one value
3601 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3602 * @retval HAL status
3603 */
3604 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3605 uint32_t *BurstBuffer, uint32_t BurstLength)
3606 {
3607 /* Check the parameters */
3608 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3609 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3610 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3611 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3612
3613 if((htim->State == HAL_TIM_STATE_BUSY))
3614 {
3615 return HAL_BUSY;
3616 }
3617 else if((htim->State == HAL_TIM_STATE_READY))
3618 {
3619 if((BurstBuffer == 0U) && (BurstLength > 0U))
3620 {
3621 return HAL_ERROR;
3622 }
3623 else
3624 {
3625 htim->State = HAL_TIM_STATE_BUSY;
3626 }
3627 }
3628 switch(BurstRequestSrc)
3629 {
3630 case TIM_DMA_UPDATE:
3631 {
3632 /* Set the DMA Period elapsed callback */
3633 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3634
3635 /* Set the DMA error callback */
3636 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3637
3638 /* Enable the DMA Stream */
3639 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3640 }
3641 break;
3642 case TIM_DMA_CC1:
3643 {
3644 /* Set the DMA Period elapsed callback */
3645 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3646
3647 /* Set the DMA error callback */
3648 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3649
3650 /* Enable the DMA Stream */
3651 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3652 }
3653 break;
3654 case TIM_DMA_CC2:
3655 {
3656 /* Set the DMA Period elapsed callback */
3657 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3658
3659 /* Set the DMA error callback */
3660 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3661
3662 /* Enable the DMA Stream */
3663 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3664 }
3665 break;
3666 case TIM_DMA_CC3:
3667 {
3668 /* Set the DMA Period elapsed callback */
3669 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
3670
3671 /* Set the DMA error callback */
3672 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3673
3674 /* Enable the DMA Stream */
3675 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3676 }
3677 break;
3678 case TIM_DMA_CC4:
3679 {
3680 /* Set the DMA Period elapsed callback */
3681 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
3682
3683 /* Set the DMA error callback */
3684 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3685
3686 /* Enable the DMA Stream */
3687 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3688 }
3689 break;
3690 case TIM_DMA_COM:
3691 {
3692 /* Set the DMA Period elapsed callback */
3693 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3694
3695 /* Set the DMA error callback */
3696 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3697
3698 /* Enable the DMA Stream */
3699 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3700 }
3701 break;
3702 case TIM_DMA_TRIGGER:
3703 {
3704 /* Set the DMA Period elapsed callback */
3705 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3706
3707 /* Set the DMA error callback */
3708 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3709
3710 /* Enable the DMA Stream */
3711 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
3712 }
3713 break;
3714 default:
3715 break;
3716 }
3717
3718 /* configure the DMA Burst Mode */
3719 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3720
3721 /* Enable the TIM DMA Request */
3722 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3723
3724 htim->State = HAL_TIM_STATE_READY;
3725
3726 /* Return function status */
3727 return HAL_OK;
3728 }
3729
3730 /**
3731 * @brief Stop the DMA burst reading
3732 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3733 * the configuration information for TIM module.
3734 * @param BurstRequestSrc: TIM DMA Request sources to disable.
3735 * @retval HAL status
3736 */
3737 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3738 {
3739 /* Check the parameters */
3740 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3741
3742 /* Abort the DMA transfer (at least disable the DMA channel) */
3743 switch(BurstRequestSrc)
3744 {
3745 case TIM_DMA_UPDATE:
3746 {
3747 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3748 }
3749 break;
3750 case TIM_DMA_CC1:
3751 {
3752 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3753 }
3754 break;
3755 case TIM_DMA_CC2:
3756 {
3757 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3758 }
3759 break;
3760 case TIM_DMA_CC3:
3761 {
3762 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3763 }
3764 break;
3765 case TIM_DMA_CC4:
3766 {
3767 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3768 }
3769 break;
3770 case TIM_DMA_COM:
3771 {
3772 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3773 }
3774 break;
3775 case TIM_DMA_TRIGGER:
3776 {
3777 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3778 }
3779 break;
3780 default:
3781 break;
3782 }
3783
3784 /* Disable the TIM Update DMA request */
3785 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3786
3787 /* Return function status */
3788 return HAL_OK;
3789 }
3790
3791 /**
3792 * @brief Generate a software event
3793 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3794 * the configuration information for TIM module.
3795 * @param EventSource: specifies the event source.
3796 * This parameter can be one of the following values:
3797 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
3798 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3799 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
3800 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
3801 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
3802 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
3803 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
3804 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
3805 * @note TIM6 and TIM7 can only generate an update event.
3806 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
3807 * @retval HAL status
3808 */
3809
3810 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3811 {
3812 /* Check the parameters */
3813 assert_param(IS_TIM_INSTANCE(htim->Instance));
3814 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3815
3816 /* Process Locked */
3817 __HAL_LOCK(htim);
3818
3819 /* Change the TIM state */
3820 htim->State = HAL_TIM_STATE_BUSY;
3821
3822 /* Set the event sources */
3823 htim->Instance->EGR = EventSource;
3824
3825 /* Change the TIM state */
3826 htim->State = HAL_TIM_STATE_READY;
3827
3828 __HAL_UNLOCK(htim);
3829
3830 /* Return function status */
3831 return HAL_OK;
3832 }
3833
3834 /**
3835 * @brief Configures the OCRef clear feature
3836 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3837 * the configuration information for TIM module.
3838 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3839 * contains the OCREF clear feature and parameters for the TIM peripheral.
3840 * @param Channel: specifies the TIM Channel.
3841 * This parameter can be one of the following values:
3842 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3843 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3844 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3845 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3846 * @retval HAL status
3847 */
3848 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3849 {
3850 /* Check the parameters */
3851 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3852 assert_param(IS_TIM_CHANNELS(Channel));
3853 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3854 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3855 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3856 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3857
3858 /* Process Locked */
3859 __HAL_LOCK(htim);
3860
3861 htim->State = HAL_TIM_STATE_BUSY;
3862
3863 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
3864 {
3865 TIM_ETR_SetConfig(htim->Instance,
3866 sClearInputConfig->ClearInputPrescaler,
3867 sClearInputConfig->ClearInputPolarity,
3868 sClearInputConfig->ClearInputFilter);
3869 }
3870
3871 switch (Channel)
3872 {
3873 case TIM_CHANNEL_1:
3874 {
3875 if(sClearInputConfig->ClearInputState != RESET)
3876 {
3877 /* Enable the Ocref clear feature for Channel 1 */
3878 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3879 }
3880 else
3881 {
3882 /* Disable the Ocref clear feature for Channel 1 */
3883 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3884 }
3885 }
3886 break;
3887 case TIM_CHANNEL_2:
3888 {
3889 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3890 if(sClearInputConfig->ClearInputState != RESET)
3891 {
3892 /* Enable the Ocref clear feature for Channel 2 */
3893 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3894 }
3895 else
3896 {
3897 /* Disable the Ocref clear feature for Channel 2 */
3898 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3899 }
3900 }
3901 break;
3902 case TIM_CHANNEL_3:
3903 {
3904 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3905 if(sClearInputConfig->ClearInputState != RESET)
3906 {
3907 /* Enable the Ocref clear feature for Channel 3 */
3908 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3909 }
3910 else
3911 {
3912 /* Disable the Ocref clear feature for Channel 3 */
3913 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3914 }
3915 }
3916 break;
3917 case TIM_CHANNEL_4:
3918 {
3919 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3920 if(sClearInputConfig->ClearInputState != RESET)
3921 {
3922 /* Enable the Ocref clear feature for Channel 4 */
3923 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3924 }
3925 else
3926 {
3927 /* Disable the Ocref clear feature for Channel 4 */
3928 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3929 }
3930 }
3931 break;
3932 default:
3933 break;
3934 }
3935
3936 htim->State = HAL_TIM_STATE_READY;
3937
3938 __HAL_UNLOCK(htim);
3939
3940 return HAL_OK;
3941 }
3942
3943 /**
3944 * @brief Configures the clock source to be used
3945 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
3946 * the configuration information for TIM module.
3947 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3948 * contains the clock source information for the TIM peripheral.
3949 * @retval HAL status
3950 */
3951 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3952 {
3953 uint32_t tmpsmcr = 0U;
3954
3955 /* Process Locked */
3956 __HAL_LOCK(htim);
3957
3958 htim->State = HAL_TIM_STATE_BUSY;
3959
3960 /* Check the parameters */
3961 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3962
3963 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3964 tmpsmcr = htim->Instance->SMCR;
3965 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3966 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3967 htim->Instance->SMCR = tmpsmcr;
3968
3969 switch (sClockSourceConfig->ClockSource)
3970 {
3971 case TIM_CLOCKSOURCE_INTERNAL:
3972 {
3973 assert_param(IS_TIM_INSTANCE(htim->Instance));
3974
3975 /* Disable slave mode to clock the prescaler directly with the internal clock */
3976 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3977 }
3978 break;
3979
3980 case TIM_CLOCKSOURCE_ETRMODE1:
3981 {
3982 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3983
3984 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3985 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3986 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3987
3988 /* Configure the ETR Clock source */
3989 TIM_ETR_SetConfig(htim->Instance,
3990 sClockSourceConfig->ClockPrescaler,
3991 sClockSourceConfig->ClockPolarity,
3992 sClockSourceConfig->ClockFilter);
3993 /* Get the TIMx SMCR register value */
3994 tmpsmcr = htim->Instance->SMCR;
3995 /* Reset the SMS and TS Bits */
3996 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3997 /* Select the External clock mode1 and the ETRF trigger */
3998 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3999 /* Write to TIMx SMCR */
4000 htim->Instance->SMCR = tmpsmcr;
4001 }
4002 break;
4003
4004 case TIM_CLOCKSOURCE_ETRMODE2:
4005 {
4006 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
4007
4008 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4009 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4010 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4011
4012 /* Configure the ETR Clock source */
4013 TIM_ETR_SetConfig(htim->Instance,
4014 sClockSourceConfig->ClockPrescaler,
4015 sClockSourceConfig->ClockPolarity,
4016 sClockSourceConfig->ClockFilter);
4017 /* Enable the External clock mode2 */
4018 htim->Instance->SMCR |= TIM_SMCR_ECE;
4019 }
4020 break;
4021
4022 case TIM_CLOCKSOURCE_TI1:
4023 {
4024 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4025
4026 /* Check TI1 input conditioning related parameters */
4027 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4028 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4029
4030 TIM_TI1_ConfigInputStage(htim->Instance,
4031 sClockSourceConfig->ClockPolarity,
4032 sClockSourceConfig->ClockFilter);
4033 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4034 }
4035 break;
4036 case TIM_CLOCKSOURCE_TI2:
4037 {
4038 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4039
4040 /* Check TI1 input conditioning related parameters */
4041 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4042 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4043
4044 TIM_TI2_ConfigInputStage(htim->Instance,
4045 sClockSourceConfig->ClockPolarity,
4046 sClockSourceConfig->ClockFilter);
4047 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4048 }
4049 break;
4050 case TIM_CLOCKSOURCE_TI1ED:
4051 {
4052 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4053
4054 /* Check TI1 input conditioning related parameters */
4055 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4056 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4057
4058 TIM_TI1_ConfigInputStage(htim->Instance,
4059 sClockSourceConfig->ClockPolarity,
4060 sClockSourceConfig->ClockFilter);
4061 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4062 }
4063 break;
4064 case TIM_CLOCKSOURCE_ITR0:
4065 {
4066 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4067 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
4068 }
4069 break;
4070 case TIM_CLOCKSOURCE_ITR1:
4071 {
4072 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4073 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
4074 }
4075 break;
4076 case TIM_CLOCKSOURCE_ITR2:
4077 {
4078 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4079 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
4080 }
4081 break;
4082 case TIM_CLOCKSOURCE_ITR3:
4083 {
4084 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4085 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
4086 }
4087 break;
4088
4089 default:
4090 break;
4091 }
4092 htim->State = HAL_TIM_STATE_READY;
4093
4094 __HAL_UNLOCK(htim);
4095
4096 return HAL_OK;
4097 }
4098
4099 /**
4100 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4101 * or a XOR combination between CH1_input, CH2_input & CH3_input
4102 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4103 * the configuration information for TIM module.
4104 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
4105 * output of a XOR gate.
4106 * This parameter can be one of the following values:
4107 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4108 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4109 * pins are connected to the TI1 input (XOR combination)
4110 * @retval HAL status
4111 */
4112 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4113 {
4114 uint32_t tmpcr2 = 0U;
4115
4116 /* Check the parameters */
4117 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4118 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4119
4120 /* Get the TIMx CR2 register value */
4121 tmpcr2 = htim->Instance->CR2;
4122
4123 /* Reset the TI1 selection */
4124 tmpcr2 &= ~TIM_CR2_TI1S;
4125
4126 /* Set the TI1 selection */
4127 tmpcr2 |= TI1_Selection;
4128
4129 /* Write to TIMxCR2 */
4130 htim->Instance->CR2 = tmpcr2;
4131
4132 return HAL_OK;
4133 }
4134
4135 /**
4136 * @brief Configures the TIM in Slave mode
4137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4138 * the configuration information for TIM module.
4139 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4140 * contains the selected trigger (internal trigger input, filtered
4141 * timer input or external trigger input) and the ) and the Slave
4142 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4143 * @retval HAL status
4144 */
4145 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
4146 {
4147 /* Check the parameters */
4148 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4149 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4150 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4151
4152 __HAL_LOCK(htim);
4153
4154 htim->State = HAL_TIM_STATE_BUSY;
4155
4156 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4157
4158 /* Disable Trigger Interrupt */
4159 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4160
4161 /* Disable Trigger DMA request */
4162 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4163
4164 htim->State = HAL_TIM_STATE_READY;
4165
4166 __HAL_UNLOCK(htim);
4167
4168 return HAL_OK;
4169 }
4170
4171 /**
4172 * @brief Configures the TIM in Slave mode in interrupt mode
4173 * @param htim: TIM handle.
4174 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4175 * contains the selected trigger (internal trigger input, filtered
4176 * timer input or external trigger input) and the ) and the Slave
4177 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4178 * @retval HAL status
4179 */
4180 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
4181 TIM_SlaveConfigTypeDef * sSlaveConfig)
4182 {
4183 /* Check the parameters */
4184 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4185 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4186 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4187
4188 __HAL_LOCK(htim);
4189
4190 htim->State = HAL_TIM_STATE_BUSY;
4191
4192 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4193
4194 /* Enable Trigger Interrupt */
4195 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4196
4197 /* Disable Trigger DMA request */
4198 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4199
4200 htim->State = HAL_TIM_STATE_READY;
4201
4202 __HAL_UNLOCK(htim);
4203
4204 return HAL_OK;
4205 }
4206
4207 /**
4208 * @brief Read the captured value from Capture Compare unit
4209 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4210 * the configuration information for TIM module.
4211 * @param Channel: TIM Channels to be enabled.
4212 * This parameter can be one of the following values:
4213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4217 * @retval Captured value
4218 */
4219 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4220 {
4221 uint32_t tmpreg = 0U;
4222
4223 __HAL_LOCK(htim);
4224
4225 switch (Channel)
4226 {
4227 case TIM_CHANNEL_1:
4228 {
4229 /* Check the parameters */
4230 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4231
4232 /* Return the capture 1 value */
4233 tmpreg = htim->Instance->CCR1;
4234
4235 break;
4236 }
4237 case TIM_CHANNEL_2:
4238 {
4239 /* Check the parameters */
4240 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4241
4242 /* Return the capture 2 value */
4243 tmpreg = htim->Instance->CCR2;
4244
4245 break;
4246 }
4247
4248 case TIM_CHANNEL_3:
4249 {
4250 /* Check the parameters */
4251 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4252
4253 /* Return the capture 3 value */
4254 tmpreg = htim->Instance->CCR3;
4255
4256 break;
4257 }
4258
4259 case TIM_CHANNEL_4:
4260 {
4261 /* Check the parameters */
4262 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4263
4264 /* Return the capture 4 value */
4265 tmpreg = htim->Instance->CCR4;
4266
4267 break;
4268 }
4269
4270 default:
4271 break;
4272 }
4273
4274 __HAL_UNLOCK(htim);
4275 return tmpreg;
4276 }
4277 /**
4278 * @}
4279 */
4280
4281 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4282 * @brief TIM Callbacks functions
4283 *
4284 @verbatim
4285 ==============================================================================
4286 ##### TIM Callbacks functions #####
4287 ==============================================================================
4288 [..]
4289 This section provides TIM callback functions:
4290 (+) Timer Period elapsed callback
4291 (+) Timer Output Compare callback
4292 (+) Timer Input capture callback
4293 (+) Timer Trigger callback
4294 (+) Timer Error callback
4295
4296 @endverbatim
4297 * @{
4298 */
4299
4300 /**
4301 * @brief Period elapsed callback in non blocking mode
4302 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4303 * the configuration information for TIM module.
4304 * @retval None
4305 */
4306 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4307 {
4308 /* Prevent unused argument(s) compilation warning */
4309 UNUSED(htim);
4310 /* NOTE : This function Should not be modified, when the callback is needed,
4311 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4312 */
4313 }
4314
4315 /**
4316 * @brief Output Compare callback in non blocking mode
4317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4318 * the configuration information for TIM module.
4319 * @retval None
4320 */
4321 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4322 {
4323 /* Prevent unused argument(s) compilation warning */
4324 UNUSED(htim);
4325 /* NOTE : This function Should not be modified, when the callback is needed,
4326 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4327 */
4328 }
4329
4330 /**
4331 * @brief Input Capture callback in non blocking mode
4332 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4333 * the configuration information for TIM module.
4334 * @retval None
4335 */
4336 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4337 {
4338 /* Prevent unused argument(s) compilation warning */
4339 UNUSED(htim);
4340 /* NOTE : This function Should not be modified, when the callback is needed,
4341 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4342 */
4343 }
4344
4345 /**
4346 * @brief PWM Pulse finished callback in non blocking mode
4347 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4348 * the configuration information for TIM module.
4349 * @retval None
4350 */
4351 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4352 {
4353 /* Prevent unused argument(s) compilation warning */
4354 UNUSED(htim);
4355 /* NOTE : This function Should not be modified, when the callback is needed,
4356 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4357 */
4358 }
4359
4360 /**
4361 * @brief Hall Trigger detection callback in non blocking mode
4362 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4363 * the configuration information for TIM module.
4364 * @retval None
4365 */
4366 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4367 {
4368 /* Prevent unused argument(s) compilation warning */
4369 UNUSED(htim);
4370 /* NOTE : This function Should not be modified, when the callback is needed,
4371 the HAL_TIM_TriggerCallback could be implemented in the user file
4372 */
4373 }
4374
4375 /**
4376 * @brief Timer error callback in non blocking mode
4377 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4378 * the configuration information for TIM module.
4379 * @retval None
4380 */
4381 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4382 {
4383 /* Prevent unused argument(s) compilation warning */
4384 UNUSED(htim);
4385 /* NOTE : This function Should not be modified, when the callback is needed,
4386 the HAL_TIM_ErrorCallback could be implemented in the user file
4387 */
4388 }
4389 /**
4390 * @}
4391 */
4392
4393 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4394 * @brief Peripheral State functions
4395 *
4396 @verbatim
4397 ==============================================================================
4398 ##### Peripheral State functions #####
4399 ==============================================================================
4400 [..]
4401 This subsection permits to get in run-time the status of the peripheral
4402 and the data flow.
4403
4404 @endverbatim
4405 * @{
4406 */
4407
4408 /**
4409 * @brief Return the TIM Base state
4410 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4411 * the configuration information for TIM module.
4412 * @retval HAL state
4413 */
4414 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4415 {
4416 return htim->State;
4417 }
4418
4419 /**
4420 * @brief Return the TIM OC state
4421 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4422 * the configuration information for TIM module.
4423 * @retval HAL state
4424 */
4425 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4426 {
4427 return htim->State;
4428 }
4429
4430 /**
4431 * @brief Return the TIM PWM state
4432 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4433 * the configuration information for TIM module.
4434 * @retval HAL state
4435 */
4436 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4437 {
4438 return htim->State;
4439 }
4440
4441 /**
4442 * @brief Return the TIM Input Capture state
4443 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4444 * the configuration information for TIM module.
4445 * @retval HAL state
4446 */
4447 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4448 {
4449 return htim->State;
4450 }
4451
4452 /**
4453 * @brief Return the TIM One Pulse Mode state
4454 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4455 * the configuration information for TIM module.
4456 * @retval HAL state
4457 */
4458 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4459 {
4460 return htim->State;
4461 }
4462
4463 /**
4464 * @brief Return the TIM Encoder Mode state
4465 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4466 * the configuration information for TIM module.
4467 * @retval HAL state
4468 */
4469 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4470 {
4471 return htim->State;
4472 }
4473 /**
4474 * @}
4475 */
4476
4477 /**
4478 * @brief Time Base configuration
4479 * @param TIMx: TIM peripheral
4480 * @param Structure: pointer on TIM Time Base required parameters
4481 * @retval None
4482 */
4483 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4484 {
4485 uint32_t tmpcr1 = 0U;
4486 tmpcr1 = TIMx->CR1;
4487
4488 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4489 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
4490 {
4491 /* Select the Counter Mode */
4492 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4493 tmpcr1 |= Structure->CounterMode;
4494 }
4495
4496 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
4497 {
4498 /* Set the clock division */
4499 tmpcr1 &= ~TIM_CR1_CKD;
4500 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4501 }
4502
4503 TIMx->CR1 = tmpcr1;
4504
4505 /* Set the Auto-reload value */
4506 TIMx->ARR = (uint32_t)Structure->Period ;
4507
4508 /* Set the Prescaler value */
4509 TIMx->PSC = (uint32_t)Structure->Prescaler;
4510
4511 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4512 {
4513 /* Set the Repetition Counter value */
4514 TIMx->RCR = Structure->RepetitionCounter;
4515 }
4516
4517 /* Generate an update event to reload the Prescaler
4518 and the repetition counter(only for TIM1 and TIM8) value immediately */
4519 TIMx->EGR = TIM_EGR_UG;
4520 }
4521
4522 /**
4523 * @brief Configure the TI1 as Input.
4524 * @param TIMx to select the TIM peripheral.
4525 * @param TIM_ICPolarity : The Input Polarity.
4526 * This parameter can be one of the following values:
4527 * @arg TIM_ICPolarity_Rising
4528 * @arg TIM_ICPolarity_Falling
4529 * @arg TIM_ICPolarity_BothEdge
4530 * @param TIM_ICSelection: specifies the input to be used.
4531 * This parameter can be one of the following values:
4532 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
4533 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
4534 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
4535 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4536 * This parameter must be a value between 0x00 and 0x0F.
4537 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
4538 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
4539 * protected against un-initialized filter and polarity values.
4540 * @retval None
4541 */
4542 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4543 uint32_t TIM_ICFilter)
4544 {
4545 uint32_t tmpccmr1 = 0U;
4546 uint32_t tmpccer = 0U;
4547
4548 /* Disable the Channel 1: Reset the CC1E Bit */
4549 TIMx->CCER &= ~TIM_CCER_CC1E;
4550 tmpccmr1 = TIMx->CCMR1;
4551 tmpccer = TIMx->CCER;
4552
4553 /* Select the Input */
4554 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4555 {
4556 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4557 tmpccmr1 |= TIM_ICSelection;
4558 }
4559 else
4560 {
4561 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4562 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4563 }
4564
4565 /* Set the filter */
4566 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4567 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
4568
4569 /* Select the Polarity and set the CC1E Bit */
4570 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4571 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
4572
4573 /* Write to TIMx CCMR1 and CCER registers */
4574 TIMx->CCMR1 = tmpccmr1;
4575 TIMx->CCER = tmpccer;
4576 }
4577
4578 /**
4579 * @brief Time Output Compare 2 configuration
4580 * @param TIMx to select the TIM peripheral
4581 * @param OC_Config: The output configuration structure
4582 * @retval None
4583 */
4584 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4585 {
4586 uint32_t tmpccmrx = 0U;
4587 uint32_t tmpccer = 0U;
4588 uint32_t tmpcr2 = 0U;
4589
4590 /* Disable the Channel 2: Reset the CC2E Bit */
4591 TIMx->CCER &= ~TIM_CCER_CC2E;
4592
4593 /* Get the TIMx CCER register value */
4594 tmpccer = TIMx->CCER;
4595 /* Get the TIMx CR2 register value */
4596 tmpcr2 = TIMx->CR2;
4597
4598 /* Get the TIMx CCMR1 register value */
4599 tmpccmrx = TIMx->CCMR1;
4600
4601 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4602 tmpccmrx &= ~TIM_CCMR1_OC2M;
4603 tmpccmrx &= ~TIM_CCMR1_CC2S;
4604
4605 /* Select the Output Compare Mode */
4606 tmpccmrx |= (OC_Config->OCMode << 8U);
4607
4608 /* Reset the Output Polarity level */
4609 tmpccer &= ~TIM_CCER_CC2P;
4610 /* Set the Output Compare Polarity */
4611 tmpccer |= (OC_Config->OCPolarity << 4U);
4612
4613 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4614 {
4615 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4616
4617 /* Reset the Output N Polarity level */
4618 tmpccer &= ~TIM_CCER_CC2NP;
4619 /* Set the Output N Polarity */
4620 tmpccer |= (OC_Config->OCNPolarity << 4U);
4621 /* Reset the Output N State */
4622 tmpccer &= ~TIM_CCER_CC2NE;
4623
4624 /* Reset the Output Compare and Output Compare N IDLE State */
4625 tmpcr2 &= ~TIM_CR2_OIS2;
4626 tmpcr2 &= ~TIM_CR2_OIS2N;
4627 /* Set the Output Idle state */
4628 tmpcr2 |= (OC_Config->OCIdleState << 2U);
4629 /* Set the Output N Idle state */
4630 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
4631 }
4632 /* Write to TIMx CR2 */
4633 TIMx->CR2 = tmpcr2;
4634
4635 /* Write to TIMx CCMR1 */
4636 TIMx->CCMR1 = tmpccmrx;
4637
4638 /* Set the Capture Compare Register value */
4639 TIMx->CCR2 = OC_Config->Pulse;
4640
4641 /* Write to TIMx CCER */
4642 TIMx->CCER = tmpccer;
4643 }
4644
4645 /**
4646 * @brief TIM DMA Delay Pulse complete callback.
4647 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4648 * the configuration information for the specified DMA module.
4649 * @retval None
4650 */
4651 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4652 {
4653 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4654
4655 htim->State= HAL_TIM_STATE_READY;
4656
4657 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
4658 {
4659 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4660 }
4661 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
4662 {
4663 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4664 }
4665 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
4666 {
4667 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4668 }
4669 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
4670 {
4671 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4672 }
4673
4674 HAL_TIM_PWM_PulseFinishedCallback(htim);
4675
4676 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4677 }
4678
4679 /**
4680 * @brief TIM DMA error callback
4681 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4682 * the configuration information for the specified DMA module.
4683 * @retval None
4684 */
4685 void TIM_DMAError(DMA_HandleTypeDef *hdma)
4686 {
4687 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4688
4689 htim->State= HAL_TIM_STATE_READY;
4690
4691 HAL_TIM_ErrorCallback(htim);
4692 }
4693
4694 /**
4695 * @brief TIM DMA Capture complete callback.
4696 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4697 * the configuration information for the specified DMA module.
4698 * @retval None
4699 */
4700 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4701 {
4702 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4703
4704 htim->State= HAL_TIM_STATE_READY;
4705
4706 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
4707 {
4708 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4709 }
4710 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
4711 {
4712 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4713 }
4714 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
4715 {
4716 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4717 }
4718 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
4719 {
4720 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4721 }
4722
4723 HAL_TIM_IC_CaptureCallback(htim);
4724
4725 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4726 }
4727
4728 /**
4729 * @brief Enables or disables the TIM Capture Compare Channel x.
4730 * @param TIMx to select the TIM peripheral
4731 * @param Channel: specifies the TIM Channel
4732 * This parameter can be one of the following values:
4733 * @arg TIM_Channel_1: TIM Channel 1
4734 * @arg TIM_Channel_2: TIM Channel 2
4735 * @arg TIM_Channel_3: TIM Channel 3
4736 * @arg TIM_Channel_4: TIM Channel 4
4737 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
4738 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
4739 * @retval None
4740 */
4741 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
4742 {
4743 uint32_t tmp = 0U;
4744
4745 /* Check the parameters */
4746 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
4747 assert_param(IS_TIM_CHANNELS(Channel));
4748
4749 tmp = TIM_CCER_CC1E << Channel;
4750
4751 /* Reset the CCxE Bit */
4752 TIMx->CCER &= ~tmp;
4753
4754 /* Set or reset the CCxE Bit */
4755 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
4756 }
4757
4758 /**
4759 * @brief TIM DMA Period Elapse complete callback.
4760 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4761 * the configuration information for the specified DMA module.
4762 * @retval None
4763 */
4764 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4765 {
4766 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4767
4768 htim->State= HAL_TIM_STATE_READY;
4769
4770 HAL_TIM_PeriodElapsedCallback(htim);
4771 }
4772
4773 /**
4774 * @brief TIM DMA Trigger callback.
4775 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4776 * the configuration information for the specified DMA module.
4777 * @retval None
4778 */
4779 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4780 {
4781 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4782
4783 htim->State= HAL_TIM_STATE_READY;
4784
4785 HAL_TIM_TriggerCallback(htim);
4786 }
4787
4788 /**
4789 * @brief Time Output Compare 1 configuration
4790 * @param TIMx to select the TIM peripheral
4791 * @param OC_Config: The output configuration structure
4792 * @retval None
4793 */
4794 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4795 {
4796 uint32_t tmpccmrx = 0U;
4797 uint32_t tmpccer = 0U;
4798 uint32_t tmpcr2 = 0U;
4799
4800 /* Disable the Channel 1: Reset the CC1E Bit */
4801 TIMx->CCER &= ~TIM_CCER_CC1E;
4802
4803 /* Get the TIMx CCER register value */
4804 tmpccer = TIMx->CCER;
4805 /* Get the TIMx CR2 register value */
4806 tmpcr2 = TIMx->CR2;
4807
4808 /* Get the TIMx CCMR1 register value */
4809 tmpccmrx = TIMx->CCMR1;
4810
4811 /* Reset the Output Compare Mode Bits */
4812 tmpccmrx &= ~TIM_CCMR1_OC1M;
4813 tmpccmrx &= ~TIM_CCMR1_CC1S;
4814 /* Select the Output Compare Mode */
4815 tmpccmrx |= OC_Config->OCMode;
4816
4817 /* Reset the Output Polarity level */
4818 tmpccer &= ~TIM_CCER_CC1P;
4819 /* Set the Output Compare Polarity */
4820 tmpccer |= OC_Config->OCPolarity;
4821
4822
4823 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4824 {
4825 /* Reset the Output N Polarity level */
4826 tmpccer &= ~TIM_CCER_CC1NP;
4827 /* Set the Output N Polarity */
4828 tmpccer |= OC_Config->OCNPolarity;
4829 /* Reset the Output N State */
4830 tmpccer &= ~TIM_CCER_CC1NE;
4831
4832 /* Reset the Output Compare and Output Compare N IDLE State */
4833 tmpcr2 &= ~TIM_CR2_OIS1;
4834 tmpcr2 &= ~TIM_CR2_OIS1N;
4835 /* Set the Output Idle state */
4836 tmpcr2 |= OC_Config->OCIdleState;
4837 /* Set the Output N Idle state */
4838 tmpcr2 |= OC_Config->OCNIdleState;
4839 }
4840 /* Write to TIMx CR2 */
4841 TIMx->CR2 = tmpcr2;
4842
4843 /* Write to TIMx CCMR1 */
4844 TIMx->CCMR1 = tmpccmrx;
4845
4846 /* Set the Capture Compare Register value */
4847 TIMx->CCR1 = OC_Config->Pulse;
4848
4849 /* Write to TIMx CCER */
4850 TIMx->CCER = tmpccer;
4851 }
4852
4853 /**
4854 * @brief Time Output Compare 3 configuration
4855 * @param TIMx to select the TIM peripheral
4856 * @param OC_Config: The output configuration structure
4857 * @retval None
4858 */
4859 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4860 {
4861 uint32_t tmpccmrx = 0U;
4862 uint32_t tmpccer = 0U;
4863 uint32_t tmpcr2 = 0U;
4864
4865 /* Disable the Channel 3: Reset the CC2E Bit */
4866 TIMx->CCER &= ~TIM_CCER_CC3E;
4867
4868 /* Get the TIMx CCER register value */
4869 tmpccer = TIMx->CCER;
4870 /* Get the TIMx CR2 register value */
4871 tmpcr2 = TIMx->CR2;
4872
4873 /* Get the TIMx CCMR2 register value */
4874 tmpccmrx = TIMx->CCMR2;
4875
4876 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4877 tmpccmrx &= ~TIM_CCMR2_OC3M;
4878 tmpccmrx &= ~TIM_CCMR2_CC3S;
4879 /* Select the Output Compare Mode */
4880 tmpccmrx |= OC_Config->OCMode;
4881
4882 /* Reset the Output Polarity level */
4883 tmpccer &= ~TIM_CCER_CC3P;
4884 /* Set the Output Compare Polarity */
4885 tmpccer |= (OC_Config->OCPolarity << 8U);
4886
4887 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4888 {
4889 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4890 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4891 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4892
4893 /* Reset the Output N Polarity level */
4894 tmpccer &= ~TIM_CCER_CC3NP;
4895 /* Set the Output N Polarity */
4896 tmpccer |= (OC_Config->OCNPolarity << 8U);
4897 /* Reset the Output N State */
4898 tmpccer &= ~TIM_CCER_CC3NE;
4899
4900 /* Reset the Output Compare and Output Compare N IDLE State */
4901 tmpcr2 &= ~TIM_CR2_OIS3;
4902 tmpcr2 &= ~TIM_CR2_OIS3N;
4903 /* Set the Output Idle state */
4904 tmpcr2 |= (OC_Config->OCIdleState << 4U);
4905 /* Set the Output N Idle state */
4906 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
4907 }
4908 /* Write to TIMx CR2 */
4909 TIMx->CR2 = tmpcr2;
4910
4911 /* Write to TIMx CCMR2 */
4912 TIMx->CCMR2 = tmpccmrx;
4913
4914 /* Set the Capture Compare Register value */
4915 TIMx->CCR3 = OC_Config->Pulse;
4916
4917 /* Write to TIMx CCER */
4918 TIMx->CCER = tmpccer;
4919 }
4920
4921 /**
4922 * @brief Time Output Compare 4 configuration
4923 * @param TIMx to select the TIM peripheral
4924 * @param OC_Config: The output configuration structure
4925 * @retval None
4926 */
4927 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4928 {
4929 uint32_t tmpccmrx = 0U;
4930 uint32_t tmpccer = 0U;
4931 uint32_t tmpcr2 = 0U;
4932
4933 /* Disable the Channel 4: Reset the CC4E Bit */
4934 TIMx->CCER &= ~TIM_CCER_CC4E;
4935
4936 /* Get the TIMx CCER register value */
4937 tmpccer = TIMx->CCER;
4938 /* Get the TIMx CR2 register value */
4939 tmpcr2 = TIMx->CR2;
4940
4941 /* Get the TIMx CCMR2 register value */
4942 tmpccmrx = TIMx->CCMR2;
4943
4944 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4945 tmpccmrx &= ~TIM_CCMR2_OC4M;
4946 tmpccmrx &= ~TIM_CCMR2_CC4S;
4947
4948 /* Select the Output Compare Mode */
4949 tmpccmrx |= (OC_Config->OCMode << 8U);
4950
4951 /* Reset the Output Polarity level */
4952 tmpccer &= ~TIM_CCER_CC4P;
4953 /* Set the Output Compare Polarity */
4954 tmpccer |= (OC_Config->OCPolarity << 12U);
4955
4956 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
4957 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
4958 {
4959 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4960 /* Reset the Output Compare IDLE State */
4961 tmpcr2 &= ~TIM_CR2_OIS4;
4962 /* Set the Output Idle state */
4963 tmpcr2 |= (OC_Config->OCIdleState << 6U);
4964 }
4965 /* Write to TIMx CR2 */
4966 TIMx->CR2 = tmpcr2;
4967
4968 /* Write to TIMx CCMR2 */
4969 TIMx->CCMR2 = tmpccmrx;
4970
4971 /* Set the Capture Compare Register value */
4972 TIMx->CCR4 = OC_Config->Pulse;
4973
4974 /* Write to TIMx CCER */
4975 TIMx->CCER = tmpccer;
4976 }
4977
4978 /**
4979 * @brief Time Output Compare 4 configuration
4980 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
4981 * the configuration information for TIM module.
4982 * @param sSlaveConfig: The slave configuration structure
4983 * @retval None
4984 */
4985 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
4986 TIM_SlaveConfigTypeDef * sSlaveConfig)
4987 {
4988 uint32_t tmpsmcr = 0U;
4989 uint32_t tmpccmr1 = 0U;
4990 uint32_t tmpccer = 0U;
4991
4992 /* Get the TIMx SMCR register value */
4993 tmpsmcr = htim->Instance->SMCR;
4994
4995 /* Reset the Trigger Selection Bits */
4996 tmpsmcr &= ~TIM_SMCR_TS;
4997 /* Set the Input Trigger source */
4998 tmpsmcr |= sSlaveConfig->InputTrigger;
4999
5000 /* Reset the slave mode Bits */
5001 tmpsmcr &= ~TIM_SMCR_SMS;
5002 /* Set the slave mode */
5003 tmpsmcr |= sSlaveConfig->SlaveMode;
5004
5005 /* Write to TIMx SMCR */
5006 htim->Instance->SMCR = tmpsmcr;
5007
5008 /* Configure the trigger prescaler, filter, and polarity */
5009 switch (sSlaveConfig->InputTrigger)
5010 {
5011 case TIM_TS_ETRF:
5012 {
5013 /* Check the parameters */
5014 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
5015 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
5016 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5017 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5018 /* Configure the ETR Trigger source */
5019 TIM_ETR_SetConfig(htim->Instance,
5020 sSlaveConfig->TriggerPrescaler,
5021 sSlaveConfig->TriggerPolarity,
5022 sSlaveConfig->TriggerFilter);
5023 }
5024 break;
5025
5026 case TIM_TS_TI1F_ED:
5027 {
5028 /* Check the parameters */
5029 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5030 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5031
5032 /* Disable the Channel 1: Reset the CC1E Bit */
5033 tmpccer = htim->Instance->CCER;
5034 htim->Instance->CCER &= ~TIM_CCER_CC1E;
5035 tmpccmr1 = htim->Instance->CCMR1;
5036
5037 /* Set the filter */
5038 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5039 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
5040
5041 /* Write to TIMx CCMR1 and CCER registers */
5042 htim->Instance->CCMR1 = tmpccmr1;
5043 htim->Instance->CCER = tmpccer;
5044
5045 }
5046 break;
5047
5048 case TIM_TS_TI1FP1:
5049 {
5050 /* Check the parameters */
5051 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5052 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5053 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5054
5055 /* Configure TI1 Filter and Polarity */
5056 TIM_TI1_ConfigInputStage(htim->Instance,
5057 sSlaveConfig->TriggerPolarity,
5058 sSlaveConfig->TriggerFilter);
5059 }
5060 break;
5061
5062 case TIM_TS_TI2FP2:
5063 {
5064 /* Check the parameters */
5065 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5066 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5067 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5068
5069 /* Configure TI2 Filter and Polarity */
5070 TIM_TI2_ConfigInputStage(htim->Instance,
5071 sSlaveConfig->TriggerPolarity,
5072 sSlaveConfig->TriggerFilter);
5073 }
5074 break;
5075
5076 case TIM_TS_ITR0:
5077 {
5078 /* Check the parameter */
5079 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5080 }
5081 break;
5082
5083 case TIM_TS_ITR1:
5084 {
5085 /* Check the parameter */
5086 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5087 }
5088 break;
5089
5090 case TIM_TS_ITR2:
5091 {
5092 /* Check the parameter */
5093 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5094 }
5095 break;
5096
5097 case TIM_TS_ITR3:
5098 {
5099 /* Check the parameter */
5100 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5101 }
5102 break;
5103
5104 default:
5105 break;
5106 }
5107 }
5108
5109
5110 /**
5111 * @brief Configure the Polarity and Filter for TI1.
5112 * @param TIMx to select the TIM peripheral.
5113 * @param TIM_ICPolarity : The Input Polarity.
5114 * This parameter can be one of the following values:
5115 * @arg TIM_ICPolarity_Rising
5116 * @arg TIM_ICPolarity_Falling
5117 * @arg TIM_ICPolarity_BothEdge
5118 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5119 * This parameter must be a value between 0x00 and 0x0F.
5120 * @retval None
5121 */
5122 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5123 {
5124 uint32_t tmpccmr1 = 0U;
5125 uint32_t tmpccer = 0U;
5126
5127 /* Disable the Channel 1: Reset the CC1E Bit */
5128 tmpccer = TIMx->CCER;
5129 TIMx->CCER &= ~TIM_CCER_CC1E;
5130 tmpccmr1 = TIMx->CCMR1;
5131
5132 /* Set the filter */
5133 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5134 tmpccmr1 |= (TIM_ICFilter << 4U);
5135
5136 /* Select the Polarity and set the CC1E Bit */
5137 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
5138 tmpccer |= TIM_ICPolarity;
5139
5140 /* Write to TIMx CCMR1 and CCER registers */
5141 TIMx->CCMR1 = tmpccmr1;
5142 TIMx->CCER = tmpccer;
5143 }
5144
5145 /**
5146 * @brief Configure the TI2 as Input.
5147 * @param TIMx to select the TIM peripheral
5148 * @param TIM_ICPolarity : The Input Polarity.
5149 * This parameter can be one of the following values:
5150 * @arg TIM_ICPolarity_Rising
5151 * @arg TIM_ICPolarity_Falling
5152 * @arg TIM_ICPolarity_BothEdge
5153 * @param TIM_ICSelection: specifies the input to be used.
5154 * This parameter can be one of the following values:
5155 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
5156 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
5157 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
5158 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5159 * This parameter must be a value between 0x00 and 0x0F.
5160 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
5161 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5162 * protected against un-initialized filter and polarity values.
5163 * @retval None
5164 */
5165 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5166 uint32_t TIM_ICFilter)
5167 {
5168 uint32_t tmpccmr1 = 0U;
5169 uint32_t tmpccer = 0U;
5170
5171 /* Disable the Channel 2: Reset the CC2E Bit */
5172 TIMx->CCER &= ~TIM_CCER_CC2E;
5173 tmpccmr1 = TIMx->CCMR1;
5174 tmpccer = TIMx->CCER;
5175
5176 /* Select the Input */
5177 tmpccmr1 &= ~TIM_CCMR1_CC2S;
5178 tmpccmr1 |= (TIM_ICSelection << 8U);
5179
5180 /* Set the filter */
5181 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5182 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
5183
5184 /* Select the Polarity and set the CC2E Bit */
5185 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5186 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
5187
5188 /* Write to TIMx CCMR1 and CCER registers */
5189 TIMx->CCMR1 = tmpccmr1 ;
5190 TIMx->CCER = tmpccer;
5191 }
5192
5193 /**
5194 * @brief Configure the Polarity and Filter for TI2.
5195 * @param TIMx to select the TIM peripheral.
5196 * @param TIM_ICPolarity : The Input Polarity.
5197 * This parameter can be one of the following values:
5198 * @arg TIM_ICPolarity_Rising
5199 * @arg TIM_ICPolarity_Falling
5200 * @arg TIM_ICPolarity_BothEdge
5201 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5202 * This parameter must be a value between 0x00 and 0x0F.
5203 * @retval None
5204 */
5205 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5206 {
5207 uint32_t tmpccmr1 = 0U;
5208 uint32_t tmpccer = 0U;
5209
5210 /* Disable the Channel 2: Reset the CC2E Bit */
5211 TIMx->CCER &= ~TIM_CCER_CC2E;
5212 tmpccmr1 = TIMx->CCMR1;
5213 tmpccer = TIMx->CCER;
5214
5215 /* Set the filter */
5216 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5217 tmpccmr1 |= (TIM_ICFilter << 12U);
5218
5219 /* Select the Polarity and set the CC2E Bit */
5220 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5221 tmpccer |= (TIM_ICPolarity << 4U);
5222
5223 /* Write to TIMx CCMR1 and CCER registers */
5224 TIMx->CCMR1 = tmpccmr1 ;
5225 TIMx->CCER = tmpccer;
5226 }
5227
5228 /**
5229 * @brief Configure the TI3 as Input.
5230 * @param TIMx to select the TIM peripheral
5231 * @param TIM_ICPolarity : The Input Polarity.
5232 * This parameter can be one of the following values:
5233 * @arg TIM_ICPolarity_Rising
5234 * @arg TIM_ICPolarity_Falling
5235 * @arg TIM_ICPolarity_BothEdge
5236 * @param TIM_ICSelection: specifies the input to be used.
5237 * This parameter can be one of the following values:
5238 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
5239 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
5240 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
5241 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5242 * This parameter must be a value between 0x00 and 0x0F.
5243 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5244 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
5245 * protected against un-initialized filter and polarity values.
5246 * @retval None
5247 */
5248 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5249 uint32_t TIM_ICFilter)
5250 {
5251 uint32_t tmpccmr2 = 0U;
5252 uint32_t tmpccer = 0U;
5253
5254 /* Disable the Channel 3: Reset the CC3E Bit */
5255 TIMx->CCER &= ~TIM_CCER_CC3E;
5256 tmpccmr2 = TIMx->CCMR2;
5257 tmpccer = TIMx->CCER;
5258
5259 /* Select the Input */
5260 tmpccmr2 &= ~TIM_CCMR2_CC3S;
5261 tmpccmr2 |= TIM_ICSelection;
5262
5263 /* Set the filter */
5264 tmpccmr2 &= ~TIM_CCMR2_IC3F;
5265 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
5266
5267 /* Select the Polarity and set the CC3E Bit */
5268 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
5269 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
5270
5271 /* Write to TIMx CCMR2 and CCER registers */
5272 TIMx->CCMR2 = tmpccmr2;
5273 TIMx->CCER = tmpccer;
5274 }
5275
5276 /**
5277 * @brief Configure the TI4 as Input.
5278 * @param TIMx to select the TIM peripheral
5279 * @param TIM_ICPolarity : The Input Polarity.
5280 * This parameter can be one of the following values:
5281 * @arg TIM_ICPolarity_Rising
5282 * @arg TIM_ICPolarity_Falling
5283 * @arg TIM_ICPolarity_BothEdge
5284 * @param TIM_ICSelection: specifies the input to be used.
5285 * This parameter can be one of the following values:
5286 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
5287 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
5288 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
5289 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5290 * This parameter must be a value between 0x00 and 0x0F.
5291 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5292 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
5293 * protected against un-initialized filter and polarity values.
5294 * @retval None
5295 */
5296 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5297 uint32_t TIM_ICFilter)
5298 {
5299 uint32_t tmpccmr2 = 0U;
5300 uint32_t tmpccer = 0U;
5301
5302 /* Disable the Channel 4: Reset the CC4E Bit */
5303 TIMx->CCER &= ~TIM_CCER_CC4E;
5304 tmpccmr2 = TIMx->CCMR2;
5305 tmpccer = TIMx->CCER;
5306
5307 /* Select the Input */
5308 tmpccmr2 &= ~TIM_CCMR2_CC4S;
5309 tmpccmr2 |= (TIM_ICSelection << 8U);
5310
5311 /* Set the filter */
5312 tmpccmr2 &= ~TIM_CCMR2_IC4F;
5313 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
5314
5315 /* Select the Polarity and set the CC4E Bit */
5316 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
5317 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
5318
5319 /* Write to TIMx CCMR2 and CCER registers */
5320 TIMx->CCMR2 = tmpccmr2;
5321 TIMx->CCER = tmpccer ;
5322 }
5323
5324 /**
5325 * @brief Selects the Input Trigger source
5326 * @param TIMx to select the TIM peripheral
5327 * @param TIM_ITRx: The Input Trigger source.
5328 * This parameter can be one of the following values:
5329 * @arg TIM_TS_ITR0: Internal Trigger 0
5330 * @arg TIM_TS_ITR1: Internal Trigger 1
5331 * @arg TIM_TS_ITR2: Internal Trigger 2
5332 * @arg TIM_TS_ITR3: Internal Trigger 3
5333 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
5334 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
5335 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
5336 * @arg TIM_TS_ETRF: External Trigger input
5337 * @retval None
5338 */
5339 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
5340 {
5341 uint32_t tmpsmcr = 0U;
5342
5343 /* Get the TIMx SMCR register value */
5344 tmpsmcr = TIMx->SMCR;
5345 /* Reset the TS Bits */
5346 tmpsmcr &= ~TIM_SMCR_TS;
5347 /* Set the Input Trigger source and the slave mode*/
5348 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
5349 /* Write to TIMx SMCR */
5350 TIMx->SMCR = tmpsmcr;
5351 }
5352
5353 /**
5354 * @brief Configures the TIMx External Trigger (ETR).
5355 * @param TIMx to select the TIM peripheral
5356 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
5357 * This parameter can be one of the following values:
5358 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
5359 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
5360 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
5361 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
5362 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
5363 * This parameter can be one of the following values:
5364 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
5365 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
5366 * @param ExtTRGFilter: External Trigger Filter.
5367 * This parameter must be a value between 0x00 and 0x0F
5368 * @retval None
5369 */
5370 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
5371 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
5372 {
5373 uint32_t tmpsmcr = 0U;
5374
5375 tmpsmcr = TIMx->SMCR;
5376
5377 /* Reset the ETR Bits */
5378 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5379
5380 /* Set the Prescaler, the Filter value and the Polarity */
5381 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
5382
5383 /* Write to TIMx SMCR */
5384 TIMx->SMCR = tmpsmcr;
5385 }
5386
5387 /**
5388 * @}
5389 */
5390
5391 #endif /* HAL_TIM_MODULE_ENABLED */
5392 /**
5393 * @}
5394 */
5395
5396 /**
5397 * @}
5398 */
5399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/