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Moved IO_GPIOPortIdx to platform (#14127)
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_bus.h
blobc5420fe1b796984d52ddeb19d60dc051f8009295
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef __STM32F7xx_LL_BUS_H
39 #define __STM32F7xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f7xx.h"
47
48 /** @addtogroup STM32F7xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
65 * @{
66 */
67
68 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
69 * @{
70 */
71 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
72 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
73 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
74 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
75 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
76 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
77 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
78 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
79 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
80 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
81 #if defined(GPIOJ)
82 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
83 #endif /* GPIOJ */
84 #if defined(GPIOK)
85 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
86 #endif /* GPIOK */
87 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
88 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
89 #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN
90 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
91 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
92 #if defined(DMA2D)
93 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
94 #endif /* DMA2D */
95 #if defined(ETH)
96 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
97 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
98 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
99 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
100 #endif /* ETH */
101 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
102 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
103 #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN
104 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
105 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
106 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
107 /**
108 * @}
109 */
110
111 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
112 * @{
113 */
114 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
115 #if defined(DCMI)
116 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
117 #endif /* DCMI */
118 #if defined(JPEG)
119 #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN
120 #endif /* JPEG */
121 #if defined(CRYP)
122 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
123 #endif /* CRYP */
124 #if defined(AES)
125 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
126 #endif /* AES */
127 #if defined(HASH)
128 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
129 #endif /* HASH */
130 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
131 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
132 /**
133 * @}
134 */
135
136 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
137 * @{
138 */
139 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
140 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
141 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
142 /**
143 * @}
144 */
145
146 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
147 * @{
148 */
149 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
150 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
151 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
152 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
153 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
154 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
155 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
156 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
157 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
158 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
159 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
160 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
161 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
162 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
163 #if defined(SPDIFRX)
164 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
165 #endif /* SPDIFRX */
166 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
167 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
168 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
169 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
170 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
171 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
172 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
173 #if defined(I2C4)
174 #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN
175 #endif /* I2C4 */
176 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
177 #if defined(CAN2)
178 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
179 #endif /* CAN2 */
180 #if defined(CAN3)
181 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
182 #endif /* CAN3 */
183 #if defined(CEC)
184 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
185 #endif /* CEC */
186 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
187 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
188 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
189 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
190 #if defined(RCC_APB1ENR_RTCEN)
191 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN
192 #endif /* RCC_APB1ENR_RTCEN */
193 /**
194 * @}
195 */
196
197 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
198 * @{
199 */
200 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
201 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
202 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
203 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
204 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
205 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
206 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
207 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
208 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
209 #if defined(SDMMC2)
210 #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN
211 #endif /* SDMMC2 */
212 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
213 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
214 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
215 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
216 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
217 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
218 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
219 #if defined(SPI6)
220 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
221 #endif /* SPI6 */
222 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
223 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
224 #if defined(LTDC)
225 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
226 #endif /* LTDC */
227 #if defined(DSI)
228 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
229 #endif /* DSI */
230 #if defined(DFSDM1_Channel0)
231 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
232 #endif /* DFSDM1_Channel0 */
233 #if defined(MDIOS)
234 #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN
235 #endif /* MDIOS */
236 #if defined(USB_HS_PHYC)
237 #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN
238 #endif /* USB_HS_PHYC */
239 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
240 /**
241 * @}
242 */
243
244 /**
245 * @}
246 */
247
248 /* Exported macro ------------------------------------------------------------*/
249 /* Exported functions --------------------------------------------------------*/
250 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
251 * @{
252 */
253
254 /** @defgroup BUS_LL_EF_AHB1 AHB1
255 * @{
256 */
257
258 /**
259 * @brief Enable AHB1 peripherals clock.
260 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
261 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
262 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
263 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
264 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
265 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
266 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
267 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
268 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
269 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
270 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
271 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
272 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
273 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n
274 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
275 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
276 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
277 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
278 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
279 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
280 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
281 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
282 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
283 * @param Periphs This parameter can be a combination of the following values:
284 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
285 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
286 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
287 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
288 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
289 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
290 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
291 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
292 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
293 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
294 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
295 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
296 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
297 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
298 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
299 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
300 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
301 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
302 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
303 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
304 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
305 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
306 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
307 *
308 * (*) value not defined in all devices.
309 * @retval None
310 */
311 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
312 {
313 __IO uint32_t tmpreg;
314 SET_BIT(RCC->AHB1ENR, Periphs);
315 /* Delay after an RCC peripheral clock enabling */
316 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
317 (void)tmpreg;
318 }
319
320 /**
321 * @brief Check if AHB1 peripheral clock is enabled or not
322 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
323 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
324 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
325 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
326 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
327 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
328 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
329 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
330 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
331 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
332 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
333 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
334 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
335 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n
336 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
337 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
338 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
339 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
340 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
341 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
342 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
343 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
344 * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock
345 * @param Periphs This parameter can be a combination of the following values:
346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
347 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
348 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
349 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
350 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
351 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
352 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
353 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
354 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
355 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
356 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
357 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
358 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
359 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
360 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
361 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
362 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
363 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
364 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
365 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
366 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
367 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
368 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
369 *
370 * (*) value not defined in all devices.
371 * @retval State of Periphs (1 or 0).
372 */
373 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
374 {
375 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
376 }
377
378 /**
379 * @brief Disable AHB1 peripherals clock.
380 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
381 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
382 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
383 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
384 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
385 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
386 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
387 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
388 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
389 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
390 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
391 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
392 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
393 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n
394 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
395 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
396 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
397 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
398 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
399 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
400 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
401 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
402 * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock
403 * @param Periphs This parameter can be a combination of the following values:
404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
412 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
413 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
414 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
415 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
416 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
417 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
418 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
420 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
421 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
422 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
423 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
424 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
425 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
426 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
427 *
428 * (*) value not defined in all devices.
429 * @retval None
430 */
431 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
432 {
433 CLEAR_BIT(RCC->AHB1ENR, Periphs);
434 }
435
436 /**
437 * @brief Force AHB1 peripherals reset.
438 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
439 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
440 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
441 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
442 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
443 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
444 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
445 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
446 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
447 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
448 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
449 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
450 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
451 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
452 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
453 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
454 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
455 * @param Periphs This parameter can be a combination of the following values:
456 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
457 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
458 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
459 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
460 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
461 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
462 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
463 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
464 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
465 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
466 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
468 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
469 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
470 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
471 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
472 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
473 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
474 *
475 * (*) value not defined in all devices.
476 * @retval None
477 */
478 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
479 {
480 SET_BIT(RCC->AHB1RSTR, Periphs);
481 }
482
483 /**
484 * @brief Release AHB1 peripherals reset.
485 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
486 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
487 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
488 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
489 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
490 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
491 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
492 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
493 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
494 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
495 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
496 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
497 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
498 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
499 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
500 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
501 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
502 * @param Periphs This parameter can be a combination of the following values:
503 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
504 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
505 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
506 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
507 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
508 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
509 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
510 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
511 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
512 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
513 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
514 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
515 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
516 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
517 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
518 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
519 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
520 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
521 *
522 * (*) value not defined in all devices.
523 * @retval None
524 */
525 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
526 {
527 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
528 }
529
530 /**
531 * @brief Enable AHB1 peripheral clocks in low-power mode
532 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
533 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
534 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
535 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
536 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
537 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
538 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
539 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
540 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
541 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
542 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
543 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
544 * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n
545 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
546 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
547 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
548 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
549 * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
550 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
551 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
552 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
553 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
554 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
555 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
556 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
557 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
558 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
559 * @param Periphs This parameter can be a combination of the following values:
560 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
561 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
562 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
563 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
564 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
565 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
566 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
567 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
568 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
569 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
570 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
571 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
572 * @arg @ref LL_AHB1_GRP1_PERIPH_AXI
573 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
574 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
575 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
576 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
577 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
578 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
579 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
580 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
581 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
582 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
583 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
584 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
585 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
586 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
587 *
588 * (*) value not defined in all devices.
589 * @retval None
590 */
591 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
592 {
593 __IO uint32_t tmpreg;
594 SET_BIT(RCC->AHB1LPENR, Periphs);
595 /* Delay after an RCC peripheral clock enabling */
596 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
597 (void)tmpreg;
598 }
599
600 /**
601 * @brief Disable AHB1 peripheral clocks in low-power mode
602 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
603 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
604 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
605 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
606 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
607 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
608 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
609 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
610 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
611 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
612 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
613 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
614 * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n
615 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
616 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
617 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
618 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
619 * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
620 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
621 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
622 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
623 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
624 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
625 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
626 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
627 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
628 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
629 * @param Periphs This parameter can be a combination of the following values:
630 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
631 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
632 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
633 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
634 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
635 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
636 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
637 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
638 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
639 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
640 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
641 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
642 * @arg @ref LL_AHB1_GRP1_PERIPH_AXI
643 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
644 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
645 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
646 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
647 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
648 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
649 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
650 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
651 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
652 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
653 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
654 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
655 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
656 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
657 *
658 * (*) value not defined in all devices.
659 * @retval None
660 */
661 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
662 {
663 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
664 }
665
666 /**
667 * @}
668 */
669
670 /** @defgroup BUS_LL_EF_AHB2 AHB2
671 * @{
672 */
673
674 /**
675 * @brief Enable AHB2 peripherals clock.
676 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
677 * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n
678 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
679 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
680 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
681 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
682 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
683 * @param Periphs This parameter can be a combination of the following values:
684 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
685 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
686 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
687 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
688 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
689 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
690 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
691 *
692 * (*) value not defined in all devices.
693 * @retval None
694 */
695 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
696 {
697 __IO uint32_t tmpreg;
698 SET_BIT(RCC->AHB2ENR, Periphs);
699 /* Delay after an RCC peripheral clock enabling */
700 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
701 (void)tmpreg;
702 }
703
704 /**
705 * @brief Check if AHB2 peripheral clock is enabled or not
706 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
707 * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n
708 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
709 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
710 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
711 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
712 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
713 * @param Periphs This parameter can be a combination of the following values:
714 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
715 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
716 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
717 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
718 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
719 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
720 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
721 *
722 * (*) value not defined in all devices.
723 * @retval State of Periphs (1 or 0).
724 */
725 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
726 {
727 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
728 }
729
730 /**
731 * @brief Disable AHB2 peripherals clock.
732 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
733 * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n
734 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
735 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
736 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
737 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
738 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
739 * @param Periphs This parameter can be a combination of the following values:
740 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
741 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
742 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
743 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
744 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
745 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
746 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
747 *
748 * (*) value not defined in all devices.
749 * @retval None
750 */
751 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
752 {
753 CLEAR_BIT(RCC->AHB2ENR, Periphs);
754 }
755
756 /**
757 * @brief Force AHB2 peripherals reset.
758 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
759 * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n
760 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
761 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
762 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
763 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
764 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
765 * @param Periphs This parameter can be a combination of the following values:
766 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
767 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
768 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
769 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
770 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
771 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
772 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
773 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
774 *
775 * (*) value not defined in all devices.
776 * @retval None
777 */
778 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
779 {
780 SET_BIT(RCC->AHB2RSTR, Periphs);
781 }
782
783 /**
784 * @brief Release AHB2 peripherals reset.
785 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
786 * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n
787 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
788 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
789 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
790 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
791 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
792 * @param Periphs This parameter can be a combination of the following values:
793 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
794 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
795 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
796 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
797 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
798 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
799 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
800 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
801 *
802 * (*) value not defined in all devices.
803 * @retval None
804 */
805 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
806 {
807 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
808 }
809
810 /**
811 * @brief Enable AHB2 peripheral clocks in low-power mode
812 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
813 * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
814 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
815 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
816 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
817 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
818 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
819 * @param Periphs This parameter can be a combination of the following values:
820 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
821 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
822 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
823 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
824 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
825 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
826 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
827 *
828 * (*) value not defined in all devices.
829 * @retval None
830 */
831 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
832 {
833 __IO uint32_t tmpreg;
834 SET_BIT(RCC->AHB2LPENR, Periphs);
835 /* Delay after an RCC peripheral clock enabling */
836 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
837 (void)tmpreg;
838 }
839
840 /**
841 * @brief Disable AHB2 peripheral clocks in low-power mode
842 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
843 * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
844 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
845 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
846 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
847 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
848 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
849 * @param Periphs This parameter can be a combination of the following values:
850 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
851 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
852 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
853 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
854 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
855 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
856 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
857 *
858 * (*) value not defined in all devices.
859 * @retval None
860 */
861 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
862 {
863 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
864 }
865
866 /**
867 * @}
868 */
869
870 /** @defgroup BUS_LL_EF_AHB3 AHB3
871 * @{
872 */
873
874 /**
875 * @brief Enable AHB3 peripherals clock.
876 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
877 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
878 * @param Periphs This parameter can be a combination of the following values:
879 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
880 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
881 *
882 * (*) value not defined in all devices.
883 * @retval None
884 */
885 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
886 {
887 __IO uint32_t tmpreg;
888 SET_BIT(RCC->AHB3ENR, Periphs);
889 /* Delay after an RCC peripheral clock enabling */
890 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
891 (void)tmpreg;
892 }
893
894 /**
895 * @brief Check if AHB3 peripheral clock is enabled or not
896 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
897 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
898 * @param Periphs This parameter can be a combination of the following values:
899 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
900 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
901 *
902 * (*) value not defined in all devices.
903 * @retval State of Periphs (1 or 0).
904 */
905 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
906 {
907 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
908 }
909
910 /**
911 * @brief Disable AHB3 peripherals clock.
912 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
913 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
914 * @param Periphs This parameter can be a combination of the following values:
915 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
916 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
917 *
918 * (*) value not defined in all devices.
919 * @retval None
920 */
921 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
922 {
923 CLEAR_BIT(RCC->AHB3ENR, Periphs);
924 }
925
926 /**
927 * @brief Force AHB3 peripherals reset.
928 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
929 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
930 * @param Periphs This parameter can be a combination of the following values:
931 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
932 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
933 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
934 *
935 * (*) value not defined in all devices.
936 * @retval None
937 */
938 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
939 {
940 SET_BIT(RCC->AHB3RSTR, Periphs);
941 }
942
943 /**
944 * @brief Release AHB3 peripherals reset.
945 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
946 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
947 * @param Periphs This parameter can be a combination of the following values:
948 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
949 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
950 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
951 *
952 * (*) value not defined in all devices.
953 * @retval None
954 */
955 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
956 {
957 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
958 }
959
960 /**
961 * @brief Enable AHB3 peripheral clocks in low-power mode
962 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
963 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
964 * @param Periphs This parameter can be a combination of the following values:
965 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
966 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
967 *
968 * (*) value not defined in all devices.
969 * @retval None
970 */
971 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
972 {
973 __IO uint32_t tmpreg;
974 SET_BIT(RCC->AHB3LPENR, Periphs);
975 /* Delay after an RCC peripheral clock enabling */
976 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
977 (void)tmpreg;
978 }
979
980 /**
981 * @brief Disable AHB3 peripheral clocks in low-power mode
982 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
983 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
984 * @param Periphs This parameter can be a combination of the following values:
985 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
986 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
987 *
988 * (*) value not defined in all devices.
989 * @retval None
990 */
991 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
992 {
993 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
994 }
995
996 /**
997 * @}
998 */
999
1000 /** @defgroup BUS_LL_EF_APB1 APB1
1001 * @{
1002 */
1003
1004 /**
1005 * @brief Enable APB1 peripherals clock.
1006 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1007 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1008 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1009 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1010 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1011 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1012 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1013 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1014 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1015 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1016 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1017 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1018 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1019 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1020 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1021 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1022 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1023 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1024 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1025 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1026 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1027 * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n
1028 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1029 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1030 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1031 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1032 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1033 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1034 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1035 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1036 * APB1ENR RTCEN LL_APB1_GRP1_EnableClock
1037 * @param Periphs This parameter can be a combination of the following values:
1038 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1039 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1040 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1041 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1042 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1043 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1044 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1045 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1046 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1047 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1048 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1049 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1050 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1051 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1052 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1053 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1054 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1055 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1056 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1057 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1058 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1059 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1060 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1061 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1062 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1063 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1064 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1065 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1066 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1067 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1068 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1069 *
1070 * (*) value not defined in all devices.
1071 * @retval None
1072 */
1073 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1074 {
1075 __IO uint32_t tmpreg;
1076 SET_BIT(RCC->APB1ENR, Periphs);
1077 /* Delay after an RCC peripheral clock enabling */
1078 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1079 (void)tmpreg;
1080 }
1081
1082 /**
1083 * @brief Check if APB1 peripheral clock is enabled or not
1084 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1085 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1086 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1087 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1088 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1089 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1090 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1091 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1092 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1093 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1094 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1095 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1096 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1097 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1098 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1099 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1100 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1101 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1102 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1103 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1104 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1105 * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n
1106 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1107 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1108 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1109 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1110 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1111 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1112 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1113 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1114 * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock
1115 * @param Periphs This parameter can be a combination of the following values:
1116 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1117 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1118 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1119 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1120 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1121 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1122 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1123 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1124 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1125 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1126 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1127 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1128 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1129 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1130 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1131 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1132 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1133 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1134 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1135 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1136 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1137 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1138 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1139 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1140 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1141 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1142 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1143 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1144 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1145 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1146 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1147 *
1148 * (*) value not defined in all devices.
1149 * @retval State of Periphs (1 or 0).
1150 */
1151 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1152 {
1153 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1154 }
1155
1156 /**
1157 * @brief Disable APB1 peripherals clock.
1158 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1159 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1160 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1161 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1162 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1163 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1164 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1165 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1166 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1167 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1168 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1169 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1170 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1171 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1172 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1173 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1174 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1175 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1176 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1177 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1178 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1179 * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n
1180 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1181 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1182 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1183 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1184 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1185 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1186 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1187 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1188 * APB1ENR RTCEN LL_APB1_GRP1_DisableClock
1189 * @param Periphs This parameter can be a combination of the following values:
1190 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1191 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1192 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1193 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1194 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1195 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1196 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1197 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1198 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1199 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1200 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1201 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1202 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1203 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1204 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1205 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1206 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1207 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1208 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1209 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1210 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1211 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1212 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1213 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1214 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1215 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1216 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1217 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1218 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1219 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1220 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1221 *
1222 * (*) value not defined in all devices.
1223 * @retval None
1224 */
1225 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1226 {
1227 CLEAR_BIT(RCC->APB1ENR, Periphs);
1228 }
1229
1230 /**
1231 * @brief Force APB1 peripherals reset.
1232 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1233 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1234 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1235 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1236 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1237 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1238 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1239 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1240 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1241 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1242 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1243 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1244 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1245 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1246 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1247 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1248 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1249 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1250 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1251 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1252 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1253 * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n
1254 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1255 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1256 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1257 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1258 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1259 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1260 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1261 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1262 * @param Periphs This parameter can be a combination of the following values:
1263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1265 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1266 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1267 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1268 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1269 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1270 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1271 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1272 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1273 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1274 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1275 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1276 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1277 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1278 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1279 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1280 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1281 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1282 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1283 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1284 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1285 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1286 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1287 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1288 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1289 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1290 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1291 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1292 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1293 *
1294 * (*) value not defined in all devices.
1295 * @retval None
1296 */
1297 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1298 {
1299 SET_BIT(RCC->APB1RSTR, Periphs);
1300 }
1301
1302 /**
1303 * @brief Release APB1 peripherals reset.
1304 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1305 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1306 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1307 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1308 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1309 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1310 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1311 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1312 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1313 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1314 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1315 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1316 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1317 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1318 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1319 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1320 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1321 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1322 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1323 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1324 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1325 * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n
1326 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1327 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1328 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1329 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1330 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1331 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1332 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1333 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1334 * @param Periphs This parameter can be a combination of the following values:
1335 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1336 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1337 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1338 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1339 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1340 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1342 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1343 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1344 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1345 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1346 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1347 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1348 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1349 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1350 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1351 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1352 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1353 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1354 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1355 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1356 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1357 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1358 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1359 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1360 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1361 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1362 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1363 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1364 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1365 *
1366 * (*) value not defined in all devices.
1367 * @retval None
1368 */
1369 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1370 {
1371 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1372 }
1373
1374 /**
1375 * @brief Enable APB1 peripheral clocks in low-power mode
1376 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1377 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1378 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1379 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1380 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1381 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1382 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1383 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1384 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1385 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1386 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1387 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1388 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1389 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1390 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1391 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1392 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1393 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1394 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1395 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1396 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1397 * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1398 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1399 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1400 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1401 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1402 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1403 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1404 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1405 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1406 * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower
1407 * @param Periphs This parameter can be a combination of the following values:
1408 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1409 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1410 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1411 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1412 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1413 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1414 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1415 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1416 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1417 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1418 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1419 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1420 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1421 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1422 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1423 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1424 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1425 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1426 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1427 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1428 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1429 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1430 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1431 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1432 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1433 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1434 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1435 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1436 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1437 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1438 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1439 *
1440 * (*) value not defined in all devices.
1441 * @retval None
1442 */
1443 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1444 {
1445 __IO uint32_t tmpreg;
1446 SET_BIT(RCC->APB1LPENR, Periphs);
1447 /* Delay after an RCC peripheral clock enabling */
1448 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1449 (void)tmpreg;
1450 }
1451
1452 /**
1453 * @brief Disable APB1 peripheral clocks in low-power mode
1454 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1455 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1456 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1457 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1458 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1459 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1460 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1461 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1462 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1463 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1464 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1465 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1466 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1467 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1468 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1469 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1470 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1471 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1472 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1473 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1474 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1475 * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1476 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1477 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1478 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1479 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1480 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1481 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1482 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1483 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1484 * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower
1485 * @param Periphs This parameter can be a combination of the following values:
1486 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1487 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1488 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1489 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1490 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1491 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1492 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1493 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1494 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1495 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1496 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1497 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1498 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1499 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1500 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1501 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1502 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1503 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1504 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1505 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1506 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1507 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1508 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1509 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1510 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1511 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1512 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1513 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1514 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1515 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1516 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1517 *
1518 * (*) value not defined in all devices.
1519 * @retval None
1520 */
1521 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1522 {
1523 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1524 }
1525
1526 /**
1527 * @}
1528 */
1529
1530 /** @defgroup BUS_LL_EF_APB2 APB2
1531 * @{
1532 */
1533
1534 /**
1535 * @brief Enable APB2 peripherals clock.
1536 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1537 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1538 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1539 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1540 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1541 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1542 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1543 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
1544 * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n
1545 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1546 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1547 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1548 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1549 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1550 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1551 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1552 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1553 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1554 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1555 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1556 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1557 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1558 * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n
1559 * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock
1560 * @param Periphs This parameter can be a combination of the following values:
1561 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1562 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1563 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1564 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1565 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1566 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1567 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1568 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1569 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1570 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1571 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1572 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1573 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1574 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1575 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1576 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1577 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1578 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1579 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1580 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1581 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1582 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1583 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1584 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1585 *
1586 * (*) value not defined in all devices.
1587 * @retval None
1588 */
1589 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1590 {
1591 __IO uint32_t tmpreg;
1592 SET_BIT(RCC->APB2ENR, Periphs);
1593 /* Delay after an RCC peripheral clock enabling */
1594 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1595 (void)tmpreg;
1596 }
1597
1598 /**
1599 * @brief Check if APB2 peripheral clock is enabled or not
1600 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1601 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1602 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1603 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1604 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1605 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1606 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1607 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
1608 * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n
1609 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1610 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1611 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1612 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1613 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1614 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1615 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1616 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1617 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1618 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1619 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1620 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1621 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1622 * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n
1623 * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock
1624 * @param Periphs This parameter can be a combination of the following values:
1625 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1626 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1627 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1628 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1629 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1630 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1631 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1632 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1633 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1634 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1635 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1636 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1637 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1638 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1639 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1640 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1641 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1642 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1643 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1644 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1645 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1646 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1647 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1648 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1649 *
1650 * (*) value not defined in all devices.
1651 * @retval State of Periphs (1 or 0).
1652 */
1653 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1654 {
1655 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1656 }
1657
1658 /**
1659 * @brief Disable APB2 peripherals clock.
1660 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1661 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1662 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1663 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1664 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1665 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1666 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1667 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
1668 * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n
1669 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1670 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1671 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1672 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1673 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1674 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1675 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1676 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1677 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1678 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1679 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1680 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1681 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1682 * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n
1683 * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock
1684 * @param Periphs This parameter can be a combination of the following values:
1685 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1686 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1687 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1688 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1689 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1690 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1691 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1692 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1693 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1694 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1695 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1696 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1697 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1698 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1699 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1700 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1701 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1702 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1703 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1704 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1705 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1706 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1707 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1708 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1709 *
1710 * (*) value not defined in all devices.
1711 * @retval None
1712 */
1713 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1714 {
1715 CLEAR_BIT(RCC->APB2ENR, Periphs);
1716 }
1717
1718 /**
1719 * @brief Force APB2 peripherals reset.
1720 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1721 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1722 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1723 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1724 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1725 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
1726 * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n
1727 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1728 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1729 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1730 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1731 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1732 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1733 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1734 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1735 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1736 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1737 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1738 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1739 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1740 * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n
1741 * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset
1742 * @param Periphs This parameter can be a combination of the following values:
1743 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1744 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1746 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1747 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1748 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1749 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1750 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1751 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1752 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1753 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1754 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1755 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1756 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1757 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1758 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1759 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1760 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1761 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1762 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1763 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1764 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1765 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1766 *
1767 * (*) value not defined in all devices.
1768 * @retval None
1769 */
1770 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1771 {
1772 SET_BIT(RCC->APB2RSTR, Periphs);
1773 }
1774
1775 /**
1776 * @brief Release APB2 peripherals reset.
1777 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1778 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1779 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1780 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1781 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1782 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
1783 * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n
1784 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1785 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1786 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1787 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1788 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1789 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1790 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1791 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1792 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1793 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1794 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1795 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1796 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1797 * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n
1798 * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset
1799 * @param Periphs This parameter can be a combination of the following values:
1800 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1801 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1802 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1803 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1804 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1805 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1806 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1807 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1808 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1809 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1810 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1811 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1812 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1813 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1814 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1815 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1816 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1817 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1818 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1819 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1820 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1821 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1822 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1823 *
1824 * (*) value not defined in all devices.
1825 * @retval None
1826 */
1827 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1828 {
1829 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1830 }
1831
1832 /**
1833 * @brief Enable APB2 peripheral clocks in low-power mode
1834 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1835 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1836 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1837 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1838 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1839 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1840 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1841 * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1842 * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1843 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1844 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1845 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1846 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1847 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1848 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1849 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1850 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1851 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1852 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1853 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1854 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1855 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1856 * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower
1857 * @param Periphs This parameter can be a combination of the following values:
1858 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1859 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1860 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1861 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1862 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1863 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1864 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1865 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1866 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1867 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1868 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1869 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1870 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1871 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1872 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1873 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1874 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1875 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1876 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1877 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1878 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1879 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1880 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1881 *
1882 * (*) value not defined in all devices.
1883 * @retval None
1884 */
1885 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
1886 {
1887 __IO uint32_t tmpreg;
1888 SET_BIT(RCC->APB2LPENR, Periphs);
1889 /* Delay after an RCC peripheral clock enabling */
1890 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
1891 (void)tmpreg;
1892 }
1893
1894 /**
1895 * @brief Disable APB2 peripheral clocks in low-power mode
1896 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1897 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
1898 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1899 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1900 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1901 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1902 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
1903 * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1904 * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1905 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1906 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
1907 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
1908 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
1909 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
1910 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
1911 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
1912 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1913 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1914 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1915 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
1916 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
1917 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1918 * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower
1919 * @param Periphs This parameter can be a combination of the following values:
1920 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1921 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1922 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1923 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1924 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1925 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1926 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1927 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1928 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1929 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1930 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1931 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1933 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1935 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1936 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1937 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1938 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1939 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1940 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1941 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1942 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1943 *
1944 * (*) value not defined in all devices.
1945 * @retval None
1946 */
1947 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
1948 {
1949 CLEAR_BIT(RCC->APB2LPENR, Periphs);
1950 }
1951
1952 /**
1953 * @}
1954 */
1955
1956 /**
1957 * @}
1958 */
1959
1960 /**
1961 * @}
1962 */
1963
1964 #endif /* defined(RCC) */
1965
1966 /**
1967 * @}
1968 */
1969
1970 #ifdef __cplusplus
1971 }
1972 #endif
1973
1974 #endif /* __STM32F7xx_LL_BUS_H */
1975
1976 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/