lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_ll_spi.c
   4   * @author  MCD Application Team
   5   * @brief   SPI LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32f7xx_ll_spi.h"
  23 #include "stm32f7xx_ll_bus.h"
  24 #include "stm32f7xx_ll_rcc.h"
  25
  26 #ifdef  USE_FULL_ASSERT
  27 #include "stm32_assert.h"
  28 #else
  29 #define assert_param(expr) ((void)0U)
  30 #endif
  31
  32 /** @addtogroup STM32F7xx_LL_Driver
  33   * @{
  34   */
  35
  36 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
  37
  38 /** @addtogroup SPI_LL
  39   * @{
  40   */
  41
  42 /* Private types -------------------------------------------------------------*/
  43 /* Private variables ---------------------------------------------------------*/
  44
  45 /* Private constants ---------------------------------------------------------*/
  46 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
  47   * @{
  48   */
  49 /* SPI registers Masks */
  50 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
  51                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
  52                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
  53                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
  54                                             SPI_CR1_BIDIMODE)
  55 /**
  56   * @}
  57   */
  58
  59 /* Private macros ------------------------------------------------------------*/
  60 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
  61   * @{
  62   */
  63 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
  64                                               || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
  65                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
  66                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
  67
  68 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
  69                                 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
  70
  71 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
  72                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
  73                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
  74                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
  75                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
  76                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
  77                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
  78                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
  79                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
  80                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
  81                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
  82                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
  83                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
  84
  85 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
  86                                     || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
  87
  88 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
  89                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
  90
  91 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
  92                                || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
  93                                || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
  94
  95 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
  96                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
  97                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
  98                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
  99                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
 100                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
 101                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
 102                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
 103
 104 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
 105                                     || ((__VALUE__) == LL_SPI_MSB_FIRST))
 106
 107 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
 108                                           || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
 109
 110 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
 111
 112 /**
 113   * @}
 114   */
 115
 116 /* Private function prototypes -----------------------------------------------*/
 117
 118 /* Exported functions --------------------------------------------------------*/
 119 /** @addtogroup SPI_LL_Exported_Functions
 120   * @{
 121   */
 122
 123 /** @addtogroup SPI_LL_EF_Init
 124   * @{
 125   */
 126
 127 /**
 128   * @brief  De-initialize the SPI registers to their default reset values.
 129   * @param  SPIx SPI Instance
 130   * @retval An ErrorStatus enumeration value:
 131   *          - SUCCESS: SPI registers are de-initialized
 132   *          - ERROR: SPI registers are not de-initialized
 133   */
 134 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
 135 {
 136   ErrorStatus status = ERROR;
 137
 138   /* Check the parameters */
 139   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 140
 141 #if defined(SPI1)
 142   if (SPIx == SPI1)
 143   {
 144     /* Force reset of SPI clock */
 145     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
 146
 147     /* Release reset of SPI clock */
 148     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
 149
 150     status = SUCCESS;
 151   }
 152 #endif /* SPI1 */
 153 #if defined(SPI2)
 154   if (SPIx == SPI2)
 155   {
 156     /* Force reset of SPI clock */
 157     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
 158
 159     /* Release reset of SPI clock */
 160     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
 161
 162     status = SUCCESS;
 163   }
 164 #endif /* SPI2 */
 165 #if defined(SPI3)
 166   if (SPIx == SPI3)
 167   {
 168     /* Force reset of SPI clock */
 169     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
 170
 171     /* Release reset of SPI clock */
 172     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
 173
 174     status = SUCCESS;
 175   }
 176 #endif /* SPI3 */
 177 #if defined(SPI4)
 178   if (SPIx == SPI4)
 179   {
 180     /* Force reset of SPI clock */
 181     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
 182
 183     /* Release reset of SPI clock */
 184     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
 185
 186     status = SUCCESS;
 187   }
 188 #endif /* SPI4 */
 189 #if defined(SPI5)
 190   if (SPIx == SPI5)
 191   {
 192     /* Force reset of SPI clock */
 193     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
 194
 195     /* Release reset of SPI clock */
 196     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
 197
 198     status = SUCCESS;
 199   }
 200 #endif /* SPI5 */
 201 #if defined(SPI6)
 202   if (SPIx == SPI6)
 203   {
 204     /* Force reset of SPI clock */
 205     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
 206
 207     /* Release reset of SPI clock */
 208     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
 209
 210     status = SUCCESS;
 211   }
 212 #endif /* SPI6 */
 213
 214   return status;
 215 }
 216
 217 /**
 218   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
 219   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 220   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 221   * @param  SPIx SPI Instance
 222   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 223   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
 224   */
 225 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
 226 {
 227   ErrorStatus status = ERROR;
 228
 229   /* Check the SPI Instance SPIx*/
 230   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 231
 232   /* Check the SPI parameters from SPI_InitStruct*/
 233   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
 234   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
 235   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
 236   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
 237   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
 238   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
 239   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
 240   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
 241   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
 242
 243   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
 244   {
 245     /*---------------------------- SPIx CR1 Configuration ------------------------
 246      * Configure SPIx CR1 with parameters:
 247      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
 248      * - Master/Slave Mode:  SPI_CR1_MSTR bit
 249      * - ClockPolarity:      SPI_CR1_CPOL bit
 250      * - ClockPhase:         SPI_CR1_CPHA bit
 251      * - NSS management:     SPI_CR1_SSM bit
 252      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
 253      * - BitOrder:           SPI_CR1_LSBFIRST bit
 254      * - CRCCalculation:     SPI_CR1_CRCEN bit
 255      */
 256     MODIFY_REG(SPIx->CR1,
 257                SPI_CR1_CLEAR_MASK,
 258                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
 259                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
 260                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
 261                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
 262
 263     /*---------------------------- SPIx CR2 Configuration ------------------------
 264      * Configure SPIx CR2 with parameters:
 265      * - DataWidth:          DS[3:0] bits
 266      * - NSS management:     SSOE bit
 267      */
 268     MODIFY_REG(SPIx->CR2,
 269                SPI_CR2_DS | SPI_CR2_SSOE,
 270                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
 271
 272     /*---------------------------- SPIx CRCPR Configuration ----------------------
 273      * Configure SPIx CRCPR with parameters:
 274      * - CRCPoly:            CRCPOLY[15:0] bits
 275      */
 276     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
 277     {
 278       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
 279       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
 280     }
 281     status = SUCCESS;
 282   }
 283
 284   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
 285   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 286   return status;
 287 }
 288
 289 /**
 290   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
 291   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 292   * whose fields will be set to default values.
 293   * @retval None
 294   */
 295 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
 296 {
 297   /* Set SPI_InitStruct fields to default values */
 298   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
 299   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
 300   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
 301   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
 302   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
 303   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
 304   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
 305   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
 306   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
 307   SPI_InitStruct->CRCPoly           = 7U;
 308 }
 309
 310 /**
 311   * @}
 312   */
 313
 314 /**
 315   * @}
 316   */
 317
 318 /**
 319   * @}
 320   */
 321
 322 /** @addtogroup I2S_LL
 323   * @{
 324   */
 325
 326 /* Private types -------------------------------------------------------------*/
 327 /* Private variables ---------------------------------------------------------*/
 328 /* Private constants ---------------------------------------------------------*/
 329 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
 330   * @{
 331   */
 332 /* I2S registers Masks */
 333 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
 334                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
 335                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
 336
 337 #define I2S_I2SPR_CLEAR_MASK               0x0002U
 338 /**
 339   * @}
 340   */
 341 /* Private macros ------------------------------------------------------------*/
 342 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
 343   * @{
 344   */
 345
 346 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
 347                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
 348                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
 349                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
 350
 351 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
 352                                        || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
 353
 354 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
 355                                        || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
 356                                        || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
 357                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
 358                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
 359
 360 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
 361                                        || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
 362                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
 363                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
 364
 365 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
 366                                        || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
 367
 368 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
 369                                        && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
 370                                        || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
 371
 372 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
 373
 374 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
 375                                            || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
 376 /**
 377   * @}
 378   */
 379
 380 /* Private function prototypes -----------------------------------------------*/
 381
 382 /* Exported functions --------------------------------------------------------*/
 383 /** @addtogroup I2S_LL_Exported_Functions
 384   * @{
 385   */
 386
 387 /** @addtogroup I2S_LL_EF_Init
 388   * @{
 389   */
 390
 391 /**
 392   * @brief  De-initialize the SPI/I2S registers to their default reset values.
 393   * @param  SPIx SPI Instance
 394   * @retval An ErrorStatus enumeration value:
 395   *          - SUCCESS: SPI registers are de-initialized
 396   *          - ERROR: SPI registers are not de-initialized
 397   */
 398 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
 399 {
 400   return LL_SPI_DeInit(SPIx);
 401 }
 402
 403 /**
 404   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
 405   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 406   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 407   * @param  SPIx SPI Instance
 408   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 409   * @retval An ErrorStatus enumeration value:
 410   *          - SUCCESS: SPI registers are Initialized
 411   *          - ERROR: SPI registers are not Initialized
 412   */
 413 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
 414 {
 415   uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
 416   uint32_t tmp;
 417   uint32_t sourceclock;
 418   ErrorStatus status = ERROR;
 419
 420   /* Check the I2S parameters */
 421   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 422   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
 423   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
 424   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
 425   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
 426   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
 427   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
 428
 429   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
 430   {
 431     /*---------------------------- SPIx I2SCFGR Configuration --------------------
 432      * Configure SPIx I2SCFGR with parameters:
 433      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
 434      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
 435      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
 436      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
 437      */
 438
 439     /* Write to SPIx I2SCFGR */
 440     MODIFY_REG(SPIx->I2SCFGR,
 441                I2S_I2SCFGR_CLEAR_MASK,
 442                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
 443                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
 444                SPI_I2SCFGR_I2SMOD);
 445
 446     /*---------------------------- SPIx I2SPR Configuration ----------------------
 447      * Configure SPIx I2SPR with parameters:
 448      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
 449      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
 450      */
 451
 452     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
 453      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
 454      */
 455     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
 456     {
 457       /* Check the frame length (For the Prescaler computing)
 458        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
 459        */
 460       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
 461       {
 462         /* Packet length is 32 bits */
 463         packetlength = 2U;
 464       }
 465
 466       /* If an external I2S clock has to be used, the specific define should be set
 467       in the project configuration or in the stm32f7xx_ll_rcc.h file */
 468       /* Get the I2S source clock value */
 469       sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
 470
 471       /* Compute the Real divider depending on the MCLK output state with a floating point */
 472       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
 473       {
 474         /* MCLK output is enabled */
 475         tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 476       }
 477       else
 478       {
 479         /* MCLK output is disabled */
 480         tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 481       }
 482
 483       /* Remove the floating point */
 484       tmp = tmp / 10U;
 485
 486       /* Check the parity of the divider */
 487       i2sodd = (tmp & (uint16_t)0x0001U);
 488
 489       /* Compute the i2sdiv prescaler */
 490       i2sdiv = ((tmp - i2sodd) / 2U);
 491
 492       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 493       i2sodd = (i2sodd << 8U);
 494     }
 495
 496     /* Test if the divider is 1 or 0 or greater than 0xFF */
 497     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
 498     {
 499       /* Set the default values */
 500       i2sdiv = 2U;
 501       i2sodd = 0U;
 502     }
 503
 504     /* Write to SPIx I2SPR register the computed value */
 505     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
 506
 507     status = SUCCESS;
 508   }
 509   return status;
 510 }
 511
 512 /**
 513   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
 514   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 515   *         whose fields will be set to default values.
 516   * @retval None
 517   */
 518 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
 519 {
 520   /*--------------- Reset I2S init structure parameters values -----------------*/
 521   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
 522   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
 523   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
 524   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
 525   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
 526   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
 527 }
 528
 529 /**
 530   * @brief  Set linear and parity prescaler.
 531   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
 532   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
 533   * @param  SPIx SPI Instance
 534   * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
 535   * @param  PrescalerParity This parameter can be one of the following values:
 536   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
 537   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
 538   * @retval None
 539   */
 540 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
 541 {
 542   /* Check the I2S parameters */
 543   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 544   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
 545   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
 546
 547   /* Write to SPIx I2SPR */
 548   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
 549 }
 550
 551 /**
 552   * @}
 553   */
 554
 555 /**
 556   * @}
 557   */
 558
 559 /**
 560   * @}
 561   */
 562
 563 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
 564
 565 /**
 566   * @}
 567   */
 568
 569 #endif /* USE_FULL_LL_DRIVER */
 570
 571 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/