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Moved IO_GPIOPortIdx to platform (#14127)
[betaflight.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_usb.c
blob5353f9afffdd417a21d1f32282dec24aeefc84f6
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_usb.c
4 * @author MCD Application Team
5 * @brief USB Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the USB Peripheral Controller:
9 * + Initialization/de-initialization functions
10 * + I/O operation functions
11 * + Peripheral Control functions
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
20
21 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
22
23 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
24
25 @endverbatim
26 ******************************************************************************
27 * @attention
28 *
29 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
30 * All rights reserved.</center></h2>
31 *
32 * This software component is licensed by ST under BSD 3-Clause license,
33 * the "License"; You may not use this file except in compliance with the
34 * License. You may obtain a copy of the License at:
35 * opensource.org/licenses/BSD-3-Clause
36 *
37 ******************************************************************************
38 */
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f7xx_hal.h"
42
43 /** @addtogroup STM32F7xx_LL_USB_DRIVER
44 * @{
45 */
46
47 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
48 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
49 /* Private typedef -----------------------------------------------------------*/
50 /* Private define ------------------------------------------------------------*/
51 /* Private macro -------------------------------------------------------------*/
52
53 /** @defgroup USB_OTG_GRSTCTL_AHBIDL_TIMEOUT_MS AHB master idle timeout
54 * @{
55 */
56 #define USB_OTG_GRSTCTL_AHBIDL_TIMEOUT_MS ((uint32_t)50U)
57
58 /** @defgroup USB_OTG_GRSTCTL_CSRST_TIMEOUT_MS Core soft reset timeout
59 * @{
60 */
61 #define USB_OTG_GRSTCTL_CSRST_TIMEOUT_MS ((uint32_t)10U)
62
63 /** @defgroup USB_OTG_GRSTCTL_TXFFLSH_TIMEOUT_MS Tx FIFO flush timeout
64 * @{
65 */
66 #define USB_OTG_GRSTCTL_TXFFLSH_TIMEOUT_MS ((uint32_t)5U)
67
68 /** @defgroup USB_OTG_GRSTCTL_RXFFLSH_TIMEOUT_MS Rx FIFO flush timeout
69 * @{
70 */
71 #define USB_OTG_GRSTCTL_RXFFLSH_TIMEOUT_MS ((uint32_t)5U)
72
73 /* Private variables ---------------------------------------------------------*/
74 /* Private function prototypes -----------------------------------------------*/
75 /* Private functions ---------------------------------------------------------*/
76 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
77 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
78
79 #ifdef USB_HS_PHYC
80 static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx);
81 #endif
82
83 /* Exported functions --------------------------------------------------------*/
84 /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
85 * @{
86 */
87
88 /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
89 * @brief Initialization and Configuration functions
90 *
91 @verbatim
92 ===============================================================================
93 ##### Initialization/de-initialization functions #####
94 ===============================================================================
95
96 @endverbatim
97 * @{
98 */
99
100 /**
101 * @brief Initializes the USB Core
102 * @param USBx USB Instance
103 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
104 * the configuration information for the specified USBx peripheral.
105 * @retval HAL status
106 */
107 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
108 {
109 HAL_StatusTypeDef ret;
110
111 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
112 {
113 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
114
115 /* Init The ULPI Interface */
116 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
117
118 /* Select vbus source */
119 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
120 if (cfg.use_external_vbus == 1U)
121 {
122 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
123 }
124 /* Reset after a PHY select */
125 ret = USB_CoreReset(USBx);
126 }
127 #ifdef USB_HS_PHYC
128 else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
129 {
130 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
131
132 /* Init The UTMI Interface */
133 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
134
135 /* Select vbus source */
136 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
137
138 /* Select UTMI Interace */
139 USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
140 USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
141
142 /* Enables control of a High Speed USB PHY */
143 if (USB_HS_PHYCInit(USBx) != HAL_OK)
144 {
145 return HAL_ERROR;
146 }
147
148 if (cfg.use_external_vbus == 1U)
149 {
150 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
151 }
152 /* Reset after a PHY select */
153 ret = USB_CoreReset(USBx);
154 }
155 #endif
156 else /* FS interface (embedded Phy) */
157 {
158 /* Select FS Embedded PHY */
159 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
160
161 /* Reset after a PHY select and set Host mode */
162 ret = USB_CoreReset(USBx);
163
164 /* Activate the USB Transceiver */
165 USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
166 }
167
168 if (cfg.dma_enable == 1U)
169 {
170 USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
171 USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
172 }
173
174 return ret;
175 }
176
177
178 /**
179 * @brief Set the USB turnaround time
180 * @param USBx USB Instance
181 * @param hclk: AHB clock frequency
182 * @retval USB turnaround time In PHY Clocks number
183 */
184 HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
185 uint32_t hclk, uint8_t speed)
186 {
187 uint32_t UsbTrd;
188
189 /* The USBTRD is configured according to the tables below, depending on AHB frequency
190 used by application. In the low AHB frequency range it is used to stretch enough the USB response
191 time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
192 latency to the Data FIFO */
193 if (speed == USB_OTG_SPEED_FULL)
194 {
195 if ((hclk >= 14200000U) && (hclk < 15000000U))
196 {
197 /* hclk Clock Range between 14.2-15 MHz */
198 UsbTrd = 0xFU;
199 }
200 else if ((hclk >= 15000000U) && (hclk < 16000000U))
201 {
202 /* hclk Clock Range between 15-16 MHz */
203 UsbTrd = 0xEU;
204 }
205 else if ((hclk >= 16000000U) && (hclk < 17200000U))
206 {
207 /* hclk Clock Range between 16-17.2 MHz */
208 UsbTrd = 0xDU;
209 }
210 else if ((hclk >= 17200000U) && (hclk < 18500000U))
211 {
212 /* hclk Clock Range between 17.2-18.5 MHz */
213 UsbTrd = 0xCU;
214 }
215 else if ((hclk >= 18500000U) && (hclk < 20000000U))
216 {
217 /* hclk Clock Range between 18.5-20 MHz */
218 UsbTrd = 0xBU;
219 }
220 else if ((hclk >= 20000000U) && (hclk < 21800000U))
221 {
222 /* hclk Clock Range between 20-21.8 MHz */
223 UsbTrd = 0xAU;
224 }
225 else if ((hclk >= 21800000U) && (hclk < 24000000U))
226 {
227 /* hclk Clock Range between 21.8-24 MHz */
228 UsbTrd = 0x9U;
229 }
230 else if ((hclk >= 24000000U) && (hclk < 27700000U))
231 {
232 /* hclk Clock Range between 24-27.7 MHz */
233 UsbTrd = 0x8U;
234 }
235 else if ((hclk >= 27700000U) && (hclk < 32000000U))
236 {
237 /* hclk Clock Range between 27.7-32 MHz */
238 UsbTrd = 0x7U;
239 }
240 else /* if(hclk >= 32000000) */
241 {
242 /* hclk Clock Range between 32-200 MHz */
243 UsbTrd = 0x6U;
244 }
245 }
246 else if (speed == USB_OTG_SPEED_HIGH)
247 {
248 UsbTrd = USBD_HS_TRDT_VALUE;
249 }
250 else
251 {
252 UsbTrd = USBD_DEFAULT_TRDT_VALUE;
253 }
254
255 USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
256 USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
257
258 return HAL_OK;
259 }
260
261 /**
262 * @brief USB_EnableGlobalInt
263 * Enables the controller's Global Int in the AHB Config reg
264 * @param USBx Selected device
265 * @retval HAL status
266 */
267 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
268 {
269 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
270 return HAL_OK;
271 }
272
273 /**
274 * @brief USB_DisableGlobalInt
275 * Disable the controller's Global Int in the AHB Config reg
276 * @param USBx Selected device
277 * @retval HAL status
278 */
279 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
280 {
281 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
282 return HAL_OK;
283 }
284
285 /**
286 * @brief USB_SetCurrentMode : Set functional mode
287 * @param USBx Selected device
288 * @param mode current core mode
289 * This parameter can be one of these values:
290 * @arg USB_DEVICE_MODE: Peripheral mode
291 * @arg USB_HOST_MODE: Host mode
292 * @arg USB_DRD_MODE: Dual Role Device mode
293 * @retval HAL status
294 */
295 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
296 {
297 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
298
299 if (mode == USB_HOST_MODE)
300 {
301 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
302 }
303 else if (mode == USB_DEVICE_MODE)
304 {
305 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
306 }
307 else
308 {
309 return HAL_ERROR;
310 }
311 HAL_Delay(50U);
312
313 return HAL_OK;
314 }
315
316 /**
317 * @brief USB_DevInit : Initializes the USB_OTG controller registers
318 * for device mode
319 * @param USBx Selected device
320 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
321 * the configuration information for the specified USBx peripheral.
322 * @retval HAL status
323 */
324 HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
325 {
326 HAL_StatusTypeDef ret = HAL_OK;
327 uint32_t USBx_BASE = (uint32_t)USBx;
328 uint32_t i;
329
330 for (i = 0U; i < 15U; i++)
331 {
332 USBx->DIEPTXF[i] = 0U;
333 }
334
335 /* VBUS Sensing setup */
336 if (cfg.vbus_sensing_enable == 0U)
337 {
338 /* Deactivate VBUS Sensing B */
339 USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
340
341 /* B-peripheral session valid override enable */
342 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
343 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
344 }
345 else
346 {
347 /* Enable HW VBUS sensing */
348 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
349 }
350
351 /* Restart the Phy Clock */
352 USBx_PCGCCTL = 0U;
353
354 /* Device mode configuration */
355 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
356
357 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
358 {
359 if (cfg.speed == USB_OTG_SPEED_HIGH)
360 {
361 /* Set High speed phy */
362 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
363 }
364 else
365 {
366 /* set High speed phy in Full speed mode */
367 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
368 }
369 }
370 else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
371 {
372 if (cfg.speed == USB_OTG_SPEED_HIGH)
373 {
374 /* Set High speed phy */
375 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
376 }
377 else
378 {
379 /* set High speed phy in Full speed mode */
380 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
381 }
382 }
383 else
384 {
385 /* Set Full speed phy */
386 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
387 }
388
389 /* Flush the FIFOs */
390 if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
391 {
392 ret = HAL_ERROR;
393 }
394
395 if (USB_FlushRxFifo(USBx) != HAL_OK)
396 {
397 ret = HAL_ERROR;
398 }
399
400 /* Clear all pending Device Interrupts */
401 USBx_DEVICE->DIEPMSK = 0U;
402 USBx_DEVICE->DOEPMSK = 0U;
403 USBx_DEVICE->DAINTMSK = 0U;
404
405 for (i = 0U; i < cfg.dev_endpoints; i++)
406 {
407 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
408 {
409 if (i == 0U)
410 {
411 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
412 }
413 else
414 {
415 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
416 }
417 }
418 else
419 {
420 USBx_INEP(i)->DIEPCTL = 0U;
421 }
422
423 USBx_INEP(i)->DIEPTSIZ = 0U;
424 USBx_INEP(i)->DIEPINT = 0xFB7FU;
425 }
426
427 for (i = 0U; i < cfg.dev_endpoints; i++)
428 {
429 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
430 {
431 if (i == 0U)
432 {
433 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
434 }
435 else
436 {
437 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
438 }
439 }
440 else
441 {
442 USBx_OUTEP(i)->DOEPCTL = 0U;
443 }
444
445 USBx_OUTEP(i)->DOEPTSIZ = 0U;
446 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
447 }
448
449 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
450
451 if (cfg.dma_enable == 1U)
452 {
453 /*Set threshold parameters */
454 USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
455 USB_OTG_DTHRCTL_RXTHRLEN_6;
456
457 USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
458 USB_OTG_DTHRCTL_ISOTHREN |
459 USB_OTG_DTHRCTL_NONISOTHREN;
460 }
461
462 /* Disable all interrupts. */
463 USBx->GINTMSK = 0U;
464
465 /* Clear any pending interrupts */
466 USBx->GINTSTS = 0xBFFFFFFFU;
467
468 /* Enable the common interrupts */
469 if (cfg.dma_enable == 0U)
470 {
471 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
472 }
473
474 /* Enable interrupts matching to the Device mode ONLY */
475 USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
476 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
477 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
478 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
479
480 if (cfg.Sof_enable != 0U)
481 {
482 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
483 }
484
485 if (cfg.vbus_sensing_enable == 1U)
486 {
487 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
488 }
489
490 return ret;
491 }
492
493 /**
494 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
495 * @param USBx Selected device
496 * @param num FIFO number
497 * This parameter can be a value from 1 to 15
498 15 means Flush all Tx FIFOs
499 * @retval HAL status
500 */
501 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
502 {
503 uint32_t tickstart;
504
505 USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
506
507 /* Get tick */
508 tickstart = HAL_GetTick();
509
510 /* Wait for AHB master IDLE state. */
511 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH)
512 {
513 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_TXFFLSH_TIMEOUT_MS)
514 {
515 return HAL_TIMEOUT;
516 }
517 }
518
519 return HAL_OK;
520 }
521
522 /**
523 * @brief USB_FlushRxFifo : Flush Rx FIFO
524 * @param USBx Selected device
525 * @retval HAL status
526 */
527 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
528 {
529 uint32_t tickstart;
530
531 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
532
533 /* Get tick */
534 tickstart = HAL_GetTick();
535
536 /* Wait for AHB master IDLE state. */
537 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH)
538 {
539 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_RXFFLSH_TIMEOUT_MS)
540 {
541 return HAL_TIMEOUT;
542 }
543 }
544
545 return HAL_OK;
546 }
547
548 /**
549 * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
550 * depending the PHY type and the enumeration speed of the device.
551 * @param USBx Selected device
552 * @param speed device speed
553 * This parameter can be one of these values:
554 * @arg USB_OTG_SPEED_HIGH: High speed mode
555 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
556 * @arg USB_OTG_SPEED_FULL: Full speed mode
557 * @retval Hal status
558 */
559 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
560 {
561 uint32_t USBx_BASE = (uint32_t)USBx;
562
563 USBx_DEVICE->DCFG |= speed;
564 return HAL_OK;
565 }
566
567 /**
568 * @brief USB_GetDevSpeed Return the Dev Speed
569 * @param USBx Selected device
570 * @retval speed device speed
571 * This parameter can be one of these values:
572 * @arg USB_OTG_SPEED_HIGH: High speed mode
573 * @arg USB_OTG_SPEED_FULL: Full speed mode
574 */
575 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
576 {
577 uint32_t USBx_BASE = (uint32_t)USBx;
578 uint8_t speed;
579 uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
580
581 if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
582 {
583 speed = USB_OTG_SPEED_HIGH;
584 }
585 else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
586 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
587 {
588 speed = USB_OTG_SPEED_FULL;
589 }
590 else
591 {
592 speed = 0U;
593 }
594
595 return speed;
596 }
597
598 /**
599 * @brief Activate and configure an endpoint
600 * @param USBx Selected device
601 * @param ep pointer to endpoint structure
602 * @retval HAL status
603 */
604 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
605 {
606 uint32_t USBx_BASE = (uint32_t)USBx;
607 uint32_t epnum = (uint32_t)ep->num;
608
609 if (ep->is_in == 1U)
610 {
611 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
612
613 if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
614 {
615 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
616 ((uint32_t)ep->type << 18) | (epnum << 22) |
617 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
618 USB_OTG_DIEPCTL_USBAEP;
619 }
620 }
621 else
622 {
623 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
624
625 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
626 {
627 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
628 ((uint32_t)ep->type << 18) |
629 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
630 USB_OTG_DOEPCTL_USBAEP;
631 }
632 }
633 return HAL_OK;
634 }
635
636 /**
637 * @brief Activate and configure a dedicated endpoint
638 * @param USBx Selected device
639 * @param ep pointer to endpoint structure
640 * @retval HAL status
641 */
642 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
643 {
644 uint32_t USBx_BASE = (uint32_t)USBx;
645 uint32_t epnum = (uint32_t)ep->num;
646
647 /* Read DEPCTLn register */
648 if (ep->is_in == 1U)
649 {
650 if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
651 {
652 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
653 ((uint32_t)ep->type << 18) | (epnum << 22) |
654 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
655 USB_OTG_DIEPCTL_USBAEP;
656 }
657
658 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
659 }
660 else
661 {
662 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
663 {
664 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
665 ((uint32_t)ep->type << 18) | (epnum << 22) |
666 USB_OTG_DOEPCTL_USBAEP;
667 }
668
669 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
670 }
671
672 return HAL_OK;
673 }
674
675 /**
676 * @brief De-activate and de-initialize an endpoint
677 * @param USBx Selected device
678 * @param ep pointer to endpoint structure
679 * @retval HAL status
680 */
681 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
682 {
683 uint32_t USBx_BASE = (uint32_t)USBx;
684 uint32_t epnum = (uint32_t)ep->num;
685
686 /* Read DEPCTLn register */
687 if (ep->is_in == 1U)
688 {
689 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
690 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
691 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
692 USB_OTG_DIEPCTL_MPSIZ |
693 USB_OTG_DIEPCTL_TXFNUM |
694 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
695 USB_OTG_DIEPCTL_EPTYP);
696 }
697 else
698 {
699 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
700 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
701 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
702 USB_OTG_DOEPCTL_MPSIZ |
703 USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
704 USB_OTG_DOEPCTL_EPTYP);
705 }
706
707 return HAL_OK;
708 }
709
710 /**
711 * @brief De-activate and de-initialize a dedicated endpoint
712 * @param USBx Selected device
713 * @param ep pointer to endpoint structure
714 * @retval HAL status
715 */
716 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
717 {
718 uint32_t USBx_BASE = (uint32_t)USBx;
719 uint32_t epnum = (uint32_t)ep->num;
720
721 /* Read DEPCTLn register */
722 if (ep->is_in == 1U)
723 {
724 USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
725 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
726 }
727 else
728 {
729 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
730 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
731 }
732
733 return HAL_OK;
734 }
735
736 /**
737 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
738 * @param USBx Selected device
739 * @param ep pointer to endpoint structure
740 * @param dma USB dma enabled or disabled
741 * This parameter can be one of these values:
742 * 0 : DMA feature not used
743 * 1 : DMA feature used
744 * @retval HAL status
745 */
746 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
747 {
748 uint32_t USBx_BASE = (uint32_t)USBx;
749 uint32_t epnum = (uint32_t)ep->num;
750 uint16_t pktcnt;
751
752 /* IN endpoint */
753 if (ep->is_in == 1U)
754 {
755 /* Zero Length Packet? */
756 if (ep->xfer_len == 0U)
757 {
758 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
759 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
760 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
761 }
762 else
763 {
764 /* Program the transfer size and packet count
765 * as follows: xfersize = N * maxpacket +
766 * short_packet pktcnt = N + (short_packet
767 * exist ? 1 : 0)
768 */
769 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
770 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
771 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
772 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
773
774 if (ep->type == EP_TYPE_ISOC)
775 {
776 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
777 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
778 }
779 }
780
781 if (dma == 1U)
782 {
783 if ((uint32_t)ep->dma_addr != 0U)
784 {
785 USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
786 }
787 }
788 else
789 {
790 if (ep->type != EP_TYPE_ISOC)
791 {
792 /* Enable the Tx FIFO Empty Interrupt for this EP */
793 if (ep->xfer_len > 0U)
794 {
795 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
796 }
797 }
798 }
799
800 if (ep->type == EP_TYPE_ISOC)
801 {
802 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
803 {
804 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
805 }
806 else
807 {
808 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
809 }
810 }
811
812 /* EP enable, IN data in FIFO */
813 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
814
815 if (ep->type == EP_TYPE_ISOC)
816 {
817 (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
818 }
819 }
820 else /* OUT endpoint */
821 {
822 /* Program the transfer size and packet count as follows:
823 * pktcnt = N
824 * xfersize = N * maxpacket
825 */
826 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
827 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
828
829 if (ep->xfer_len == 0U)
830 {
831 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
832 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
833 }
834 else
835 {
836 pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
837 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
838 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
839 }
840
841 if (dma == 1U)
842 {
843 if ((uint32_t)ep->xfer_buff != 0U)
844 {
845 USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
846 }
847 }
848
849 if (ep->type == EP_TYPE_ISOC)
850 {
851 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
852 {
853 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
854 }
855 else
856 {
857 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
858 }
859 }
860 /* EP enable */
861 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
862 }
863
864 return HAL_OK;
865 }
866
867 /**
868 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
869 * @param USBx Selected device
870 * @param ep pointer to endpoint structure
871 * @param dma USB dma enabled or disabled
872 * This parameter can be one of these values:
873 * 0 : DMA feature not used
874 * 1 : DMA feature used
875 * @retval HAL status
876 */
877 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
878 {
879 uint32_t USBx_BASE = (uint32_t)USBx;
880 uint32_t epnum = (uint32_t)ep->num;
881
882 /* IN endpoint */
883 if (ep->is_in == 1U)
884 {
885 /* Zero Length Packet? */
886 if (ep->xfer_len == 0U)
887 {
888 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
889 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
890 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
891 }
892 else
893 {
894 /* Program the transfer size and packet count
895 * as follows: xfersize = N * maxpacket +
896 * short_packet pktcnt = N + (short_packet
897 * exist ? 1 : 0)
898 */
899 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
900 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
901
902 if (ep->xfer_len > ep->maxpacket)
903 {
904 ep->xfer_len = ep->maxpacket;
905 }
906 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
907 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
908 }
909
910 if (dma == 1U)
911 {
912 if ((uint32_t)ep->dma_addr != 0U)
913 {
914 USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
915 }
916 }
917 else
918 {
919 /* Enable the Tx FIFO Empty Interrupt for this EP */
920 if (ep->xfer_len > 0U)
921 {
922 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
923 }
924 }
925
926 /* EP enable, IN data in FIFO */
927 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
928 }
929 else /* OUT endpoint */
930 {
931 /* Program the transfer size and packet count as follows:
932 * pktcnt = N
933 * xfersize = N * maxpacket
934 */
935 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
936 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
937
938 if (ep->xfer_len > 0U)
939 {
940 ep->xfer_len = ep->maxpacket;
941 }
942
943 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
944 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
945
946 if (dma == 1U)
947 {
948 if ((uint32_t)ep->xfer_buff != 0U)
949 {
950 USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
951 }
952 }
953
954 /* EP enable */
955 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
956 }
957
958 return HAL_OK;
959 }
960
961 /**
962 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
963 * with the EP/channel
964 * @param USBx Selected device
965 * @param src pointer to source buffer
966 * @param ch_ep_num endpoint or host channel number
967 * @param len Number of bytes to write
968 * @param dma USB dma enabled or disabled
969 * This parameter can be one of these values:
970 * 0 : DMA feature not used
971 * 1 : DMA feature used
972 * @retval HAL status
973 */
974 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
975 {
976 uint32_t USBx_BASE = (uint32_t)USBx;
977 uint32_t *pSrc = (uint32_t *)src;
978 uint32_t count32b, i;
979
980 if (dma == 0U)
981 {
982 count32b = ((uint32_t)len + 3U) / 4U;
983 for (i = 0U; i < count32b; i++)
984 {
985 USBx_DFIFO((uint32_t)ch_ep_num) = *((uint32_t *)pSrc);
986 pSrc++;
987 }
988 }
989
990 return HAL_OK;
991 }
992
993 /**
994 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
995 * with the EP/channel
996 * @param USBx Selected device
997 * @param dest source pointer
998 * @param len Number of bytes to read
999 * @param dma USB dma enabled or disabled
1000 * This parameter can be one of these values:
1001 * 0 : DMA feature not used
1002 * 1 : DMA feature used
1003 * @retval pointer to destination buffer
1004 */
1005 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
1006 {
1007 uint32_t USBx_BASE = (uint32_t)USBx;
1008 uint32_t *pDest = (uint32_t *)dest;
1009 uint32_t i;
1010 uint32_t count32b = ((uint32_t)len + 3U) / 4U;
1011
1012 for (i = 0U; i < count32b; i++)
1013 {
1014 *(uint32_t *)pDest = USBx_DFIFO(0U);
1015 pDest++;
1016 }
1017
1018 return ((void *)pDest);
1019 }
1020
1021 /**
1022 * @brief USB_EPSetStall : set a stall condition over an EP
1023 * @param USBx Selected device
1024 * @param ep pointer to endpoint structure
1025 * @retval HAL status
1026 */
1027 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
1028 {
1029 uint32_t USBx_BASE = (uint32_t)USBx;
1030 uint32_t epnum = (uint32_t)ep->num;
1031
1032 if (ep->is_in == 1U)
1033 {
1034 if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
1035 {
1036 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
1037 }
1038 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
1039 }
1040 else
1041 {
1042 if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
1043 {
1044 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
1045 }
1046 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
1047 }
1048
1049 return HAL_OK;
1050 }
1051
1052 /**
1053 * @brief USB_EPClearStall : Clear a stall condition over an EP
1054 * @param USBx Selected device
1055 * @param ep pointer to endpoint structure
1056 * @retval HAL status
1057 */
1058 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
1059 {
1060 uint32_t USBx_BASE = (uint32_t)USBx;
1061 uint32_t epnum = (uint32_t)ep->num;
1062
1063 if (ep->is_in == 1U)
1064 {
1065 USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
1066 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
1067 {
1068 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
1069 }
1070 }
1071 else
1072 {
1073 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
1074 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
1075 {
1076 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
1077 }
1078 }
1079 return HAL_OK;
1080 }
1081
1082 /**
1083 * @brief USB_StopDevice : Stop the usb device mode
1084 * @param USBx Selected device
1085 * @retval HAL status
1086 */
1087 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
1088 {
1089 HAL_StatusTypeDef ret;
1090 uint32_t USBx_BASE = (uint32_t)USBx;
1091 uint32_t i;
1092
1093 /* Clear Pending interrupt */
1094 for (i = 0U; i < 15U; i++)
1095 {
1096 USBx_INEP(i)->DIEPINT = 0xFB7FU;
1097 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
1098 }
1099
1100 /* Clear interrupt masks */
1101 USBx_DEVICE->DIEPMSK = 0U;
1102 USBx_DEVICE->DOEPMSK = 0U;
1103 USBx_DEVICE->DAINTMSK = 0U;
1104
1105 /* Flush the FIFO */
1106 ret = USB_FlushRxFifo(USBx);
1107 if (ret != HAL_OK)
1108 {
1109 return ret;
1110 }
1111
1112 ret = USB_FlushTxFifo(USBx, 0x10U);
1113 if (ret != HAL_OK)
1114 {
1115 return ret;
1116 }
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief USB_SetDevAddress : Stop the usb device mode
1123 * @param USBx Selected device
1124 * @param address new device address to be assigned
1125 * This parameter can be a value from 0 to 255
1126 * @retval HAL status
1127 */
1128 HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
1129 {
1130 uint32_t USBx_BASE = (uint32_t)USBx;
1131
1132 USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
1133 USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
1134
1135 return HAL_OK;
1136 }
1137
1138 /**
1139 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
1140 * @param USBx Selected device
1141 * @retval HAL status
1142 */
1143 HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
1144 {
1145 uint32_t USBx_BASE = (uint32_t)USBx;
1146
1147 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
1148 HAL_Delay(3U);
1149
1150 return HAL_OK;
1151 }
1152
1153 /**
1154 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
1155 * @param USBx Selected device
1156 * @retval HAL status
1157 */
1158 HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
1159 {
1160 uint32_t USBx_BASE = (uint32_t)USBx;
1161
1162 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
1163 HAL_Delay(3U);
1164
1165 return HAL_OK;
1166 }
1167
1168 /**
1169 * @brief USB_ReadInterrupts: return the global USB interrupt status
1170 * @param USBx Selected device
1171 * @retval HAL status
1172 */
1173 uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
1174 {
1175 uint32_t tmpreg;
1176
1177 tmpreg = USBx->GINTSTS;
1178 tmpreg &= USBx->GINTMSK;
1179
1180 return tmpreg;
1181 }
1182
1183 /**
1184 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
1185 * @param USBx Selected device
1186 * @retval HAL status
1187 */
1188 uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
1189 {
1190 uint32_t USBx_BASE = (uint32_t)USBx;
1191 uint32_t tmpreg;
1192
1193 tmpreg = USBx_DEVICE->DAINT;
1194 tmpreg &= USBx_DEVICE->DAINTMSK;
1195
1196 return ((tmpreg & 0xffff0000U) >> 16);
1197 }
1198
1199 /**
1200 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
1201 * @param USBx Selected device
1202 * @retval HAL status
1203 */
1204 uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
1205 {
1206 uint32_t USBx_BASE = (uint32_t)USBx;
1207 uint32_t tmpreg;
1208
1209 tmpreg = USBx_DEVICE->DAINT;
1210 tmpreg &= USBx_DEVICE->DAINTMSK;
1211
1212 return ((tmpreg & 0xFFFFU));
1213 }
1214
1215 /**
1216 * @brief Returns Device OUT EP Interrupt register
1217 * @param USBx Selected device
1218 * @param epnum endpoint number
1219 * This parameter can be a value from 0 to 15
1220 * @retval Device OUT EP Interrupt register
1221 */
1222 uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
1223 {
1224 uint32_t USBx_BASE = (uint32_t)USBx;
1225 uint32_t tmpreg;
1226
1227 tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
1228 tmpreg &= USBx_DEVICE->DOEPMSK;
1229
1230 return tmpreg;
1231 }
1232
1233 /**
1234 * @brief Returns Device IN EP Interrupt register
1235 * @param USBx Selected device
1236 * @param epnum endpoint number
1237 * This parameter can be a value from 0 to 15
1238 * @retval Device IN EP Interrupt register
1239 */
1240 uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
1241 {
1242 uint32_t USBx_BASE = (uint32_t)USBx;
1243 uint32_t tmpreg, msk, emp;
1244
1245 msk = USBx_DEVICE->DIEPMSK;
1246 emp = USBx_DEVICE->DIEPEMPMSK;
1247 msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
1248 tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
1249
1250 return tmpreg;
1251 }
1252
1253 /**
1254 * @brief USB_ClearInterrupts: clear a USB interrupt
1255 * @param USBx Selected device
1256 * @param interrupt interrupt flag
1257 * @retval None
1258 */
1259 void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
1260 {
1261 USBx->GINTSTS |= interrupt;
1262 }
1263
1264 /**
1265 * @brief Returns USB core mode
1266 * @param USBx Selected device
1267 * @retval return core mode : Host or Device
1268 * This parameter can be one of these values:
1269 * 0 : Host
1270 * 1 : Device
1271 */
1272 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
1273 {
1274 return ((USBx->GINTSTS) & 0x1U);
1275 }
1276
1277 /**
1278 * @brief Activate EP0 for Setup transactions
1279 * @param USBx Selected device
1280 * @retval HAL status
1281 */
1282 HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
1283 {
1284 uint32_t USBx_BASE = (uint32_t)USBx;
1285
1286 /* Set the MPS of the IN EP based on the enumeration speed */
1287 USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
1288
1289 if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
1290 {
1291 USBx_INEP(0U)->DIEPCTL |= 3U;
1292 }
1293 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
1294
1295 return HAL_OK;
1296 }
1297
1298 /**
1299 * @brief Prepare the EP0 to start the first control setup
1300 * @param USBx Selected device
1301 * @param dma USB dma enabled or disabled
1302 * This parameter can be one of these values:
1303 * 0 : DMA feature not used
1304 * 1 : DMA feature used
1305 * @param psetup pointer to setup packet
1306 * @retval HAL status
1307 */
1308 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
1309 {
1310 uint32_t USBx_BASE = (uint32_t)USBx;
1311 uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
1312
1313 if (gSNPSiD > USB_OTG_CORE_ID_300A)
1314 {
1315 if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
1316 {
1317 return HAL_OK;
1318 }
1319 }
1320
1321 USBx_OUTEP(0U)->DOEPTSIZ = 0U;
1322 USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
1323 USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
1324 USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
1325
1326 if (dma == 1U)
1327 {
1328 USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
1329 /* EP enable */
1330 USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
1331 }
1332
1333 return HAL_OK;
1334 }
1335
1336 /**
1337 * @brief Reset the USB Core (needed after USB clock settings change)
1338 * @param USBx Selected device
1339 * @retval HAL status
1340 */
1341 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
1342 {
1343 uint32_t tickstart;
1344
1345 /* Get tick */
1346 tickstart = HAL_GetTick();
1347
1348 /* Wait for AHB master IDLE state. */
1349 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U)
1350 {
1351 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_AHBIDL_TIMEOUT_MS)
1352 {
1353 return HAL_TIMEOUT;
1354 }
1355 }
1356
1357 /* Core Soft Reset */
1358 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
1359
1360 /* Get tick */
1361 tickstart = HAL_GetTick();
1362
1363 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST)
1364 {
1365 if ((HAL_GetTick() - tickstart) > USB_OTG_GRSTCTL_CSRST_TIMEOUT_MS)
1366 {
1367 return HAL_TIMEOUT;
1368 }
1369 }
1370
1371 return HAL_OK;
1372 }
1373
1374 #ifdef USB_HS_PHYC
1375 /**
1376 * @brief Enables control of a High Speed USB PHYÂ’s
1377 * Init the low level hardware : GPIO, CLOCK, NVIC...
1378 * @param USBx Selected device
1379 * @retval HAL status
1380 */
1381 static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
1382 {
1383 UNUSED(USBx);
1384 uint32_t count = 0U;
1385
1386 /* Enable LDO */
1387 USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
1388
1389 /* wait for LDO Ready */
1390 while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U)
1391 {
1392 if (++count > 200000U)
1393 {
1394 return HAL_TIMEOUT;
1395 }
1396 }
1397
1398 /* Controls PHY frequency operation selection */
1399 if (HSE_VALUE == 12000000U) /* HSE = 12MHz */
1400 {
1401 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1);
1402 }
1403 else if (HSE_VALUE == 12500000U) /* HSE = 12.5MHz */
1404 {
1405 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1);
1406 }
1407 else if (HSE_VALUE == 16000000U) /* HSE = 16MHz */
1408 {
1409 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1);
1410 }
1411 else if (HSE_VALUE == 24000000U) /* HSE = 24MHz */
1412 {
1413 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1);
1414 }
1415 else if (HSE_VALUE == 25000000U) /* HSE = 25MHz */
1416 {
1417 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1);
1418 }
1419 else if (HSE_VALUE == 32000000U) /* HSE = 32MHz */
1420 {
1421 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1);
1422 }
1423 else
1424 {
1425 /* ... */
1426 }
1427
1428 /* Control the tuning interface of the High Speed PHY */
1429 USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
1430
1431 /* Enable PLL internal PHY */
1432 USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
1433
1434 /* 2ms Delay required to get internal phy clock stable */
1435 HAL_Delay(2U);
1436
1437 return HAL_OK;
1438 }
1439
1440 #endif /* USB_HS_PHYC */
1441 /**
1442 * @brief USB_HostInit : Initializes the USB OTG controller registers
1443 * for Host mode
1444 * @param USBx Selected device
1445 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
1446 * the configuration information for the specified USBx peripheral.
1447 * @retval HAL status
1448 */
1449 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
1450 {
1451 uint32_t USBx_BASE = (uint32_t)USBx;
1452 uint32_t i;
1453
1454 /* Restart the Phy Clock */
1455 USBx_PCGCCTL = 0U;
1456
1457 /* Disable VBUS sensing */
1458 USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
1459
1460 if ((USBx->CID & (0x1U << 8)) != 0U)
1461 {
1462 if (cfg.speed == USB_OTG_SPEED_FULL)
1463 {
1464 /* Force Device Enumeration to FS/LS mode only */
1465 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
1466 }
1467 else
1468 {
1469 /* Set default Max speed support */
1470 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1471 }
1472 }
1473 else
1474 {
1475 /* Set default Max speed support */
1476 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1477 }
1478
1479 /* Make sure the FIFOs are flushed. */
1480 (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
1481 (void)USB_FlushRxFifo(USBx);
1482
1483 /* Clear all pending HC Interrupts */
1484 for (i = 0U; i < cfg.Host_channels; i++)
1485 {
1486 USBx_HC(i)->HCINT = 0xFFFFFFFFU;
1487 USBx_HC(i)->HCINTMSK = 0U;
1488 }
1489
1490 /* Enable VBUS driving */
1491 (void)USB_DriveVbus(USBx, 1U);
1492
1493 HAL_Delay(200U);
1494
1495 /* Disable all interrupts. */
1496 USBx->GINTMSK = 0U;
1497
1498 /* Clear any pending interrupts */
1499 USBx->GINTSTS = 0xFFFFFFFFU;
1500
1501 if ((USBx->CID & (0x1U << 8)) != 0U)
1502 {
1503 /* set Rx FIFO size */
1504 USBx->GRXFSIZ = 0x200U;
1505 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
1506 USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
1507 }
1508 else
1509 {
1510 /* set Rx FIFO size */
1511 USBx->GRXFSIZ = 0x80U;
1512 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
1513 USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
1514 }
1515
1516 /* Enable the common interrupts */
1517 if (cfg.dma_enable == 0U)
1518 {
1519 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
1520 }
1521
1522 /* Enable interrupts matching to the Host mode ONLY */
1523 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
1524 USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
1525 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
1526
1527 return HAL_OK;
1528 }
1529
1530 /**
1531 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
1532 * HCFG register on the PHY type and set the right frame interval
1533 * @param USBx Selected device
1534 * @param freq clock frequency
1535 * This parameter can be one of these values:
1536 * HCFG_48_MHZ : Full Speed 48 MHz Clock
1537 * HCFG_6_MHZ : Low Speed 6 MHz Clock
1538 * @retval HAL status
1539 */
1540 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
1541 {
1542 uint32_t USBx_BASE = (uint32_t)USBx;
1543
1544 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
1545 USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
1546
1547 if (freq == HCFG_48_MHZ)
1548 {
1549 USBx_HOST->HFIR = 48000U;
1550 }
1551 else if (freq == HCFG_6_MHZ)
1552 {
1553 USBx_HOST->HFIR = 6000U;
1554 }
1555 else
1556 {
1557 /* ... */
1558 }
1559
1560 return HAL_OK;
1561 }
1562
1563 /**
1564 * @brief USB_OTG_ResetPort : Reset Host Port
1565 * @param USBx Selected device
1566 * @retval HAL status
1567 * @note (1)The application must wait at least 10 ms
1568 * before clearing the reset bit.
1569 */
1570 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
1571 {
1572 uint32_t USBx_BASE = (uint32_t)USBx;
1573
1574 __IO uint32_t hprt0 = 0U;
1575
1576 hprt0 = USBx_HPRT0;
1577
1578 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1579 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1580
1581 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
1582 HAL_Delay(100U); /* See Note #1 */
1583 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
1584 HAL_Delay(10U);
1585
1586 return HAL_OK;
1587 }
1588
1589 /**
1590 * @brief USB_DriveVbus : activate or de-activate vbus
1591 * @param state VBUS state
1592 * This parameter can be one of these values:
1593 * 0 : VBUS Active
1594 * 1 : VBUS Inactive
1595 * @retval HAL status
1596 */
1597 HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
1598 {
1599 uint32_t USBx_BASE = (uint32_t)USBx;
1600 __IO uint32_t hprt0 = 0U;
1601
1602 hprt0 = USBx_HPRT0;
1603
1604 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1605 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1606
1607 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
1608 {
1609 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
1610 }
1611 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
1612 {
1613 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
1614 }
1615 return HAL_OK;
1616 }
1617
1618 /**
1619 * @brief Return Host Core speed
1620 * @param USBx Selected device
1621 * @retval speed : Host speed
1622 * This parameter can be one of these values:
1623 * @arg USB_OTG_SPEED_HIGH: High speed mode
1624 * @arg USB_OTG_SPEED_FULL: Full speed mode
1625 * @arg USB_OTG_SPEED_LOW: Low speed mode
1626 */
1627 uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
1628 {
1629 uint32_t USBx_BASE = (uint32_t)USBx;
1630 __IO uint32_t hprt0 = 0U;
1631
1632 hprt0 = USBx_HPRT0;
1633 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
1634 }
1635
1636 /**
1637 * @brief Return Host Current Frame number
1638 * @param USBx Selected device
1639 * @retval current frame number
1640 */
1641 uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
1642 {
1643 uint32_t USBx_BASE = (uint32_t)USBx;
1644
1645 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
1646 }
1647
1648 /**
1649 * @brief Initialize a host channel
1650 * @param USBx Selected device
1651 * @param ch_num Channel number
1652 * This parameter can be a value from 1 to 15
1653 * @param epnum Endpoint number
1654 * This parameter can be a value from 1 to 15
1655 * @param dev_address Current device address
1656 * This parameter can be a value from 0 to 255
1657 * @param speed Current device speed
1658 * This parameter can be one of these values:
1659 * @arg USB_OTG_SPEED_HIGH: High speed mode
1660 * @arg USB_OTG_SPEED_FULL: Full speed mode
1661 * @arg USB_OTG_SPEED_LOW: Low speed mode
1662 * @param ep_type Endpoint Type
1663 * This parameter can be one of these values:
1664 * @arg EP_TYPE_CTRL: Control type
1665 * @arg EP_TYPE_ISOC: Isochronous type
1666 * @arg EP_TYPE_BULK: Bulk type
1667 * @arg EP_TYPE_INTR: Interrupt type
1668 * @param mps Max Packet Size
1669 * This parameter can be a value from 0 to32K
1670 * @retval HAL state
1671 */
1672 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
1673 uint8_t ch_num,
1674 uint8_t epnum,
1675 uint8_t dev_address,
1676 uint8_t speed,
1677 uint8_t ep_type,
1678 uint16_t mps)
1679 {
1680 HAL_StatusTypeDef ret = HAL_OK;
1681 uint32_t USBx_BASE = (uint32_t)USBx;
1682 uint32_t HCcharEpDir, HCcharLowSpeed;
1683
1684 /* Clear old interrupt conditions for this host channel. */
1685 USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
1686
1687 /* Enable channel interrupts required for this transfer. */
1688 switch (ep_type)
1689 {
1690 case EP_TYPE_CTRL:
1691 case EP_TYPE_BULK:
1692 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1693 USB_OTG_HCINTMSK_STALLM |
1694 USB_OTG_HCINTMSK_TXERRM |
1695 USB_OTG_HCINTMSK_DTERRM |
1696 USB_OTG_HCINTMSK_AHBERR |
1697 USB_OTG_HCINTMSK_NAKM;
1698
1699 if ((epnum & 0x80U) == 0x80U)
1700 {
1701 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1702 }
1703 else
1704 {
1705 if ((USBx->CID & (0x1U << 8)) != 0U)
1706 {
1707 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1708 }
1709 }
1710 break;
1711
1712 case EP_TYPE_INTR:
1713 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1714 USB_OTG_HCINTMSK_STALLM |
1715 USB_OTG_HCINTMSK_TXERRM |
1716 USB_OTG_HCINTMSK_DTERRM |
1717 USB_OTG_HCINTMSK_NAKM |
1718 USB_OTG_HCINTMSK_AHBERR |
1719 USB_OTG_HCINTMSK_FRMORM;
1720
1721 if ((epnum & 0x80U) == 0x80U)
1722 {
1723 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1724 }
1725
1726 break;
1727
1728 case EP_TYPE_ISOC:
1729 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1730 USB_OTG_HCINTMSK_ACKM |
1731 USB_OTG_HCINTMSK_AHBERR |
1732 USB_OTG_HCINTMSK_FRMORM;
1733
1734 if ((epnum & 0x80U) == 0x80U)
1735 {
1736 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
1737 }
1738 break;
1739
1740 default:
1741 ret = HAL_ERROR;
1742 break;
1743 }
1744
1745 /* Enable the top level host channel interrupt. */
1746 USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
1747
1748 /* Make sure host channel interrupts are enabled. */
1749 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
1750
1751 /* Program the HCCHAR register */
1752 if ((epnum & 0x80U) == 0x80U)
1753 {
1754 HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
1755 }
1756 else
1757 {
1758 HCcharEpDir = 0U;
1759 }
1760
1761 if (speed == HPRT0_PRTSPD_LOW_SPEED)
1762 {
1763 HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
1764 }
1765 else
1766 {
1767 HCcharLowSpeed = 0U;
1768 }
1769
1770 USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
1771 ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
1772 (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
1773 ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
1774
1775 if (ep_type == EP_TYPE_INTR)
1776 {
1777 USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
1778 }
1779
1780 return ret;
1781 }
1782
1783 /**
1784 * @brief Start a transfer over a host channel
1785 * @param USBx Selected device
1786 * @param hc pointer to host channel structure
1787 * @param dma USB dma enabled or disabled
1788 * This parameter can be one of these values:
1789 * 0 : DMA feature not used
1790 * 1 : DMA feature used
1791 * @retval HAL state
1792 */
1793 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
1794 {
1795 uint32_t USBx_BASE = (uint32_t)USBx;
1796 uint32_t ch_num = (uint32_t)hc->ch_num;
1797 static __IO uint32_t tmpreg = 0U;
1798 uint8_t is_oddframe;
1799 uint16_t len_words;
1800 uint16_t num_packets;
1801 uint16_t max_hc_pkt_count = 256U;
1802
1803 if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USB_OTG_SPEED_HIGH))
1804 {
1805 if ((dma == 0U) && (hc->do_ping == 1U))
1806 {
1807 (void)USB_DoPing(USBx, hc->ch_num);
1808 return HAL_OK;
1809 }
1810 else if (dma == 1U)
1811 {
1812 USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1813 hc->do_ping = 0U;
1814 }
1815 else
1816 {
1817 /* ... */
1818 }
1819 }
1820
1821 /* Compute the expected number of packets associated to the transfer */
1822 if (hc->xfer_len > 0U)
1823 {
1824 num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
1825
1826 if (num_packets > max_hc_pkt_count)
1827 {
1828 num_packets = max_hc_pkt_count;
1829 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1830 }
1831 }
1832 else
1833 {
1834 num_packets = 1U;
1835 }
1836 if (hc->ep_is_in != 0U)
1837 {
1838 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1839 }
1840
1841 /* Initialize the HCTSIZn register */
1842 USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
1843 (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1844 (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
1845
1846 if (dma != 0U)
1847 {
1848 /* xfer_buff MUST be 32-bits aligned */
1849 USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
1850 }
1851
1852 is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
1853 USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
1854 USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
1855
1856 /* Set host channel enable */
1857 tmpreg = USBx_HC(ch_num)->HCCHAR;
1858 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1859
1860 /* make sure to set the correct ep direction */
1861 if (hc->ep_is_in != 0U)
1862 {
1863 tmpreg |= USB_OTG_HCCHAR_EPDIR;
1864 }
1865 else
1866 {
1867 tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
1868 }
1869 tmpreg |= USB_OTG_HCCHAR_CHENA;
1870 USBx_HC(ch_num)->HCCHAR = tmpreg;
1871
1872 if (dma == 0U) /* Slave mode */
1873 {
1874 if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
1875 {
1876 switch (hc->ep_type)
1877 {
1878 /* Non periodic transfer */
1879 case EP_TYPE_CTRL:
1880 case EP_TYPE_BULK:
1881
1882 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1883
1884 /* check if there is enough space in FIFO space */
1885 if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
1886 {
1887 /* need to process data in nptxfempty interrupt */
1888 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
1889 }
1890 break;
1891
1892 /* Periodic transfer */
1893 case EP_TYPE_INTR:
1894 case EP_TYPE_ISOC:
1895 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1896 /* check if there is enough space in FIFO space */
1897 if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
1898 {
1899 /* need to process data in ptxfempty interrupt */
1900 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
1901 }
1902 break;
1903
1904 default:
1905 break;
1906 }
1907
1908 /* Write packet into the Tx FIFO. */
1909 (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
1910 }
1911 }
1912
1913 return HAL_OK;
1914 }
1915
1916 /**
1917 * @brief Read all host channel interrupts status
1918 * @param USBx Selected device
1919 * @retval HAL state
1920 */
1921 uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
1922 {
1923 uint32_t USBx_BASE = (uint32_t)USBx;
1924
1925 return ((USBx_HOST->HAINT) & 0xFFFFU);
1926 }
1927
1928 /**
1929 * @brief Halt a host channel
1930 * @param USBx Selected device
1931 * @param hc_num Host Channel number
1932 * This parameter can be a value from 1 to 15
1933 * @retval HAL state
1934 */
1935 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
1936 {
1937 uint32_t USBx_BASE = (uint32_t)USBx;
1938 uint32_t hcnum = (uint32_t)hc_num;
1939 uint32_t count = 0U;
1940 uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
1941
1942 /* Check for space in the request queue to issue the halt. */
1943 if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
1944 {
1945 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1946
1947 if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
1948 {
1949 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1950 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1951 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1952 do
1953 {
1954 if (++count > 1000U)
1955 {
1956 break;
1957 }
1958 }
1959 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1960 }
1961 else
1962 {
1963 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1964 }
1965 }
1966 else
1967 {
1968 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1969
1970 if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
1971 {
1972 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1973 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1974 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1975 do
1976 {
1977 if (++count > 1000U)
1978 {
1979 break;
1980 }
1981 }
1982 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1983 }
1984 else
1985 {
1986 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1987 }
1988 }
1989
1990 return HAL_OK;
1991 }
1992
1993 /**
1994 * @brief Initiate Do Ping protocol
1995 * @param USBx Selected device
1996 * @param hc_num Host Channel number
1997 * This parameter can be a value from 1 to 15
1998 * @retval HAL state
1999 */
2000 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
2001 {
2002 uint32_t USBx_BASE = (uint32_t)USBx;
2003 uint32_t chnum = (uint32_t)ch_num;
2004 uint32_t num_packets = 1U;
2005 uint32_t tmpreg;
2006
2007 USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
2008 USB_OTG_HCTSIZ_DOPING;
2009
2010 /* Set host channel enable */
2011 tmpreg = USBx_HC(chnum)->HCCHAR;
2012 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
2013 tmpreg |= USB_OTG_HCCHAR_CHENA;
2014 USBx_HC(chnum)->HCCHAR = tmpreg;
2015
2016 return HAL_OK;
2017 }
2018
2019 /**
2020 * @brief Stop Host Core
2021 * @param USBx Selected device
2022 * @retval HAL state
2023 */
2024 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
2025 {
2026 uint32_t USBx_BASE = (uint32_t)USBx;
2027 uint32_t count = 0U;
2028 uint32_t value;
2029 uint32_t i;
2030
2031
2032 (void)USB_DisableGlobalInt(USBx);
2033
2034 /* Flush FIFO */
2035 (void)USB_FlushTxFifo(USBx, 0x10U);
2036 (void)USB_FlushRxFifo(USBx);
2037
2038 /* Flush out any leftover queued requests. */
2039 for (i = 0U; i <= 15U; i++)
2040 {
2041 value = USBx_HC(i)->HCCHAR;
2042 value |= USB_OTG_HCCHAR_CHDIS;
2043 value &= ~USB_OTG_HCCHAR_CHENA;
2044 value &= ~USB_OTG_HCCHAR_EPDIR;
2045 USBx_HC(i)->HCCHAR = value;
2046 }
2047
2048 /* Halt all channels to put them into a known state. */
2049 for (i = 0U; i <= 15U; i++)
2050 {
2051 value = USBx_HC(i)->HCCHAR;
2052 value |= USB_OTG_HCCHAR_CHDIS;
2053 value |= USB_OTG_HCCHAR_CHENA;
2054 value &= ~USB_OTG_HCCHAR_EPDIR;
2055 USBx_HC(i)->HCCHAR = value;
2056
2057 do
2058 {
2059 if (++count > 1000U)
2060 {
2061 break;
2062 }
2063 }
2064 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
2065 }
2066
2067 /* Clear any pending Host interrupts */
2068 USBx_HOST->HAINT = 0xFFFFFFFFU;
2069 USBx->GINTSTS = 0xFFFFFFFFU;
2070 (void)USB_EnableGlobalInt(USBx);
2071
2072 return HAL_OK;
2073 }
2074
2075 /**
2076 * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
2077 * @param USBx Selected device
2078 * @retval HAL status
2079 */
2080 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
2081 {
2082 uint32_t USBx_BASE = (uint32_t)USBx;
2083
2084 if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
2085 {
2086 /* active Remote wakeup signalling */
2087 USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
2088 }
2089
2090 return HAL_OK;
2091 }
2092
2093 /**
2094 * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
2095 * @param USBx Selected device
2096 * @retval HAL status
2097 */
2098 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
2099 {
2100 uint32_t USBx_BASE = (uint32_t)USBx;
2101
2102 /* active Remote wakeup signalling */
2103 USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
2104
2105 return HAL_OK;
2106 }
2107 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
2108
2109
2110 /**
2111 * @}
2112 */
2113
2114 /**
2115 * @}
2116 */
2117 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
2118 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
2119
2120 /**
2121 * @}
2122 */
2123
2124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/