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FIX: Flash page size check is STM (or clone) specific (#14130)
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_pwr.c
blob964c9473d0079106118318e9b4c0948cd264019a
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Peripheral Control functions.
10 * + Interrupt Handling functions.
11 @verbatim
12 ==============================================================================
13 ##### PWR peripheral overview #####
14 ==============================================================================
15 [..]
16 (#) The Power control (PWR) provides an overview of the supply architecture
17 for the different power domains and of the supply configuration
18 controller.
19 In the H7 family, the number of power domains is different between
20 device lines. This difference is due to characteristics of each device.
21
22 (#) Domain architecture overview for the different H7 lines:
23 (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
24 These devices have 3 power domains (D1, D2 and D3).
25 The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
26 peripherals. The D2 domain contains peripherals and a CPU
27 (Cortex-M4). The D3 domain contains the system control, I/O logic
28 and low-power peripherals.
29 (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753
30 devices have 3 power domains (D1, D2 and D3).
31 The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
32 peripherals. The D2 domain contains peripherals. The D3 domains
33 contains the system control, I/O logic and low-power peripherals.
34 (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD).
35 The core domain (CD) contains a CPU (Cortex-M7), a Flash
36 memory and peripherals. The SmartRun domain contains the system
37 control, I/O logic and low-power peripherals.
38
39 (#) Every entity have low power mode as decribed below :
40 (#) The CPU low power modes are :
41 (+) CPU CRUN.
42 (+) CPU CSLEEP.
43 (+) CPU CSTOP.
44 (#) The domain low power modes are :
45 (+) DRUN.
46 (+) DSTOP.
47 (+) DSTANDBY.
48 (#) The SYSTEM low power modes are :
49 (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
50 Standby. In Run* mode, the performance is limited and the
51 system supply configuration shall be programmed. The system
52 enters Run mode only when the ACTVOSRDY bit in PWR control
53 status register 1 (PWR_CSR1) is set to 1.
54 (+) RUN.
55 (+) STOP.
56 (+) STANDBY.
57
58 ==============================================================================
59 ##### How to use this driver #####
60 ==============================================================================
61 [..]
62 (#) Power management peripheral is active by default at startup level in
63 STM32h7xx lines.
64
65 (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
66 to enable/disable access to the backup domain (RTC registers, RTC backup
67 data registers and backup SRAM).
68
69 (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
70 mode and voltage threshold) in order to set up the Power Voltage Detector,
71 then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start
72 and stop the PVD detection.
73 (+) PVD level could be one of the following values :
74 (++) 1V95
75 (++) 2V1
76 (++) 2V25
77 (++) 2V4
78 (++) 2V55
79 (++) 2V7
80 (++) 2V85
81 (++) External voltage level
82
83 (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
84 with the right parameter to configure the wake up pin polarity (Low or
85 High) and to enable and disable it.
86
87 (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
88 mode. Wake-up from SLEEP mode could be following to an event or an
89 interrupt according to low power mode intrinsic request called (__WFI()
90 or __WFE()).
91 Please ensure to clear all CPU pending events by calling
92 HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
93 in SLEEP mode with __WFE() entry.
94
95 (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
96 mode for single core devices. For dual core devices, this API will enter
97 the domain (containing Cortex-Mx that executing this function) in DSTOP
98 mode. According to the used parameter, user could select the regulator to
99 be kept actif in low power mode and wake-up event type.
100 Please ensure to clear all CPU pending events by calling
101 HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
102 in CSTOP mode with __WFE() entry.
103
104 (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
105 STANDBY mode for single core devices. For dual core devices, this API
106 will enter the domain (containing Cortex-Mx that executing this function)
107 in DSTANDBY mode.
108
109 (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
110 enable and disable the Cortex-Mx re-entring in SLEEP mode after an
111 interruption handling is over.
112
113 (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
114 to configure the Cortex-Mx to wake-up after any pending event / interrupt
115 even if it's disabled or has insufficient priority to cause exception
116 entry.
117
118 (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
119 request.
120
121 *** PWR HAL driver macros list ***
122 =============================================
123 [..]
124 Below the list of most used macros in PWR HAL driver.
125
126 (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
127 regulator output voltage.
128 (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
129 (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
130
131 @endverbatim
132 ******************************************************************************
133 * @attention
134 *
135 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
136 * All rights reserved.</center></h2>
137 *
138 * This software component is licensed by ST under BSD 3-Clause license,
139 * the "License"; You may not use this file except in compliance with the
140 * License. You may obtain a copy of the License at:
141 * opensource.org/licenses/BSD-3-Clause
142 *
143 ******************************************************************************
144 */
145
146 /* Includes ------------------------------------------------------------------*/
147 #include "stm32h7xx_hal.h"
148
149 /** @addtogroup STM32H7xx_HAL_Driver
150 * @{
151 */
152
153 /** @defgroup PWR PWR
154 * @brief PWR HAL module driver
155 * @{
156 */
157
158 #ifdef HAL_PWR_MODULE_ENABLED
159
160 /* Private typedef -----------------------------------------------------------*/
161 /* Private define ------------------------------------------------------------*/
162
163 /** @addtogroup PWR_Private_Constants PWR Private Constants
164 * @{
165 */
166
167 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
168 * @{
169 */
170 #if !defined (DUAL_CORE)
171 #define PVD_MODE_IT (0x00010000U)
172 #define PVD_MODE_EVT (0x00020000U)
173 #endif /* !defined (DUAL_CORE) */
174
175 #define PVD_RISING_EDGE (0x00000001U)
176 #define PVD_FALLING_EDGE (0x00000002U)
177 #define PVD_RISING_FALLING_EDGE (0x00000003U)
178 /**
179 * @}
180 */
181
182 /**
183 * @}
184 */
185
186 /* Private macro -------------------------------------------------------------*/
187 /* Private variables ---------------------------------------------------------*/
188 /* Private function prototypes -----------------------------------------------*/
189 /* Private functions ---------------------------------------------------------*/
190
191 /** @defgroup PWR_Exported_Functions PWR Exported Functions
192 * @{
193 */
194
195 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
196 * @brief Initialization and De-Initialization functions
197 *
198 @verbatim
199 ===============================================================================
200 ##### Initialization and De-Initialization Functions #####
201 ===============================================================================
202 [..]
203 This section provides functions allowing to deinitialize power peripheral.
204
205 [..]
206 After system reset, the backup domain (RTC registers, RTC backup data
207 registers and backup SRAM) is protected against possible unwanted write
208 accesses.
209 The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
210 domain.
211 The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
212 domain.
213
214 @endverbatim
215 * @{
216 */
217
218 /**
219 * @brief Deinitialize the HAL PWR peripheral registers to their default reset
220 * values.
221 * @note This functionality is not available in this product.
222 * The prototype is kept just to maintain compatibility with other
223 * products.
224 * @retval None.
225 */
226 void HAL_PWR_DeInit (void)
227 {
228 }
229
230 /**
231 * @brief Enable access to the backup domain (RTC registers, RTC backup data
232 * registers and backup SRAM).
233 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
234 * Backup Domain Access should be kept enabled.
235 * @retval None.
236 */
237 void HAL_PWR_EnableBkUpAccess (void)
238 {
239 /* Enable access to RTC and backup registers */
240 SET_BIT (PWR->CR1, PWR_CR1_DBP);
241 }
242
243 /**
244 * @brief Disable access to the backup domain (RTC registers, RTC backup data
245 * registers and backup SRAM).
246 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
247 * Backup Domain Access should be kept enabled.
248 * @retval None.
249 */
250 void HAL_PWR_DisableBkUpAccess (void)
251 {
252 /* Disable access to RTC and backup registers */
253 CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
254 }
255 /**
256 * @}
257 */
258
259 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
260 * @brief Power Control functions
261 *
262 @verbatim
263 ===============================================================================
264 ##### Peripheral Control Functions #####
265 ===============================================================================
266 [..]
267 This section provides functions allowing to control power peripheral.
268
269 *** PVD configuration ***
270 =========================
271 [..]
272 (+) The PVD is used to monitor the VDD power supply by comparing it to a
273 threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
274 register).
275
276 (+) A PVDO flag is available to indicate if VDD is higher or lower
277 than the PVD threshold. This event is internally connected to the EXTI
278 line 16 to generate an interrupt if enabled.
279 It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
280
281 (+) The PVD is stopped in STANDBY mode.
282
283 *** Wake-up pin configuration ***
284 =================================
285 [..]
286 (+) Wake-up pin is used to wake up the system from STANDBY mode.
287 The pin pull is configurable through the WKUPEPR register to be in
288 No-pull, Pull-up and Pull-down.
289 The pin polarity is configurable through the WKUPEPR register to be
290 active on rising or falling edges.
291
292 (+) There are up to six Wake-up pin in the STM32H7 devices family.
293
294 *** Low Power modes configuration ***
295 =====================================
296 [..]
297 The device present 3 principles low-power modes features:
298 (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining
299 active (Powered and Clocked).
300
301 (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the
302 regulator is running. The Main regulator or the LP
303 regulator could be selected.
304
305 (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
306 supply regulator is powered off.
307
308 *** SLEEP mode ***
309 ==================
310 [..]
311 (+) Entry:
312 The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
313 SLEEPEntry) function.
314
315 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
316 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
317
318 -@@- The Regulator parameter is not used for the STM32H7 family
319 and is kept as parameter just to maintain compatibility with the
320 lower power families (STM32L).
321
322 (+) Exit:
323 Any peripheral interrupt acknowledged by the nested vectored interrupt
324 controller (NVIC) can wake up the device from SLEEP mode.
325
326 *** STOP mode ***
327 =================
328 [..]
329 In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
330 the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
331 register contents are preserved.
332 The voltage regulator can be configured either in normal or low-power mode.
333 To minimize the consumption in STOP mode, FLASH can be powered off before
334 entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
335 It can be switched on again by software after exiting the STOP mode using
336 the HAL_PWREx_DisableFlashPowerDown() function.
337
338 (+) Entry:
339 The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
340 STOPEntry) function with:
341
342 (++) Regulator:
343 (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
344 (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
345
346 (++) STOPEntry:
347 (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
348 (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
349
350 (+) Exit:
351 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
352
353 *** STANDBY mode ***
354 ====================
355 [..]
356 (+)
357 The system STANDBY mode allows to achieve the lowest power consumption.
358 It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
359 disabled. The system is consequently powered off. The PLL, the HSI
360 oscillator and the HSE oscillator are also switched off. SRAM and register
361 contents are lost except for the RTC registers, RTC backup registers,
362 backup SRAM and standby circuitry.
363
364 [..]
365 The voltage regulator is OFF.
366
367 (++) Entry:
368 (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
369 function.
370
371 (++) Exit:
372 (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
373 RTC wakeup, tamper event, time stamp event, external reset in NRST
374 pin, IWDG reset.
375
376 *** Auto-wakeup (AWU) from low-power mode ***
377 =============================================
378 [..]
379 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
380 RTC Wakeup event, a tamper event or a time-stamp event, without
381 depending on an external interrupt (Auto-wakeup mode).
382
383 (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
384
385 (++) To wake up from the STOP mode with an RTC alarm event, it is
386 necessary to configure the RTC to generate the RTC alarm using the
387 HAL_RTC_SetAlarm_IT() function.
388
389 (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
390 it is necessary to configure the RTC to detect the tamper or time
391 stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
392 HAL_RTCEx_SetTamper_IT() functions.
393
394 (++) To wake up from the STOP mode with an RTC WakeUp event, it is
395 necessary to configure the RTC to generate the RTC WakeUp event
396 using the HAL_RTCEx_SetWakeUpTimer_IT() function.
397
398 @endverbatim
399 * @{
400 */
401
402 /**
403 * @brief Configure the event mode and the voltage threshold detected by the
404 * Programmable Voltage Detector(PVD).
405 * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
406 * the configuration information for the PVD.
407 * @note Refer to the electrical characteristics of your device datasheet for
408 * more details about the voltage threshold corresponding to each
409 * detection level.
410 * @note For dual core devices, please ensure to configure the EXTI lines for
411 * the different Cortex-Mx through PWR_Exported_Macro provided by this
412 * driver. All combination are allowed: wake up only Cortex-M7, wake up
413 * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
414 * @retval None.
415 */
416 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
417 {
418 /* Check the PVD configuration parameter */
419 if (sConfigPVD == NULL)
420 {
421 return;
422 }
423
424 /* Check the parameters */
425 assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
426 assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
427
428 /* Set PLS[7:5] bits according to PVDLevel value */
429 MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
430
431 /* Clear previous config */
432 #if !defined (DUAL_CORE)
433 __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
434 __HAL_PWR_PVD_EXTI_DISABLE_IT ();
435 #endif /* !defined (DUAL_CORE) */
436
437 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
438 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
439
440 #if !defined (DUAL_CORE)
441 /* Interrupt mode configuration */
442 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
443 {
444 __HAL_PWR_PVD_EXTI_ENABLE_IT ();
445 }
446
447 /* Event mode configuration */
448 if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
449 {
450 __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
451 }
452 #endif /* !defined (DUAL_CORE) */
453
454 /* Rising edge configuration */
455 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
456 {
457 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
458 }
459
460 /* Falling edge configuration */
461 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
462 {
463 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
464 }
465 }
466
467 /**
468 * @brief Enable the Programmable Voltage Detector (PVD).
469 * @retval None.
470 */
471 void HAL_PWR_EnablePVD (void)
472 {
473 /* Enable the power voltage detector */
474 SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
475 }
476
477 /**
478 * @brief Disable the Programmable Voltage Detector (PVD).
479 * @retval None.
480 */
481 void HAL_PWR_DisablePVD (void)
482 {
483 /* Disable the power voltage detector */
484 CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
485 }
486
487 /**
488 * @brief Enable the WakeUp PINx functionality.
489 * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
490 * This parameter can be one of the following legacy values, which
491 * sets the default (rising edge):
492 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
493 * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
494 * or one of the following values where the user can explicitly states
495 * the enabled pin and the chosen polarity:
496 * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
497 * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
498 * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
499 * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
500 * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
501 * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
502 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
503 * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
504 * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
505 * GPIOI port.
506 * @retval None.
507 */
508 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
509 {
510 /* Check the parameters */
511 assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
512
513 /*
514 Enable and Specify the Wake-Up pin polarity and the pull configuration
515 for the event detection (rising or falling edge).
516 */
517 MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
518 }
519
520 /**
521 * @brief Disable the WakeUp PINx functionality.
522 * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
523 * This parameter can be one of the following values:
524 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
525 * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
526 * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
527 * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
528 * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
529 * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
530 * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
531 * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
532 * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
533 * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
534 * GPIOI port.
535 * @retval None.
536 */
537 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
538 {
539 /* Check the parameters */
540 assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
541
542 /* Disable the wake up pin selected */
543 CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
544 }
545
546 /**
547 * @brief Enter the current core in SLEEP mode (CSLEEP).
548 * @param Regulator : Specifies the regulator state in SLEEP mode.
549 * This parameter can be one of the following values:
550 * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON.
551 * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
552 * regulator ON.
553 * @note This parameter is not used for the STM32H7 family and is kept as
554 * parameter just to maintain compatibility with the lower power
555 * families.
556 * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
557 * intrinsic instruction.
558 * This parameter can be one of the following values:
559 * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
560 * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
561 * @note Ensure to clear pending events before calling this API through
562 * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
563 * @retval None.
564 */
565 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
566 {
567 UNUSED(Regulator);
568
569 /* Check the parameters */
570 assert_param (IS_PWR_REGULATOR (Regulator));
571 assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
572
573 /* Clear SLEEPDEEP bit of Cortex System Control Register */
574 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
575
576 /* Select SLEEP mode entry */
577 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
578 {
579 /* Request Wait For Interrupt */
580 __WFI ();
581 }
582 else
583 {
584 /* Request Wait For Event */
585 __WFE ();
586 }
587 }
588
589 /**
590 * @brief Enter STOP mode.
591 * @note For single core devices, this API will enter the system in STOP mode
592 * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
593 * cleared.
594 * For dual core devices, this API will enter the domain (containing
595 * Cortex-Mx that executing this function) in DSTOP mode. If all
596 * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
597 * cleared, all the system will enter in STOP mode.
598 * @param Regulator : Specifies the regulator state in STOP mode.
599 * This parameter can be one of the following values:
600 * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
601 * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
602 * regulator ON.
603 * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
604 * intrinsic instruction.
605 * This parameter can be one of the following values:
606 * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
607 * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
608 * @note In System STOP mode, all I/O pins keep the same state as in Run mode.
609 * @note When exiting System STOP mode by issuing an interrupt or a wakeup
610 * event, the HSI RC oscillator is selected as default system wakeup
611 * clock.
612 * @note In System STOP mode, when the voltage regulator operates in low
613 * power mode, an additional startup delay is incurred when the system
614 * is waking up. By keeping the internal regulator ON during STOP mode,
615 * the consumption is higher although the startup time is reduced.
616 * @retval None.
617 */
618 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
619 {
620 /* Check the parameters */
621 assert_param (IS_PWR_REGULATOR (Regulator));
622 assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
623
624 /* Select the regulator state in STOP mode */
625 MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
626
627 /* Configure the PWR mode for the different Domains */
628 #if defined (DUAL_CORE)
629 /* Check CPU ID */
630 if (HAL_GetCurrentCPUID () == CM7_CPUID)
631 {
632 /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
633 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
634 }
635 else
636 {
637 /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
638 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
639 }
640 #else /* Single core devices */
641 /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
642 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
643
644 #if defined (PWR_CPUCR_PDDS_D2)
645 /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
646 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
647 #endif /* PWR_CPUCR_PDDS_D2 */
648 #endif /* defined (DUAL_CORE) */
649
650 /* Set SLEEPDEEP bit of Cortex System Control Register */
651 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
652
653 /* Ensure that all instructions are done before entering STOP mode */
654 __DSB ();
655 __ISB ();
656
657 /* Select STOP mode entry */
658 if (STOPEntry == PWR_STOPENTRY_WFI)
659 {
660 /* Request Wait For Interrupt */
661 __WFI ();
662 }
663 else
664 {
665 /* Request Wait For Event */
666 __WFE ();
667 }
668
669 /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
670 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
671 }
672
673 /**
674 * @brief Enter STANDBY mode.
675 * @note For single core devices, this API will enter the system in STANDBY
676 * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
677 * regiter is cleared.
678 * For dual core devices, this API will enter the domain (containing
679 * Cortex-Mx that executing this function) in DSTANDBY mode. If all
680 * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
681 * is cleared, all the system will enter in STANDBY mode.
682 * @note The system enters Standby mode only when all domains are in DSTANDBY.
683 * @note When the System exit STANDBY mode by issuing an interrupt or a
684 * wakeup event, the HSI RC oscillator is selected as system clock.
685 * @note It is recommended to disable all regulators before entring STANDBY
686 * mode for power consumption saving purpose.
687 * @retval None.
688 */
689 void HAL_PWR_EnterSTANDBYMode (void)
690 {
691 /* Configure the PWR mode for the different Domains */
692 #if defined (DUAL_CORE)
693 /* Check CPU ID */
694 if (HAL_GetCurrentCPUID () == CM7_CPUID)
695 {
696 /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
697 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
698 SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
699 }
700 else
701 {
702 /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
703 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
704 SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
705 }
706 #else /* Single core devices */
707 /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
708 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
709
710 #if defined (PWR_CPUCR_PDDS_D2)
711 /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
712 SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
713 #endif /* PWR_CPUCR_PDDS_D2 */
714 #endif /* defined (DUAL_CORE) */
715
716 /* Set SLEEPDEEP bit of Cortex System Control Register */
717 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
718
719 /* Ensure that all instructions are done before entering STOP mode */
720 __DSB ();
721 __ISB ();
722
723 /* This option is used to ensure that store operations are completed */
724 #if defined (__CC_ARM)
725 __force_stores();
726 #endif /* defined (__CC_ARM) */
727
728 /* Request Wait For Interrupt */
729 __WFI ();
730 }
731
732 /**
733 * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to
734 * Thread mode.
735 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
736 * processor re-enters SLEEP mode when an interruption handling is over.
737 * Setting this bit is useful when the processor is expected to run
738 * only on interruptions handling.
739 * @retval None.
740 */
741 void HAL_PWR_EnableSleepOnExit (void)
742 {
743 /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
744 SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
745 }
746
747 /**
748 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to
749 * Thread mode.
750 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
751 * processor re-enters SLEEP mode when an interruption handling is over.
752 * @retval None
753 */
754 void HAL_PWR_DisableSleepOnExit (void)
755 {
756 /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
757 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
758 }
759
760 /**
761 * @brief Enable CORTEX SEVONPEND feature.
762 * @note Sets SEVONPEND bit of SCR register. When this bit is set, any
763 * pending event / interrupt even if it's disabled or has insufficient
764 * priority to cause exception entry wakes up the Cortex-Mx.
765 * @retval None.
766 */
767 void HAL_PWR_EnableSEVOnPend (void)
768 {
769 /* Set SEVONPEND bit of Cortex-Mx System Control Register */
770 SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
771 }
772
773 /**
774 * @brief Disable CORTEX SEVONPEND feature.
775 * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
776 * enabled pending causes exception entry wakes up the Cortex-Mx.
777 * @retval None.
778 */
779 void HAL_PWR_DisableSEVOnPend (void)
780 {
781 /* Clear SEVONPEND bit of Cortex System Control Register */
782 CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
783 }
784 /**
785 * @}
786 */
787
788 /** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
789 * @brief Interrupt Handling functions
790 *
791 @verbatim
792 ===============================================================================
793 ##### Interrupt Handling Functions #####
794 ===============================================================================
795 [..]
796 This section provides functions allowing to handle the PVD pending
797 interrupts.
798
799 @endverbatim
800 * @{
801 */
802
803 /**
804 * @brief This function handles the PWR PVD interrupt request.
805 * @note This API should be called under the PVD_AVD_IRQHandler().
806 * @retval None.
807 */
808 void HAL_PWR_PVD_IRQHandler (void)
809 {
810 #if defined (DUAL_CORE)
811 /* Check Cortex-Mx ID */
812 if (HAL_GetCurrentCPUID () == CM7_CPUID)
813 {
814 /* Check PWR EXTI D1 flag */
815 if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
816 {
817 /* Clear PWR EXTI D1 pending bit */
818 __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
819
820 /* PWR PVD interrupt user callback */
821 HAL_PWR_PVDCallback ();
822 }
823 }
824 else
825 {
826 /* Check PWR EXTI D2 flag */
827 if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
828 {
829 /* Clear PWR EXTI D2 pending bit */
830 __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
831
832 /* PWR PVD interrupt user callback */
833 HAL_PWR_PVDCallback ();
834 }
835 }
836 #else /* Single core devices */
837 /* PVD EXTI line interrupt detected */
838 if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
839 {
840 /* Clear PWR EXTI pending bit */
841 __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
842
843 /* PWR PVD interrupt user callback */
844 HAL_PWR_PVDCallback ();
845 }
846 #endif /* defined (DUAL_CORE) */
847 }
848
849 /**
850 * @brief PWR PVD interrupt callback.
851 * @retval None.
852 */
853 __weak void HAL_PWR_PVDCallback (void)
854 {
855 /* NOTE : This function should not be modified, when the callback is needed,
856 the HAL_PWR_PVDCallback can be implemented in the user file
857 */
858 }
859
860 /**
861 * @}
862 */
863
864 /**
865 * @}
866 */
867
868 #endif /* HAL_PWR_MODULE_ENABLED */
869 /**
870 * @}
871 */
872
873 /**
874 * @}
875 */
876
877 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/