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FIX: Flash page size check is STM (or clone) specific (#14130)
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_spi.c
blob3573de53028e7d73480f297f3f7756f9e3f5358e
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_spi.h"
23 #include "stm32h7xx_ll_bus.h"
24 #include "stm32h7xx_ll_rcc.h"
25 #ifdef GENERATOR_I2S_PRESENT
26 #include "stm32h7xx_ll_rcc.h"
27 #endif /* GENERATOR_I2S_PRESENT*/
28
29 /** @addtogroup STM32H7xx_LL_Driver
30 * @{
31 */
32
33 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
34
35 /** @addtogroup SPI_LL
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup SPI_LL_Private_Macros
44 * @{
45 */
46
47 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
48 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
49
50 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) \
51 || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) \
52 || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) \
53 || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) \
54 || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) \
55 || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) \
56 || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) \
57 || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) \
58 || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) \
59 || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) \
60 || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) \
61 || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) \
62 || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) \
63 || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) \
64 || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) \
65 || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
66
67 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) \
68 || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) \
69 || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) \
70 || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) \
71 || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) \
72 || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) \
73 || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) \
74 || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) \
75 || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) \
76 || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) \
77 || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) \
78 || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) \
79 || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) \
80 || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) \
81 || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) \
82 || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
83
84 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) \
85 || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
86
87 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) \
88 || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
89
90 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \
91 || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) \
92 || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
93
94 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \
95 || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) \
96 || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
97
98 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) \
99 || ((__VALUE__) == LL_SPI_PROTOCOL_TI))
100
101 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
102 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
103
104 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
105 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
106
107 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
108 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
109 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
110 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
111 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
112 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
113 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
114 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
115
116 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
117 || ((__VALUE__) == LL_SPI_MSB_FIRST))
118
119 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
120 || ((__VALUE__) == LL_SPI_SIMPLEX_TX) \
121 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
122 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
123 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
124
125 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
126 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
127 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
128 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
129 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
130 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
131 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
132 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
133 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
134 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
135 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
136 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
137 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) \
138 || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) \
139 || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) \
140 || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) \
141 || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) \
142 || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) \
143 || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) \
144 || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) \
145 || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) \
146 || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) \
147 || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) \
148 || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) \
149 || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) \
150 || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) \
151 || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) \
152 || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) \
153 || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
154
155 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) \
156 || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) \
157 || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) \
158 || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) \
159 || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) \
160 || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) \
161 || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) \
162 || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) \
163 || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) \
164 || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) \
165 || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) \
166 || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) \
167 || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) \
168 || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) \
169 || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) \
170 || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
171
172 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) \
173 || ((__VALUE__) == LL_SPI_CRC_5BIT) \
174 || ((__VALUE__) == LL_SPI_CRC_6BIT) \
175 || ((__VALUE__) == LL_SPI_CRC_7BIT) \
176 || ((__VALUE__) == LL_SPI_CRC_8BIT) \
177 || ((__VALUE__) == LL_SPI_CRC_9BIT) \
178 || ((__VALUE__) == LL_SPI_CRC_10BIT) \
179 || ((__VALUE__) == LL_SPI_CRC_11BIT) \
180 || ((__VALUE__) == LL_SPI_CRC_12BIT) \
181 || ((__VALUE__) == LL_SPI_CRC_13BIT) \
182 || ((__VALUE__) == LL_SPI_CRC_14BIT) \
183 || ((__VALUE__) == LL_SPI_CRC_15BIT) \
184 || ((__VALUE__) == LL_SPI_CRC_16BIT) \
185 || ((__VALUE__) == LL_SPI_CRC_17BIT) \
186 || ((__VALUE__) == LL_SPI_CRC_18BIT) \
187 || ((__VALUE__) == LL_SPI_CRC_19BIT) \
188 || ((__VALUE__) == LL_SPI_CRC_20BIT) \
189 || ((__VALUE__) == LL_SPI_CRC_21BIT) \
190 || ((__VALUE__) == LL_SPI_CRC_22BIT) \
191 || ((__VALUE__) == LL_SPI_CRC_23BIT) \
192 || ((__VALUE__) == LL_SPI_CRC_24BIT) \
193 || ((__VALUE__) == LL_SPI_CRC_25BIT) \
194 || ((__VALUE__) == LL_SPI_CRC_26BIT) \
195 || ((__VALUE__) == LL_SPI_CRC_27BIT) \
196 || ((__VALUE__) == LL_SPI_CRC_28BIT) \
197 || ((__VALUE__) == LL_SPI_CRC_29BIT) \
198 || ((__VALUE__) == LL_SPI_CRC_30BIT) \
199 || ((__VALUE__) == LL_SPI_CRC_31BIT) \
200 || ((__VALUE__) == LL_SPI_CRC_32BIT))
201
202 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
203 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
204 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
205
206 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) \
207 || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) \
208 || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) \
209 || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
210
211 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
212 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
213
214 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
215
216 /**
217 * @}
218 */
219
220 /* Private function prototypes -----------------------------------------------*/
221
222 /* Exported functions --------------------------------------------------------*/
223 /** @addtogroup SPI_LL_Exported_Functions
224 * @{
225 */
226
227 /** @addtogroup SPI_LL_EF_Init
228 * @{
229 */
230
231 /**
232 * @brief De-initialize the SPI registers to their default reset values.
233 * @param SPIx SPI Instance
234 * @retval An ErrorStatus enumeration value:
235 * - SUCCESS: SPI registers are de-initialized
236 * - ERROR: SPI registers are not de-initialized
237 */
238 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
239 {
240 ErrorStatus status = ERROR;
241
242 /* Check the parameters */
243 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
244
245 #if defined(SPI1)
246 if (SPIx == SPI1)
247 {
248 /* Force reset of SPI clock */
249 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
250
251 /* Release reset of SPI clock */
252 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
253
254 status = SUCCESS;
255 }
256 #endif /* SPI1 */
257 #if defined(SPI2)
258 if (SPIx == SPI2)
259 {
260 /* Force reset of SPI clock */
261 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
262
263 /* Release reset of SPI clock */
264 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
265
266 status = SUCCESS;
267 }
268 #endif /* SPI2 */
269 #if defined(SPI3)
270 if (SPIx == SPI3)
271 {
272 /* Force reset of SPI clock */
273 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
274
275 /* Release reset of SPI clock */
276 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
277
278 status = SUCCESS;
279 }
280 #endif /* SPI3 */
281 #if defined(SPI4)
282 if (SPIx == SPI4)
283 {
284 /* Force reset of SPI clock */
285 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
286
287 /* Release reset of SPI clock */
288 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
289
290 status = SUCCESS;
291 }
292 #endif /* SPI4 */
293 #if defined(SPI5)
294 if (SPIx == SPI5)
295 {
296 /* Force reset of SPI clock */
297 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
298
299 /* Release reset of SPI clock */
300 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
301
302 status = SUCCESS;
303 }
304 #endif /* SPI5 */
305 #if defined(SPI6)
306 if (SPIx == SPI6)
307 {
308 /* Force reset of SPI clock */
309 LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6);
310
311 /* Release reset of SPI clock */
312 LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
313
314 status = SUCCESS;
315 }
316 #endif /* SPI6 */
317
318 return status;
319 }
320
321 /**
322 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
323 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
324 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
325 * @param SPIx SPI Instance
326 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
327 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
328 */
329 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
330 {
331 ErrorStatus status = ERROR;
332 uint32_t tmp_nss;
333 uint32_t tmp_mode;
334
335 /* Check the SPI Instance SPIx*/
336 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
337
338 /* Check the SPI parameters from SPI_InitStruct*/
339 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
340 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
341 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
342 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
343 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
344 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
345 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
346 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
347 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
348
349 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
350 {
351 /*---------------------------- SPIx CFG1 Configuration ------------------------
352 * Configure SPIx CFG1 with parameters:
353 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits
354 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
355 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
356 */
357 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
358 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
359
360 tmp_nss = SPI_InitStruct->NSS;
361 tmp_mode = SPI_InitStruct->Mode;
362
363 /* Checks to setup Internal SS signal level and avoid a MODF Error */
364 if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_MASTER))
365 {
366 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
367 }
368
369 /*---------------------------- SPIx CFG2 Configuration ------------------------
370 * Configure SPIx CFG2 with parameters:
371 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
372 * - ClockPolarity : SPI_CFG2_CPOL bit
373 * - ClockPhase : SPI_CFG2_CPHA bit
374 * - BitOrder : SPI_CFG2_LSBFRST bit
375 * - Master/Slave Mode : SPI_CFG2_MASTER bit
376 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
377 */
378 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
379 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
380 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
381 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
382 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
383 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
384
385 /*---------------------------- SPIx CR1 Configuration ------------------------
386 * Configure SPIx CR1 with parameter:
387 * - Half Duplex Direction : SPI_CR1_HDDIR bit
388 */
389 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
390
391 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
392 * Configure SPIx CRCPOLY with parameter:
393 * - CRCPoly : CRCPOLY[31:0] bits
394 */
395 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
396 {
397 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
398 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
399 }
400
401 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
402 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
403
404 status = SUCCESS;
405 }
406
407 return status;
408 }
409
410 /**
411 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
412 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
413 * whose fields will be set to default values.
414 * @retval None
415 */
416 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
417 {
418 /* Set SPI_InitStruct fields to default values */
419 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
420 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
421 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
422 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
423 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
424 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
425 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
426 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
427 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
428 SPI_InitStruct->CRCPoly = 7UL;
429 }
430
431 /**
432 * @}
433 */
434
435 /**
436 * @}
437 */
438
439 /**
440 * @}
441 */
442
443 /** @addtogroup I2S_LL
444 * @{
445 */
446
447 /* Private types -------------------------------------------------------------*/
448 /* Private variables ---------------------------------------------------------*/
449 /* Private constants ---------------------------------------------------------*/
450 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
451 * @{
452 */
453 /* I2S registers Masks */
454 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
455 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \
456 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \
457 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
458
459 /**
460 * @}
461 */
462 /* Private macros ------------------------------------------------------------*/
463 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
464 * @{
465 */
466
467 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
468 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
469 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
470 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \
471 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
472
473 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) \
474 || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
475
476 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
477 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
478
479 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
480 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
481 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
482 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
483 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
484
485 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
486 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
487 || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) \
488 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
489 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX) \
490 || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
491
492 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
493 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
494
495 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
496 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
497 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
498
499 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
500
501 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
502 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
503
504 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) \
505 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) \
506 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) \
507 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) \
508 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) \
509 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) \
510 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) \
511 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
512
513 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) \
514 || ((__VALUE__) == LL_I2S_MSB_FIRST))
515 /**
516 * @}
517 */
518
519 /* Private function prototypes -----------------------------------------------*/
520
521 /* Exported functions --------------------------------------------------------*/
522 /** @addtogroup I2S_LL_Exported_Functions
523 * @{
524 */
525
526 /** @addtogroup I2S_LL_EF_Init
527 * @{
528 */
529
530 /**
531 * @brief De-initialize the SPI/I2S registers to their default reset values.
532 * @param SPIx SPI Instance
533 * @retval An ErrorStatus enumeration value:
534 * - SUCCESS: SPI registers are de-initialized
535 * - ERROR: SPI registers are not de-initialized
536 */
537 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
538 {
539 return LL_SPI_DeInit(SPIx);
540 }
541
542 /**
543 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
544 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
545 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
546 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
547 * @param SPIx SPI Instance
548 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
549 * @retval An ErrorStatus enumeration value:
550 * - SUCCESS: SPI registers are Initialized
551 * - ERROR: SPI registers are not Initialized
552 */
553 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
554 {
555 uint32_t i2sdiv = 0UL, i2sodd = 0UL, packetlength = 1UL, ispcm = 0UL;
556 uint32_t tmp;
557 uint32_t sourceclock;
558 ErrorStatus status = ERROR;
559
560 /* Check the I2S parameters */
561 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
562 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
563 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
564 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
565 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
566 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
567 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
568
569 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
570 * In this case, it is useless to check if the I2SMOD bit is set to 0 because
571 * this bit I2SMOD only serves to select the desired mode.
572 */
573 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
574 {
575 /*---------------------------- SPIx I2SCFGR Configuration --------------------
576 * Configure SPIx I2SCFGR with parameters:
577 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits
578 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
579 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
580 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit
581 * - MCLKOutput : SPI_I2SPR_MCKOE bit
582 * - I2S mode : SPI_I2SCFGR_I2SMOD bit
583 */
584
585 /* Write to SPIx I2SCFGR */
586 MODIFY_REG(SPIx->I2SCFGR,
587 I2S_I2SCFGR_CLEAR_MASK,
588 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
589 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
590 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
591
592 /*---------------------------- SPIx I2SCFGR Configuration ----------------------
593 * Configure SPIx I2SCFGR with parameters:
594 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
595 */
596
597 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
598 * else, default values are used: i2sodd = 0U, i2sdiv = 0U.
599 */
600 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
601 {
602 /* Check the frame length (For the Prescaler computing)
603 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
604 */
605 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
606 {
607 /* Packet length is 32 bits */
608 packetlength = 2UL;
609 }
610
611 /* Check if PCM standard is used */
612 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
613 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
614 {
615 ispcm = 1UL;
616 }
617
618 /* Get the I2S (SPI) source clock value */
619 #if defined (SPI_SPI6I2S_SUPPORT)
620 if (SPIx == SPI6)
621 {
622 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
623 }
624 else
625 {
626 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
627 }
628 #else
629 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
630 #endif
631
632 /* Compute the Real divider depending on the MCLK output state with a fixed point */
633 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
634 {
635 /* MCLK output is enabled */
636 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
637 }
638 else
639 {
640 /* MCLK output is disabled */
641 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
642 }
643
644 /* Remove the fixed point */
645 tmp = tmp / 16UL;
646
647 /* Check the parity of the divider */
648 i2sodd = tmp & 0x1UL;
649
650 /* Compute the i2sdiv prescaler */
651 i2sdiv = tmp / 2UL;
652 }
653
654 /* Test if the obtain values are forbiden or out of range */
655 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
656 {
657 /* Set the default values */
658 i2sdiv = 0UL;
659 i2sodd = 0UL;
660 }
661
662 /* Write to SPIx I2SCFGR register the computed value */
663 MODIFY_REG(SPIx->I2SCFGR,
664 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV,
665 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
666
667 status = SUCCESS;
668 }
669
670 return status;
671 }
672
673 /**
674 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
675 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
676 * whose fields will be set to default values.
677 * @retval None
678 */
679 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
680 {
681 /*--------------- Reset I2S init structure parameters values -----------------*/
682 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
683 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
684 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
685 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
686 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
687 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
688 }
689
690 /**
691 * @brief Set linear and parity prescaler.
692 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
693 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
694 * @param SPIx SPI Instance
695 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
696 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
697 * @param PrescalerParity This parameter can be one of the following values:
698 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
699 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
700 * @retval None
701 */
702 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
703 {
704 /* Check the I2S parameters */
705 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
706 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
707 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
708
709 /* Write to SPIx I2SPR */
710 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
711 (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
712 }
713
714 /**
715 * @}
716 */
717
718 /**
719 * @}
720 */
721
722 /**
723 * @}
724 */
725
726 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
727
728 /**
729 * @}
730 */
731 #endif /* USE_FULL_LL_DRIVER */
732
733 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/