lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb.h

   1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
   2
   3 /**
   4  * Copyright (c) 2024 Raspberry Pi Ltd.
   5  *
   6  * SPDX-License-Identifier: BSD-3-Clause
   7  */
   8 // =============================================================================
   9 // Register block : USB
  10 // Version        : 1
  11 // Bus type       : ahbl
  12 // Description    : USB FS/LS controller device registers
  13 // =============================================================================
  14 #ifndef _HARDWARE_REGS_USB_H
  15 #define _HARDWARE_REGS_USB_H
  16 // =============================================================================
  17 // Register    : USB_ADDR_ENDP
  18 // Description : Device address and endpoint control
  19 #define USB_ADDR_ENDP_OFFSET _u(0x00000000)
  20 #define USB_ADDR_ENDP_BITS   _u(0x000f007f)
  21 #define USB_ADDR_ENDP_RESET  _u(0x00000000)
  22 // -----------------------------------------------------------------------------
  23 // Field       : USB_ADDR_ENDP_ENDPOINT
  24 // Description : Device endpoint to send data to. Only valid for HOST mode.
  25 #define USB_ADDR_ENDP_ENDPOINT_RESET  _u(0x0)
  26 #define USB_ADDR_ENDP_ENDPOINT_BITS   _u(0x000f0000)
  27 #define USB_ADDR_ENDP_ENDPOINT_MSB    _u(19)
  28 #define USB_ADDR_ENDP_ENDPOINT_LSB    _u(16)
  29 #define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW"
  30 // -----------------------------------------------------------------------------
  31 // Field       : USB_ADDR_ENDP_ADDRESS
  32 // Description : In device mode, the address that the device should respond to.
  33 //               Set in response to a SET_ADDR setup packet from the host. In
  34 //               host mode set to the address of the device to communicate with.
  35 #define USB_ADDR_ENDP_ADDRESS_RESET  _u(0x00)
  36 #define USB_ADDR_ENDP_ADDRESS_BITS   _u(0x0000007f)
  37 #define USB_ADDR_ENDP_ADDRESS_MSB    _u(6)
  38 #define USB_ADDR_ENDP_ADDRESS_LSB    _u(0)
  39 #define USB_ADDR_ENDP_ADDRESS_ACCESS "RW"
  40 // =============================================================================
  41 // Register    : USB_ADDR_ENDP1
  42 // Description : Interrupt endpoint 1. Only valid for HOST mode.
  43 #define USB_ADDR_ENDP1_OFFSET _u(0x00000004)
  44 #define USB_ADDR_ENDP1_BITS   _u(0x060f007f)
  45 #define USB_ADDR_ENDP1_RESET  _u(0x00000000)
  46 // -----------------------------------------------------------------------------
  47 // Field       : USB_ADDR_ENDP1_INTEP_PREAMBLE
  48 // Description : Interrupt EP requires preamble (is a low speed device on a full
  49 //               speed hub)
  50 #define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET  _u(0x0)
  51 #define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS   _u(0x04000000)
  52 #define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB    _u(26)
  53 #define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB    _u(26)
  54 #define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW"
  55 // -----------------------------------------------------------------------------
  56 // Field       : USB_ADDR_ENDP1_INTEP_DIR
  57 // Description : Direction of the interrupt endpoint. In=0, Out=1
  58 #define USB_ADDR_ENDP1_INTEP_DIR_RESET  _u(0x0)
  59 #define USB_ADDR_ENDP1_INTEP_DIR_BITS   _u(0x02000000)
  60 #define USB_ADDR_ENDP1_INTEP_DIR_MSB    _u(25)
  61 #define USB_ADDR_ENDP1_INTEP_DIR_LSB    _u(25)
  62 #define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW"
  63 // -----------------------------------------------------------------------------
  64 // Field       : USB_ADDR_ENDP1_ENDPOINT
  65 // Description : Endpoint number of the interrupt endpoint
  66 #define USB_ADDR_ENDP1_ENDPOINT_RESET  _u(0x0)
  67 #define USB_ADDR_ENDP1_ENDPOINT_BITS   _u(0x000f0000)
  68 #define USB_ADDR_ENDP1_ENDPOINT_MSB    _u(19)
  69 #define USB_ADDR_ENDP1_ENDPOINT_LSB    _u(16)
  70 #define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW"
  71 // -----------------------------------------------------------------------------
  72 // Field       : USB_ADDR_ENDP1_ADDRESS
  73 // Description : Device address
  74 #define USB_ADDR_ENDP1_ADDRESS_RESET  _u(0x00)
  75 #define USB_ADDR_ENDP1_ADDRESS_BITS   _u(0x0000007f)
  76 #define USB_ADDR_ENDP1_ADDRESS_MSB    _u(6)
  77 #define USB_ADDR_ENDP1_ADDRESS_LSB    _u(0)
  78 #define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW"
  79 // =============================================================================
  80 // Register    : USB_ADDR_ENDP2
  81 // Description : Interrupt endpoint 2. Only valid for HOST mode.
  82 #define USB_ADDR_ENDP2_OFFSET _u(0x00000008)
  83 #define USB_ADDR_ENDP2_BITS   _u(0x060f007f)
  84 #define USB_ADDR_ENDP2_RESET  _u(0x00000000)
  85 // -----------------------------------------------------------------------------
  86 // Field       : USB_ADDR_ENDP2_INTEP_PREAMBLE
  87 // Description : Interrupt EP requires preamble (is a low speed device on a full
  88 //               speed hub)
  89 #define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET  _u(0x0)
  90 #define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS   _u(0x04000000)
  91 #define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB    _u(26)
  92 #define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB    _u(26)
  93 #define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW"
  94 // -----------------------------------------------------------------------------
  95 // Field       : USB_ADDR_ENDP2_INTEP_DIR
  96 // Description : Direction of the interrupt endpoint. In=0, Out=1
  97 #define USB_ADDR_ENDP2_INTEP_DIR_RESET  _u(0x0)
  98 #define USB_ADDR_ENDP2_INTEP_DIR_BITS   _u(0x02000000)
  99 #define USB_ADDR_ENDP2_INTEP_DIR_MSB    _u(25)
 100 #define USB_ADDR_ENDP2_INTEP_DIR_LSB    _u(25)
 101 #define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW"
 102 // -----------------------------------------------------------------------------
 103 // Field       : USB_ADDR_ENDP2_ENDPOINT
 104 // Description : Endpoint number of the interrupt endpoint
 105 #define USB_ADDR_ENDP2_ENDPOINT_RESET  _u(0x0)
 106 #define USB_ADDR_ENDP2_ENDPOINT_BITS   _u(0x000f0000)
 107 #define USB_ADDR_ENDP2_ENDPOINT_MSB    _u(19)
 108 #define USB_ADDR_ENDP2_ENDPOINT_LSB    _u(16)
 109 #define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW"
 110 // -----------------------------------------------------------------------------
 111 // Field       : USB_ADDR_ENDP2_ADDRESS
 112 // Description : Device address
 113 #define USB_ADDR_ENDP2_ADDRESS_RESET  _u(0x00)
 114 #define USB_ADDR_ENDP2_ADDRESS_BITS   _u(0x0000007f)
 115 #define USB_ADDR_ENDP2_ADDRESS_MSB    _u(6)
 116 #define USB_ADDR_ENDP2_ADDRESS_LSB    _u(0)
 117 #define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW"
 118 // =============================================================================
 119 // Register    : USB_ADDR_ENDP3
 120 // Description : Interrupt endpoint 3. Only valid for HOST mode.
 121 #define USB_ADDR_ENDP3_OFFSET _u(0x0000000c)
 122 #define USB_ADDR_ENDP3_BITS   _u(0x060f007f)
 123 #define USB_ADDR_ENDP3_RESET  _u(0x00000000)
 124 // -----------------------------------------------------------------------------
 125 // Field       : USB_ADDR_ENDP3_INTEP_PREAMBLE
 126 // Description : Interrupt EP requires preamble (is a low speed device on a full
 127 //               speed hub)
 128 #define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET  _u(0x0)
 129 #define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS   _u(0x04000000)
 130 #define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB    _u(26)
 131 #define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB    _u(26)
 132 #define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW"
 133 // -----------------------------------------------------------------------------
 134 // Field       : USB_ADDR_ENDP3_INTEP_DIR
 135 // Description : Direction of the interrupt endpoint. In=0, Out=1
 136 #define USB_ADDR_ENDP3_INTEP_DIR_RESET  _u(0x0)
 137 #define USB_ADDR_ENDP3_INTEP_DIR_BITS   _u(0x02000000)
 138 #define USB_ADDR_ENDP3_INTEP_DIR_MSB    _u(25)
 139 #define USB_ADDR_ENDP3_INTEP_DIR_LSB    _u(25)
 140 #define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW"
 141 // -----------------------------------------------------------------------------
 142 // Field       : USB_ADDR_ENDP3_ENDPOINT
 143 // Description : Endpoint number of the interrupt endpoint
 144 #define USB_ADDR_ENDP3_ENDPOINT_RESET  _u(0x0)
 145 #define USB_ADDR_ENDP3_ENDPOINT_BITS   _u(0x000f0000)
 146 #define USB_ADDR_ENDP3_ENDPOINT_MSB    _u(19)
 147 #define USB_ADDR_ENDP3_ENDPOINT_LSB    _u(16)
 148 #define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW"
 149 // -----------------------------------------------------------------------------
 150 // Field       : USB_ADDR_ENDP3_ADDRESS
 151 // Description : Device address
 152 #define USB_ADDR_ENDP3_ADDRESS_RESET  _u(0x00)
 153 #define USB_ADDR_ENDP3_ADDRESS_BITS   _u(0x0000007f)
 154 #define USB_ADDR_ENDP3_ADDRESS_MSB    _u(6)
 155 #define USB_ADDR_ENDP3_ADDRESS_LSB    _u(0)
 156 #define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW"
 157 // =============================================================================
 158 // Register    : USB_ADDR_ENDP4
 159 // Description : Interrupt endpoint 4. Only valid for HOST mode.
 160 #define USB_ADDR_ENDP4_OFFSET _u(0x00000010)
 161 #define USB_ADDR_ENDP4_BITS   _u(0x060f007f)
 162 #define USB_ADDR_ENDP4_RESET  _u(0x00000000)
 163 // -----------------------------------------------------------------------------
 164 // Field       : USB_ADDR_ENDP4_INTEP_PREAMBLE
 165 // Description : Interrupt EP requires preamble (is a low speed device on a full
 166 //               speed hub)
 167 #define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET  _u(0x0)
 168 #define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS   _u(0x04000000)
 169 #define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB    _u(26)
 170 #define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB    _u(26)
 171 #define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW"
 172 // -----------------------------------------------------------------------------
 173 // Field       : USB_ADDR_ENDP4_INTEP_DIR
 174 // Description : Direction of the interrupt endpoint. In=0, Out=1
 175 #define USB_ADDR_ENDP4_INTEP_DIR_RESET  _u(0x0)
 176 #define USB_ADDR_ENDP4_INTEP_DIR_BITS   _u(0x02000000)
 177 #define USB_ADDR_ENDP4_INTEP_DIR_MSB    _u(25)
 178 #define USB_ADDR_ENDP4_INTEP_DIR_LSB    _u(25)
 179 #define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW"
 180 // -----------------------------------------------------------------------------
 181 // Field       : USB_ADDR_ENDP4_ENDPOINT
 182 // Description : Endpoint number of the interrupt endpoint
 183 #define USB_ADDR_ENDP4_ENDPOINT_RESET  _u(0x0)
 184 #define USB_ADDR_ENDP4_ENDPOINT_BITS   _u(0x000f0000)
 185 #define USB_ADDR_ENDP4_ENDPOINT_MSB    _u(19)
 186 #define USB_ADDR_ENDP4_ENDPOINT_LSB    _u(16)
 187 #define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW"
 188 // -----------------------------------------------------------------------------
 189 // Field       : USB_ADDR_ENDP4_ADDRESS
 190 // Description : Device address
 191 #define USB_ADDR_ENDP4_ADDRESS_RESET  _u(0x00)
 192 #define USB_ADDR_ENDP4_ADDRESS_BITS   _u(0x0000007f)
 193 #define USB_ADDR_ENDP4_ADDRESS_MSB    _u(6)
 194 #define USB_ADDR_ENDP4_ADDRESS_LSB    _u(0)
 195 #define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW"
 196 // =============================================================================
 197 // Register    : USB_ADDR_ENDP5
 198 // Description : Interrupt endpoint 5. Only valid for HOST mode.
 199 #define USB_ADDR_ENDP5_OFFSET _u(0x00000014)
 200 #define USB_ADDR_ENDP5_BITS   _u(0x060f007f)
 201 #define USB_ADDR_ENDP5_RESET  _u(0x00000000)
 202 // -----------------------------------------------------------------------------
 203 // Field       : USB_ADDR_ENDP5_INTEP_PREAMBLE
 204 // Description : Interrupt EP requires preamble (is a low speed device on a full
 205 //               speed hub)
 206 #define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET  _u(0x0)
 207 #define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS   _u(0x04000000)
 208 #define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB    _u(26)
 209 #define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB    _u(26)
 210 #define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW"
 211 // -----------------------------------------------------------------------------
 212 // Field       : USB_ADDR_ENDP5_INTEP_DIR
 213 // Description : Direction of the interrupt endpoint. In=0, Out=1
 214 #define USB_ADDR_ENDP5_INTEP_DIR_RESET  _u(0x0)
 215 #define USB_ADDR_ENDP5_INTEP_DIR_BITS   _u(0x02000000)
 216 #define USB_ADDR_ENDP5_INTEP_DIR_MSB    _u(25)
 217 #define USB_ADDR_ENDP5_INTEP_DIR_LSB    _u(25)
 218 #define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW"
 219 // -----------------------------------------------------------------------------
 220 // Field       : USB_ADDR_ENDP5_ENDPOINT
 221 // Description : Endpoint number of the interrupt endpoint
 222 #define USB_ADDR_ENDP5_ENDPOINT_RESET  _u(0x0)
 223 #define USB_ADDR_ENDP5_ENDPOINT_BITS   _u(0x000f0000)
 224 #define USB_ADDR_ENDP5_ENDPOINT_MSB    _u(19)
 225 #define USB_ADDR_ENDP5_ENDPOINT_LSB    _u(16)
 226 #define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW"
 227 // -----------------------------------------------------------------------------
 228 // Field       : USB_ADDR_ENDP5_ADDRESS
 229 // Description : Device address
 230 #define USB_ADDR_ENDP5_ADDRESS_RESET  _u(0x00)
 231 #define USB_ADDR_ENDP5_ADDRESS_BITS   _u(0x0000007f)
 232 #define USB_ADDR_ENDP5_ADDRESS_MSB    _u(6)
 233 #define USB_ADDR_ENDP5_ADDRESS_LSB    _u(0)
 234 #define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW"
 235 // =============================================================================
 236 // Register    : USB_ADDR_ENDP6
 237 // Description : Interrupt endpoint 6. Only valid for HOST mode.
 238 #define USB_ADDR_ENDP6_OFFSET _u(0x00000018)
 239 #define USB_ADDR_ENDP6_BITS   _u(0x060f007f)
 240 #define USB_ADDR_ENDP6_RESET  _u(0x00000000)
 241 // -----------------------------------------------------------------------------
 242 // Field       : USB_ADDR_ENDP6_INTEP_PREAMBLE
 243 // Description : Interrupt EP requires preamble (is a low speed device on a full
 244 //               speed hub)
 245 #define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET  _u(0x0)
 246 #define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS   _u(0x04000000)
 247 #define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB    _u(26)
 248 #define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB    _u(26)
 249 #define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW"
 250 // -----------------------------------------------------------------------------
 251 // Field       : USB_ADDR_ENDP6_INTEP_DIR
 252 // Description : Direction of the interrupt endpoint. In=0, Out=1
 253 #define USB_ADDR_ENDP6_INTEP_DIR_RESET  _u(0x0)
 254 #define USB_ADDR_ENDP6_INTEP_DIR_BITS   _u(0x02000000)
 255 #define USB_ADDR_ENDP6_INTEP_DIR_MSB    _u(25)
 256 #define USB_ADDR_ENDP6_INTEP_DIR_LSB    _u(25)
 257 #define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW"
 258 // -----------------------------------------------------------------------------
 259 // Field       : USB_ADDR_ENDP6_ENDPOINT
 260 // Description : Endpoint number of the interrupt endpoint
 261 #define USB_ADDR_ENDP6_ENDPOINT_RESET  _u(0x0)
 262 #define USB_ADDR_ENDP6_ENDPOINT_BITS   _u(0x000f0000)
 263 #define USB_ADDR_ENDP6_ENDPOINT_MSB    _u(19)
 264 #define USB_ADDR_ENDP6_ENDPOINT_LSB    _u(16)
 265 #define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW"
 266 // -----------------------------------------------------------------------------
 267 // Field       : USB_ADDR_ENDP6_ADDRESS
 268 // Description : Device address
 269 #define USB_ADDR_ENDP6_ADDRESS_RESET  _u(0x00)
 270 #define USB_ADDR_ENDP6_ADDRESS_BITS   _u(0x0000007f)
 271 #define USB_ADDR_ENDP6_ADDRESS_MSB    _u(6)
 272 #define USB_ADDR_ENDP6_ADDRESS_LSB    _u(0)
 273 #define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW"
 274 // =============================================================================
 275 // Register    : USB_ADDR_ENDP7
 276 // Description : Interrupt endpoint 7. Only valid for HOST mode.
 277 #define USB_ADDR_ENDP7_OFFSET _u(0x0000001c)
 278 #define USB_ADDR_ENDP7_BITS   _u(0x060f007f)
 279 #define USB_ADDR_ENDP7_RESET  _u(0x00000000)
 280 // -----------------------------------------------------------------------------
 281 // Field       : USB_ADDR_ENDP7_INTEP_PREAMBLE
 282 // Description : Interrupt EP requires preamble (is a low speed device on a full
 283 //               speed hub)
 284 #define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET  _u(0x0)
 285 #define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS   _u(0x04000000)
 286 #define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB    _u(26)
 287 #define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB    _u(26)
 288 #define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW"
 289 // -----------------------------------------------------------------------------
 290 // Field       : USB_ADDR_ENDP7_INTEP_DIR
 291 // Description : Direction of the interrupt endpoint. In=0, Out=1
 292 #define USB_ADDR_ENDP7_INTEP_DIR_RESET  _u(0x0)
 293 #define USB_ADDR_ENDP7_INTEP_DIR_BITS   _u(0x02000000)
 294 #define USB_ADDR_ENDP7_INTEP_DIR_MSB    _u(25)
 295 #define USB_ADDR_ENDP7_INTEP_DIR_LSB    _u(25)
 296 #define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW"
 297 // -----------------------------------------------------------------------------
 298 // Field       : USB_ADDR_ENDP7_ENDPOINT
 299 // Description : Endpoint number of the interrupt endpoint
 300 #define USB_ADDR_ENDP7_ENDPOINT_RESET  _u(0x0)
 301 #define USB_ADDR_ENDP7_ENDPOINT_BITS   _u(0x000f0000)
 302 #define USB_ADDR_ENDP7_ENDPOINT_MSB    _u(19)
 303 #define USB_ADDR_ENDP7_ENDPOINT_LSB    _u(16)
 304 #define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW"
 305 // -----------------------------------------------------------------------------
 306 // Field       : USB_ADDR_ENDP7_ADDRESS
 307 // Description : Device address
 308 #define USB_ADDR_ENDP7_ADDRESS_RESET  _u(0x00)
 309 #define USB_ADDR_ENDP7_ADDRESS_BITS   _u(0x0000007f)
 310 #define USB_ADDR_ENDP7_ADDRESS_MSB    _u(6)
 311 #define USB_ADDR_ENDP7_ADDRESS_LSB    _u(0)
 312 #define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW"
 313 // =============================================================================
 314 // Register    : USB_ADDR_ENDP8
 315 // Description : Interrupt endpoint 8. Only valid for HOST mode.
 316 #define USB_ADDR_ENDP8_OFFSET _u(0x00000020)
 317 #define USB_ADDR_ENDP8_BITS   _u(0x060f007f)
 318 #define USB_ADDR_ENDP8_RESET  _u(0x00000000)
 319 // -----------------------------------------------------------------------------
 320 // Field       : USB_ADDR_ENDP8_INTEP_PREAMBLE
 321 // Description : Interrupt EP requires preamble (is a low speed device on a full
 322 //               speed hub)
 323 #define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET  _u(0x0)
 324 #define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS   _u(0x04000000)
 325 #define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB    _u(26)
 326 #define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB    _u(26)
 327 #define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW"
 328 // -----------------------------------------------------------------------------
 329 // Field       : USB_ADDR_ENDP8_INTEP_DIR
 330 // Description : Direction of the interrupt endpoint. In=0, Out=1
 331 #define USB_ADDR_ENDP8_INTEP_DIR_RESET  _u(0x0)
 332 #define USB_ADDR_ENDP8_INTEP_DIR_BITS   _u(0x02000000)
 333 #define USB_ADDR_ENDP8_INTEP_DIR_MSB    _u(25)
 334 #define USB_ADDR_ENDP8_INTEP_DIR_LSB    _u(25)
 335 #define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW"
 336 // -----------------------------------------------------------------------------
 337 // Field       : USB_ADDR_ENDP8_ENDPOINT
 338 // Description : Endpoint number of the interrupt endpoint
 339 #define USB_ADDR_ENDP8_ENDPOINT_RESET  _u(0x0)
 340 #define USB_ADDR_ENDP8_ENDPOINT_BITS   _u(0x000f0000)
 341 #define USB_ADDR_ENDP8_ENDPOINT_MSB    _u(19)
 342 #define USB_ADDR_ENDP8_ENDPOINT_LSB    _u(16)
 343 #define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW"
 344 // -----------------------------------------------------------------------------
 345 // Field       : USB_ADDR_ENDP8_ADDRESS
 346 // Description : Device address
 347 #define USB_ADDR_ENDP8_ADDRESS_RESET  _u(0x00)
 348 #define USB_ADDR_ENDP8_ADDRESS_BITS   _u(0x0000007f)
 349 #define USB_ADDR_ENDP8_ADDRESS_MSB    _u(6)
 350 #define USB_ADDR_ENDP8_ADDRESS_LSB    _u(0)
 351 #define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW"
 352 // =============================================================================
 353 // Register    : USB_ADDR_ENDP9
 354 // Description : Interrupt endpoint 9. Only valid for HOST mode.
 355 #define USB_ADDR_ENDP9_OFFSET _u(0x00000024)
 356 #define USB_ADDR_ENDP9_BITS   _u(0x060f007f)
 357 #define USB_ADDR_ENDP9_RESET  _u(0x00000000)
 358 // -----------------------------------------------------------------------------
 359 // Field       : USB_ADDR_ENDP9_INTEP_PREAMBLE
 360 // Description : Interrupt EP requires preamble (is a low speed device on a full
 361 //               speed hub)
 362 #define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET  _u(0x0)
 363 #define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS   _u(0x04000000)
 364 #define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB    _u(26)
 365 #define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB    _u(26)
 366 #define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW"
 367 // -----------------------------------------------------------------------------
 368 // Field       : USB_ADDR_ENDP9_INTEP_DIR
 369 // Description : Direction of the interrupt endpoint. In=0, Out=1
 370 #define USB_ADDR_ENDP9_INTEP_DIR_RESET  _u(0x0)
 371 #define USB_ADDR_ENDP9_INTEP_DIR_BITS   _u(0x02000000)
 372 #define USB_ADDR_ENDP9_INTEP_DIR_MSB    _u(25)
 373 #define USB_ADDR_ENDP9_INTEP_DIR_LSB    _u(25)
 374 #define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW"
 375 // -----------------------------------------------------------------------------
 376 // Field       : USB_ADDR_ENDP9_ENDPOINT
 377 // Description : Endpoint number of the interrupt endpoint
 378 #define USB_ADDR_ENDP9_ENDPOINT_RESET  _u(0x0)
 379 #define USB_ADDR_ENDP9_ENDPOINT_BITS   _u(0x000f0000)
 380 #define USB_ADDR_ENDP9_ENDPOINT_MSB    _u(19)
 381 #define USB_ADDR_ENDP9_ENDPOINT_LSB    _u(16)
 382 #define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW"
 383 // -----------------------------------------------------------------------------
 384 // Field       : USB_ADDR_ENDP9_ADDRESS
 385 // Description : Device address
 386 #define USB_ADDR_ENDP9_ADDRESS_RESET  _u(0x00)
 387 #define USB_ADDR_ENDP9_ADDRESS_BITS   _u(0x0000007f)
 388 #define USB_ADDR_ENDP9_ADDRESS_MSB    _u(6)
 389 #define USB_ADDR_ENDP9_ADDRESS_LSB    _u(0)
 390 #define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW"
 391 // =============================================================================
 392 // Register    : USB_ADDR_ENDP10
 393 // Description : Interrupt endpoint 10. Only valid for HOST mode.
 394 #define USB_ADDR_ENDP10_OFFSET _u(0x00000028)
 395 #define USB_ADDR_ENDP10_BITS   _u(0x060f007f)
 396 #define USB_ADDR_ENDP10_RESET  _u(0x00000000)
 397 // -----------------------------------------------------------------------------
 398 // Field       : USB_ADDR_ENDP10_INTEP_PREAMBLE
 399 // Description : Interrupt EP requires preamble (is a low speed device on a full
 400 //               speed hub)
 401 #define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET  _u(0x0)
 402 #define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS   _u(0x04000000)
 403 #define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB    _u(26)
 404 #define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB    _u(26)
 405 #define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW"
 406 // -----------------------------------------------------------------------------
 407 // Field       : USB_ADDR_ENDP10_INTEP_DIR
 408 // Description : Direction of the interrupt endpoint. In=0, Out=1
 409 #define USB_ADDR_ENDP10_INTEP_DIR_RESET  _u(0x0)
 410 #define USB_ADDR_ENDP10_INTEP_DIR_BITS   _u(0x02000000)
 411 #define USB_ADDR_ENDP10_INTEP_DIR_MSB    _u(25)
 412 #define USB_ADDR_ENDP10_INTEP_DIR_LSB    _u(25)
 413 #define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW"
 414 // -----------------------------------------------------------------------------
 415 // Field       : USB_ADDR_ENDP10_ENDPOINT
 416 // Description : Endpoint number of the interrupt endpoint
 417 #define USB_ADDR_ENDP10_ENDPOINT_RESET  _u(0x0)
 418 #define USB_ADDR_ENDP10_ENDPOINT_BITS   _u(0x000f0000)
 419 #define USB_ADDR_ENDP10_ENDPOINT_MSB    _u(19)
 420 #define USB_ADDR_ENDP10_ENDPOINT_LSB    _u(16)
 421 #define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW"
 422 // -----------------------------------------------------------------------------
 423 // Field       : USB_ADDR_ENDP10_ADDRESS
 424 // Description : Device address
 425 #define USB_ADDR_ENDP10_ADDRESS_RESET  _u(0x00)
 426 #define USB_ADDR_ENDP10_ADDRESS_BITS   _u(0x0000007f)
 427 #define USB_ADDR_ENDP10_ADDRESS_MSB    _u(6)
 428 #define USB_ADDR_ENDP10_ADDRESS_LSB    _u(0)
 429 #define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW"
 430 // =============================================================================
 431 // Register    : USB_ADDR_ENDP11
 432 // Description : Interrupt endpoint 11. Only valid for HOST mode.
 433 #define USB_ADDR_ENDP11_OFFSET _u(0x0000002c)
 434 #define USB_ADDR_ENDP11_BITS   _u(0x060f007f)
 435 #define USB_ADDR_ENDP11_RESET  _u(0x00000000)
 436 // -----------------------------------------------------------------------------
 437 // Field       : USB_ADDR_ENDP11_INTEP_PREAMBLE
 438 // Description : Interrupt EP requires preamble (is a low speed device on a full
 439 //               speed hub)
 440 #define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET  _u(0x0)
 441 #define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS   _u(0x04000000)
 442 #define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB    _u(26)
 443 #define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB    _u(26)
 444 #define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW"
 445 // -----------------------------------------------------------------------------
 446 // Field       : USB_ADDR_ENDP11_INTEP_DIR
 447 // Description : Direction of the interrupt endpoint. In=0, Out=1
 448 #define USB_ADDR_ENDP11_INTEP_DIR_RESET  _u(0x0)
 449 #define USB_ADDR_ENDP11_INTEP_DIR_BITS   _u(0x02000000)
 450 #define USB_ADDR_ENDP11_INTEP_DIR_MSB    _u(25)
 451 #define USB_ADDR_ENDP11_INTEP_DIR_LSB    _u(25)
 452 #define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW"
 453 // -----------------------------------------------------------------------------
 454 // Field       : USB_ADDR_ENDP11_ENDPOINT
 455 // Description : Endpoint number of the interrupt endpoint
 456 #define USB_ADDR_ENDP11_ENDPOINT_RESET  _u(0x0)
 457 #define USB_ADDR_ENDP11_ENDPOINT_BITS   _u(0x000f0000)
 458 #define USB_ADDR_ENDP11_ENDPOINT_MSB    _u(19)
 459 #define USB_ADDR_ENDP11_ENDPOINT_LSB    _u(16)
 460 #define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW"
 461 // -----------------------------------------------------------------------------
 462 // Field       : USB_ADDR_ENDP11_ADDRESS
 463 // Description : Device address
 464 #define USB_ADDR_ENDP11_ADDRESS_RESET  _u(0x00)
 465 #define USB_ADDR_ENDP11_ADDRESS_BITS   _u(0x0000007f)
 466 #define USB_ADDR_ENDP11_ADDRESS_MSB    _u(6)
 467 #define USB_ADDR_ENDP11_ADDRESS_LSB    _u(0)
 468 #define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW"
 469 // =============================================================================
 470 // Register    : USB_ADDR_ENDP12
 471 // Description : Interrupt endpoint 12. Only valid for HOST mode.
 472 #define USB_ADDR_ENDP12_OFFSET _u(0x00000030)
 473 #define USB_ADDR_ENDP12_BITS   _u(0x060f007f)
 474 #define USB_ADDR_ENDP12_RESET  _u(0x00000000)
 475 // -----------------------------------------------------------------------------
 476 // Field       : USB_ADDR_ENDP12_INTEP_PREAMBLE
 477 // Description : Interrupt EP requires preamble (is a low speed device on a full
 478 //               speed hub)
 479 #define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET  _u(0x0)
 480 #define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS   _u(0x04000000)
 481 #define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB    _u(26)
 482 #define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB    _u(26)
 483 #define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW"
 484 // -----------------------------------------------------------------------------
 485 // Field       : USB_ADDR_ENDP12_INTEP_DIR
 486 // Description : Direction of the interrupt endpoint. In=0, Out=1
 487 #define USB_ADDR_ENDP12_INTEP_DIR_RESET  _u(0x0)
 488 #define USB_ADDR_ENDP12_INTEP_DIR_BITS   _u(0x02000000)
 489 #define USB_ADDR_ENDP12_INTEP_DIR_MSB    _u(25)
 490 #define USB_ADDR_ENDP12_INTEP_DIR_LSB    _u(25)
 491 #define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW"
 492 // -----------------------------------------------------------------------------
 493 // Field       : USB_ADDR_ENDP12_ENDPOINT
 494 // Description : Endpoint number of the interrupt endpoint
 495 #define USB_ADDR_ENDP12_ENDPOINT_RESET  _u(0x0)
 496 #define USB_ADDR_ENDP12_ENDPOINT_BITS   _u(0x000f0000)
 497 #define USB_ADDR_ENDP12_ENDPOINT_MSB    _u(19)
 498 #define USB_ADDR_ENDP12_ENDPOINT_LSB    _u(16)
 499 #define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW"
 500 // -----------------------------------------------------------------------------
 501 // Field       : USB_ADDR_ENDP12_ADDRESS
 502 // Description : Device address
 503 #define USB_ADDR_ENDP12_ADDRESS_RESET  _u(0x00)
 504 #define USB_ADDR_ENDP12_ADDRESS_BITS   _u(0x0000007f)
 505 #define USB_ADDR_ENDP12_ADDRESS_MSB    _u(6)
 506 #define USB_ADDR_ENDP12_ADDRESS_LSB    _u(0)
 507 #define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW"
 508 // =============================================================================
 509 // Register    : USB_ADDR_ENDP13
 510 // Description : Interrupt endpoint 13. Only valid for HOST mode.
 511 #define USB_ADDR_ENDP13_OFFSET _u(0x00000034)
 512 #define USB_ADDR_ENDP13_BITS   _u(0x060f007f)
 513 #define USB_ADDR_ENDP13_RESET  _u(0x00000000)
 514 // -----------------------------------------------------------------------------
 515 // Field       : USB_ADDR_ENDP13_INTEP_PREAMBLE
 516 // Description : Interrupt EP requires preamble (is a low speed device on a full
 517 //               speed hub)
 518 #define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET  _u(0x0)
 519 #define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS   _u(0x04000000)
 520 #define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB    _u(26)
 521 #define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB    _u(26)
 522 #define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW"
 523 // -----------------------------------------------------------------------------
 524 // Field       : USB_ADDR_ENDP13_INTEP_DIR
 525 // Description : Direction of the interrupt endpoint. In=0, Out=1
 526 #define USB_ADDR_ENDP13_INTEP_DIR_RESET  _u(0x0)
 527 #define USB_ADDR_ENDP13_INTEP_DIR_BITS   _u(0x02000000)
 528 #define USB_ADDR_ENDP13_INTEP_DIR_MSB    _u(25)
 529 #define USB_ADDR_ENDP13_INTEP_DIR_LSB    _u(25)
 530 #define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW"
 531 // -----------------------------------------------------------------------------
 532 // Field       : USB_ADDR_ENDP13_ENDPOINT
 533 // Description : Endpoint number of the interrupt endpoint
 534 #define USB_ADDR_ENDP13_ENDPOINT_RESET  _u(0x0)
 535 #define USB_ADDR_ENDP13_ENDPOINT_BITS   _u(0x000f0000)
 536 #define USB_ADDR_ENDP13_ENDPOINT_MSB    _u(19)
 537 #define USB_ADDR_ENDP13_ENDPOINT_LSB    _u(16)
 538 #define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW"
 539 // -----------------------------------------------------------------------------
 540 // Field       : USB_ADDR_ENDP13_ADDRESS
 541 // Description : Device address
 542 #define USB_ADDR_ENDP13_ADDRESS_RESET  _u(0x00)
 543 #define USB_ADDR_ENDP13_ADDRESS_BITS   _u(0x0000007f)
 544 #define USB_ADDR_ENDP13_ADDRESS_MSB    _u(6)
 545 #define USB_ADDR_ENDP13_ADDRESS_LSB    _u(0)
 546 #define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW"
 547 // =============================================================================
 548 // Register    : USB_ADDR_ENDP14
 549 // Description : Interrupt endpoint 14. Only valid for HOST mode.
 550 #define USB_ADDR_ENDP14_OFFSET _u(0x00000038)
 551 #define USB_ADDR_ENDP14_BITS   _u(0x060f007f)
 552 #define USB_ADDR_ENDP14_RESET  _u(0x00000000)
 553 // -----------------------------------------------------------------------------
 554 // Field       : USB_ADDR_ENDP14_INTEP_PREAMBLE
 555 // Description : Interrupt EP requires preamble (is a low speed device on a full
 556 //               speed hub)
 557 #define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET  _u(0x0)
 558 #define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS   _u(0x04000000)
 559 #define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB    _u(26)
 560 #define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB    _u(26)
 561 #define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW"
 562 // -----------------------------------------------------------------------------
 563 // Field       : USB_ADDR_ENDP14_INTEP_DIR
 564 // Description : Direction of the interrupt endpoint. In=0, Out=1
 565 #define USB_ADDR_ENDP14_INTEP_DIR_RESET  _u(0x0)
 566 #define USB_ADDR_ENDP14_INTEP_DIR_BITS   _u(0x02000000)
 567 #define USB_ADDR_ENDP14_INTEP_DIR_MSB    _u(25)
 568 #define USB_ADDR_ENDP14_INTEP_DIR_LSB    _u(25)
 569 #define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW"
 570 // -----------------------------------------------------------------------------
 571 // Field       : USB_ADDR_ENDP14_ENDPOINT
 572 // Description : Endpoint number of the interrupt endpoint
 573 #define USB_ADDR_ENDP14_ENDPOINT_RESET  _u(0x0)
 574 #define USB_ADDR_ENDP14_ENDPOINT_BITS   _u(0x000f0000)
 575 #define USB_ADDR_ENDP14_ENDPOINT_MSB    _u(19)
 576 #define USB_ADDR_ENDP14_ENDPOINT_LSB    _u(16)
 577 #define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW"
 578 // -----------------------------------------------------------------------------
 579 // Field       : USB_ADDR_ENDP14_ADDRESS
 580 // Description : Device address
 581 #define USB_ADDR_ENDP14_ADDRESS_RESET  _u(0x00)
 582 #define USB_ADDR_ENDP14_ADDRESS_BITS   _u(0x0000007f)
 583 #define USB_ADDR_ENDP14_ADDRESS_MSB    _u(6)
 584 #define USB_ADDR_ENDP14_ADDRESS_LSB    _u(0)
 585 #define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW"
 586 // =============================================================================
 587 // Register    : USB_ADDR_ENDP15
 588 // Description : Interrupt endpoint 15. Only valid for HOST mode.
 589 #define USB_ADDR_ENDP15_OFFSET _u(0x0000003c)
 590 #define USB_ADDR_ENDP15_BITS   _u(0x060f007f)
 591 #define USB_ADDR_ENDP15_RESET  _u(0x00000000)
 592 // -----------------------------------------------------------------------------
 593 // Field       : USB_ADDR_ENDP15_INTEP_PREAMBLE
 594 // Description : Interrupt EP requires preamble (is a low speed device on a full
 595 //               speed hub)
 596 #define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET  _u(0x0)
 597 #define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS   _u(0x04000000)
 598 #define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB    _u(26)
 599 #define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB    _u(26)
 600 #define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW"
 601 // -----------------------------------------------------------------------------
 602 // Field       : USB_ADDR_ENDP15_INTEP_DIR
 603 // Description : Direction of the interrupt endpoint. In=0, Out=1
 604 #define USB_ADDR_ENDP15_INTEP_DIR_RESET  _u(0x0)
 605 #define USB_ADDR_ENDP15_INTEP_DIR_BITS   _u(0x02000000)
 606 #define USB_ADDR_ENDP15_INTEP_DIR_MSB    _u(25)
 607 #define USB_ADDR_ENDP15_INTEP_DIR_LSB    _u(25)
 608 #define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW"
 609 // -----------------------------------------------------------------------------
 610 // Field       : USB_ADDR_ENDP15_ENDPOINT
 611 // Description : Endpoint number of the interrupt endpoint
 612 #define USB_ADDR_ENDP15_ENDPOINT_RESET  _u(0x0)
 613 #define USB_ADDR_ENDP15_ENDPOINT_BITS   _u(0x000f0000)
 614 #define USB_ADDR_ENDP15_ENDPOINT_MSB    _u(19)
 615 #define USB_ADDR_ENDP15_ENDPOINT_LSB    _u(16)
 616 #define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW"
 617 // -----------------------------------------------------------------------------
 618 // Field       : USB_ADDR_ENDP15_ADDRESS
 619 // Description : Device address
 620 #define USB_ADDR_ENDP15_ADDRESS_RESET  _u(0x00)
 621 #define USB_ADDR_ENDP15_ADDRESS_BITS   _u(0x0000007f)
 622 #define USB_ADDR_ENDP15_ADDRESS_MSB    _u(6)
 623 #define USB_ADDR_ENDP15_ADDRESS_LSB    _u(0)
 624 #define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW"
 625 // =============================================================================
 626 // Register    : USB_MAIN_CTRL
 627 // Description : Main control register
 628 #define USB_MAIN_CTRL_OFFSET _u(0x00000040)
 629 #define USB_MAIN_CTRL_BITS   _u(0x80000007)
 630 #define USB_MAIN_CTRL_RESET  _u(0x00000004)
 631 // -----------------------------------------------------------------------------
 632 // Field       : USB_MAIN_CTRL_SIM_TIMING
 633 // Description : Reduced timings for simulation
 634 #define USB_MAIN_CTRL_SIM_TIMING_RESET  _u(0x0)
 635 #define USB_MAIN_CTRL_SIM_TIMING_BITS   _u(0x80000000)
 636 #define USB_MAIN_CTRL_SIM_TIMING_MSB    _u(31)
 637 #define USB_MAIN_CTRL_SIM_TIMING_LSB    _u(31)
 638 #define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW"
 639 // -----------------------------------------------------------------------------
 640 // Field       : USB_MAIN_CTRL_PHY_ISO
 641 // Description : Isolates USB phy after controller power-up
 642 //               Remove isolation once software has configured the controller
 643 //               Not isolated = 0, Isolated = 1
 644 #define USB_MAIN_CTRL_PHY_ISO_RESET  _u(0x1)
 645 #define USB_MAIN_CTRL_PHY_ISO_BITS   _u(0x00000004)
 646 #define USB_MAIN_CTRL_PHY_ISO_MSB    _u(2)
 647 #define USB_MAIN_CTRL_PHY_ISO_LSB    _u(2)
 648 #define USB_MAIN_CTRL_PHY_ISO_ACCESS "RW"
 649 // -----------------------------------------------------------------------------
 650 // Field       : USB_MAIN_CTRL_HOST_NDEVICE
 651 // Description : Device mode = 0, Host mode = 1
 652 #define USB_MAIN_CTRL_HOST_NDEVICE_RESET  _u(0x0)
 653 #define USB_MAIN_CTRL_HOST_NDEVICE_BITS   _u(0x00000002)
 654 #define USB_MAIN_CTRL_HOST_NDEVICE_MSB    _u(1)
 655 #define USB_MAIN_CTRL_HOST_NDEVICE_LSB    _u(1)
 656 #define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW"
 657 // -----------------------------------------------------------------------------
 658 // Field       : USB_MAIN_CTRL_CONTROLLER_EN
 659 // Description : Enable controller
 660 #define USB_MAIN_CTRL_CONTROLLER_EN_RESET  _u(0x0)
 661 #define USB_MAIN_CTRL_CONTROLLER_EN_BITS   _u(0x00000001)
 662 #define USB_MAIN_CTRL_CONTROLLER_EN_MSB    _u(0)
 663 #define USB_MAIN_CTRL_CONTROLLER_EN_LSB    _u(0)
 664 #define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW"
 665 // =============================================================================
 666 // Register    : USB_SOF_WR
 667 // Description : Set the SOF (Start of Frame) frame number in the host
 668 //               controller. The SOF packet is sent every 1ms and the host will
 669 //               increment the frame number by 1 each time.
 670 #define USB_SOF_WR_OFFSET _u(0x00000044)
 671 #define USB_SOF_WR_BITS   _u(0x000007ff)
 672 #define USB_SOF_WR_RESET  _u(0x00000000)
 673 // -----------------------------------------------------------------------------
 674 // Field       : USB_SOF_WR_COUNT
 675 #define USB_SOF_WR_COUNT_RESET  _u(0x000)
 676 #define USB_SOF_WR_COUNT_BITS   _u(0x000007ff)
 677 #define USB_SOF_WR_COUNT_MSB    _u(10)
 678 #define USB_SOF_WR_COUNT_LSB    _u(0)
 679 #define USB_SOF_WR_COUNT_ACCESS "WF"
 680 // =============================================================================
 681 // Register    : USB_SOF_RD
 682 // Description : Read the last SOF (Start of Frame) frame number seen. In device
 683 //               mode the last SOF received from the host. In host mode the last
 684 //               SOF sent by the host.
 685 #define USB_SOF_RD_OFFSET _u(0x00000048)
 686 #define USB_SOF_RD_BITS   _u(0x000007ff)
 687 #define USB_SOF_RD_RESET  _u(0x00000000)
 688 // -----------------------------------------------------------------------------
 689 // Field       : USB_SOF_RD_COUNT
 690 #define USB_SOF_RD_COUNT_RESET  _u(0x000)
 691 #define USB_SOF_RD_COUNT_BITS   _u(0x000007ff)
 692 #define USB_SOF_RD_COUNT_MSB    _u(10)
 693 #define USB_SOF_RD_COUNT_LSB    _u(0)
 694 #define USB_SOF_RD_COUNT_ACCESS "RO"
 695 // =============================================================================
 696 // Register    : USB_SIE_CTRL
 697 // Description : SIE control register
 698 #define USB_SIE_CTRL_OFFSET _u(0x0000004c)
 699 #define USB_SIE_CTRL_BITS   _u(0xff0fbf5f)
 700 #define USB_SIE_CTRL_RESET  _u(0x00008000)
 701 // -----------------------------------------------------------------------------
 702 // Field       : USB_SIE_CTRL_EP0_INT_STALL
 703 // Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
 704 #define USB_SIE_CTRL_EP0_INT_STALL_RESET  _u(0x0)
 705 #define USB_SIE_CTRL_EP0_INT_STALL_BITS   _u(0x80000000)
 706 #define USB_SIE_CTRL_EP0_INT_STALL_MSB    _u(31)
 707 #define USB_SIE_CTRL_EP0_INT_STALL_LSB    _u(31)
 708 #define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW"
 709 // -----------------------------------------------------------------------------
 710 // Field       : USB_SIE_CTRL_EP0_DOUBLE_BUF
 711 // Description : Device: EP0 single buffered = 0, double buffered = 1
 712 #define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET  _u(0x0)
 713 #define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS   _u(0x40000000)
 714 #define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB    _u(30)
 715 #define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB    _u(30)
 716 #define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW"
 717 // -----------------------------------------------------------------------------
 718 // Field       : USB_SIE_CTRL_EP0_INT_1BUF
 719 // Description : Device: Set bit in BUFF_STATUS for every buffer completed on
 720 //               EP0
 721 #define USB_SIE_CTRL_EP0_INT_1BUF_RESET  _u(0x0)
 722 #define USB_SIE_CTRL_EP0_INT_1BUF_BITS   _u(0x20000000)
 723 #define USB_SIE_CTRL_EP0_INT_1BUF_MSB    _u(29)
 724 #define USB_SIE_CTRL_EP0_INT_1BUF_LSB    _u(29)
 725 #define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW"
 726 // -----------------------------------------------------------------------------
 727 // Field       : USB_SIE_CTRL_EP0_INT_2BUF
 728 // Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on
 729 //               EP0
 730 #define USB_SIE_CTRL_EP0_INT_2BUF_RESET  _u(0x0)
 731 #define USB_SIE_CTRL_EP0_INT_2BUF_BITS   _u(0x10000000)
 732 #define USB_SIE_CTRL_EP0_INT_2BUF_MSB    _u(28)
 733 #define USB_SIE_CTRL_EP0_INT_2BUF_LSB    _u(28)
 734 #define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW"
 735 // -----------------------------------------------------------------------------
 736 // Field       : USB_SIE_CTRL_EP0_INT_NAK
 737 // Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
 738 #define USB_SIE_CTRL_EP0_INT_NAK_RESET  _u(0x0)
 739 #define USB_SIE_CTRL_EP0_INT_NAK_BITS   _u(0x08000000)
 740 #define USB_SIE_CTRL_EP0_INT_NAK_MSB    _u(27)
 741 #define USB_SIE_CTRL_EP0_INT_NAK_LSB    _u(27)
 742 #define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW"
 743 // -----------------------------------------------------------------------------
 744 // Field       : USB_SIE_CTRL_DIRECT_EN
 745 // Description : Direct bus drive enable
 746 #define USB_SIE_CTRL_DIRECT_EN_RESET  _u(0x0)
 747 #define USB_SIE_CTRL_DIRECT_EN_BITS   _u(0x04000000)
 748 #define USB_SIE_CTRL_DIRECT_EN_MSB    _u(26)
 749 #define USB_SIE_CTRL_DIRECT_EN_LSB    _u(26)
 750 #define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW"
 751 // -----------------------------------------------------------------------------
 752 // Field       : USB_SIE_CTRL_DIRECT_DP
 753 // Description : Direct control of DP
 754 #define USB_SIE_CTRL_DIRECT_DP_RESET  _u(0x0)
 755 #define USB_SIE_CTRL_DIRECT_DP_BITS   _u(0x02000000)
 756 #define USB_SIE_CTRL_DIRECT_DP_MSB    _u(25)
 757 #define USB_SIE_CTRL_DIRECT_DP_LSB    _u(25)
 758 #define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW"
 759 // -----------------------------------------------------------------------------
 760 // Field       : USB_SIE_CTRL_DIRECT_DM
 761 // Description : Direct control of DM
 762 #define USB_SIE_CTRL_DIRECT_DM_RESET  _u(0x0)
 763 #define USB_SIE_CTRL_DIRECT_DM_BITS   _u(0x01000000)
 764 #define USB_SIE_CTRL_DIRECT_DM_MSB    _u(24)
 765 #define USB_SIE_CTRL_DIRECT_DM_LSB    _u(24)
 766 #define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW"
 767 // -----------------------------------------------------------------------------
 768 // Field       : USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET
 769 // Description : Device: Stop EP0 on a short packet.
 770 #define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_RESET  _u(0x0)
 771 #define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_BITS   _u(0x00080000)
 772 #define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_MSB    _u(19)
 773 #define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_LSB    _u(19)
 774 #define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_ACCESS "RW"
 775 // -----------------------------------------------------------------------------
 776 // Field       : USB_SIE_CTRL_TRANSCEIVER_PD
 777 // Description : Power down bus transceiver
 778 #define USB_SIE_CTRL_TRANSCEIVER_PD_RESET  _u(0x0)
 779 #define USB_SIE_CTRL_TRANSCEIVER_PD_BITS   _u(0x00040000)
 780 #define USB_SIE_CTRL_TRANSCEIVER_PD_MSB    _u(18)
 781 #define USB_SIE_CTRL_TRANSCEIVER_PD_LSB    _u(18)
 782 #define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW"
 783 // -----------------------------------------------------------------------------
 784 // Field       : USB_SIE_CTRL_RPU_OPT
 785 // Description : Device: Pull-up strength (0=1K2, 1=2k3)
 786 #define USB_SIE_CTRL_RPU_OPT_RESET  _u(0x0)
 787 #define USB_SIE_CTRL_RPU_OPT_BITS   _u(0x00020000)
 788 #define USB_SIE_CTRL_RPU_OPT_MSB    _u(17)
 789 #define USB_SIE_CTRL_RPU_OPT_LSB    _u(17)
 790 #define USB_SIE_CTRL_RPU_OPT_ACCESS "RW"
 791 // -----------------------------------------------------------------------------
 792 // Field       : USB_SIE_CTRL_PULLUP_EN
 793 // Description : Device: Enable pull up resistor
 794 #define USB_SIE_CTRL_PULLUP_EN_RESET  _u(0x0)
 795 #define USB_SIE_CTRL_PULLUP_EN_BITS   _u(0x00010000)
 796 #define USB_SIE_CTRL_PULLUP_EN_MSB    _u(16)
 797 #define USB_SIE_CTRL_PULLUP_EN_LSB    _u(16)
 798 #define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW"
 799 // -----------------------------------------------------------------------------
 800 // Field       : USB_SIE_CTRL_PULLDOWN_EN
 801 // Description : Host: Enable pull down resistors
 802 #define USB_SIE_CTRL_PULLDOWN_EN_RESET  _u(0x1)
 803 #define USB_SIE_CTRL_PULLDOWN_EN_BITS   _u(0x00008000)
 804 #define USB_SIE_CTRL_PULLDOWN_EN_MSB    _u(15)
 805 #define USB_SIE_CTRL_PULLDOWN_EN_LSB    _u(15)
 806 #define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW"
 807 // -----------------------------------------------------------------------------
 808 // Field       : USB_SIE_CTRL_RESET_BUS
 809 // Description : Host: Reset bus
 810 #define USB_SIE_CTRL_RESET_BUS_RESET  _u(0x0)
 811 #define USB_SIE_CTRL_RESET_BUS_BITS   _u(0x00002000)
 812 #define USB_SIE_CTRL_RESET_BUS_MSB    _u(13)
 813 #define USB_SIE_CTRL_RESET_BUS_LSB    _u(13)
 814 #define USB_SIE_CTRL_RESET_BUS_ACCESS "SC"
 815 // -----------------------------------------------------------------------------
 816 // Field       : USB_SIE_CTRL_RESUME
 817 // Description : Device: Remote wakeup. Device can initiate its own resume after
 818 //               suspend.
 819 #define USB_SIE_CTRL_RESUME_RESET  _u(0x0)
 820 #define USB_SIE_CTRL_RESUME_BITS   _u(0x00001000)
 821 #define USB_SIE_CTRL_RESUME_MSB    _u(12)
 822 #define USB_SIE_CTRL_RESUME_LSB    _u(12)
 823 #define USB_SIE_CTRL_RESUME_ACCESS "SC"
 824 // -----------------------------------------------------------------------------
 825 // Field       : USB_SIE_CTRL_VBUS_EN
 826 // Description : Host: Enable VBUS
 827 #define USB_SIE_CTRL_VBUS_EN_RESET  _u(0x0)
 828 #define USB_SIE_CTRL_VBUS_EN_BITS   _u(0x00000800)
 829 #define USB_SIE_CTRL_VBUS_EN_MSB    _u(11)
 830 #define USB_SIE_CTRL_VBUS_EN_LSB    _u(11)
 831 #define USB_SIE_CTRL_VBUS_EN_ACCESS "RW"
 832 // -----------------------------------------------------------------------------
 833 // Field       : USB_SIE_CTRL_KEEP_ALIVE_EN
 834 // Description : Host: Enable keep alive packet (for low speed bus)
 835 #define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET  _u(0x0)
 836 #define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS   _u(0x00000400)
 837 #define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB    _u(10)
 838 #define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB    _u(10)
 839 #define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW"
 840 // -----------------------------------------------------------------------------
 841 // Field       : USB_SIE_CTRL_SOF_EN
 842 // Description : Host: Enable SOF generation (for full speed bus)
 843 #define USB_SIE_CTRL_SOF_EN_RESET  _u(0x0)
 844 #define USB_SIE_CTRL_SOF_EN_BITS   _u(0x00000200)
 845 #define USB_SIE_CTRL_SOF_EN_MSB    _u(9)
 846 #define USB_SIE_CTRL_SOF_EN_LSB    _u(9)
 847 #define USB_SIE_CTRL_SOF_EN_ACCESS "RW"
 848 // -----------------------------------------------------------------------------
 849 // Field       : USB_SIE_CTRL_SOF_SYNC
 850 // Description : Host: Delay packet(s) until after SOF
 851 #define USB_SIE_CTRL_SOF_SYNC_RESET  _u(0x0)
 852 #define USB_SIE_CTRL_SOF_SYNC_BITS   _u(0x00000100)
 853 #define USB_SIE_CTRL_SOF_SYNC_MSB    _u(8)
 854 #define USB_SIE_CTRL_SOF_SYNC_LSB    _u(8)
 855 #define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW"
 856 // -----------------------------------------------------------------------------
 857 // Field       : USB_SIE_CTRL_PREAMBLE_EN
 858 // Description : Host: Preable enable for LS device on FS hub
 859 #define USB_SIE_CTRL_PREAMBLE_EN_RESET  _u(0x0)
 860 #define USB_SIE_CTRL_PREAMBLE_EN_BITS   _u(0x00000040)
 861 #define USB_SIE_CTRL_PREAMBLE_EN_MSB    _u(6)
 862 #define USB_SIE_CTRL_PREAMBLE_EN_LSB    _u(6)
 863 #define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW"
 864 // -----------------------------------------------------------------------------
 865 // Field       : USB_SIE_CTRL_STOP_TRANS
 866 // Description : Host: Stop transaction
 867 #define USB_SIE_CTRL_STOP_TRANS_RESET  _u(0x0)
 868 #define USB_SIE_CTRL_STOP_TRANS_BITS   _u(0x00000010)
 869 #define USB_SIE_CTRL_STOP_TRANS_MSB    _u(4)
 870 #define USB_SIE_CTRL_STOP_TRANS_LSB    _u(4)
 871 #define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC"
 872 // -----------------------------------------------------------------------------
 873 // Field       : USB_SIE_CTRL_RECEIVE_DATA
 874 // Description : Host: Receive transaction (IN to host)
 875 #define USB_SIE_CTRL_RECEIVE_DATA_RESET  _u(0x0)
 876 #define USB_SIE_CTRL_RECEIVE_DATA_BITS   _u(0x00000008)
 877 #define USB_SIE_CTRL_RECEIVE_DATA_MSB    _u(3)
 878 #define USB_SIE_CTRL_RECEIVE_DATA_LSB    _u(3)
 879 #define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW"
 880 // -----------------------------------------------------------------------------
 881 // Field       : USB_SIE_CTRL_SEND_DATA
 882 // Description : Host: Send transaction (OUT from host)
 883 #define USB_SIE_CTRL_SEND_DATA_RESET  _u(0x0)
 884 #define USB_SIE_CTRL_SEND_DATA_BITS   _u(0x00000004)
 885 #define USB_SIE_CTRL_SEND_DATA_MSB    _u(2)
 886 #define USB_SIE_CTRL_SEND_DATA_LSB    _u(2)
 887 #define USB_SIE_CTRL_SEND_DATA_ACCESS "RW"
 888 // -----------------------------------------------------------------------------
 889 // Field       : USB_SIE_CTRL_SEND_SETUP
 890 // Description : Host: Send Setup packet
 891 #define USB_SIE_CTRL_SEND_SETUP_RESET  _u(0x0)
 892 #define USB_SIE_CTRL_SEND_SETUP_BITS   _u(0x00000002)
 893 #define USB_SIE_CTRL_SEND_SETUP_MSB    _u(1)
 894 #define USB_SIE_CTRL_SEND_SETUP_LSB    _u(1)
 895 #define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW"
 896 // -----------------------------------------------------------------------------
 897 // Field       : USB_SIE_CTRL_START_TRANS
 898 // Description : Host: Start transaction
 899 #define USB_SIE_CTRL_START_TRANS_RESET  _u(0x0)
 900 #define USB_SIE_CTRL_START_TRANS_BITS   _u(0x00000001)
 901 #define USB_SIE_CTRL_START_TRANS_MSB    _u(0)
 902 #define USB_SIE_CTRL_START_TRANS_LSB    _u(0)
 903 #define USB_SIE_CTRL_START_TRANS_ACCESS "SC"
 904 // =============================================================================
 905 // Register    : USB_SIE_STATUS
 906 // Description : SIE status register
 907 #define USB_SIE_STATUS_OFFSET _u(0x00000050)
 908 #define USB_SIE_STATUS_BITS   _u(0xff8f1f1d)
 909 #define USB_SIE_STATUS_RESET  _u(0x00000000)
 910 // -----------------------------------------------------------------------------
 911 // Field       : USB_SIE_STATUS_DATA_SEQ_ERROR
 912 // Description : Data Sequence Error.
 913 //
 914 //               The device can raise a sequence error in the following
 915 //               conditions:
 916 //
 917 //               * A SETUP packet is received followed by a DATA1 packet (data
 918 //               phase should always be DATA0) * An OUT packet is received from
 919 //               the host but doesn't match the data pid in the buffer control
 920 //               register read from DPSRAM
 921 //
 922 //               The host can raise a data sequence error in the following
 923 //               conditions:
 924 //
 925 //               * An IN packet from the device has the wrong data PID
 926 #define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET  _u(0x0)
 927 #define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS   _u(0x80000000)
 928 #define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB    _u(31)
 929 #define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB    _u(31)
 930 #define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC"
 931 // -----------------------------------------------------------------------------
 932 // Field       : USB_SIE_STATUS_ACK_REC
 933 // Description : ACK received. Raised by both host and device.
 934 #define USB_SIE_STATUS_ACK_REC_RESET  _u(0x0)
 935 #define USB_SIE_STATUS_ACK_REC_BITS   _u(0x40000000)
 936 #define USB_SIE_STATUS_ACK_REC_MSB    _u(30)
 937 #define USB_SIE_STATUS_ACK_REC_LSB    _u(30)
 938 #define USB_SIE_STATUS_ACK_REC_ACCESS "WC"
 939 // -----------------------------------------------------------------------------
 940 // Field       : USB_SIE_STATUS_STALL_REC
 941 // Description : Host: STALL received
 942 #define USB_SIE_STATUS_STALL_REC_RESET  _u(0x0)
 943 #define USB_SIE_STATUS_STALL_REC_BITS   _u(0x20000000)
 944 #define USB_SIE_STATUS_STALL_REC_MSB    _u(29)
 945 #define USB_SIE_STATUS_STALL_REC_LSB    _u(29)
 946 #define USB_SIE_STATUS_STALL_REC_ACCESS "WC"
 947 // -----------------------------------------------------------------------------
 948 // Field       : USB_SIE_STATUS_NAK_REC
 949 // Description : Host: NAK received
 950 #define USB_SIE_STATUS_NAK_REC_RESET  _u(0x0)
 951 #define USB_SIE_STATUS_NAK_REC_BITS   _u(0x10000000)
 952 #define USB_SIE_STATUS_NAK_REC_MSB    _u(28)
 953 #define USB_SIE_STATUS_NAK_REC_LSB    _u(28)
 954 #define USB_SIE_STATUS_NAK_REC_ACCESS "WC"
 955 // -----------------------------------------------------------------------------
 956 // Field       : USB_SIE_STATUS_RX_TIMEOUT
 957 // Description : RX timeout is raised by both the host and device if an ACK is
 958 //               not received in the maximum time specified by the USB spec.
 959 #define USB_SIE_STATUS_RX_TIMEOUT_RESET  _u(0x0)
 960 #define USB_SIE_STATUS_RX_TIMEOUT_BITS   _u(0x08000000)
 961 #define USB_SIE_STATUS_RX_TIMEOUT_MSB    _u(27)
 962 #define USB_SIE_STATUS_RX_TIMEOUT_LSB    _u(27)
 963 #define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC"
 964 // -----------------------------------------------------------------------------
 965 // Field       : USB_SIE_STATUS_RX_OVERFLOW
 966 // Description : RX overflow is raised by the Serial RX engine if the incoming
 967 //               data is too fast.
 968 #define USB_SIE_STATUS_RX_OVERFLOW_RESET  _u(0x0)
 969 #define USB_SIE_STATUS_RX_OVERFLOW_BITS   _u(0x04000000)
 970 #define USB_SIE_STATUS_RX_OVERFLOW_MSB    _u(26)
 971 #define USB_SIE_STATUS_RX_OVERFLOW_LSB    _u(26)
 972 #define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC"
 973 // -----------------------------------------------------------------------------
 974 // Field       : USB_SIE_STATUS_BIT_STUFF_ERROR
 975 // Description : Bit Stuff Error. Raised by the Serial RX engine.
 976 #define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET  _u(0x0)
 977 #define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS   _u(0x02000000)
 978 #define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB    _u(25)
 979 #define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB    _u(25)
 980 #define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC"
 981 // -----------------------------------------------------------------------------
 982 // Field       : USB_SIE_STATUS_CRC_ERROR
 983 // Description : CRC Error. Raised by the Serial RX engine.
 984 #define USB_SIE_STATUS_CRC_ERROR_RESET  _u(0x0)
 985 #define USB_SIE_STATUS_CRC_ERROR_BITS   _u(0x01000000)
 986 #define USB_SIE_STATUS_CRC_ERROR_MSB    _u(24)
 987 #define USB_SIE_STATUS_CRC_ERROR_LSB    _u(24)
 988 #define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC"
 989 // -----------------------------------------------------------------------------
 990 // Field       : USB_SIE_STATUS_ENDPOINT_ERROR
 991 // Description : An endpoint has encountered an error. Read the ep_rx_error and
 992 //               ep_tx_error registers to find out which endpoint had an error.
 993 #define USB_SIE_STATUS_ENDPOINT_ERROR_RESET  _u(0x0)
 994 #define USB_SIE_STATUS_ENDPOINT_ERROR_BITS   _u(0x00800000)
 995 #define USB_SIE_STATUS_ENDPOINT_ERROR_MSB    _u(23)
 996 #define USB_SIE_STATUS_ENDPOINT_ERROR_LSB    _u(23)
 997 #define USB_SIE_STATUS_ENDPOINT_ERROR_ACCESS "WC"
 998 // -----------------------------------------------------------------------------
 999 // Field       : USB_SIE_STATUS_BUS_RESET
1000 // Description : Device: bus reset received
1001 #define USB_SIE_STATUS_BUS_RESET_RESET  _u(0x0)
1002 #define USB_SIE_STATUS_BUS_RESET_BITS   _u(0x00080000)
1003 #define USB_SIE_STATUS_BUS_RESET_MSB    _u(19)
1004 #define USB_SIE_STATUS_BUS_RESET_LSB    _u(19)
1005 #define USB_SIE_STATUS_BUS_RESET_ACCESS "WC"
1006 // -----------------------------------------------------------------------------
1007 // Field       : USB_SIE_STATUS_TRANS_COMPLETE
1008 // Description : Transaction complete.
1009 //
1010 //               Raised by device if:
1011 //
1012 //               * An IN or OUT packet is sent with the `LAST_BUFF` bit set in
1013 //               the buffer control register
1014 //
1015 //               Raised by host if:
1016 //
1017 //               * A setup packet is sent when no data in or data out
1018 //               transaction follows * An IN packet is received and the
1019 //               `LAST_BUFF` bit is set in the buffer control register * An IN
1020 //               packet is received with zero length * An OUT packet is sent and
1021 //               the `LAST_BUFF` bit is set
1022 #define USB_SIE_STATUS_TRANS_COMPLETE_RESET  _u(0x0)
1023 #define USB_SIE_STATUS_TRANS_COMPLETE_BITS   _u(0x00040000)
1024 #define USB_SIE_STATUS_TRANS_COMPLETE_MSB    _u(18)
1025 #define USB_SIE_STATUS_TRANS_COMPLETE_LSB    _u(18)
1026 #define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC"
1027 // -----------------------------------------------------------------------------
1028 // Field       : USB_SIE_STATUS_SETUP_REC
1029 // Description : Device: Setup packet received
1030 #define USB_SIE_STATUS_SETUP_REC_RESET  _u(0x0)
1031 #define USB_SIE_STATUS_SETUP_REC_BITS   _u(0x00020000)
1032 #define USB_SIE_STATUS_SETUP_REC_MSB    _u(17)
1033 #define USB_SIE_STATUS_SETUP_REC_LSB    _u(17)
1034 #define USB_SIE_STATUS_SETUP_REC_ACCESS "WC"
1035 // -----------------------------------------------------------------------------
1036 // Field       : USB_SIE_STATUS_CONNECTED
1037 // Description : Device: connected
1038 #define USB_SIE_STATUS_CONNECTED_RESET  _u(0x0)
1039 #define USB_SIE_STATUS_CONNECTED_BITS   _u(0x00010000)
1040 #define USB_SIE_STATUS_CONNECTED_MSB    _u(16)
1041 #define USB_SIE_STATUS_CONNECTED_LSB    _u(16)
1042 #define USB_SIE_STATUS_CONNECTED_ACCESS "RO"
1043 // -----------------------------------------------------------------------------
1044 // Field       : USB_SIE_STATUS_RX_SHORT_PACKET
1045 // Description : Device or Host has received a short packet. This is when the
1046 //               data received is less than configured in the buffer control
1047 //               register. Device: If using double buffered mode on device the
1048 //               buffer select will not be toggled after writing status back to
1049 //               the buffer control register. This is to prevent any further
1050 //               transactions on that endpoint until the user has reset the
1051 //               buffer control registers. Host: the current transfer will be
1052 //               stopped early.
1053 #define USB_SIE_STATUS_RX_SHORT_PACKET_RESET  _u(0x0)
1054 #define USB_SIE_STATUS_RX_SHORT_PACKET_BITS   _u(0x00001000)
1055 #define USB_SIE_STATUS_RX_SHORT_PACKET_MSB    _u(12)
1056 #define USB_SIE_STATUS_RX_SHORT_PACKET_LSB    _u(12)
1057 #define USB_SIE_STATUS_RX_SHORT_PACKET_ACCESS "WC"
1058 // -----------------------------------------------------------------------------
1059 // Field       : USB_SIE_STATUS_RESUME
1060 // Description : Host: Device has initiated a remote resume. Device: host has
1061 //               initiated a resume.
1062 #define USB_SIE_STATUS_RESUME_RESET  _u(0x0)
1063 #define USB_SIE_STATUS_RESUME_BITS   _u(0x00000800)
1064 #define USB_SIE_STATUS_RESUME_MSB    _u(11)
1065 #define USB_SIE_STATUS_RESUME_LSB    _u(11)
1066 #define USB_SIE_STATUS_RESUME_ACCESS "WC"
1067 // -----------------------------------------------------------------------------
1068 // Field       : USB_SIE_STATUS_VBUS_OVER_CURR
1069 // Description : VBUS over current detected
1070 #define USB_SIE_STATUS_VBUS_OVER_CURR_RESET  _u(0x0)
1071 #define USB_SIE_STATUS_VBUS_OVER_CURR_BITS   _u(0x00000400)
1072 #define USB_SIE_STATUS_VBUS_OVER_CURR_MSB    _u(10)
1073 #define USB_SIE_STATUS_VBUS_OVER_CURR_LSB    _u(10)
1074 #define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO"
1075 // -----------------------------------------------------------------------------
1076 // Field       : USB_SIE_STATUS_SPEED
1077 // Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10
1078 #define USB_SIE_STATUS_SPEED_RESET  _u(0x0)
1079 #define USB_SIE_STATUS_SPEED_BITS   _u(0x00000300)
1080 #define USB_SIE_STATUS_SPEED_MSB    _u(9)
1081 #define USB_SIE_STATUS_SPEED_LSB    _u(8)
1082 #define USB_SIE_STATUS_SPEED_ACCESS "RO"
1083 // -----------------------------------------------------------------------------
1084 // Field       : USB_SIE_STATUS_SUSPENDED
1085 // Description : Bus in suspended state. Valid for device. Device will go into
1086 //               suspend if neither Keep Alive / SOF frames are enabled.
1087 #define USB_SIE_STATUS_SUSPENDED_RESET  _u(0x0)
1088 #define USB_SIE_STATUS_SUSPENDED_BITS   _u(0x00000010)
1089 #define USB_SIE_STATUS_SUSPENDED_MSB    _u(4)
1090 #define USB_SIE_STATUS_SUSPENDED_LSB    _u(4)
1091 #define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
1092 // -----------------------------------------------------------------------------
1093 // Field       : USB_SIE_STATUS_LINE_STATE
1094 // Description : USB bus line state
1095 #define USB_SIE_STATUS_LINE_STATE_RESET  _u(0x0)
1096 #define USB_SIE_STATUS_LINE_STATE_BITS   _u(0x0000000c)
1097 #define USB_SIE_STATUS_LINE_STATE_MSB    _u(3)
1098 #define USB_SIE_STATUS_LINE_STATE_LSB    _u(2)
1099 #define USB_SIE_STATUS_LINE_STATE_ACCESS "RO"
1100 // -----------------------------------------------------------------------------
1101 // Field       : USB_SIE_STATUS_VBUS_DETECTED
1102 // Description : Device: VBUS Detected
1103 #define USB_SIE_STATUS_VBUS_DETECTED_RESET  _u(0x0)
1104 #define USB_SIE_STATUS_VBUS_DETECTED_BITS   _u(0x00000001)
1105 #define USB_SIE_STATUS_VBUS_DETECTED_MSB    _u(0)
1106 #define USB_SIE_STATUS_VBUS_DETECTED_LSB    _u(0)
1107 #define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO"
1108 // =============================================================================
1109 // Register    : USB_INT_EP_CTRL
1110 // Description : interrupt endpoint control register
1111 #define USB_INT_EP_CTRL_OFFSET _u(0x00000054)
1112 #define USB_INT_EP_CTRL_BITS   _u(0x0000fffe)
1113 #define USB_INT_EP_CTRL_RESET  _u(0x00000000)
1114 // -----------------------------------------------------------------------------
1115 // Field       : USB_INT_EP_CTRL_INT_EP_ACTIVE
1116 // Description : Host: Enable interrupt endpoint 1 -> 15
1117 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET  _u(0x0000)
1118 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS   _u(0x0000fffe)
1119 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB    _u(15)
1120 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB    _u(1)
1121 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW"
1122 // =============================================================================
1123 // Register    : USB_BUFF_STATUS
1124 // Description : Buffer status register. A bit set here indicates that a buffer
1125 //               has completed on the endpoint (if the buffer interrupt is
1126 //               enabled). It is possible for 2 buffers to be completed, so
1127 //               clearing the buffer status bit may instantly re set it on the
1128 //               next clock cycle.
1129 #define USB_BUFF_STATUS_OFFSET _u(0x00000058)
1130 #define USB_BUFF_STATUS_BITS   _u(0xffffffff)
1131 #define USB_BUFF_STATUS_RESET  _u(0x00000000)
1132 // -----------------------------------------------------------------------------
1133 // Field       : USB_BUFF_STATUS_EP15_OUT
1134 #define USB_BUFF_STATUS_EP15_OUT_RESET  _u(0x0)
1135 #define USB_BUFF_STATUS_EP15_OUT_BITS   _u(0x80000000)
1136 #define USB_BUFF_STATUS_EP15_OUT_MSB    _u(31)
1137 #define USB_BUFF_STATUS_EP15_OUT_LSB    _u(31)
1138 #define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC"
1139 // -----------------------------------------------------------------------------
1140 // Field       : USB_BUFF_STATUS_EP15_IN
1141 #define USB_BUFF_STATUS_EP15_IN_RESET  _u(0x0)
1142 #define USB_BUFF_STATUS_EP15_IN_BITS   _u(0x40000000)
1143 #define USB_BUFF_STATUS_EP15_IN_MSB    _u(30)
1144 #define USB_BUFF_STATUS_EP15_IN_LSB    _u(30)
1145 #define USB_BUFF_STATUS_EP15_IN_ACCESS "WC"
1146 // -----------------------------------------------------------------------------
1147 // Field       : USB_BUFF_STATUS_EP14_OUT
1148 #define USB_BUFF_STATUS_EP14_OUT_RESET  _u(0x0)
1149 #define USB_BUFF_STATUS_EP14_OUT_BITS   _u(0x20000000)
1150 #define USB_BUFF_STATUS_EP14_OUT_MSB    _u(29)
1151 #define USB_BUFF_STATUS_EP14_OUT_LSB    _u(29)
1152 #define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC"
1153 // -----------------------------------------------------------------------------
1154 // Field       : USB_BUFF_STATUS_EP14_IN
1155 #define USB_BUFF_STATUS_EP14_IN_RESET  _u(0x0)
1156 #define USB_BUFF_STATUS_EP14_IN_BITS   _u(0x10000000)
1157 #define USB_BUFF_STATUS_EP14_IN_MSB    _u(28)
1158 #define USB_BUFF_STATUS_EP14_IN_LSB    _u(28)
1159 #define USB_BUFF_STATUS_EP14_IN_ACCESS "WC"
1160 // -----------------------------------------------------------------------------
1161 // Field       : USB_BUFF_STATUS_EP13_OUT
1162 #define USB_BUFF_STATUS_EP13_OUT_RESET  _u(0x0)
1163 #define USB_BUFF_STATUS_EP13_OUT_BITS   _u(0x08000000)
1164 #define USB_BUFF_STATUS_EP13_OUT_MSB    _u(27)
1165 #define USB_BUFF_STATUS_EP13_OUT_LSB    _u(27)
1166 #define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC"
1167 // -----------------------------------------------------------------------------
1168 // Field       : USB_BUFF_STATUS_EP13_IN
1169 #define USB_BUFF_STATUS_EP13_IN_RESET  _u(0x0)
1170 #define USB_BUFF_STATUS_EP13_IN_BITS   _u(0x04000000)
1171 #define USB_BUFF_STATUS_EP13_IN_MSB    _u(26)
1172 #define USB_BUFF_STATUS_EP13_IN_LSB    _u(26)
1173 #define USB_BUFF_STATUS_EP13_IN_ACCESS "WC"
1174 // -----------------------------------------------------------------------------
1175 // Field       : USB_BUFF_STATUS_EP12_OUT
1176 #define USB_BUFF_STATUS_EP12_OUT_RESET  _u(0x0)
1177 #define USB_BUFF_STATUS_EP12_OUT_BITS   _u(0x02000000)
1178 #define USB_BUFF_STATUS_EP12_OUT_MSB    _u(25)
1179 #define USB_BUFF_STATUS_EP12_OUT_LSB    _u(25)
1180 #define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC"
1181 // -----------------------------------------------------------------------------
1182 // Field       : USB_BUFF_STATUS_EP12_IN
1183 #define USB_BUFF_STATUS_EP12_IN_RESET  _u(0x0)
1184 #define USB_BUFF_STATUS_EP12_IN_BITS   _u(0x01000000)
1185 #define USB_BUFF_STATUS_EP12_IN_MSB    _u(24)
1186 #define USB_BUFF_STATUS_EP12_IN_LSB    _u(24)
1187 #define USB_BUFF_STATUS_EP12_IN_ACCESS "WC"
1188 // -----------------------------------------------------------------------------
1189 // Field       : USB_BUFF_STATUS_EP11_OUT
1190 #define USB_BUFF_STATUS_EP11_OUT_RESET  _u(0x0)
1191 #define USB_BUFF_STATUS_EP11_OUT_BITS   _u(0x00800000)
1192 #define USB_BUFF_STATUS_EP11_OUT_MSB    _u(23)
1193 #define USB_BUFF_STATUS_EP11_OUT_LSB    _u(23)
1194 #define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC"
1195 // -----------------------------------------------------------------------------
1196 // Field       : USB_BUFF_STATUS_EP11_IN
1197 #define USB_BUFF_STATUS_EP11_IN_RESET  _u(0x0)
1198 #define USB_BUFF_STATUS_EP11_IN_BITS   _u(0x00400000)
1199 #define USB_BUFF_STATUS_EP11_IN_MSB    _u(22)
1200 #define USB_BUFF_STATUS_EP11_IN_LSB    _u(22)
1201 #define USB_BUFF_STATUS_EP11_IN_ACCESS "WC"
1202 // -----------------------------------------------------------------------------
1203 // Field       : USB_BUFF_STATUS_EP10_OUT
1204 #define USB_BUFF_STATUS_EP10_OUT_RESET  _u(0x0)
1205 #define USB_BUFF_STATUS_EP10_OUT_BITS   _u(0x00200000)
1206 #define USB_BUFF_STATUS_EP10_OUT_MSB    _u(21)
1207 #define USB_BUFF_STATUS_EP10_OUT_LSB    _u(21)
1208 #define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC"
1209 // -----------------------------------------------------------------------------
1210 // Field       : USB_BUFF_STATUS_EP10_IN
1211 #define USB_BUFF_STATUS_EP10_IN_RESET  _u(0x0)
1212 #define USB_BUFF_STATUS_EP10_IN_BITS   _u(0x00100000)
1213 #define USB_BUFF_STATUS_EP10_IN_MSB    _u(20)
1214 #define USB_BUFF_STATUS_EP10_IN_LSB    _u(20)
1215 #define USB_BUFF_STATUS_EP10_IN_ACCESS "WC"
1216 // -----------------------------------------------------------------------------
1217 // Field       : USB_BUFF_STATUS_EP9_OUT
1218 #define USB_BUFF_STATUS_EP9_OUT_RESET  _u(0x0)
1219 #define USB_BUFF_STATUS_EP9_OUT_BITS   _u(0x00080000)
1220 #define USB_BUFF_STATUS_EP9_OUT_MSB    _u(19)
1221 #define USB_BUFF_STATUS_EP9_OUT_LSB    _u(19)
1222 #define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC"
1223 // -----------------------------------------------------------------------------
1224 // Field       : USB_BUFF_STATUS_EP9_IN
1225 #define USB_BUFF_STATUS_EP9_IN_RESET  _u(0x0)
1226 #define USB_BUFF_STATUS_EP9_IN_BITS   _u(0x00040000)
1227 #define USB_BUFF_STATUS_EP9_IN_MSB    _u(18)
1228 #define USB_BUFF_STATUS_EP9_IN_LSB    _u(18)
1229 #define USB_BUFF_STATUS_EP9_IN_ACCESS "WC"
1230 // -----------------------------------------------------------------------------
1231 // Field       : USB_BUFF_STATUS_EP8_OUT
1232 #define USB_BUFF_STATUS_EP8_OUT_RESET  _u(0x0)
1233 #define USB_BUFF_STATUS_EP8_OUT_BITS   _u(0x00020000)
1234 #define USB_BUFF_STATUS_EP8_OUT_MSB    _u(17)
1235 #define USB_BUFF_STATUS_EP8_OUT_LSB    _u(17)
1236 #define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC"
1237 // -----------------------------------------------------------------------------
1238 // Field       : USB_BUFF_STATUS_EP8_IN
1239 #define USB_BUFF_STATUS_EP8_IN_RESET  _u(0x0)
1240 #define USB_BUFF_STATUS_EP8_IN_BITS   _u(0x00010000)
1241 #define USB_BUFF_STATUS_EP8_IN_MSB    _u(16)
1242 #define USB_BUFF_STATUS_EP8_IN_LSB    _u(16)
1243 #define USB_BUFF_STATUS_EP8_IN_ACCESS "WC"
1244 // -----------------------------------------------------------------------------
1245 // Field       : USB_BUFF_STATUS_EP7_OUT
1246 #define USB_BUFF_STATUS_EP7_OUT_RESET  _u(0x0)
1247 #define USB_BUFF_STATUS_EP7_OUT_BITS   _u(0x00008000)
1248 #define USB_BUFF_STATUS_EP7_OUT_MSB    _u(15)
1249 #define USB_BUFF_STATUS_EP7_OUT_LSB    _u(15)
1250 #define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC"
1251 // -----------------------------------------------------------------------------
1252 // Field       : USB_BUFF_STATUS_EP7_IN
1253 #define USB_BUFF_STATUS_EP7_IN_RESET  _u(0x0)
1254 #define USB_BUFF_STATUS_EP7_IN_BITS   _u(0x00004000)
1255 #define USB_BUFF_STATUS_EP7_IN_MSB    _u(14)
1256 #define USB_BUFF_STATUS_EP7_IN_LSB    _u(14)
1257 #define USB_BUFF_STATUS_EP7_IN_ACCESS "WC"
1258 // -----------------------------------------------------------------------------
1259 // Field       : USB_BUFF_STATUS_EP6_OUT
1260 #define USB_BUFF_STATUS_EP6_OUT_RESET  _u(0x0)
1261 #define USB_BUFF_STATUS_EP6_OUT_BITS   _u(0x00002000)
1262 #define USB_BUFF_STATUS_EP6_OUT_MSB    _u(13)
1263 #define USB_BUFF_STATUS_EP6_OUT_LSB    _u(13)
1264 #define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC"
1265 // -----------------------------------------------------------------------------
1266 // Field       : USB_BUFF_STATUS_EP6_IN
1267 #define USB_BUFF_STATUS_EP6_IN_RESET  _u(0x0)
1268 #define USB_BUFF_STATUS_EP6_IN_BITS   _u(0x00001000)
1269 #define USB_BUFF_STATUS_EP6_IN_MSB    _u(12)
1270 #define USB_BUFF_STATUS_EP6_IN_LSB    _u(12)
1271 #define USB_BUFF_STATUS_EP6_IN_ACCESS "WC"
1272 // -----------------------------------------------------------------------------
1273 // Field       : USB_BUFF_STATUS_EP5_OUT
1274 #define USB_BUFF_STATUS_EP5_OUT_RESET  _u(0x0)
1275 #define USB_BUFF_STATUS_EP5_OUT_BITS   _u(0x00000800)
1276 #define USB_BUFF_STATUS_EP5_OUT_MSB    _u(11)
1277 #define USB_BUFF_STATUS_EP5_OUT_LSB    _u(11)
1278 #define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC"
1279 // -----------------------------------------------------------------------------
1280 // Field       : USB_BUFF_STATUS_EP5_IN
1281 #define USB_BUFF_STATUS_EP5_IN_RESET  _u(0x0)
1282 #define USB_BUFF_STATUS_EP5_IN_BITS   _u(0x00000400)
1283 #define USB_BUFF_STATUS_EP5_IN_MSB    _u(10)
1284 #define USB_BUFF_STATUS_EP5_IN_LSB    _u(10)
1285 #define USB_BUFF_STATUS_EP5_IN_ACCESS "WC"
1286 // -----------------------------------------------------------------------------
1287 // Field       : USB_BUFF_STATUS_EP4_OUT
1288 #define USB_BUFF_STATUS_EP4_OUT_RESET  _u(0x0)
1289 #define USB_BUFF_STATUS_EP4_OUT_BITS   _u(0x00000200)
1290 #define USB_BUFF_STATUS_EP4_OUT_MSB    _u(9)
1291 #define USB_BUFF_STATUS_EP4_OUT_LSB    _u(9)
1292 #define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC"
1293 // -----------------------------------------------------------------------------
1294 // Field       : USB_BUFF_STATUS_EP4_IN
1295 #define USB_BUFF_STATUS_EP4_IN_RESET  _u(0x0)
1296 #define USB_BUFF_STATUS_EP4_IN_BITS   _u(0x00000100)
1297 #define USB_BUFF_STATUS_EP4_IN_MSB    _u(8)
1298 #define USB_BUFF_STATUS_EP4_IN_LSB    _u(8)
1299 #define USB_BUFF_STATUS_EP4_IN_ACCESS "WC"
1300 // -----------------------------------------------------------------------------
1301 // Field       : USB_BUFF_STATUS_EP3_OUT
1302 #define USB_BUFF_STATUS_EP3_OUT_RESET  _u(0x0)
1303 #define USB_BUFF_STATUS_EP3_OUT_BITS   _u(0x00000080)
1304 #define USB_BUFF_STATUS_EP3_OUT_MSB    _u(7)
1305 #define USB_BUFF_STATUS_EP3_OUT_LSB    _u(7)
1306 #define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC"
1307 // -----------------------------------------------------------------------------
1308 // Field       : USB_BUFF_STATUS_EP3_IN
1309 #define USB_BUFF_STATUS_EP3_IN_RESET  _u(0x0)
1310 #define USB_BUFF_STATUS_EP3_IN_BITS   _u(0x00000040)
1311 #define USB_BUFF_STATUS_EP3_IN_MSB    _u(6)
1312 #define USB_BUFF_STATUS_EP3_IN_LSB    _u(6)
1313 #define USB_BUFF_STATUS_EP3_IN_ACCESS "WC"
1314 // -----------------------------------------------------------------------------
1315 // Field       : USB_BUFF_STATUS_EP2_OUT
1316 #define USB_BUFF_STATUS_EP2_OUT_RESET  _u(0x0)
1317 #define USB_BUFF_STATUS_EP2_OUT_BITS   _u(0x00000020)
1318 #define USB_BUFF_STATUS_EP2_OUT_MSB    _u(5)
1319 #define USB_BUFF_STATUS_EP2_OUT_LSB    _u(5)
1320 #define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC"
1321 // -----------------------------------------------------------------------------
1322 // Field       : USB_BUFF_STATUS_EP2_IN
1323 #define USB_BUFF_STATUS_EP2_IN_RESET  _u(0x0)
1324 #define USB_BUFF_STATUS_EP2_IN_BITS   _u(0x00000010)
1325 #define USB_BUFF_STATUS_EP2_IN_MSB    _u(4)
1326 #define USB_BUFF_STATUS_EP2_IN_LSB    _u(4)
1327 #define USB_BUFF_STATUS_EP2_IN_ACCESS "WC"
1328 // -----------------------------------------------------------------------------
1329 // Field       : USB_BUFF_STATUS_EP1_OUT
1330 #define USB_BUFF_STATUS_EP1_OUT_RESET  _u(0x0)
1331 #define USB_BUFF_STATUS_EP1_OUT_BITS   _u(0x00000008)
1332 #define USB_BUFF_STATUS_EP1_OUT_MSB    _u(3)
1333 #define USB_BUFF_STATUS_EP1_OUT_LSB    _u(3)
1334 #define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC"
1335 // -----------------------------------------------------------------------------
1336 // Field       : USB_BUFF_STATUS_EP1_IN
1337 #define USB_BUFF_STATUS_EP1_IN_RESET  _u(0x0)
1338 #define USB_BUFF_STATUS_EP1_IN_BITS   _u(0x00000004)
1339 #define USB_BUFF_STATUS_EP1_IN_MSB    _u(2)
1340 #define USB_BUFF_STATUS_EP1_IN_LSB    _u(2)
1341 #define USB_BUFF_STATUS_EP1_IN_ACCESS "WC"
1342 // -----------------------------------------------------------------------------
1343 // Field       : USB_BUFF_STATUS_EP0_OUT
1344 #define USB_BUFF_STATUS_EP0_OUT_RESET  _u(0x0)
1345 #define USB_BUFF_STATUS_EP0_OUT_BITS   _u(0x00000002)
1346 #define USB_BUFF_STATUS_EP0_OUT_MSB    _u(1)
1347 #define USB_BUFF_STATUS_EP0_OUT_LSB    _u(1)
1348 #define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC"
1349 // -----------------------------------------------------------------------------
1350 // Field       : USB_BUFF_STATUS_EP0_IN
1351 #define USB_BUFF_STATUS_EP0_IN_RESET  _u(0x0)
1352 #define USB_BUFF_STATUS_EP0_IN_BITS   _u(0x00000001)
1353 #define USB_BUFF_STATUS_EP0_IN_MSB    _u(0)
1354 #define USB_BUFF_STATUS_EP0_IN_LSB    _u(0)
1355 #define USB_BUFF_STATUS_EP0_IN_ACCESS "WC"
1356 // =============================================================================
1357 // Register    : USB_BUFF_CPU_SHOULD_HANDLE
1358 // Description : Which of the double buffers should be handled. Only valid if
1359 //               using an interrupt per buffer (i.e. not per 2 buffers). Not
1360 //               valid for host interrupt endpoint polling because they are only
1361 //               single buffered.
1362 #define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c)
1363 #define USB_BUFF_CPU_SHOULD_HANDLE_BITS   _u(0xffffffff)
1364 #define USB_BUFF_CPU_SHOULD_HANDLE_RESET  _u(0x00000000)
1365 // -----------------------------------------------------------------------------
1366 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT
1367 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET  _u(0x0)
1368 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS   _u(0x80000000)
1369 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB    _u(31)
1370 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB    _u(31)
1371 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO"
1372 // -----------------------------------------------------------------------------
1373 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN
1374 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET  _u(0x0)
1375 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS   _u(0x40000000)
1376 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB    _u(30)
1377 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB    _u(30)
1378 #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO"
1379 // -----------------------------------------------------------------------------
1380 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT
1381 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET  _u(0x0)
1382 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS   _u(0x20000000)
1383 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB    _u(29)
1384 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB    _u(29)
1385 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO"
1386 // -----------------------------------------------------------------------------
1387 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN
1388 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET  _u(0x0)
1389 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS   _u(0x10000000)
1390 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB    _u(28)
1391 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB    _u(28)
1392 #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO"
1393 // -----------------------------------------------------------------------------
1394 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT
1395 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET  _u(0x0)
1396 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS   _u(0x08000000)
1397 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB    _u(27)
1398 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB    _u(27)
1399 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO"
1400 // -----------------------------------------------------------------------------
1401 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN
1402 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET  _u(0x0)
1403 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS   _u(0x04000000)
1404 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB    _u(26)
1405 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB    _u(26)
1406 #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO"
1407 // -----------------------------------------------------------------------------
1408 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT
1409 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET  _u(0x0)
1410 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS   _u(0x02000000)
1411 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB    _u(25)
1412 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB    _u(25)
1413 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO"
1414 // -----------------------------------------------------------------------------
1415 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN
1416 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET  _u(0x0)
1417 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS   _u(0x01000000)
1418 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB    _u(24)
1419 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB    _u(24)
1420 #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO"
1421 // -----------------------------------------------------------------------------
1422 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT
1423 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET  _u(0x0)
1424 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS   _u(0x00800000)
1425 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB    _u(23)
1426 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB    _u(23)
1427 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO"
1428 // -----------------------------------------------------------------------------
1429 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN
1430 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET  _u(0x0)
1431 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS   _u(0x00400000)
1432 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB    _u(22)
1433 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB    _u(22)
1434 #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO"
1435 // -----------------------------------------------------------------------------
1436 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT
1437 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET  _u(0x0)
1438 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS   _u(0x00200000)
1439 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB    _u(21)
1440 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB    _u(21)
1441 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO"
1442 // -----------------------------------------------------------------------------
1443 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN
1444 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET  _u(0x0)
1445 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS   _u(0x00100000)
1446 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB    _u(20)
1447 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB    _u(20)
1448 #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO"
1449 // -----------------------------------------------------------------------------
1450 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT
1451 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET  _u(0x0)
1452 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS   _u(0x00080000)
1453 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB    _u(19)
1454 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB    _u(19)
1455 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO"
1456 // -----------------------------------------------------------------------------
1457 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN
1458 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET  _u(0x0)
1459 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS   _u(0x00040000)
1460 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB    _u(18)
1461 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB    _u(18)
1462 #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO"
1463 // -----------------------------------------------------------------------------
1464 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT
1465 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET  _u(0x0)
1466 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS   _u(0x00020000)
1467 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB    _u(17)
1468 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB    _u(17)
1469 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO"
1470 // -----------------------------------------------------------------------------
1471 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN
1472 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET  _u(0x0)
1473 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS   _u(0x00010000)
1474 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB    _u(16)
1475 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB    _u(16)
1476 #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO"
1477 // -----------------------------------------------------------------------------
1478 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT
1479 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET  _u(0x0)
1480 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS   _u(0x00008000)
1481 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB    _u(15)
1482 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB    _u(15)
1483 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO"
1484 // -----------------------------------------------------------------------------
1485 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN
1486 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET  _u(0x0)
1487 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS   _u(0x00004000)
1488 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB    _u(14)
1489 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB    _u(14)
1490 #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO"
1491 // -----------------------------------------------------------------------------
1492 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT
1493 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET  _u(0x0)
1494 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS   _u(0x00002000)
1495 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB    _u(13)
1496 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB    _u(13)
1497 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO"
1498 // -----------------------------------------------------------------------------
1499 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN
1500 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET  _u(0x0)
1501 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS   _u(0x00001000)
1502 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB    _u(12)
1503 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB    _u(12)
1504 #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO"
1505 // -----------------------------------------------------------------------------
1506 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT
1507 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET  _u(0x0)
1508 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS   _u(0x00000800)
1509 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB    _u(11)
1510 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB    _u(11)
1511 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO"
1512 // -----------------------------------------------------------------------------
1513 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN
1514 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET  _u(0x0)
1515 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS   _u(0x00000400)
1516 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB    _u(10)
1517 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB    _u(10)
1518 #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO"
1519 // -----------------------------------------------------------------------------
1520 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT
1521 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET  _u(0x0)
1522 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS   _u(0x00000200)
1523 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB    _u(9)
1524 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB    _u(9)
1525 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO"
1526 // -----------------------------------------------------------------------------
1527 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN
1528 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET  _u(0x0)
1529 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS   _u(0x00000100)
1530 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB    _u(8)
1531 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB    _u(8)
1532 #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO"
1533 // -----------------------------------------------------------------------------
1534 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT
1535 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET  _u(0x0)
1536 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS   _u(0x00000080)
1537 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB    _u(7)
1538 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB    _u(7)
1539 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO"
1540 // -----------------------------------------------------------------------------
1541 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN
1542 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET  _u(0x0)
1543 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS   _u(0x00000040)
1544 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB    _u(6)
1545 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB    _u(6)
1546 #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO"
1547 // -----------------------------------------------------------------------------
1548 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT
1549 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET  _u(0x0)
1550 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS   _u(0x00000020)
1551 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB    _u(5)
1552 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB    _u(5)
1553 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO"
1554 // -----------------------------------------------------------------------------
1555 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN
1556 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET  _u(0x0)
1557 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS   _u(0x00000010)
1558 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB    _u(4)
1559 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB    _u(4)
1560 #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO"
1561 // -----------------------------------------------------------------------------
1562 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT
1563 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET  _u(0x0)
1564 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS   _u(0x00000008)
1565 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB    _u(3)
1566 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB    _u(3)
1567 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO"
1568 // -----------------------------------------------------------------------------
1569 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN
1570 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET  _u(0x0)
1571 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS   _u(0x00000004)
1572 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB    _u(2)
1573 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB    _u(2)
1574 #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO"
1575 // -----------------------------------------------------------------------------
1576 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT
1577 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET  _u(0x0)
1578 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS   _u(0x00000002)
1579 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB    _u(1)
1580 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB    _u(1)
1581 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO"
1582 // -----------------------------------------------------------------------------
1583 // Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN
1584 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET  _u(0x0)
1585 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS   _u(0x00000001)
1586 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB    _u(0)
1587 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB    _u(0)
1588 #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO"
1589 // =============================================================================
1590 // Register    : USB_EP_ABORT
1591 // Description : Device only: Can be set to ignore the buffer control register
1592 //               for this endpoint in case you would like to revoke a buffer. A
1593 //               NAK will be sent for every access to the endpoint until this
1594 //               bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set
1595 //               when it is safe to modify the buffer control register.
1596 #define USB_EP_ABORT_OFFSET _u(0x00000060)
1597 #define USB_EP_ABORT_BITS   _u(0xffffffff)
1598 #define USB_EP_ABORT_RESET  _u(0x00000000)
1599 // -----------------------------------------------------------------------------
1600 // Field       : USB_EP_ABORT_EP15_OUT
1601 #define USB_EP_ABORT_EP15_OUT_RESET  _u(0x0)
1602 #define USB_EP_ABORT_EP15_OUT_BITS   _u(0x80000000)
1603 #define USB_EP_ABORT_EP15_OUT_MSB    _u(31)
1604 #define USB_EP_ABORT_EP15_OUT_LSB    _u(31)
1605 #define USB_EP_ABORT_EP15_OUT_ACCESS "RW"
1606 // -----------------------------------------------------------------------------
1607 // Field       : USB_EP_ABORT_EP15_IN
1608 #define USB_EP_ABORT_EP15_IN_RESET  _u(0x0)
1609 #define USB_EP_ABORT_EP15_IN_BITS   _u(0x40000000)
1610 #define USB_EP_ABORT_EP15_IN_MSB    _u(30)
1611 #define USB_EP_ABORT_EP15_IN_LSB    _u(30)
1612 #define USB_EP_ABORT_EP15_IN_ACCESS "RW"
1613 // -----------------------------------------------------------------------------
1614 // Field       : USB_EP_ABORT_EP14_OUT
1615 #define USB_EP_ABORT_EP14_OUT_RESET  _u(0x0)
1616 #define USB_EP_ABORT_EP14_OUT_BITS   _u(0x20000000)
1617 #define USB_EP_ABORT_EP14_OUT_MSB    _u(29)
1618 #define USB_EP_ABORT_EP14_OUT_LSB    _u(29)
1619 #define USB_EP_ABORT_EP14_OUT_ACCESS "RW"
1620 // -----------------------------------------------------------------------------
1621 // Field       : USB_EP_ABORT_EP14_IN
1622 #define USB_EP_ABORT_EP14_IN_RESET  _u(0x0)
1623 #define USB_EP_ABORT_EP14_IN_BITS   _u(0x10000000)
1624 #define USB_EP_ABORT_EP14_IN_MSB    _u(28)
1625 #define USB_EP_ABORT_EP14_IN_LSB    _u(28)
1626 #define USB_EP_ABORT_EP14_IN_ACCESS "RW"
1627 // -----------------------------------------------------------------------------
1628 // Field       : USB_EP_ABORT_EP13_OUT
1629 #define USB_EP_ABORT_EP13_OUT_RESET  _u(0x0)
1630 #define USB_EP_ABORT_EP13_OUT_BITS   _u(0x08000000)
1631 #define USB_EP_ABORT_EP13_OUT_MSB    _u(27)
1632 #define USB_EP_ABORT_EP13_OUT_LSB    _u(27)
1633 #define USB_EP_ABORT_EP13_OUT_ACCESS "RW"
1634 // -----------------------------------------------------------------------------
1635 // Field       : USB_EP_ABORT_EP13_IN
1636 #define USB_EP_ABORT_EP13_IN_RESET  _u(0x0)
1637 #define USB_EP_ABORT_EP13_IN_BITS   _u(0x04000000)
1638 #define USB_EP_ABORT_EP13_IN_MSB    _u(26)
1639 #define USB_EP_ABORT_EP13_IN_LSB    _u(26)
1640 #define USB_EP_ABORT_EP13_IN_ACCESS "RW"
1641 // -----------------------------------------------------------------------------
1642 // Field       : USB_EP_ABORT_EP12_OUT
1643 #define USB_EP_ABORT_EP12_OUT_RESET  _u(0x0)
1644 #define USB_EP_ABORT_EP12_OUT_BITS   _u(0x02000000)
1645 #define USB_EP_ABORT_EP12_OUT_MSB    _u(25)
1646 #define USB_EP_ABORT_EP12_OUT_LSB    _u(25)
1647 #define USB_EP_ABORT_EP12_OUT_ACCESS "RW"
1648 // -----------------------------------------------------------------------------
1649 // Field       : USB_EP_ABORT_EP12_IN
1650 #define USB_EP_ABORT_EP12_IN_RESET  _u(0x0)
1651 #define USB_EP_ABORT_EP12_IN_BITS   _u(0x01000000)
1652 #define USB_EP_ABORT_EP12_IN_MSB    _u(24)
1653 #define USB_EP_ABORT_EP12_IN_LSB    _u(24)
1654 #define USB_EP_ABORT_EP12_IN_ACCESS "RW"
1655 // -----------------------------------------------------------------------------
1656 // Field       : USB_EP_ABORT_EP11_OUT
1657 #define USB_EP_ABORT_EP11_OUT_RESET  _u(0x0)
1658 #define USB_EP_ABORT_EP11_OUT_BITS   _u(0x00800000)
1659 #define USB_EP_ABORT_EP11_OUT_MSB    _u(23)
1660 #define USB_EP_ABORT_EP11_OUT_LSB    _u(23)
1661 #define USB_EP_ABORT_EP11_OUT_ACCESS "RW"
1662 // -----------------------------------------------------------------------------
1663 // Field       : USB_EP_ABORT_EP11_IN
1664 #define USB_EP_ABORT_EP11_IN_RESET  _u(0x0)
1665 #define USB_EP_ABORT_EP11_IN_BITS   _u(0x00400000)
1666 #define USB_EP_ABORT_EP11_IN_MSB    _u(22)
1667 #define USB_EP_ABORT_EP11_IN_LSB    _u(22)
1668 #define USB_EP_ABORT_EP11_IN_ACCESS "RW"
1669 // -----------------------------------------------------------------------------
1670 // Field       : USB_EP_ABORT_EP10_OUT
1671 #define USB_EP_ABORT_EP10_OUT_RESET  _u(0x0)
1672 #define USB_EP_ABORT_EP10_OUT_BITS   _u(0x00200000)
1673 #define USB_EP_ABORT_EP10_OUT_MSB    _u(21)
1674 #define USB_EP_ABORT_EP10_OUT_LSB    _u(21)
1675 #define USB_EP_ABORT_EP10_OUT_ACCESS "RW"
1676 // -----------------------------------------------------------------------------
1677 // Field       : USB_EP_ABORT_EP10_IN
1678 #define USB_EP_ABORT_EP10_IN_RESET  _u(0x0)
1679 #define USB_EP_ABORT_EP10_IN_BITS   _u(0x00100000)
1680 #define USB_EP_ABORT_EP10_IN_MSB    _u(20)
1681 #define USB_EP_ABORT_EP10_IN_LSB    _u(20)
1682 #define USB_EP_ABORT_EP10_IN_ACCESS "RW"
1683 // -----------------------------------------------------------------------------
1684 // Field       : USB_EP_ABORT_EP9_OUT
1685 #define USB_EP_ABORT_EP9_OUT_RESET  _u(0x0)
1686 #define USB_EP_ABORT_EP9_OUT_BITS   _u(0x00080000)
1687 #define USB_EP_ABORT_EP9_OUT_MSB    _u(19)
1688 #define USB_EP_ABORT_EP9_OUT_LSB    _u(19)
1689 #define USB_EP_ABORT_EP9_OUT_ACCESS "RW"
1690 // -----------------------------------------------------------------------------
1691 // Field       : USB_EP_ABORT_EP9_IN
1692 #define USB_EP_ABORT_EP9_IN_RESET  _u(0x0)
1693 #define USB_EP_ABORT_EP9_IN_BITS   _u(0x00040000)
1694 #define USB_EP_ABORT_EP9_IN_MSB    _u(18)
1695 #define USB_EP_ABORT_EP9_IN_LSB    _u(18)
1696 #define USB_EP_ABORT_EP9_IN_ACCESS "RW"
1697 // -----------------------------------------------------------------------------
1698 // Field       : USB_EP_ABORT_EP8_OUT
1699 #define USB_EP_ABORT_EP8_OUT_RESET  _u(0x0)
1700 #define USB_EP_ABORT_EP8_OUT_BITS   _u(0x00020000)
1701 #define USB_EP_ABORT_EP8_OUT_MSB    _u(17)
1702 #define USB_EP_ABORT_EP8_OUT_LSB    _u(17)
1703 #define USB_EP_ABORT_EP8_OUT_ACCESS "RW"
1704 // -----------------------------------------------------------------------------
1705 // Field       : USB_EP_ABORT_EP8_IN
1706 #define USB_EP_ABORT_EP8_IN_RESET  _u(0x0)
1707 #define USB_EP_ABORT_EP8_IN_BITS   _u(0x00010000)
1708 #define USB_EP_ABORT_EP8_IN_MSB    _u(16)
1709 #define USB_EP_ABORT_EP8_IN_LSB    _u(16)
1710 #define USB_EP_ABORT_EP8_IN_ACCESS "RW"
1711 // -----------------------------------------------------------------------------
1712 // Field       : USB_EP_ABORT_EP7_OUT
1713 #define USB_EP_ABORT_EP7_OUT_RESET  _u(0x0)
1714 #define USB_EP_ABORT_EP7_OUT_BITS   _u(0x00008000)
1715 #define USB_EP_ABORT_EP7_OUT_MSB    _u(15)
1716 #define USB_EP_ABORT_EP7_OUT_LSB    _u(15)
1717 #define USB_EP_ABORT_EP7_OUT_ACCESS "RW"
1718 // -----------------------------------------------------------------------------
1719 // Field       : USB_EP_ABORT_EP7_IN
1720 #define USB_EP_ABORT_EP7_IN_RESET  _u(0x0)
1721 #define USB_EP_ABORT_EP7_IN_BITS   _u(0x00004000)
1722 #define USB_EP_ABORT_EP7_IN_MSB    _u(14)
1723 #define USB_EP_ABORT_EP7_IN_LSB    _u(14)
1724 #define USB_EP_ABORT_EP7_IN_ACCESS "RW"
1725 // -----------------------------------------------------------------------------
1726 // Field       : USB_EP_ABORT_EP6_OUT
1727 #define USB_EP_ABORT_EP6_OUT_RESET  _u(0x0)
1728 #define USB_EP_ABORT_EP6_OUT_BITS   _u(0x00002000)
1729 #define USB_EP_ABORT_EP6_OUT_MSB    _u(13)
1730 #define USB_EP_ABORT_EP6_OUT_LSB    _u(13)
1731 #define USB_EP_ABORT_EP6_OUT_ACCESS "RW"
1732 // -----------------------------------------------------------------------------
1733 // Field       : USB_EP_ABORT_EP6_IN
1734 #define USB_EP_ABORT_EP6_IN_RESET  _u(0x0)
1735 #define USB_EP_ABORT_EP6_IN_BITS   _u(0x00001000)
1736 #define USB_EP_ABORT_EP6_IN_MSB    _u(12)
1737 #define USB_EP_ABORT_EP6_IN_LSB    _u(12)
1738 #define USB_EP_ABORT_EP6_IN_ACCESS "RW"
1739 // -----------------------------------------------------------------------------
1740 // Field       : USB_EP_ABORT_EP5_OUT
1741 #define USB_EP_ABORT_EP5_OUT_RESET  _u(0x0)
1742 #define USB_EP_ABORT_EP5_OUT_BITS   _u(0x00000800)
1743 #define USB_EP_ABORT_EP5_OUT_MSB    _u(11)
1744 #define USB_EP_ABORT_EP5_OUT_LSB    _u(11)
1745 #define USB_EP_ABORT_EP5_OUT_ACCESS "RW"
1746 // -----------------------------------------------------------------------------
1747 // Field       : USB_EP_ABORT_EP5_IN
1748 #define USB_EP_ABORT_EP5_IN_RESET  _u(0x0)
1749 #define USB_EP_ABORT_EP5_IN_BITS   _u(0x00000400)
1750 #define USB_EP_ABORT_EP5_IN_MSB    _u(10)
1751 #define USB_EP_ABORT_EP5_IN_LSB    _u(10)
1752 #define USB_EP_ABORT_EP5_IN_ACCESS "RW"
1753 // -----------------------------------------------------------------------------
1754 // Field       : USB_EP_ABORT_EP4_OUT
1755 #define USB_EP_ABORT_EP4_OUT_RESET  _u(0x0)
1756 #define USB_EP_ABORT_EP4_OUT_BITS   _u(0x00000200)
1757 #define USB_EP_ABORT_EP4_OUT_MSB    _u(9)
1758 #define USB_EP_ABORT_EP4_OUT_LSB    _u(9)
1759 #define USB_EP_ABORT_EP4_OUT_ACCESS "RW"
1760 // -----------------------------------------------------------------------------
1761 // Field       : USB_EP_ABORT_EP4_IN
1762 #define USB_EP_ABORT_EP4_IN_RESET  _u(0x0)
1763 #define USB_EP_ABORT_EP4_IN_BITS   _u(0x00000100)
1764 #define USB_EP_ABORT_EP4_IN_MSB    _u(8)
1765 #define USB_EP_ABORT_EP4_IN_LSB    _u(8)
1766 #define USB_EP_ABORT_EP4_IN_ACCESS "RW"
1767 // -----------------------------------------------------------------------------
1768 // Field       : USB_EP_ABORT_EP3_OUT
1769 #define USB_EP_ABORT_EP3_OUT_RESET  _u(0x0)
1770 #define USB_EP_ABORT_EP3_OUT_BITS   _u(0x00000080)
1771 #define USB_EP_ABORT_EP3_OUT_MSB    _u(7)
1772 #define USB_EP_ABORT_EP3_OUT_LSB    _u(7)
1773 #define USB_EP_ABORT_EP3_OUT_ACCESS "RW"
1774 // -----------------------------------------------------------------------------
1775 // Field       : USB_EP_ABORT_EP3_IN
1776 #define USB_EP_ABORT_EP3_IN_RESET  _u(0x0)
1777 #define USB_EP_ABORT_EP3_IN_BITS   _u(0x00000040)
1778 #define USB_EP_ABORT_EP3_IN_MSB    _u(6)
1779 #define USB_EP_ABORT_EP3_IN_LSB    _u(6)
1780 #define USB_EP_ABORT_EP3_IN_ACCESS "RW"
1781 // -----------------------------------------------------------------------------
1782 // Field       : USB_EP_ABORT_EP2_OUT
1783 #define USB_EP_ABORT_EP2_OUT_RESET  _u(0x0)
1784 #define USB_EP_ABORT_EP2_OUT_BITS   _u(0x00000020)
1785 #define USB_EP_ABORT_EP2_OUT_MSB    _u(5)
1786 #define USB_EP_ABORT_EP2_OUT_LSB    _u(5)
1787 #define USB_EP_ABORT_EP2_OUT_ACCESS "RW"
1788 // -----------------------------------------------------------------------------
1789 // Field       : USB_EP_ABORT_EP2_IN
1790 #define USB_EP_ABORT_EP2_IN_RESET  _u(0x0)
1791 #define USB_EP_ABORT_EP2_IN_BITS   _u(0x00000010)
1792 #define USB_EP_ABORT_EP2_IN_MSB    _u(4)
1793 #define USB_EP_ABORT_EP2_IN_LSB    _u(4)
1794 #define USB_EP_ABORT_EP2_IN_ACCESS "RW"
1795 // -----------------------------------------------------------------------------
1796 // Field       : USB_EP_ABORT_EP1_OUT
1797 #define USB_EP_ABORT_EP1_OUT_RESET  _u(0x0)
1798 #define USB_EP_ABORT_EP1_OUT_BITS   _u(0x00000008)
1799 #define USB_EP_ABORT_EP1_OUT_MSB    _u(3)
1800 #define USB_EP_ABORT_EP1_OUT_LSB    _u(3)
1801 #define USB_EP_ABORT_EP1_OUT_ACCESS "RW"
1802 // -----------------------------------------------------------------------------
1803 // Field       : USB_EP_ABORT_EP1_IN
1804 #define USB_EP_ABORT_EP1_IN_RESET  _u(0x0)
1805 #define USB_EP_ABORT_EP1_IN_BITS   _u(0x00000004)
1806 #define USB_EP_ABORT_EP1_IN_MSB    _u(2)
1807 #define USB_EP_ABORT_EP1_IN_LSB    _u(2)
1808 #define USB_EP_ABORT_EP1_IN_ACCESS "RW"
1809 // -----------------------------------------------------------------------------
1810 // Field       : USB_EP_ABORT_EP0_OUT
1811 #define USB_EP_ABORT_EP0_OUT_RESET  _u(0x0)
1812 #define USB_EP_ABORT_EP0_OUT_BITS   _u(0x00000002)
1813 #define USB_EP_ABORT_EP0_OUT_MSB    _u(1)
1814 #define USB_EP_ABORT_EP0_OUT_LSB    _u(1)
1815 #define USB_EP_ABORT_EP0_OUT_ACCESS "RW"
1816 // -----------------------------------------------------------------------------
1817 // Field       : USB_EP_ABORT_EP0_IN
1818 #define USB_EP_ABORT_EP0_IN_RESET  _u(0x0)
1819 #define USB_EP_ABORT_EP0_IN_BITS   _u(0x00000001)
1820 #define USB_EP_ABORT_EP0_IN_MSB    _u(0)
1821 #define USB_EP_ABORT_EP0_IN_LSB    _u(0)
1822 #define USB_EP_ABORT_EP0_IN_ACCESS "RW"
1823 // =============================================================================
1824 // Register    : USB_EP_ABORT_DONE
1825 // Description : Device only: Used in conjunction with `EP_ABORT`. Set once an
1826 //               endpoint is idle so the programmer knows it is safe to modify
1827 //               the buffer control register.
1828 #define USB_EP_ABORT_DONE_OFFSET _u(0x00000064)
1829 #define USB_EP_ABORT_DONE_BITS   _u(0xffffffff)
1830 #define USB_EP_ABORT_DONE_RESET  _u(0x00000000)
1831 // -----------------------------------------------------------------------------
1832 // Field       : USB_EP_ABORT_DONE_EP15_OUT
1833 #define USB_EP_ABORT_DONE_EP15_OUT_RESET  _u(0x0)
1834 #define USB_EP_ABORT_DONE_EP15_OUT_BITS   _u(0x80000000)
1835 #define USB_EP_ABORT_DONE_EP15_OUT_MSB    _u(31)
1836 #define USB_EP_ABORT_DONE_EP15_OUT_LSB    _u(31)
1837 #define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC"
1838 // -----------------------------------------------------------------------------
1839 // Field       : USB_EP_ABORT_DONE_EP15_IN
1840 #define USB_EP_ABORT_DONE_EP15_IN_RESET  _u(0x0)
1841 #define USB_EP_ABORT_DONE_EP15_IN_BITS   _u(0x40000000)
1842 #define USB_EP_ABORT_DONE_EP15_IN_MSB    _u(30)
1843 #define USB_EP_ABORT_DONE_EP15_IN_LSB    _u(30)
1844 #define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC"
1845 // -----------------------------------------------------------------------------
1846 // Field       : USB_EP_ABORT_DONE_EP14_OUT
1847 #define USB_EP_ABORT_DONE_EP14_OUT_RESET  _u(0x0)
1848 #define USB_EP_ABORT_DONE_EP14_OUT_BITS   _u(0x20000000)
1849 #define USB_EP_ABORT_DONE_EP14_OUT_MSB    _u(29)
1850 #define USB_EP_ABORT_DONE_EP14_OUT_LSB    _u(29)
1851 #define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC"
1852 // -----------------------------------------------------------------------------
1853 // Field       : USB_EP_ABORT_DONE_EP14_IN
1854 #define USB_EP_ABORT_DONE_EP14_IN_RESET  _u(0x0)
1855 #define USB_EP_ABORT_DONE_EP14_IN_BITS   _u(0x10000000)
1856 #define USB_EP_ABORT_DONE_EP14_IN_MSB    _u(28)
1857 #define USB_EP_ABORT_DONE_EP14_IN_LSB    _u(28)
1858 #define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC"
1859 // -----------------------------------------------------------------------------
1860 // Field       : USB_EP_ABORT_DONE_EP13_OUT
1861 #define USB_EP_ABORT_DONE_EP13_OUT_RESET  _u(0x0)
1862 #define USB_EP_ABORT_DONE_EP13_OUT_BITS   _u(0x08000000)
1863 #define USB_EP_ABORT_DONE_EP13_OUT_MSB    _u(27)
1864 #define USB_EP_ABORT_DONE_EP13_OUT_LSB    _u(27)
1865 #define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC"
1866 // -----------------------------------------------------------------------------
1867 // Field       : USB_EP_ABORT_DONE_EP13_IN
1868 #define USB_EP_ABORT_DONE_EP13_IN_RESET  _u(0x0)
1869 #define USB_EP_ABORT_DONE_EP13_IN_BITS   _u(0x04000000)
1870 #define USB_EP_ABORT_DONE_EP13_IN_MSB    _u(26)
1871 #define USB_EP_ABORT_DONE_EP13_IN_LSB    _u(26)
1872 #define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC"
1873 // -----------------------------------------------------------------------------
1874 // Field       : USB_EP_ABORT_DONE_EP12_OUT
1875 #define USB_EP_ABORT_DONE_EP12_OUT_RESET  _u(0x0)
1876 #define USB_EP_ABORT_DONE_EP12_OUT_BITS   _u(0x02000000)
1877 #define USB_EP_ABORT_DONE_EP12_OUT_MSB    _u(25)
1878 #define USB_EP_ABORT_DONE_EP12_OUT_LSB    _u(25)
1879 #define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC"
1880 // -----------------------------------------------------------------------------
1881 // Field       : USB_EP_ABORT_DONE_EP12_IN
1882 #define USB_EP_ABORT_DONE_EP12_IN_RESET  _u(0x0)
1883 #define USB_EP_ABORT_DONE_EP12_IN_BITS   _u(0x01000000)
1884 #define USB_EP_ABORT_DONE_EP12_IN_MSB    _u(24)
1885 #define USB_EP_ABORT_DONE_EP12_IN_LSB    _u(24)
1886 #define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC"
1887 // -----------------------------------------------------------------------------
1888 // Field       : USB_EP_ABORT_DONE_EP11_OUT
1889 #define USB_EP_ABORT_DONE_EP11_OUT_RESET  _u(0x0)
1890 #define USB_EP_ABORT_DONE_EP11_OUT_BITS   _u(0x00800000)
1891 #define USB_EP_ABORT_DONE_EP11_OUT_MSB    _u(23)
1892 #define USB_EP_ABORT_DONE_EP11_OUT_LSB    _u(23)
1893 #define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC"
1894 // -----------------------------------------------------------------------------
1895 // Field       : USB_EP_ABORT_DONE_EP11_IN
1896 #define USB_EP_ABORT_DONE_EP11_IN_RESET  _u(0x0)
1897 #define USB_EP_ABORT_DONE_EP11_IN_BITS   _u(0x00400000)
1898 #define USB_EP_ABORT_DONE_EP11_IN_MSB    _u(22)
1899 #define USB_EP_ABORT_DONE_EP11_IN_LSB    _u(22)
1900 #define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC"
1901 // -----------------------------------------------------------------------------
1902 // Field       : USB_EP_ABORT_DONE_EP10_OUT
1903 #define USB_EP_ABORT_DONE_EP10_OUT_RESET  _u(0x0)
1904 #define USB_EP_ABORT_DONE_EP10_OUT_BITS   _u(0x00200000)
1905 #define USB_EP_ABORT_DONE_EP10_OUT_MSB    _u(21)
1906 #define USB_EP_ABORT_DONE_EP10_OUT_LSB    _u(21)
1907 #define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC"
1908 // -----------------------------------------------------------------------------
1909 // Field       : USB_EP_ABORT_DONE_EP10_IN
1910 #define USB_EP_ABORT_DONE_EP10_IN_RESET  _u(0x0)
1911 #define USB_EP_ABORT_DONE_EP10_IN_BITS   _u(0x00100000)
1912 #define USB_EP_ABORT_DONE_EP10_IN_MSB    _u(20)
1913 #define USB_EP_ABORT_DONE_EP10_IN_LSB    _u(20)
1914 #define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC"
1915 // -----------------------------------------------------------------------------
1916 // Field       : USB_EP_ABORT_DONE_EP9_OUT
1917 #define USB_EP_ABORT_DONE_EP9_OUT_RESET  _u(0x0)
1918 #define USB_EP_ABORT_DONE_EP9_OUT_BITS   _u(0x00080000)
1919 #define USB_EP_ABORT_DONE_EP9_OUT_MSB    _u(19)
1920 #define USB_EP_ABORT_DONE_EP9_OUT_LSB    _u(19)
1921 #define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC"
1922 // -----------------------------------------------------------------------------
1923 // Field       : USB_EP_ABORT_DONE_EP9_IN
1924 #define USB_EP_ABORT_DONE_EP9_IN_RESET  _u(0x0)
1925 #define USB_EP_ABORT_DONE_EP9_IN_BITS   _u(0x00040000)
1926 #define USB_EP_ABORT_DONE_EP9_IN_MSB    _u(18)
1927 #define USB_EP_ABORT_DONE_EP9_IN_LSB    _u(18)
1928 #define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC"
1929 // -----------------------------------------------------------------------------
1930 // Field       : USB_EP_ABORT_DONE_EP8_OUT
1931 #define USB_EP_ABORT_DONE_EP8_OUT_RESET  _u(0x0)
1932 #define USB_EP_ABORT_DONE_EP8_OUT_BITS   _u(0x00020000)
1933 #define USB_EP_ABORT_DONE_EP8_OUT_MSB    _u(17)
1934 #define USB_EP_ABORT_DONE_EP8_OUT_LSB    _u(17)
1935 #define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC"
1936 // -----------------------------------------------------------------------------
1937 // Field       : USB_EP_ABORT_DONE_EP8_IN
1938 #define USB_EP_ABORT_DONE_EP8_IN_RESET  _u(0x0)
1939 #define USB_EP_ABORT_DONE_EP8_IN_BITS   _u(0x00010000)
1940 #define USB_EP_ABORT_DONE_EP8_IN_MSB    _u(16)
1941 #define USB_EP_ABORT_DONE_EP8_IN_LSB    _u(16)
1942 #define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC"
1943 // -----------------------------------------------------------------------------
1944 // Field       : USB_EP_ABORT_DONE_EP7_OUT
1945 #define USB_EP_ABORT_DONE_EP7_OUT_RESET  _u(0x0)
1946 #define USB_EP_ABORT_DONE_EP7_OUT_BITS   _u(0x00008000)
1947 #define USB_EP_ABORT_DONE_EP7_OUT_MSB    _u(15)
1948 #define USB_EP_ABORT_DONE_EP7_OUT_LSB    _u(15)
1949 #define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC"
1950 // -----------------------------------------------------------------------------
1951 // Field       : USB_EP_ABORT_DONE_EP7_IN
1952 #define USB_EP_ABORT_DONE_EP7_IN_RESET  _u(0x0)
1953 #define USB_EP_ABORT_DONE_EP7_IN_BITS   _u(0x00004000)
1954 #define USB_EP_ABORT_DONE_EP7_IN_MSB    _u(14)
1955 #define USB_EP_ABORT_DONE_EP7_IN_LSB    _u(14)
1956 #define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC"
1957 // -----------------------------------------------------------------------------
1958 // Field       : USB_EP_ABORT_DONE_EP6_OUT
1959 #define USB_EP_ABORT_DONE_EP6_OUT_RESET  _u(0x0)
1960 #define USB_EP_ABORT_DONE_EP6_OUT_BITS   _u(0x00002000)
1961 #define USB_EP_ABORT_DONE_EP6_OUT_MSB    _u(13)
1962 #define USB_EP_ABORT_DONE_EP6_OUT_LSB    _u(13)
1963 #define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC"
1964 // -----------------------------------------------------------------------------
1965 // Field       : USB_EP_ABORT_DONE_EP6_IN
1966 #define USB_EP_ABORT_DONE_EP6_IN_RESET  _u(0x0)
1967 #define USB_EP_ABORT_DONE_EP6_IN_BITS   _u(0x00001000)
1968 #define USB_EP_ABORT_DONE_EP6_IN_MSB    _u(12)
1969 #define USB_EP_ABORT_DONE_EP6_IN_LSB    _u(12)
1970 #define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC"
1971 // -----------------------------------------------------------------------------
1972 // Field       : USB_EP_ABORT_DONE_EP5_OUT
1973 #define USB_EP_ABORT_DONE_EP5_OUT_RESET  _u(0x0)
1974 #define USB_EP_ABORT_DONE_EP5_OUT_BITS   _u(0x00000800)
1975 #define USB_EP_ABORT_DONE_EP5_OUT_MSB    _u(11)
1976 #define USB_EP_ABORT_DONE_EP5_OUT_LSB    _u(11)
1977 #define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC"
1978 // -----------------------------------------------------------------------------
1979 // Field       : USB_EP_ABORT_DONE_EP5_IN
1980 #define USB_EP_ABORT_DONE_EP5_IN_RESET  _u(0x0)
1981 #define USB_EP_ABORT_DONE_EP5_IN_BITS   _u(0x00000400)
1982 #define USB_EP_ABORT_DONE_EP5_IN_MSB    _u(10)
1983 #define USB_EP_ABORT_DONE_EP5_IN_LSB    _u(10)
1984 #define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC"
1985 // -----------------------------------------------------------------------------
1986 // Field       : USB_EP_ABORT_DONE_EP4_OUT
1987 #define USB_EP_ABORT_DONE_EP4_OUT_RESET  _u(0x0)
1988 #define USB_EP_ABORT_DONE_EP4_OUT_BITS   _u(0x00000200)
1989 #define USB_EP_ABORT_DONE_EP4_OUT_MSB    _u(9)
1990 #define USB_EP_ABORT_DONE_EP4_OUT_LSB    _u(9)
1991 #define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC"
1992 // -----------------------------------------------------------------------------
1993 // Field       : USB_EP_ABORT_DONE_EP4_IN
1994 #define USB_EP_ABORT_DONE_EP4_IN_RESET  _u(0x0)
1995 #define USB_EP_ABORT_DONE_EP4_IN_BITS   _u(0x00000100)
1996 #define USB_EP_ABORT_DONE_EP4_IN_MSB    _u(8)
1997 #define USB_EP_ABORT_DONE_EP4_IN_LSB    _u(8)
1998 #define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC"
1999 // -----------------------------------------------------------------------------
2000 // Field       : USB_EP_ABORT_DONE_EP3_OUT
2001 #define USB_EP_ABORT_DONE_EP3_OUT_RESET  _u(0x0)
2002 #define USB_EP_ABORT_DONE_EP3_OUT_BITS   _u(0x00000080)
2003 #define USB_EP_ABORT_DONE_EP3_OUT_MSB    _u(7)
2004 #define USB_EP_ABORT_DONE_EP3_OUT_LSB    _u(7)
2005 #define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC"
2006 // -----------------------------------------------------------------------------
2007 // Field       : USB_EP_ABORT_DONE_EP3_IN
2008 #define USB_EP_ABORT_DONE_EP3_IN_RESET  _u(0x0)
2009 #define USB_EP_ABORT_DONE_EP3_IN_BITS   _u(0x00000040)
2010 #define USB_EP_ABORT_DONE_EP3_IN_MSB    _u(6)
2011 #define USB_EP_ABORT_DONE_EP3_IN_LSB    _u(6)
2012 #define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC"
2013 // -----------------------------------------------------------------------------
2014 // Field       : USB_EP_ABORT_DONE_EP2_OUT
2015 #define USB_EP_ABORT_DONE_EP2_OUT_RESET  _u(0x0)
2016 #define USB_EP_ABORT_DONE_EP2_OUT_BITS   _u(0x00000020)
2017 #define USB_EP_ABORT_DONE_EP2_OUT_MSB    _u(5)
2018 #define USB_EP_ABORT_DONE_EP2_OUT_LSB    _u(5)
2019 #define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC"
2020 // -----------------------------------------------------------------------------
2021 // Field       : USB_EP_ABORT_DONE_EP2_IN
2022 #define USB_EP_ABORT_DONE_EP2_IN_RESET  _u(0x0)
2023 #define USB_EP_ABORT_DONE_EP2_IN_BITS   _u(0x00000010)
2024 #define USB_EP_ABORT_DONE_EP2_IN_MSB    _u(4)
2025 #define USB_EP_ABORT_DONE_EP2_IN_LSB    _u(4)
2026 #define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC"
2027 // -----------------------------------------------------------------------------
2028 // Field       : USB_EP_ABORT_DONE_EP1_OUT
2029 #define USB_EP_ABORT_DONE_EP1_OUT_RESET  _u(0x0)
2030 #define USB_EP_ABORT_DONE_EP1_OUT_BITS   _u(0x00000008)
2031 #define USB_EP_ABORT_DONE_EP1_OUT_MSB    _u(3)
2032 #define USB_EP_ABORT_DONE_EP1_OUT_LSB    _u(3)
2033 #define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC"
2034 // -----------------------------------------------------------------------------
2035 // Field       : USB_EP_ABORT_DONE_EP1_IN
2036 #define USB_EP_ABORT_DONE_EP1_IN_RESET  _u(0x0)
2037 #define USB_EP_ABORT_DONE_EP1_IN_BITS   _u(0x00000004)
2038 #define USB_EP_ABORT_DONE_EP1_IN_MSB    _u(2)
2039 #define USB_EP_ABORT_DONE_EP1_IN_LSB    _u(2)
2040 #define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC"
2041 // -----------------------------------------------------------------------------
2042 // Field       : USB_EP_ABORT_DONE_EP0_OUT
2043 #define USB_EP_ABORT_DONE_EP0_OUT_RESET  _u(0x0)
2044 #define USB_EP_ABORT_DONE_EP0_OUT_BITS   _u(0x00000002)
2045 #define USB_EP_ABORT_DONE_EP0_OUT_MSB    _u(1)
2046 #define USB_EP_ABORT_DONE_EP0_OUT_LSB    _u(1)
2047 #define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC"
2048 // -----------------------------------------------------------------------------
2049 // Field       : USB_EP_ABORT_DONE_EP0_IN
2050 #define USB_EP_ABORT_DONE_EP0_IN_RESET  _u(0x0)
2051 #define USB_EP_ABORT_DONE_EP0_IN_BITS   _u(0x00000001)
2052 #define USB_EP_ABORT_DONE_EP0_IN_MSB    _u(0)
2053 #define USB_EP_ABORT_DONE_EP0_IN_LSB    _u(0)
2054 #define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC"
2055 // =============================================================================
2056 // Register    : USB_EP_STALL_ARM
2057 // Description : Device: this bit must be set in conjunction with the `STALL`
2058 //               bit in the buffer control register to send a STALL on EP0. The
2059 //               device controller clears these bits when a SETUP packet is
2060 //               received because the USB spec requires that a STALL condition
2061 //               is cleared when a SETUP packet is received.
2062 #define USB_EP_STALL_ARM_OFFSET _u(0x00000068)
2063 #define USB_EP_STALL_ARM_BITS   _u(0x00000003)
2064 #define USB_EP_STALL_ARM_RESET  _u(0x00000000)
2065 // -----------------------------------------------------------------------------
2066 // Field       : USB_EP_STALL_ARM_EP0_OUT
2067 #define USB_EP_STALL_ARM_EP0_OUT_RESET  _u(0x0)
2068 #define USB_EP_STALL_ARM_EP0_OUT_BITS   _u(0x00000002)
2069 #define USB_EP_STALL_ARM_EP0_OUT_MSB    _u(1)
2070 #define USB_EP_STALL_ARM_EP0_OUT_LSB    _u(1)
2071 #define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW"
2072 // -----------------------------------------------------------------------------
2073 // Field       : USB_EP_STALL_ARM_EP0_IN
2074 #define USB_EP_STALL_ARM_EP0_IN_RESET  _u(0x0)
2075 #define USB_EP_STALL_ARM_EP0_IN_BITS   _u(0x00000001)
2076 #define USB_EP_STALL_ARM_EP0_IN_MSB    _u(0)
2077 #define USB_EP_STALL_ARM_EP0_IN_LSB    _u(0)
2078 #define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW"
2079 // =============================================================================
2080 // Register    : USB_NAK_POLL
2081 // Description : Used by the host controller. Sets the wait time in microseconds
2082 //               before trying again if the device replies with a NAK.
2083 #define USB_NAK_POLL_OFFSET _u(0x0000006c)
2084 #define USB_NAK_POLL_BITS   _u(0xffffffff)
2085 #define USB_NAK_POLL_RESET  _u(0x00100010)
2086 // -----------------------------------------------------------------------------
2087 // Field       : USB_NAK_POLL_RETRY_COUNT_HI
2088 // Description : Bits 9:6 of nak_retry count
2089 #define USB_NAK_POLL_RETRY_COUNT_HI_RESET  _u(0x0)
2090 #define USB_NAK_POLL_RETRY_COUNT_HI_BITS   _u(0xf0000000)
2091 #define USB_NAK_POLL_RETRY_COUNT_HI_MSB    _u(31)
2092 #define USB_NAK_POLL_RETRY_COUNT_HI_LSB    _u(28)
2093 #define USB_NAK_POLL_RETRY_COUNT_HI_ACCESS "RO"
2094 // -----------------------------------------------------------------------------
2095 // Field       : USB_NAK_POLL_EPX_STOPPED_ON_NAK
2096 // Description : EPX polling has stopped because a nak was received
2097 #define USB_NAK_POLL_EPX_STOPPED_ON_NAK_RESET  _u(0x0)
2098 #define USB_NAK_POLL_EPX_STOPPED_ON_NAK_BITS   _u(0x08000000)
2099 #define USB_NAK_POLL_EPX_STOPPED_ON_NAK_MSB    _u(27)
2100 #define USB_NAK_POLL_EPX_STOPPED_ON_NAK_LSB    _u(27)
2101 #define USB_NAK_POLL_EPX_STOPPED_ON_NAK_ACCESS "WC"
2102 // -----------------------------------------------------------------------------
2103 // Field       : USB_NAK_POLL_STOP_EPX_ON_NAK
2104 // Description : Stop polling epx when a nak is received
2105 #define USB_NAK_POLL_STOP_EPX_ON_NAK_RESET  _u(0x0)
2106 #define USB_NAK_POLL_STOP_EPX_ON_NAK_BITS   _u(0x04000000)
2107 #define USB_NAK_POLL_STOP_EPX_ON_NAK_MSB    _u(26)
2108 #define USB_NAK_POLL_STOP_EPX_ON_NAK_LSB    _u(26)
2109 #define USB_NAK_POLL_STOP_EPX_ON_NAK_ACCESS "RW"
2110 // -----------------------------------------------------------------------------
2111 // Field       : USB_NAK_POLL_DELAY_FS
2112 // Description : NAK polling interval for a full speed device
2113 #define USB_NAK_POLL_DELAY_FS_RESET  _u(0x010)
2114 #define USB_NAK_POLL_DELAY_FS_BITS   _u(0x03ff0000)
2115 #define USB_NAK_POLL_DELAY_FS_MSB    _u(25)
2116 #define USB_NAK_POLL_DELAY_FS_LSB    _u(16)
2117 #define USB_NAK_POLL_DELAY_FS_ACCESS "RW"
2118 // -----------------------------------------------------------------------------
2119 // Field       : USB_NAK_POLL_RETRY_COUNT_LO
2120 // Description : Bits 5:0 of nak_retry_count
2121 #define USB_NAK_POLL_RETRY_COUNT_LO_RESET  _u(0x00)
2122 #define USB_NAK_POLL_RETRY_COUNT_LO_BITS   _u(0x0000fc00)
2123 #define USB_NAK_POLL_RETRY_COUNT_LO_MSB    _u(15)
2124 #define USB_NAK_POLL_RETRY_COUNT_LO_LSB    _u(10)
2125 #define USB_NAK_POLL_RETRY_COUNT_LO_ACCESS "RO"
2126 // -----------------------------------------------------------------------------
2127 // Field       : USB_NAK_POLL_DELAY_LS
2128 // Description : NAK polling interval for a low speed device
2129 #define USB_NAK_POLL_DELAY_LS_RESET  _u(0x010)
2130 #define USB_NAK_POLL_DELAY_LS_BITS   _u(0x000003ff)
2131 #define USB_NAK_POLL_DELAY_LS_MSB    _u(9)
2132 #define USB_NAK_POLL_DELAY_LS_LSB    _u(0)
2133 #define USB_NAK_POLL_DELAY_LS_ACCESS "RW"
2134 // =============================================================================
2135 // Register    : USB_EP_STATUS_STALL_NAK
2136 // Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL`
2137 //               bits are set. For EP0 this comes from `SIE_CTRL`. For all other
2138 //               endpoints it comes from the endpoint control register.
2139 #define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070)
2140 #define USB_EP_STATUS_STALL_NAK_BITS   _u(0xffffffff)
2141 #define USB_EP_STATUS_STALL_NAK_RESET  _u(0x00000000)
2142 // -----------------------------------------------------------------------------
2143 // Field       : USB_EP_STATUS_STALL_NAK_EP15_OUT
2144 #define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET  _u(0x0)
2145 #define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS   _u(0x80000000)
2146 #define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB    _u(31)
2147 #define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB    _u(31)
2148 #define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC"
2149 // -----------------------------------------------------------------------------
2150 // Field       : USB_EP_STATUS_STALL_NAK_EP15_IN
2151 #define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET  _u(0x0)
2152 #define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS   _u(0x40000000)
2153 #define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB    _u(30)
2154 #define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB    _u(30)
2155 #define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC"
2156 // -----------------------------------------------------------------------------
2157 // Field       : USB_EP_STATUS_STALL_NAK_EP14_OUT
2158 #define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET  _u(0x0)
2159 #define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS   _u(0x20000000)
2160 #define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB    _u(29)
2161 #define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB    _u(29)
2162 #define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC"
2163 // -----------------------------------------------------------------------------
2164 // Field       : USB_EP_STATUS_STALL_NAK_EP14_IN
2165 #define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET  _u(0x0)
2166 #define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS   _u(0x10000000)
2167 #define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB    _u(28)
2168 #define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB    _u(28)
2169 #define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC"
2170 // -----------------------------------------------------------------------------
2171 // Field       : USB_EP_STATUS_STALL_NAK_EP13_OUT
2172 #define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET  _u(0x0)
2173 #define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS   _u(0x08000000)
2174 #define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB    _u(27)
2175 #define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB    _u(27)
2176 #define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC"
2177 // -----------------------------------------------------------------------------
2178 // Field       : USB_EP_STATUS_STALL_NAK_EP13_IN
2179 #define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET  _u(0x0)
2180 #define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS   _u(0x04000000)
2181 #define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB    _u(26)
2182 #define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB    _u(26)
2183 #define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC"
2184 // -----------------------------------------------------------------------------
2185 // Field       : USB_EP_STATUS_STALL_NAK_EP12_OUT
2186 #define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET  _u(0x0)
2187 #define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS   _u(0x02000000)
2188 #define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB    _u(25)
2189 #define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB    _u(25)
2190 #define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC"
2191 // -----------------------------------------------------------------------------
2192 // Field       : USB_EP_STATUS_STALL_NAK_EP12_IN
2193 #define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET  _u(0x0)
2194 #define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS   _u(0x01000000)
2195 #define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB    _u(24)
2196 #define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB    _u(24)
2197 #define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC"
2198 // -----------------------------------------------------------------------------
2199 // Field       : USB_EP_STATUS_STALL_NAK_EP11_OUT
2200 #define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET  _u(0x0)
2201 #define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS   _u(0x00800000)
2202 #define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB    _u(23)
2203 #define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB    _u(23)
2204 #define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC"
2205 // -----------------------------------------------------------------------------
2206 // Field       : USB_EP_STATUS_STALL_NAK_EP11_IN
2207 #define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET  _u(0x0)
2208 #define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS   _u(0x00400000)
2209 #define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB    _u(22)
2210 #define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB    _u(22)
2211 #define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC"
2212 // -----------------------------------------------------------------------------
2213 // Field       : USB_EP_STATUS_STALL_NAK_EP10_OUT
2214 #define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET  _u(0x0)
2215 #define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS   _u(0x00200000)
2216 #define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB    _u(21)
2217 #define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB    _u(21)
2218 #define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC"
2219 // -----------------------------------------------------------------------------
2220 // Field       : USB_EP_STATUS_STALL_NAK_EP10_IN
2221 #define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET  _u(0x0)
2222 #define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS   _u(0x00100000)
2223 #define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB    _u(20)
2224 #define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB    _u(20)
2225 #define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC"
2226 // -----------------------------------------------------------------------------
2227 // Field       : USB_EP_STATUS_STALL_NAK_EP9_OUT
2228 #define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET  _u(0x0)
2229 #define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS   _u(0x00080000)
2230 #define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB    _u(19)
2231 #define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB    _u(19)
2232 #define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC"
2233 // -----------------------------------------------------------------------------
2234 // Field       : USB_EP_STATUS_STALL_NAK_EP9_IN
2235 #define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET  _u(0x0)
2236 #define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS   _u(0x00040000)
2237 #define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB    _u(18)
2238 #define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB    _u(18)
2239 #define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC"
2240 // -----------------------------------------------------------------------------
2241 // Field       : USB_EP_STATUS_STALL_NAK_EP8_OUT
2242 #define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET  _u(0x0)
2243 #define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS   _u(0x00020000)
2244 #define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB    _u(17)
2245 #define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB    _u(17)
2246 #define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC"
2247 // -----------------------------------------------------------------------------
2248 // Field       : USB_EP_STATUS_STALL_NAK_EP8_IN
2249 #define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET  _u(0x0)
2250 #define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS   _u(0x00010000)
2251 #define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB    _u(16)
2252 #define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB    _u(16)
2253 #define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC"
2254 // -----------------------------------------------------------------------------
2255 // Field       : USB_EP_STATUS_STALL_NAK_EP7_OUT
2256 #define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET  _u(0x0)
2257 #define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS   _u(0x00008000)
2258 #define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB    _u(15)
2259 #define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB    _u(15)
2260 #define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC"
2261 // -----------------------------------------------------------------------------
2262 // Field       : USB_EP_STATUS_STALL_NAK_EP7_IN
2263 #define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET  _u(0x0)
2264 #define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS   _u(0x00004000)
2265 #define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB    _u(14)
2266 #define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB    _u(14)
2267 #define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC"
2268 // -----------------------------------------------------------------------------
2269 // Field       : USB_EP_STATUS_STALL_NAK_EP6_OUT
2270 #define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET  _u(0x0)
2271 #define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS   _u(0x00002000)
2272 #define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB    _u(13)
2273 #define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB    _u(13)
2274 #define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC"
2275 // -----------------------------------------------------------------------------
2276 // Field       : USB_EP_STATUS_STALL_NAK_EP6_IN
2277 #define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET  _u(0x0)
2278 #define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS   _u(0x00001000)
2279 #define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB    _u(12)
2280 #define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB    _u(12)
2281 #define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC"
2282 // -----------------------------------------------------------------------------
2283 // Field       : USB_EP_STATUS_STALL_NAK_EP5_OUT
2284 #define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET  _u(0x0)
2285 #define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS   _u(0x00000800)
2286 #define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB    _u(11)
2287 #define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB    _u(11)
2288 #define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC"
2289 // -----------------------------------------------------------------------------
2290 // Field       : USB_EP_STATUS_STALL_NAK_EP5_IN
2291 #define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET  _u(0x0)
2292 #define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS   _u(0x00000400)
2293 #define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB    _u(10)
2294 #define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB    _u(10)
2295 #define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC"
2296 // -----------------------------------------------------------------------------
2297 // Field       : USB_EP_STATUS_STALL_NAK_EP4_OUT
2298 #define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET  _u(0x0)
2299 #define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS   _u(0x00000200)
2300 #define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB    _u(9)
2301 #define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB    _u(9)
2302 #define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC"
2303 // -----------------------------------------------------------------------------
2304 // Field       : USB_EP_STATUS_STALL_NAK_EP4_IN
2305 #define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET  _u(0x0)
2306 #define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS   _u(0x00000100)
2307 #define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB    _u(8)
2308 #define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB    _u(8)
2309 #define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC"
2310 // -----------------------------------------------------------------------------
2311 // Field       : USB_EP_STATUS_STALL_NAK_EP3_OUT
2312 #define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET  _u(0x0)
2313 #define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS   _u(0x00000080)
2314 #define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB    _u(7)
2315 #define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB    _u(7)
2316 #define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC"
2317 // -----------------------------------------------------------------------------
2318 // Field       : USB_EP_STATUS_STALL_NAK_EP3_IN
2319 #define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET  _u(0x0)
2320 #define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS   _u(0x00000040)
2321 #define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB    _u(6)
2322 #define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB    _u(6)
2323 #define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC"
2324 // -----------------------------------------------------------------------------
2325 // Field       : USB_EP_STATUS_STALL_NAK_EP2_OUT
2326 #define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET  _u(0x0)
2327 #define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS   _u(0x00000020)
2328 #define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB    _u(5)
2329 #define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB    _u(5)
2330 #define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC"
2331 // -----------------------------------------------------------------------------
2332 // Field       : USB_EP_STATUS_STALL_NAK_EP2_IN
2333 #define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET  _u(0x0)
2334 #define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS   _u(0x00000010)
2335 #define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB    _u(4)
2336 #define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB    _u(4)
2337 #define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC"
2338 // -----------------------------------------------------------------------------
2339 // Field       : USB_EP_STATUS_STALL_NAK_EP1_OUT
2340 #define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET  _u(0x0)
2341 #define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS   _u(0x00000008)
2342 #define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB    _u(3)
2343 #define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB    _u(3)
2344 #define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC"
2345 // -----------------------------------------------------------------------------
2346 // Field       : USB_EP_STATUS_STALL_NAK_EP1_IN
2347 #define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET  _u(0x0)
2348 #define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS   _u(0x00000004)
2349 #define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB    _u(2)
2350 #define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB    _u(2)
2351 #define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC"
2352 // -----------------------------------------------------------------------------
2353 // Field       : USB_EP_STATUS_STALL_NAK_EP0_OUT
2354 #define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET  _u(0x0)
2355 #define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS   _u(0x00000002)
2356 #define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB    _u(1)
2357 #define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB    _u(1)
2358 #define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC"
2359 // -----------------------------------------------------------------------------
2360 // Field       : USB_EP_STATUS_STALL_NAK_EP0_IN
2361 #define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET  _u(0x0)
2362 #define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS   _u(0x00000001)
2363 #define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB    _u(0)
2364 #define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB    _u(0)
2365 #define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC"
2366 // =============================================================================
2367 // Register    : USB_USB_MUXING
2368 // Description : Where to connect the USB controller. Should be to_phy by
2369 //               default.
2370 #define USB_USB_MUXING_OFFSET _u(0x00000074)
2371 #define USB_USB_MUXING_BITS   _u(0x8000001f)
2372 #define USB_USB_MUXING_RESET  _u(0x00000001)
2373 // -----------------------------------------------------------------------------
2374 // Field       : USB_USB_MUXING_SWAP_DPDM
2375 // Description : Swap the USB PHY DP and DM pins and all related controls and
2376 //               flip receive differential data. Can be used to switch USB DP/DP
2377 //               on the PCB.
2378 //               This is done at a low level so overrides all other controls.
2379 #define USB_USB_MUXING_SWAP_DPDM_RESET  _u(0x0)
2380 #define USB_USB_MUXING_SWAP_DPDM_BITS   _u(0x80000000)
2381 #define USB_USB_MUXING_SWAP_DPDM_MSB    _u(31)
2382 #define USB_USB_MUXING_SWAP_DPDM_LSB    _u(31)
2383 #define USB_USB_MUXING_SWAP_DPDM_ACCESS "RW"
2384 // -----------------------------------------------------------------------------
2385 // Field       : USB_USB_MUXING_USBPHY_AS_GPIO
2386 // Description : Use the usb DP and DM pins as GPIO pins instead of connecting
2387 //               them to the USB controller.
2388 #define USB_USB_MUXING_USBPHY_AS_GPIO_RESET  _u(0x0)
2389 #define USB_USB_MUXING_USBPHY_AS_GPIO_BITS   _u(0x00000010)
2390 #define USB_USB_MUXING_USBPHY_AS_GPIO_MSB    _u(4)
2391 #define USB_USB_MUXING_USBPHY_AS_GPIO_LSB    _u(4)
2392 #define USB_USB_MUXING_USBPHY_AS_GPIO_ACCESS "RW"
2393 // -----------------------------------------------------------------------------
2394 // Field       : USB_USB_MUXING_SOFTCON
2395 #define USB_USB_MUXING_SOFTCON_RESET  _u(0x0)
2396 #define USB_USB_MUXING_SOFTCON_BITS   _u(0x00000008)
2397 #define USB_USB_MUXING_SOFTCON_MSB    _u(3)
2398 #define USB_USB_MUXING_SOFTCON_LSB    _u(3)
2399 #define USB_USB_MUXING_SOFTCON_ACCESS "RW"
2400 // -----------------------------------------------------------------------------
2401 // Field       : USB_USB_MUXING_TO_DIGITAL_PAD
2402 #define USB_USB_MUXING_TO_DIGITAL_PAD_RESET  _u(0x0)
2403 #define USB_USB_MUXING_TO_DIGITAL_PAD_BITS   _u(0x00000004)
2404 #define USB_USB_MUXING_TO_DIGITAL_PAD_MSB    _u(2)
2405 #define USB_USB_MUXING_TO_DIGITAL_PAD_LSB    _u(2)
2406 #define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW"
2407 // -----------------------------------------------------------------------------
2408 // Field       : USB_USB_MUXING_TO_EXTPHY
2409 #define USB_USB_MUXING_TO_EXTPHY_RESET  _u(0x0)
2410 #define USB_USB_MUXING_TO_EXTPHY_BITS   _u(0x00000002)
2411 #define USB_USB_MUXING_TO_EXTPHY_MSB    _u(1)
2412 #define USB_USB_MUXING_TO_EXTPHY_LSB    _u(1)
2413 #define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW"
2414 // -----------------------------------------------------------------------------
2415 // Field       : USB_USB_MUXING_TO_PHY
2416 #define USB_USB_MUXING_TO_PHY_RESET  _u(0x1)
2417 #define USB_USB_MUXING_TO_PHY_BITS   _u(0x00000001)
2418 #define USB_USB_MUXING_TO_PHY_MSB    _u(0)
2419 #define USB_USB_MUXING_TO_PHY_LSB    _u(0)
2420 #define USB_USB_MUXING_TO_PHY_ACCESS "RW"
2421 // =============================================================================
2422 // Register    : USB_USB_PWR
2423 // Description : Overrides for the power signals in the event that the VBUS
2424 //               signals are not hooked up to GPIO. Set the value of the
2425 //               override and then the override enable to switch over to the
2426 //               override value.
2427 #define USB_USB_PWR_OFFSET _u(0x00000078)
2428 #define USB_USB_PWR_BITS   _u(0x0000003f)
2429 #define USB_USB_PWR_RESET  _u(0x00000000)
2430 // -----------------------------------------------------------------------------
2431 // Field       : USB_USB_PWR_OVERCURR_DETECT_EN
2432 #define USB_USB_PWR_OVERCURR_DETECT_EN_RESET  _u(0x0)
2433 #define USB_USB_PWR_OVERCURR_DETECT_EN_BITS   _u(0x00000020)
2434 #define USB_USB_PWR_OVERCURR_DETECT_EN_MSB    _u(5)
2435 #define USB_USB_PWR_OVERCURR_DETECT_EN_LSB    _u(5)
2436 #define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW"
2437 // -----------------------------------------------------------------------------
2438 // Field       : USB_USB_PWR_OVERCURR_DETECT
2439 #define USB_USB_PWR_OVERCURR_DETECT_RESET  _u(0x0)
2440 #define USB_USB_PWR_OVERCURR_DETECT_BITS   _u(0x00000010)
2441 #define USB_USB_PWR_OVERCURR_DETECT_MSB    _u(4)
2442 #define USB_USB_PWR_OVERCURR_DETECT_LSB    _u(4)
2443 #define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW"
2444 // -----------------------------------------------------------------------------
2445 // Field       : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN
2446 #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET  _u(0x0)
2447 #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS   _u(0x00000008)
2448 #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB    _u(3)
2449 #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB    _u(3)
2450 #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW"
2451 // -----------------------------------------------------------------------------
2452 // Field       : USB_USB_PWR_VBUS_DETECT
2453 #define USB_USB_PWR_VBUS_DETECT_RESET  _u(0x0)
2454 #define USB_USB_PWR_VBUS_DETECT_BITS   _u(0x00000004)
2455 #define USB_USB_PWR_VBUS_DETECT_MSB    _u(2)
2456 #define USB_USB_PWR_VBUS_DETECT_LSB    _u(2)
2457 #define USB_USB_PWR_VBUS_DETECT_ACCESS "RW"
2458 // -----------------------------------------------------------------------------
2459 // Field       : USB_USB_PWR_VBUS_EN_OVERRIDE_EN
2460 #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET  _u(0x0)
2461 #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS   _u(0x00000002)
2462 #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB    _u(1)
2463 #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB    _u(1)
2464 #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW"
2465 // -----------------------------------------------------------------------------
2466 // Field       : USB_USB_PWR_VBUS_EN
2467 #define USB_USB_PWR_VBUS_EN_RESET  _u(0x0)
2468 #define USB_USB_PWR_VBUS_EN_BITS   _u(0x00000001)
2469 #define USB_USB_PWR_VBUS_EN_MSB    _u(0)
2470 #define USB_USB_PWR_VBUS_EN_LSB    _u(0)
2471 #define USB_USB_PWR_VBUS_EN_ACCESS "RW"
2472 // =============================================================================
2473 // Register    : USB_USBPHY_DIRECT
2474 // Description : This register allows for direct control of the USB phy. Use in
2475 //               conjunction with usbphy_direct_override register to enable each
2476 //               override bit.
2477 #define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c)
2478 #define USB_USBPHY_DIRECT_BITS   _u(0x03ffff77)
2479 #define USB_USBPHY_DIRECT_RESET  _u(0x00000000)
2480 // -----------------------------------------------------------------------------
2481 // Field       : USB_USBPHY_DIRECT_RX_DM_OVERRIDE
2482 // Description : Override rx_dm value into controller
2483 #define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_RESET  _u(0x0)
2484 #define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_BITS   _u(0x02000000)
2485 #define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_MSB    _u(25)
2486 #define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_LSB    _u(25)
2487 #define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_ACCESS "RW"
2488 // -----------------------------------------------------------------------------
2489 // Field       : USB_USBPHY_DIRECT_RX_DP_OVERRIDE
2490 // Description : Override rx_dp value into controller
2491 #define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_RESET  _u(0x0)
2492 #define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_BITS   _u(0x01000000)
2493 #define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_MSB    _u(24)
2494 #define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_LSB    _u(24)
2495 #define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_ACCESS "RW"
2496 // -----------------------------------------------------------------------------
2497 // Field       : USB_USBPHY_DIRECT_RX_DD_OVERRIDE
2498 // Description : Override rx_dd value into controller
2499 #define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_RESET  _u(0x0)
2500 #define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_BITS   _u(0x00800000)
2501 #define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_MSB    _u(23)
2502 #define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_LSB    _u(23)
2503 #define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_ACCESS "RW"
2504 // -----------------------------------------------------------------------------
2505 // Field       : USB_USBPHY_DIRECT_DM_OVV
2506 // Description : DM over voltage
2507 #define USB_USBPHY_DIRECT_DM_OVV_RESET  _u(0x0)
2508 #define USB_USBPHY_DIRECT_DM_OVV_BITS   _u(0x00400000)
2509 #define USB_USBPHY_DIRECT_DM_OVV_MSB    _u(22)
2510 #define USB_USBPHY_DIRECT_DM_OVV_LSB    _u(22)
2511 #define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO"
2512 // -----------------------------------------------------------------------------
2513 // Field       : USB_USBPHY_DIRECT_DP_OVV
2514 // Description : DP over voltage
2515 #define USB_USBPHY_DIRECT_DP_OVV_RESET  _u(0x0)
2516 #define USB_USBPHY_DIRECT_DP_OVV_BITS   _u(0x00200000)
2517 #define USB_USBPHY_DIRECT_DP_OVV_MSB    _u(21)
2518 #define USB_USBPHY_DIRECT_DP_OVV_LSB    _u(21)
2519 #define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO"
2520 // -----------------------------------------------------------------------------
2521 // Field       : USB_USBPHY_DIRECT_DM_OVCN
2522 // Description : DM overcurrent
2523 #define USB_USBPHY_DIRECT_DM_OVCN_RESET  _u(0x0)
2524 #define USB_USBPHY_DIRECT_DM_OVCN_BITS   _u(0x00100000)
2525 #define USB_USBPHY_DIRECT_DM_OVCN_MSB    _u(20)
2526 #define USB_USBPHY_DIRECT_DM_OVCN_LSB    _u(20)
2527 #define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO"
2528 // -----------------------------------------------------------------------------
2529 // Field       : USB_USBPHY_DIRECT_DP_OVCN
2530 // Description : DP overcurrent
2531 #define USB_USBPHY_DIRECT_DP_OVCN_RESET  _u(0x0)
2532 #define USB_USBPHY_DIRECT_DP_OVCN_BITS   _u(0x00080000)
2533 #define USB_USBPHY_DIRECT_DP_OVCN_MSB    _u(19)
2534 #define USB_USBPHY_DIRECT_DP_OVCN_LSB    _u(19)
2535 #define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO"
2536 // -----------------------------------------------------------------------------
2537 // Field       : USB_USBPHY_DIRECT_RX_DM
2538 // Description : DPM pin state
2539 #define USB_USBPHY_DIRECT_RX_DM_RESET  _u(0x0)
2540 #define USB_USBPHY_DIRECT_RX_DM_BITS   _u(0x00040000)
2541 #define USB_USBPHY_DIRECT_RX_DM_MSB    _u(18)
2542 #define USB_USBPHY_DIRECT_RX_DM_LSB    _u(18)
2543 #define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO"
2544 // -----------------------------------------------------------------------------
2545 // Field       : USB_USBPHY_DIRECT_RX_DP
2546 // Description : DPP pin state
2547 #define USB_USBPHY_DIRECT_RX_DP_RESET  _u(0x0)
2548 #define USB_USBPHY_DIRECT_RX_DP_BITS   _u(0x00020000)
2549 #define USB_USBPHY_DIRECT_RX_DP_MSB    _u(17)
2550 #define USB_USBPHY_DIRECT_RX_DP_LSB    _u(17)
2551 #define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO"
2552 // -----------------------------------------------------------------------------
2553 // Field       : USB_USBPHY_DIRECT_RX_DD
2554 // Description : Differential RX
2555 #define USB_USBPHY_DIRECT_RX_DD_RESET  _u(0x0)
2556 #define USB_USBPHY_DIRECT_RX_DD_BITS   _u(0x00010000)
2557 #define USB_USBPHY_DIRECT_RX_DD_MSB    _u(16)
2558 #define USB_USBPHY_DIRECT_RX_DD_LSB    _u(16)
2559 #define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO"
2560 // -----------------------------------------------------------------------------
2561 // Field       : USB_USBPHY_DIRECT_TX_DIFFMODE
2562 // Description : TX_DIFFMODE=0: Single ended mode
2563 //               TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE
2564 //               ignored)
2565 #define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET  _u(0x0)
2566 #define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS   _u(0x00008000)
2567 #define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB    _u(15)
2568 #define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB    _u(15)
2569 #define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW"
2570 // -----------------------------------------------------------------------------
2571 // Field       : USB_USBPHY_DIRECT_TX_FSSLEW
2572 // Description : TX_FSSLEW=0: Low speed slew rate
2573 //               TX_FSSLEW=1: Full speed slew rate
2574 #define USB_USBPHY_DIRECT_TX_FSSLEW_RESET  _u(0x0)
2575 #define USB_USBPHY_DIRECT_TX_FSSLEW_BITS   _u(0x00004000)
2576 #define USB_USBPHY_DIRECT_TX_FSSLEW_MSB    _u(14)
2577 #define USB_USBPHY_DIRECT_TX_FSSLEW_LSB    _u(14)
2578 #define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW"
2579 // -----------------------------------------------------------------------------
2580 // Field       : USB_USBPHY_DIRECT_TX_PD
2581 // Description : TX power down override (if override enable is set). 1 = powered
2582 //               down.
2583 #define USB_USBPHY_DIRECT_TX_PD_RESET  _u(0x0)
2584 #define USB_USBPHY_DIRECT_TX_PD_BITS   _u(0x00002000)
2585 #define USB_USBPHY_DIRECT_TX_PD_MSB    _u(13)
2586 #define USB_USBPHY_DIRECT_TX_PD_LSB    _u(13)
2587 #define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW"
2588 // -----------------------------------------------------------------------------
2589 // Field       : USB_USBPHY_DIRECT_RX_PD
2590 // Description : RX power down override (if override enable is set). 1 = powered
2591 //               down.
2592 #define USB_USBPHY_DIRECT_RX_PD_RESET  _u(0x0)
2593 #define USB_USBPHY_DIRECT_RX_PD_BITS   _u(0x00001000)
2594 #define USB_USBPHY_DIRECT_RX_PD_MSB    _u(12)
2595 #define USB_USBPHY_DIRECT_RX_PD_LSB    _u(12)
2596 #define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW"
2597 // -----------------------------------------------------------------------------
2598 // Field       : USB_USBPHY_DIRECT_TX_DM
2599 // Description : Output data. TX_DIFFMODE=1, Ignored
2600 //               TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive.
2601 //               DPM=TX_DM
2602 #define USB_USBPHY_DIRECT_TX_DM_RESET  _u(0x0)
2603 #define USB_USBPHY_DIRECT_TX_DM_BITS   _u(0x00000800)
2604 #define USB_USBPHY_DIRECT_TX_DM_MSB    _u(11)
2605 #define USB_USBPHY_DIRECT_TX_DM_LSB    _u(11)
2606 #define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW"
2607 // -----------------------------------------------------------------------------
2608 // Field       : USB_USBPHY_DIRECT_TX_DP
2609 // Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair.
2610 //               TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
2611 //               If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive.
2612 //               DPP=TX_DP
2613 #define USB_USBPHY_DIRECT_TX_DP_RESET  _u(0x0)
2614 #define USB_USBPHY_DIRECT_TX_DP_BITS   _u(0x00000400)
2615 #define USB_USBPHY_DIRECT_TX_DP_MSB    _u(10)
2616 #define USB_USBPHY_DIRECT_TX_DP_LSB    _u(10)
2617 #define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW"
2618 // -----------------------------------------------------------------------------
2619 // Field       : USB_USBPHY_DIRECT_TX_DM_OE
2620 // Description : Output enable. If TX_DIFFMODE=1, Ignored.
2621 //               If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 -
2622 //               DPM driving
2623 #define USB_USBPHY_DIRECT_TX_DM_OE_RESET  _u(0x0)
2624 #define USB_USBPHY_DIRECT_TX_DM_OE_BITS   _u(0x00000200)
2625 #define USB_USBPHY_DIRECT_TX_DM_OE_MSB    _u(9)
2626 #define USB_USBPHY_DIRECT_TX_DM_OE_LSB    _u(9)
2627 #define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW"
2628 // -----------------------------------------------------------------------------
2629 // Field       : USB_USBPHY_DIRECT_TX_DP_OE
2630 // Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 -
2631 //               DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
2632 //               If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 -
2633 //               DPP driving
2634 #define USB_USBPHY_DIRECT_TX_DP_OE_RESET  _u(0x0)
2635 #define USB_USBPHY_DIRECT_TX_DP_OE_BITS   _u(0x00000100)
2636 #define USB_USBPHY_DIRECT_TX_DP_OE_MSB    _u(8)
2637 #define USB_USBPHY_DIRECT_TX_DP_OE_LSB    _u(8)
2638 #define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW"
2639 // -----------------------------------------------------------------------------
2640 // Field       : USB_USBPHY_DIRECT_DM_PULLDN_EN
2641 // Description : DM pull down enable
2642 #define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET  _u(0x0)
2643 #define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS   _u(0x00000040)
2644 #define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB    _u(6)
2645 #define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB    _u(6)
2646 #define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW"
2647 // -----------------------------------------------------------------------------
2648 // Field       : USB_USBPHY_DIRECT_DM_PULLUP_EN
2649 // Description : DM pull up enable
2650 #define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET  _u(0x0)
2651 #define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS   _u(0x00000020)
2652 #define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB    _u(5)
2653 #define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB    _u(5)
2654 #define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW"
2655 // -----------------------------------------------------------------------------
2656 // Field       : USB_USBPHY_DIRECT_DM_PULLUP_HISEL
2657 // Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 -
2658 //               Pull = Rpu1 + Rpu2
2659 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET  _u(0x0)
2660 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS   _u(0x00000010)
2661 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB    _u(4)
2662 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB    _u(4)
2663 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW"
2664 // -----------------------------------------------------------------------------
2665 // Field       : USB_USBPHY_DIRECT_DP_PULLDN_EN
2666 // Description : DP pull down enable
2667 #define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET  _u(0x0)
2668 #define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS   _u(0x00000004)
2669 #define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB    _u(2)
2670 #define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB    _u(2)
2671 #define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW"
2672 // -----------------------------------------------------------------------------
2673 // Field       : USB_USBPHY_DIRECT_DP_PULLUP_EN
2674 // Description : DP pull up enable
2675 #define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET  _u(0x0)
2676 #define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS   _u(0x00000002)
2677 #define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB    _u(1)
2678 #define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB    _u(1)
2679 #define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW"
2680 // -----------------------------------------------------------------------------
2681 // Field       : USB_USBPHY_DIRECT_DP_PULLUP_HISEL
2682 // Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 -
2683 //               Pull = Rpu1 + Rpu2
2684 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET  _u(0x0)
2685 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS   _u(0x00000001)
2686 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB    _u(0)
2687 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB    _u(0)
2688 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW"
2689 // =============================================================================
2690 // Register    : USB_USBPHY_DIRECT_OVERRIDE
2691 // Description : Override enable for each control in usbphy_direct
2692 #define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080)
2693 #define USB_USBPHY_DIRECT_OVERRIDE_BITS   _u(0x00079fff)
2694 #define USB_USBPHY_DIRECT_OVERRIDE_RESET  _u(0x00000000)
2695 // -----------------------------------------------------------------------------
2696 // Field       : USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN
2697 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_RESET  _u(0x0)
2698 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_BITS   _u(0x00040000)
2699 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_MSB    _u(18)
2700 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_LSB    _u(18)
2701 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_ACCESS "RW"
2702 // -----------------------------------------------------------------------------
2703 // Field       : USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN
2704 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_RESET  _u(0x0)
2705 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_BITS   _u(0x00020000)
2706 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_MSB    _u(17)
2707 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_LSB    _u(17)
2708 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_ACCESS "RW"
2709 // -----------------------------------------------------------------------------
2710 // Field       : USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN
2711 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_RESET  _u(0x0)
2712 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_BITS   _u(0x00010000)
2713 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_MSB    _u(16)
2714 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_LSB    _u(16)
2715 #define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_ACCESS "RW"
2716 // -----------------------------------------------------------------------------
2717 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN
2718 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET  _u(0x0)
2719 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS   _u(0x00008000)
2720 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB    _u(15)
2721 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB    _u(15)
2722 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW"
2723 // -----------------------------------------------------------------------------
2724 // Field       : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN
2725 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET  _u(0x0)
2726 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS   _u(0x00001000)
2727 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB    _u(12)
2728 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB    _u(12)
2729 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW"
2730 // -----------------------------------------------------------------------------
2731 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN
2732 #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET  _u(0x0)
2733 #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS   _u(0x00000800)
2734 #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB    _u(11)
2735 #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB    _u(11)
2736 #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW"
2737 // -----------------------------------------------------------------------------
2738 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN
2739 #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET  _u(0x0)
2740 #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS   _u(0x00000400)
2741 #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB    _u(10)
2742 #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB    _u(10)
2743 #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW"
2744 // -----------------------------------------------------------------------------
2745 // Field       : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN
2746 #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET  _u(0x0)
2747 #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS   _u(0x00000200)
2748 #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB    _u(9)
2749 #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB    _u(9)
2750 #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW"
2751 // -----------------------------------------------------------------------------
2752 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN
2753 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET  _u(0x0)
2754 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS   _u(0x00000100)
2755 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB    _u(8)
2756 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB    _u(8)
2757 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW"
2758 // -----------------------------------------------------------------------------
2759 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN
2760 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET  _u(0x0)
2761 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS   _u(0x00000080)
2762 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB    _u(7)
2763 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB    _u(7)
2764 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW"
2765 // -----------------------------------------------------------------------------
2766 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN
2767 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET  _u(0x0)
2768 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS   _u(0x00000040)
2769 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB    _u(6)
2770 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB    _u(6)
2771 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW"
2772 // -----------------------------------------------------------------------------
2773 // Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN
2774 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET  _u(0x0)
2775 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS   _u(0x00000020)
2776 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB    _u(5)
2777 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB    _u(5)
2778 #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW"
2779 // -----------------------------------------------------------------------------
2780 // Field       : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN
2781 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET  _u(0x0)
2782 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS   _u(0x00000010)
2783 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB    _u(4)
2784 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB    _u(4)
2785 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
2786 // -----------------------------------------------------------------------------
2787 // Field       : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN
2788 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET  _u(0x0)
2789 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS   _u(0x00000008)
2790 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB    _u(3)
2791 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB    _u(3)
2792 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
2793 // -----------------------------------------------------------------------------
2794 // Field       : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN
2795 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET  _u(0x0)
2796 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS   _u(0x00000004)
2797 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB    _u(2)
2798 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB    _u(2)
2799 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW"
2800 // -----------------------------------------------------------------------------
2801 // Field       : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN
2802 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET  _u(0x0)
2803 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS   _u(0x00000002)
2804 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB    _u(1)
2805 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB    _u(1)
2806 #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
2807 // -----------------------------------------------------------------------------
2808 // Field       : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN
2809 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET  _u(0x0)
2810 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS   _u(0x00000001)
2811 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB    _u(0)
2812 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB    _u(0)
2813 #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
2814 // =============================================================================
2815 // Register    : USB_USBPHY_TRIM
2816 // Description : Used to adjust trim values of USB phy pull down resistors.
2817 #define USB_USBPHY_TRIM_OFFSET _u(0x00000084)
2818 #define USB_USBPHY_TRIM_BITS   _u(0x00001f1f)
2819 #define USB_USBPHY_TRIM_RESET  _u(0x00001f1f)
2820 // -----------------------------------------------------------------------------
2821 // Field       : USB_USBPHY_TRIM_DM_PULLDN_TRIM
2822 // Description : Value to drive to USB PHY
2823 //               DM pulldown resistor trim control
2824 //               Experimental data suggests that the reset value will work, but
2825 //               this register allows adjustment if required
2826 #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET  _u(0x1f)
2827 #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS   _u(0x00001f00)
2828 #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB    _u(12)
2829 #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB    _u(8)
2830 #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW"
2831 // -----------------------------------------------------------------------------
2832 // Field       : USB_USBPHY_TRIM_DP_PULLDN_TRIM
2833 // Description : Value to drive to USB PHY
2834 //               DP pulldown resistor trim control
2835 //               Experimental data suggests that the reset value will work, but
2836 //               this register allows adjustment if required
2837 #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET  _u(0x1f)
2838 #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS   _u(0x0000001f)
2839 #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB    _u(4)
2840 #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB    _u(0)
2841 #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW"
2842 // =============================================================================
2843 // Register    : USB_LINESTATE_TUNING
2844 // Description : Used for debug only.
2845 #define USB_LINESTATE_TUNING_OFFSET _u(0x00000088)
2846 #define USB_LINESTATE_TUNING_BITS   _u(0x00000fff)
2847 #define USB_LINESTATE_TUNING_RESET  _u(0x000000f8)
2848 // -----------------------------------------------------------------------------
2849 // Field       : USB_LINESTATE_TUNING_SPARE_FIX
2850 #define USB_LINESTATE_TUNING_SPARE_FIX_RESET  _u(0x0)
2851 #define USB_LINESTATE_TUNING_SPARE_FIX_BITS   _u(0x00000f00)
2852 #define USB_LINESTATE_TUNING_SPARE_FIX_MSB    _u(11)
2853 #define USB_LINESTATE_TUNING_SPARE_FIX_LSB    _u(8)
2854 #define USB_LINESTATE_TUNING_SPARE_FIX_ACCESS "RW"
2855 // -----------------------------------------------------------------------------
2856 // Field       : USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX
2857 // Description : Device - exit suspend on any non-idle signalling, not qualified
2858 //               with a 1ms timer
2859 #define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_RESET  _u(0x1)
2860 #define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_BITS   _u(0x00000080)
2861 #define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_MSB    _u(7)
2862 #define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_LSB    _u(7)
2863 #define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_ACCESS "RW"
2864 // -----------------------------------------------------------------------------
2865 // Field       : USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE
2866 // Description : Device - suppress repeated errors until the device FSM is next
2867 //               in the process of decoding an inbound packet.
2868 #define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_RESET  _u(0x1)
2869 #define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_BITS   _u(0x00000040)
2870 #define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_MSB    _u(6)
2871 #define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_LSB    _u(6)
2872 #define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_ACCESS "RW"
2873 // -----------------------------------------------------------------------------
2874 // Field       : USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX
2875 // Description : RX - when recovering from line chatter or bitstuff errors,
2876 //               treat SE0 as the end of chatter as well as
2877 //               8 consecutive idle bits.
2878 #define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_RESET  _u(0x1)
2879 #define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_BITS   _u(0x00000020)
2880 #define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_MSB    _u(5)
2881 #define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_LSB    _u(5)
2882 #define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_ACCESS "RW"
2883 // -----------------------------------------------------------------------------
2884 // Field       : USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX
2885 // Description : RX - when a bitstuff error is signalled by rx_dasm,
2886 //               unconditionally terminate RX decode to
2887 //               avoid a hang during certain packet phases.
2888 #define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_RESET  _u(0x1)
2889 #define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_BITS   _u(0x00000010)
2890 #define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_MSB    _u(4)
2891 #define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_LSB    _u(4)
2892 #define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_ACCESS "RW"
2893 // -----------------------------------------------------------------------------
2894 // Field       : USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX
2895 // Description : Device - the controller FSM performs two reads of the buffer
2896 //               status memory address to
2897 //               avoid sampling metastable data. An enabled buffer is only used
2898 //               if both reads match.
2899 #define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_RESET  _u(0x1)
2900 #define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_BITS   _u(0x00000008)
2901 #define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_MSB    _u(3)
2902 #define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_LSB    _u(3)
2903 #define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_ACCESS "RW"
2904 // -----------------------------------------------------------------------------
2905 // Field       : USB_LINESTATE_TUNING_MULTI_HUB_FIX
2906 // Description : Host - increase inter-packet and turnaround timeouts to
2907 //               accommodate worst-case hub delays.
2908 #define USB_LINESTATE_TUNING_MULTI_HUB_FIX_RESET  _u(0x0)
2909 #define USB_LINESTATE_TUNING_MULTI_HUB_FIX_BITS   _u(0x00000004)
2910 #define USB_LINESTATE_TUNING_MULTI_HUB_FIX_MSB    _u(2)
2911 #define USB_LINESTATE_TUNING_MULTI_HUB_FIX_LSB    _u(2)
2912 #define USB_LINESTATE_TUNING_MULTI_HUB_FIX_ACCESS "RW"
2913 // -----------------------------------------------------------------------------
2914 // Field       : USB_LINESTATE_TUNING_LINESTATE_DELAY
2915 // Description : Device/Host - add an extra 1-bit debounce of linestate
2916 //               sampling.
2917 #define USB_LINESTATE_TUNING_LINESTATE_DELAY_RESET  _u(0x0)
2918 #define USB_LINESTATE_TUNING_LINESTATE_DELAY_BITS   _u(0x00000002)
2919 #define USB_LINESTATE_TUNING_LINESTATE_DELAY_MSB    _u(1)
2920 #define USB_LINESTATE_TUNING_LINESTATE_DELAY_LSB    _u(1)
2921 #define USB_LINESTATE_TUNING_LINESTATE_DELAY_ACCESS "RW"
2922 // -----------------------------------------------------------------------------
2923 // Field       : USB_LINESTATE_TUNING_RCV_DELAY
2924 // Description : Device - register the received data to account for hub bit
2925 //               dribble before EOP. Only affects certain hubs.
2926 #define USB_LINESTATE_TUNING_RCV_DELAY_RESET  _u(0x0)
2927 #define USB_LINESTATE_TUNING_RCV_DELAY_BITS   _u(0x00000001)
2928 #define USB_LINESTATE_TUNING_RCV_DELAY_MSB    _u(0)
2929 #define USB_LINESTATE_TUNING_RCV_DELAY_LSB    _u(0)
2930 #define USB_LINESTATE_TUNING_RCV_DELAY_ACCESS "RW"
2931 // =============================================================================
2932 // Register    : USB_INTR
2933 // Description : Raw Interrupts
2934 #define USB_INTR_OFFSET _u(0x0000008c)
2935 #define USB_INTR_BITS   _u(0x00ffffff)
2936 #define USB_INTR_RESET  _u(0x00000000)
2937 // -----------------------------------------------------------------------------
2938 // Field       : USB_INTR_EPX_STOPPED_ON_NAK
2939 // Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK
2940 #define USB_INTR_EPX_STOPPED_ON_NAK_RESET  _u(0x0)
2941 #define USB_INTR_EPX_STOPPED_ON_NAK_BITS   _u(0x00800000)
2942 #define USB_INTR_EPX_STOPPED_ON_NAK_MSB    _u(23)
2943 #define USB_INTR_EPX_STOPPED_ON_NAK_LSB    _u(23)
2944 #define USB_INTR_EPX_STOPPED_ON_NAK_ACCESS "RO"
2945 // -----------------------------------------------------------------------------
2946 // Field       : USB_INTR_DEV_SM_WATCHDOG_FIRED
2947 // Description : Source: DEV_SM_WATCHDOG.FIRED
2948 #define USB_INTR_DEV_SM_WATCHDOG_FIRED_RESET  _u(0x0)
2949 #define USB_INTR_DEV_SM_WATCHDOG_FIRED_BITS   _u(0x00400000)
2950 #define USB_INTR_DEV_SM_WATCHDOG_FIRED_MSB    _u(22)
2951 #define USB_INTR_DEV_SM_WATCHDOG_FIRED_LSB    _u(22)
2952 #define USB_INTR_DEV_SM_WATCHDOG_FIRED_ACCESS "RO"
2953 // -----------------------------------------------------------------------------
2954 // Field       : USB_INTR_ENDPOINT_ERROR
2955 // Description : Source: SIE_STATUS.ENDPOINT_ERROR
2956 #define USB_INTR_ENDPOINT_ERROR_RESET  _u(0x0)
2957 #define USB_INTR_ENDPOINT_ERROR_BITS   _u(0x00200000)
2958 #define USB_INTR_ENDPOINT_ERROR_MSB    _u(21)
2959 #define USB_INTR_ENDPOINT_ERROR_LSB    _u(21)
2960 #define USB_INTR_ENDPOINT_ERROR_ACCESS "RO"
2961 // -----------------------------------------------------------------------------
2962 // Field       : USB_INTR_RX_SHORT_PACKET
2963 // Description : Source: SIE_STATUS.RX_SHORT_PACKET
2964 #define USB_INTR_RX_SHORT_PACKET_RESET  _u(0x0)
2965 #define USB_INTR_RX_SHORT_PACKET_BITS   _u(0x00100000)
2966 #define USB_INTR_RX_SHORT_PACKET_MSB    _u(20)
2967 #define USB_INTR_RX_SHORT_PACKET_LSB    _u(20)
2968 #define USB_INTR_RX_SHORT_PACKET_ACCESS "RO"
2969 // -----------------------------------------------------------------------------
2970 // Field       : USB_INTR_EP_STALL_NAK
2971 // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
2972 //               clearing all bits in EP_STATUS_STALL_NAK.
2973 #define USB_INTR_EP_STALL_NAK_RESET  _u(0x0)
2974 #define USB_INTR_EP_STALL_NAK_BITS   _u(0x00080000)
2975 #define USB_INTR_EP_STALL_NAK_MSB    _u(19)
2976 #define USB_INTR_EP_STALL_NAK_LSB    _u(19)
2977 #define USB_INTR_EP_STALL_NAK_ACCESS "RO"
2978 // -----------------------------------------------------------------------------
2979 // Field       : USB_INTR_ABORT_DONE
2980 // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
2981 //               bits in ABORT_DONE.
2982 #define USB_INTR_ABORT_DONE_RESET  _u(0x0)
2983 #define USB_INTR_ABORT_DONE_BITS   _u(0x00040000)
2984 #define USB_INTR_ABORT_DONE_MSB    _u(18)
2985 #define USB_INTR_ABORT_DONE_LSB    _u(18)
2986 #define USB_INTR_ABORT_DONE_ACCESS "RO"
2987 // -----------------------------------------------------------------------------
2988 // Field       : USB_INTR_DEV_SOF
2989 // Description : Set every time the device receives a SOF (Start of Frame)
2990 //               packet. Cleared by reading SOF_RD
2991 #define USB_INTR_DEV_SOF_RESET  _u(0x0)
2992 #define USB_INTR_DEV_SOF_BITS   _u(0x00020000)
2993 #define USB_INTR_DEV_SOF_MSB    _u(17)
2994 #define USB_INTR_DEV_SOF_LSB    _u(17)
2995 #define USB_INTR_DEV_SOF_ACCESS "RO"
2996 // -----------------------------------------------------------------------------
2997 // Field       : USB_INTR_SETUP_REQ
2998 // Description : Device. Source: SIE_STATUS.SETUP_REC
2999 #define USB_INTR_SETUP_REQ_RESET  _u(0x0)
3000 #define USB_INTR_SETUP_REQ_BITS   _u(0x00010000)
3001 #define USB_INTR_SETUP_REQ_MSB    _u(16)
3002 #define USB_INTR_SETUP_REQ_LSB    _u(16)
3003 #define USB_INTR_SETUP_REQ_ACCESS "RO"
3004 // -----------------------------------------------------------------------------
3005 // Field       : USB_INTR_DEV_RESUME_FROM_HOST
3006 // Description : Set when the device receives a resume from the host. Cleared by
3007 //               writing to SIE_STATUS.RESUME
3008 #define USB_INTR_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
3009 #define USB_INTR_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
3010 #define USB_INTR_DEV_RESUME_FROM_HOST_MSB    _u(15)
3011 #define USB_INTR_DEV_RESUME_FROM_HOST_LSB    _u(15)
3012 #define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO"
3013 // -----------------------------------------------------------------------------
3014 // Field       : USB_INTR_DEV_SUSPEND
3015 // Description : Set when the device suspend state changes. Cleared by writing
3016 //               to SIE_STATUS.SUSPENDED
3017 #define USB_INTR_DEV_SUSPEND_RESET  _u(0x0)
3018 #define USB_INTR_DEV_SUSPEND_BITS   _u(0x00004000)
3019 #define USB_INTR_DEV_SUSPEND_MSB    _u(14)
3020 #define USB_INTR_DEV_SUSPEND_LSB    _u(14)
3021 #define USB_INTR_DEV_SUSPEND_ACCESS "RO"
3022 // -----------------------------------------------------------------------------
3023 // Field       : USB_INTR_DEV_CONN_DIS
3024 // Description : Set when the device connection state changes. Cleared by
3025 //               writing to SIE_STATUS.CONNECTED
3026 #define USB_INTR_DEV_CONN_DIS_RESET  _u(0x0)
3027 #define USB_INTR_DEV_CONN_DIS_BITS   _u(0x00002000)
3028 #define USB_INTR_DEV_CONN_DIS_MSB    _u(13)
3029 #define USB_INTR_DEV_CONN_DIS_LSB    _u(13)
3030 #define USB_INTR_DEV_CONN_DIS_ACCESS "RO"
3031 // -----------------------------------------------------------------------------
3032 // Field       : USB_INTR_BUS_RESET
3033 // Description : Source: SIE_STATUS.BUS_RESET
3034 #define USB_INTR_BUS_RESET_RESET  _u(0x0)
3035 #define USB_INTR_BUS_RESET_BITS   _u(0x00001000)
3036 #define USB_INTR_BUS_RESET_MSB    _u(12)
3037 #define USB_INTR_BUS_RESET_LSB    _u(12)
3038 #define USB_INTR_BUS_RESET_ACCESS "RO"
3039 // -----------------------------------------------------------------------------
3040 // Field       : USB_INTR_VBUS_DETECT
3041 // Description : Source: SIE_STATUS.VBUS_DETECTED
3042 #define USB_INTR_VBUS_DETECT_RESET  _u(0x0)
3043 #define USB_INTR_VBUS_DETECT_BITS   _u(0x00000800)
3044 #define USB_INTR_VBUS_DETECT_MSB    _u(11)
3045 #define USB_INTR_VBUS_DETECT_LSB    _u(11)
3046 #define USB_INTR_VBUS_DETECT_ACCESS "RO"
3047 // -----------------------------------------------------------------------------
3048 // Field       : USB_INTR_STALL
3049 // Description : Source: SIE_STATUS.STALL_REC
3050 #define USB_INTR_STALL_RESET  _u(0x0)
3051 #define USB_INTR_STALL_BITS   _u(0x00000400)
3052 #define USB_INTR_STALL_MSB    _u(10)
3053 #define USB_INTR_STALL_LSB    _u(10)
3054 #define USB_INTR_STALL_ACCESS "RO"
3055 // -----------------------------------------------------------------------------
3056 // Field       : USB_INTR_ERROR_CRC
3057 // Description : Source: SIE_STATUS.CRC_ERROR
3058 #define USB_INTR_ERROR_CRC_RESET  _u(0x0)
3059 #define USB_INTR_ERROR_CRC_BITS   _u(0x00000200)
3060 #define USB_INTR_ERROR_CRC_MSB    _u(9)
3061 #define USB_INTR_ERROR_CRC_LSB    _u(9)
3062 #define USB_INTR_ERROR_CRC_ACCESS "RO"
3063 // -----------------------------------------------------------------------------
3064 // Field       : USB_INTR_ERROR_BIT_STUFF
3065 // Description : Source: SIE_STATUS.BIT_STUFF_ERROR
3066 #define USB_INTR_ERROR_BIT_STUFF_RESET  _u(0x0)
3067 #define USB_INTR_ERROR_BIT_STUFF_BITS   _u(0x00000100)
3068 #define USB_INTR_ERROR_BIT_STUFF_MSB    _u(8)
3069 #define USB_INTR_ERROR_BIT_STUFF_LSB    _u(8)
3070 #define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO"
3071 // -----------------------------------------------------------------------------
3072 // Field       : USB_INTR_ERROR_RX_OVERFLOW
3073 // Description : Source: SIE_STATUS.RX_OVERFLOW
3074 #define USB_INTR_ERROR_RX_OVERFLOW_RESET  _u(0x0)
3075 #define USB_INTR_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
3076 #define USB_INTR_ERROR_RX_OVERFLOW_MSB    _u(7)
3077 #define USB_INTR_ERROR_RX_OVERFLOW_LSB    _u(7)
3078 #define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO"
3079 // -----------------------------------------------------------------------------
3080 // Field       : USB_INTR_ERROR_RX_TIMEOUT
3081 // Description : Source: SIE_STATUS.RX_TIMEOUT
3082 #define USB_INTR_ERROR_RX_TIMEOUT_RESET  _u(0x0)
3083 #define USB_INTR_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
3084 #define USB_INTR_ERROR_RX_TIMEOUT_MSB    _u(6)
3085 #define USB_INTR_ERROR_RX_TIMEOUT_LSB    _u(6)
3086 #define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO"
3087 // -----------------------------------------------------------------------------
3088 // Field       : USB_INTR_ERROR_DATA_SEQ
3089 // Description : Source: SIE_STATUS.DATA_SEQ_ERROR
3090 #define USB_INTR_ERROR_DATA_SEQ_RESET  _u(0x0)
3091 #define USB_INTR_ERROR_DATA_SEQ_BITS   _u(0x00000020)
3092 #define USB_INTR_ERROR_DATA_SEQ_MSB    _u(5)
3093 #define USB_INTR_ERROR_DATA_SEQ_LSB    _u(5)
3094 #define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO"
3095 // -----------------------------------------------------------------------------
3096 // Field       : USB_INTR_BUFF_STATUS
3097 // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
3098 //               all bits in BUFF_STATUS.
3099 #define USB_INTR_BUFF_STATUS_RESET  _u(0x0)
3100 #define USB_INTR_BUFF_STATUS_BITS   _u(0x00000010)
3101 #define USB_INTR_BUFF_STATUS_MSB    _u(4)
3102 #define USB_INTR_BUFF_STATUS_LSB    _u(4)
3103 #define USB_INTR_BUFF_STATUS_ACCESS "RO"
3104 // -----------------------------------------------------------------------------
3105 // Field       : USB_INTR_TRANS_COMPLETE
3106 // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
3107 //               writing to this bit.
3108 #define USB_INTR_TRANS_COMPLETE_RESET  _u(0x0)
3109 #define USB_INTR_TRANS_COMPLETE_BITS   _u(0x00000008)
3110 #define USB_INTR_TRANS_COMPLETE_MSB    _u(3)
3111 #define USB_INTR_TRANS_COMPLETE_LSB    _u(3)
3112 #define USB_INTR_TRANS_COMPLETE_ACCESS "RO"
3113 // -----------------------------------------------------------------------------
3114 // Field       : USB_INTR_HOST_SOF
3115 // Description : Host: raised every time the host sends a SOF (Start of Frame).
3116 //               Cleared by reading SOF_RD
3117 #define USB_INTR_HOST_SOF_RESET  _u(0x0)
3118 #define USB_INTR_HOST_SOF_BITS   _u(0x00000004)
3119 #define USB_INTR_HOST_SOF_MSB    _u(2)
3120 #define USB_INTR_HOST_SOF_LSB    _u(2)
3121 #define USB_INTR_HOST_SOF_ACCESS "RO"
3122 // -----------------------------------------------------------------------------
3123 // Field       : USB_INTR_HOST_RESUME
3124 // Description : Host: raised when a device wakes up the host. Cleared by
3125 //               writing to SIE_STATUS.RESUME
3126 #define USB_INTR_HOST_RESUME_RESET  _u(0x0)
3127 #define USB_INTR_HOST_RESUME_BITS   _u(0x00000002)
3128 #define USB_INTR_HOST_RESUME_MSB    _u(1)
3129 #define USB_INTR_HOST_RESUME_LSB    _u(1)
3130 #define USB_INTR_HOST_RESUME_ACCESS "RO"
3131 // -----------------------------------------------------------------------------
3132 // Field       : USB_INTR_HOST_CONN_DIS
3133 // Description : Host: raised when a device is connected or disconnected (i.e.
3134 //               when SIE_STATUS.SPEED changes). Cleared by writing to
3135 //               SIE_STATUS.SPEED
3136 #define USB_INTR_HOST_CONN_DIS_RESET  _u(0x0)
3137 #define USB_INTR_HOST_CONN_DIS_BITS   _u(0x00000001)
3138 #define USB_INTR_HOST_CONN_DIS_MSB    _u(0)
3139 #define USB_INTR_HOST_CONN_DIS_LSB    _u(0)
3140 #define USB_INTR_HOST_CONN_DIS_ACCESS "RO"
3141 // =============================================================================
3142 // Register    : USB_INTE
3143 // Description : Interrupt Enable
3144 #define USB_INTE_OFFSET _u(0x00000090)
3145 #define USB_INTE_BITS   _u(0x00ffffff)
3146 #define USB_INTE_RESET  _u(0x00000000)
3147 // -----------------------------------------------------------------------------
3148 // Field       : USB_INTE_EPX_STOPPED_ON_NAK
3149 // Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK
3150 #define USB_INTE_EPX_STOPPED_ON_NAK_RESET  _u(0x0)
3151 #define USB_INTE_EPX_STOPPED_ON_NAK_BITS   _u(0x00800000)
3152 #define USB_INTE_EPX_STOPPED_ON_NAK_MSB    _u(23)
3153 #define USB_INTE_EPX_STOPPED_ON_NAK_LSB    _u(23)
3154 #define USB_INTE_EPX_STOPPED_ON_NAK_ACCESS "RW"
3155 // -----------------------------------------------------------------------------
3156 // Field       : USB_INTE_DEV_SM_WATCHDOG_FIRED
3157 // Description : Source: DEV_SM_WATCHDOG.FIRED
3158 #define USB_INTE_DEV_SM_WATCHDOG_FIRED_RESET  _u(0x0)
3159 #define USB_INTE_DEV_SM_WATCHDOG_FIRED_BITS   _u(0x00400000)
3160 #define USB_INTE_DEV_SM_WATCHDOG_FIRED_MSB    _u(22)
3161 #define USB_INTE_DEV_SM_WATCHDOG_FIRED_LSB    _u(22)
3162 #define USB_INTE_DEV_SM_WATCHDOG_FIRED_ACCESS "RW"
3163 // -----------------------------------------------------------------------------
3164 // Field       : USB_INTE_ENDPOINT_ERROR
3165 // Description : Source: SIE_STATUS.ENDPOINT_ERROR
3166 #define USB_INTE_ENDPOINT_ERROR_RESET  _u(0x0)
3167 #define USB_INTE_ENDPOINT_ERROR_BITS   _u(0x00200000)
3168 #define USB_INTE_ENDPOINT_ERROR_MSB    _u(21)
3169 #define USB_INTE_ENDPOINT_ERROR_LSB    _u(21)
3170 #define USB_INTE_ENDPOINT_ERROR_ACCESS "RW"
3171 // -----------------------------------------------------------------------------
3172 // Field       : USB_INTE_RX_SHORT_PACKET
3173 // Description : Source: SIE_STATUS.RX_SHORT_PACKET
3174 #define USB_INTE_RX_SHORT_PACKET_RESET  _u(0x0)
3175 #define USB_INTE_RX_SHORT_PACKET_BITS   _u(0x00100000)
3176 #define USB_INTE_RX_SHORT_PACKET_MSB    _u(20)
3177 #define USB_INTE_RX_SHORT_PACKET_LSB    _u(20)
3178 #define USB_INTE_RX_SHORT_PACKET_ACCESS "RW"
3179 // -----------------------------------------------------------------------------
3180 // Field       : USB_INTE_EP_STALL_NAK
3181 // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
3182 //               clearing all bits in EP_STATUS_STALL_NAK.
3183 #define USB_INTE_EP_STALL_NAK_RESET  _u(0x0)
3184 #define USB_INTE_EP_STALL_NAK_BITS   _u(0x00080000)
3185 #define USB_INTE_EP_STALL_NAK_MSB    _u(19)
3186 #define USB_INTE_EP_STALL_NAK_LSB    _u(19)
3187 #define USB_INTE_EP_STALL_NAK_ACCESS "RW"
3188 // -----------------------------------------------------------------------------
3189 // Field       : USB_INTE_ABORT_DONE
3190 // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
3191 //               bits in ABORT_DONE.
3192 #define USB_INTE_ABORT_DONE_RESET  _u(0x0)
3193 #define USB_INTE_ABORT_DONE_BITS   _u(0x00040000)
3194 #define USB_INTE_ABORT_DONE_MSB    _u(18)
3195 #define USB_INTE_ABORT_DONE_LSB    _u(18)
3196 #define USB_INTE_ABORT_DONE_ACCESS "RW"
3197 // -----------------------------------------------------------------------------
3198 // Field       : USB_INTE_DEV_SOF
3199 // Description : Set every time the device receives a SOF (Start of Frame)
3200 //               packet. Cleared by reading SOF_RD
3201 #define USB_INTE_DEV_SOF_RESET  _u(0x0)
3202 #define USB_INTE_DEV_SOF_BITS   _u(0x00020000)
3203 #define USB_INTE_DEV_SOF_MSB    _u(17)
3204 #define USB_INTE_DEV_SOF_LSB    _u(17)
3205 #define USB_INTE_DEV_SOF_ACCESS "RW"
3206 // -----------------------------------------------------------------------------
3207 // Field       : USB_INTE_SETUP_REQ
3208 // Description : Device. Source: SIE_STATUS.SETUP_REC
3209 #define USB_INTE_SETUP_REQ_RESET  _u(0x0)
3210 #define USB_INTE_SETUP_REQ_BITS   _u(0x00010000)
3211 #define USB_INTE_SETUP_REQ_MSB    _u(16)
3212 #define USB_INTE_SETUP_REQ_LSB    _u(16)
3213 #define USB_INTE_SETUP_REQ_ACCESS "RW"
3214 // -----------------------------------------------------------------------------
3215 // Field       : USB_INTE_DEV_RESUME_FROM_HOST
3216 // Description : Set when the device receives a resume from the host. Cleared by
3217 //               writing to SIE_STATUS.RESUME
3218 #define USB_INTE_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
3219 #define USB_INTE_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
3220 #define USB_INTE_DEV_RESUME_FROM_HOST_MSB    _u(15)
3221 #define USB_INTE_DEV_RESUME_FROM_HOST_LSB    _u(15)
3222 #define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW"
3223 // -----------------------------------------------------------------------------
3224 // Field       : USB_INTE_DEV_SUSPEND
3225 // Description : Set when the device suspend state changes. Cleared by writing
3226 //               to SIE_STATUS.SUSPENDED
3227 #define USB_INTE_DEV_SUSPEND_RESET  _u(0x0)
3228 #define USB_INTE_DEV_SUSPEND_BITS   _u(0x00004000)
3229 #define USB_INTE_DEV_SUSPEND_MSB    _u(14)
3230 #define USB_INTE_DEV_SUSPEND_LSB    _u(14)
3231 #define USB_INTE_DEV_SUSPEND_ACCESS "RW"
3232 // -----------------------------------------------------------------------------
3233 // Field       : USB_INTE_DEV_CONN_DIS
3234 // Description : Set when the device connection state changes. Cleared by
3235 //               writing to SIE_STATUS.CONNECTED
3236 #define USB_INTE_DEV_CONN_DIS_RESET  _u(0x0)
3237 #define USB_INTE_DEV_CONN_DIS_BITS   _u(0x00002000)
3238 #define USB_INTE_DEV_CONN_DIS_MSB    _u(13)
3239 #define USB_INTE_DEV_CONN_DIS_LSB    _u(13)
3240 #define USB_INTE_DEV_CONN_DIS_ACCESS "RW"
3241 // -----------------------------------------------------------------------------
3242 // Field       : USB_INTE_BUS_RESET
3243 // Description : Source: SIE_STATUS.BUS_RESET
3244 #define USB_INTE_BUS_RESET_RESET  _u(0x0)
3245 #define USB_INTE_BUS_RESET_BITS   _u(0x00001000)
3246 #define USB_INTE_BUS_RESET_MSB    _u(12)
3247 #define USB_INTE_BUS_RESET_LSB    _u(12)
3248 #define USB_INTE_BUS_RESET_ACCESS "RW"
3249 // -----------------------------------------------------------------------------
3250 // Field       : USB_INTE_VBUS_DETECT
3251 // Description : Source: SIE_STATUS.VBUS_DETECTED
3252 #define USB_INTE_VBUS_DETECT_RESET  _u(0x0)
3253 #define USB_INTE_VBUS_DETECT_BITS   _u(0x00000800)
3254 #define USB_INTE_VBUS_DETECT_MSB    _u(11)
3255 #define USB_INTE_VBUS_DETECT_LSB    _u(11)
3256 #define USB_INTE_VBUS_DETECT_ACCESS "RW"
3257 // -----------------------------------------------------------------------------
3258 // Field       : USB_INTE_STALL
3259 // Description : Source: SIE_STATUS.STALL_REC
3260 #define USB_INTE_STALL_RESET  _u(0x0)
3261 #define USB_INTE_STALL_BITS   _u(0x00000400)
3262 #define USB_INTE_STALL_MSB    _u(10)
3263 #define USB_INTE_STALL_LSB    _u(10)
3264 #define USB_INTE_STALL_ACCESS "RW"
3265 // -----------------------------------------------------------------------------
3266 // Field       : USB_INTE_ERROR_CRC
3267 // Description : Source: SIE_STATUS.CRC_ERROR
3268 #define USB_INTE_ERROR_CRC_RESET  _u(0x0)
3269 #define USB_INTE_ERROR_CRC_BITS   _u(0x00000200)
3270 #define USB_INTE_ERROR_CRC_MSB    _u(9)
3271 #define USB_INTE_ERROR_CRC_LSB    _u(9)
3272 #define USB_INTE_ERROR_CRC_ACCESS "RW"
3273 // -----------------------------------------------------------------------------
3274 // Field       : USB_INTE_ERROR_BIT_STUFF
3275 // Description : Source: SIE_STATUS.BIT_STUFF_ERROR
3276 #define USB_INTE_ERROR_BIT_STUFF_RESET  _u(0x0)
3277 #define USB_INTE_ERROR_BIT_STUFF_BITS   _u(0x00000100)
3278 #define USB_INTE_ERROR_BIT_STUFF_MSB    _u(8)
3279 #define USB_INTE_ERROR_BIT_STUFF_LSB    _u(8)
3280 #define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW"
3281 // -----------------------------------------------------------------------------
3282 // Field       : USB_INTE_ERROR_RX_OVERFLOW
3283 // Description : Source: SIE_STATUS.RX_OVERFLOW
3284 #define USB_INTE_ERROR_RX_OVERFLOW_RESET  _u(0x0)
3285 #define USB_INTE_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
3286 #define USB_INTE_ERROR_RX_OVERFLOW_MSB    _u(7)
3287 #define USB_INTE_ERROR_RX_OVERFLOW_LSB    _u(7)
3288 #define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW"
3289 // -----------------------------------------------------------------------------
3290 // Field       : USB_INTE_ERROR_RX_TIMEOUT
3291 // Description : Source: SIE_STATUS.RX_TIMEOUT
3292 #define USB_INTE_ERROR_RX_TIMEOUT_RESET  _u(0x0)
3293 #define USB_INTE_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
3294 #define USB_INTE_ERROR_RX_TIMEOUT_MSB    _u(6)
3295 #define USB_INTE_ERROR_RX_TIMEOUT_LSB    _u(6)
3296 #define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW"
3297 // -----------------------------------------------------------------------------
3298 // Field       : USB_INTE_ERROR_DATA_SEQ
3299 // Description : Source: SIE_STATUS.DATA_SEQ_ERROR
3300 #define USB_INTE_ERROR_DATA_SEQ_RESET  _u(0x0)
3301 #define USB_INTE_ERROR_DATA_SEQ_BITS   _u(0x00000020)
3302 #define USB_INTE_ERROR_DATA_SEQ_MSB    _u(5)
3303 #define USB_INTE_ERROR_DATA_SEQ_LSB    _u(5)
3304 #define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW"
3305 // -----------------------------------------------------------------------------
3306 // Field       : USB_INTE_BUFF_STATUS
3307 // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
3308 //               all bits in BUFF_STATUS.
3309 #define USB_INTE_BUFF_STATUS_RESET  _u(0x0)
3310 #define USB_INTE_BUFF_STATUS_BITS   _u(0x00000010)
3311 #define USB_INTE_BUFF_STATUS_MSB    _u(4)
3312 #define USB_INTE_BUFF_STATUS_LSB    _u(4)
3313 #define USB_INTE_BUFF_STATUS_ACCESS "RW"
3314 // -----------------------------------------------------------------------------
3315 // Field       : USB_INTE_TRANS_COMPLETE
3316 // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
3317 //               writing to this bit.
3318 #define USB_INTE_TRANS_COMPLETE_RESET  _u(0x0)
3319 #define USB_INTE_TRANS_COMPLETE_BITS   _u(0x00000008)
3320 #define USB_INTE_TRANS_COMPLETE_MSB    _u(3)
3321 #define USB_INTE_TRANS_COMPLETE_LSB    _u(3)
3322 #define USB_INTE_TRANS_COMPLETE_ACCESS "RW"
3323 // -----------------------------------------------------------------------------
3324 // Field       : USB_INTE_HOST_SOF
3325 // Description : Host: raised every time the host sends a SOF (Start of Frame).
3326 //               Cleared by reading SOF_RD
3327 #define USB_INTE_HOST_SOF_RESET  _u(0x0)
3328 #define USB_INTE_HOST_SOF_BITS   _u(0x00000004)
3329 #define USB_INTE_HOST_SOF_MSB    _u(2)
3330 #define USB_INTE_HOST_SOF_LSB    _u(2)
3331 #define USB_INTE_HOST_SOF_ACCESS "RW"
3332 // -----------------------------------------------------------------------------
3333 // Field       : USB_INTE_HOST_RESUME
3334 // Description : Host: raised when a device wakes up the host. Cleared by
3335 //               writing to SIE_STATUS.RESUME
3336 #define USB_INTE_HOST_RESUME_RESET  _u(0x0)
3337 #define USB_INTE_HOST_RESUME_BITS   _u(0x00000002)
3338 #define USB_INTE_HOST_RESUME_MSB    _u(1)
3339 #define USB_INTE_HOST_RESUME_LSB    _u(1)
3340 #define USB_INTE_HOST_RESUME_ACCESS "RW"
3341 // -----------------------------------------------------------------------------
3342 // Field       : USB_INTE_HOST_CONN_DIS
3343 // Description : Host: raised when a device is connected or disconnected (i.e.
3344 //               when SIE_STATUS.SPEED changes). Cleared by writing to
3345 //               SIE_STATUS.SPEED
3346 #define USB_INTE_HOST_CONN_DIS_RESET  _u(0x0)
3347 #define USB_INTE_HOST_CONN_DIS_BITS   _u(0x00000001)
3348 #define USB_INTE_HOST_CONN_DIS_MSB    _u(0)
3349 #define USB_INTE_HOST_CONN_DIS_LSB    _u(0)
3350 #define USB_INTE_HOST_CONN_DIS_ACCESS "RW"
3351 // =============================================================================
3352 // Register    : USB_INTF
3353 // Description : Interrupt Force
3354 #define USB_INTF_OFFSET _u(0x00000094)
3355 #define USB_INTF_BITS   _u(0x00ffffff)
3356 #define USB_INTF_RESET  _u(0x00000000)
3357 // -----------------------------------------------------------------------------
3358 // Field       : USB_INTF_EPX_STOPPED_ON_NAK
3359 // Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK
3360 #define USB_INTF_EPX_STOPPED_ON_NAK_RESET  _u(0x0)
3361 #define USB_INTF_EPX_STOPPED_ON_NAK_BITS   _u(0x00800000)
3362 #define USB_INTF_EPX_STOPPED_ON_NAK_MSB    _u(23)
3363 #define USB_INTF_EPX_STOPPED_ON_NAK_LSB    _u(23)
3364 #define USB_INTF_EPX_STOPPED_ON_NAK_ACCESS "RW"
3365 // -----------------------------------------------------------------------------
3366 // Field       : USB_INTF_DEV_SM_WATCHDOG_FIRED
3367 // Description : Source: DEV_SM_WATCHDOG.FIRED
3368 #define USB_INTF_DEV_SM_WATCHDOG_FIRED_RESET  _u(0x0)
3369 #define USB_INTF_DEV_SM_WATCHDOG_FIRED_BITS   _u(0x00400000)
3370 #define USB_INTF_DEV_SM_WATCHDOG_FIRED_MSB    _u(22)
3371 #define USB_INTF_DEV_SM_WATCHDOG_FIRED_LSB    _u(22)
3372 #define USB_INTF_DEV_SM_WATCHDOG_FIRED_ACCESS "RW"
3373 // -----------------------------------------------------------------------------
3374 // Field       : USB_INTF_ENDPOINT_ERROR
3375 // Description : Source: SIE_STATUS.ENDPOINT_ERROR
3376 #define USB_INTF_ENDPOINT_ERROR_RESET  _u(0x0)
3377 #define USB_INTF_ENDPOINT_ERROR_BITS   _u(0x00200000)
3378 #define USB_INTF_ENDPOINT_ERROR_MSB    _u(21)
3379 #define USB_INTF_ENDPOINT_ERROR_LSB    _u(21)
3380 #define USB_INTF_ENDPOINT_ERROR_ACCESS "RW"
3381 // -----------------------------------------------------------------------------
3382 // Field       : USB_INTF_RX_SHORT_PACKET
3383 // Description : Source: SIE_STATUS.RX_SHORT_PACKET
3384 #define USB_INTF_RX_SHORT_PACKET_RESET  _u(0x0)
3385 #define USB_INTF_RX_SHORT_PACKET_BITS   _u(0x00100000)
3386 #define USB_INTF_RX_SHORT_PACKET_MSB    _u(20)
3387 #define USB_INTF_RX_SHORT_PACKET_LSB    _u(20)
3388 #define USB_INTF_RX_SHORT_PACKET_ACCESS "RW"
3389 // -----------------------------------------------------------------------------
3390 // Field       : USB_INTF_EP_STALL_NAK
3391 // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
3392 //               clearing all bits in EP_STATUS_STALL_NAK.
3393 #define USB_INTF_EP_STALL_NAK_RESET  _u(0x0)
3394 #define USB_INTF_EP_STALL_NAK_BITS   _u(0x00080000)
3395 #define USB_INTF_EP_STALL_NAK_MSB    _u(19)
3396 #define USB_INTF_EP_STALL_NAK_LSB    _u(19)
3397 #define USB_INTF_EP_STALL_NAK_ACCESS "RW"
3398 // -----------------------------------------------------------------------------
3399 // Field       : USB_INTF_ABORT_DONE
3400 // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
3401 //               bits in ABORT_DONE.
3402 #define USB_INTF_ABORT_DONE_RESET  _u(0x0)
3403 #define USB_INTF_ABORT_DONE_BITS   _u(0x00040000)
3404 #define USB_INTF_ABORT_DONE_MSB    _u(18)
3405 #define USB_INTF_ABORT_DONE_LSB    _u(18)
3406 #define USB_INTF_ABORT_DONE_ACCESS "RW"
3407 // -----------------------------------------------------------------------------
3408 // Field       : USB_INTF_DEV_SOF
3409 // Description : Set every time the device receives a SOF (Start of Frame)
3410 //               packet. Cleared by reading SOF_RD
3411 #define USB_INTF_DEV_SOF_RESET  _u(0x0)
3412 #define USB_INTF_DEV_SOF_BITS   _u(0x00020000)
3413 #define USB_INTF_DEV_SOF_MSB    _u(17)
3414 #define USB_INTF_DEV_SOF_LSB    _u(17)
3415 #define USB_INTF_DEV_SOF_ACCESS "RW"
3416 // -----------------------------------------------------------------------------
3417 // Field       : USB_INTF_SETUP_REQ
3418 // Description : Device. Source: SIE_STATUS.SETUP_REC
3419 #define USB_INTF_SETUP_REQ_RESET  _u(0x0)
3420 #define USB_INTF_SETUP_REQ_BITS   _u(0x00010000)
3421 #define USB_INTF_SETUP_REQ_MSB    _u(16)
3422 #define USB_INTF_SETUP_REQ_LSB    _u(16)
3423 #define USB_INTF_SETUP_REQ_ACCESS "RW"
3424 // -----------------------------------------------------------------------------
3425 // Field       : USB_INTF_DEV_RESUME_FROM_HOST
3426 // Description : Set when the device receives a resume from the host. Cleared by
3427 //               writing to SIE_STATUS.RESUME
3428 #define USB_INTF_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
3429 #define USB_INTF_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
3430 #define USB_INTF_DEV_RESUME_FROM_HOST_MSB    _u(15)
3431 #define USB_INTF_DEV_RESUME_FROM_HOST_LSB    _u(15)
3432 #define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW"
3433 // -----------------------------------------------------------------------------
3434 // Field       : USB_INTF_DEV_SUSPEND
3435 // Description : Set when the device suspend state changes. Cleared by writing
3436 //               to SIE_STATUS.SUSPENDED
3437 #define USB_INTF_DEV_SUSPEND_RESET  _u(0x0)
3438 #define USB_INTF_DEV_SUSPEND_BITS   _u(0x00004000)
3439 #define USB_INTF_DEV_SUSPEND_MSB    _u(14)
3440 #define USB_INTF_DEV_SUSPEND_LSB    _u(14)
3441 #define USB_INTF_DEV_SUSPEND_ACCESS "RW"
3442 // -----------------------------------------------------------------------------
3443 // Field       : USB_INTF_DEV_CONN_DIS
3444 // Description : Set when the device connection state changes. Cleared by
3445 //               writing to SIE_STATUS.CONNECTED
3446 #define USB_INTF_DEV_CONN_DIS_RESET  _u(0x0)
3447 #define USB_INTF_DEV_CONN_DIS_BITS   _u(0x00002000)
3448 #define USB_INTF_DEV_CONN_DIS_MSB    _u(13)
3449 #define USB_INTF_DEV_CONN_DIS_LSB    _u(13)
3450 #define USB_INTF_DEV_CONN_DIS_ACCESS "RW"
3451 // -----------------------------------------------------------------------------
3452 // Field       : USB_INTF_BUS_RESET
3453 // Description : Source: SIE_STATUS.BUS_RESET
3454 #define USB_INTF_BUS_RESET_RESET  _u(0x0)
3455 #define USB_INTF_BUS_RESET_BITS   _u(0x00001000)
3456 #define USB_INTF_BUS_RESET_MSB    _u(12)
3457 #define USB_INTF_BUS_RESET_LSB    _u(12)
3458 #define USB_INTF_BUS_RESET_ACCESS "RW"
3459 // -----------------------------------------------------------------------------
3460 // Field       : USB_INTF_VBUS_DETECT
3461 // Description : Source: SIE_STATUS.VBUS_DETECTED
3462 #define USB_INTF_VBUS_DETECT_RESET  _u(0x0)
3463 #define USB_INTF_VBUS_DETECT_BITS   _u(0x00000800)
3464 #define USB_INTF_VBUS_DETECT_MSB    _u(11)
3465 #define USB_INTF_VBUS_DETECT_LSB    _u(11)
3466 #define USB_INTF_VBUS_DETECT_ACCESS "RW"
3467 // -----------------------------------------------------------------------------
3468 // Field       : USB_INTF_STALL
3469 // Description : Source: SIE_STATUS.STALL_REC
3470 #define USB_INTF_STALL_RESET  _u(0x0)
3471 #define USB_INTF_STALL_BITS   _u(0x00000400)
3472 #define USB_INTF_STALL_MSB    _u(10)
3473 #define USB_INTF_STALL_LSB    _u(10)
3474 #define USB_INTF_STALL_ACCESS "RW"
3475 // -----------------------------------------------------------------------------
3476 // Field       : USB_INTF_ERROR_CRC
3477 // Description : Source: SIE_STATUS.CRC_ERROR
3478 #define USB_INTF_ERROR_CRC_RESET  _u(0x0)
3479 #define USB_INTF_ERROR_CRC_BITS   _u(0x00000200)
3480 #define USB_INTF_ERROR_CRC_MSB    _u(9)
3481 #define USB_INTF_ERROR_CRC_LSB    _u(9)
3482 #define USB_INTF_ERROR_CRC_ACCESS "RW"
3483 // -----------------------------------------------------------------------------
3484 // Field       : USB_INTF_ERROR_BIT_STUFF
3485 // Description : Source: SIE_STATUS.BIT_STUFF_ERROR
3486 #define USB_INTF_ERROR_BIT_STUFF_RESET  _u(0x0)
3487 #define USB_INTF_ERROR_BIT_STUFF_BITS   _u(0x00000100)
3488 #define USB_INTF_ERROR_BIT_STUFF_MSB    _u(8)
3489 #define USB_INTF_ERROR_BIT_STUFF_LSB    _u(8)
3490 #define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW"
3491 // -----------------------------------------------------------------------------
3492 // Field       : USB_INTF_ERROR_RX_OVERFLOW
3493 // Description : Source: SIE_STATUS.RX_OVERFLOW
3494 #define USB_INTF_ERROR_RX_OVERFLOW_RESET  _u(0x0)
3495 #define USB_INTF_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
3496 #define USB_INTF_ERROR_RX_OVERFLOW_MSB    _u(7)
3497 #define USB_INTF_ERROR_RX_OVERFLOW_LSB    _u(7)
3498 #define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW"
3499 // -----------------------------------------------------------------------------
3500 // Field       : USB_INTF_ERROR_RX_TIMEOUT
3501 // Description : Source: SIE_STATUS.RX_TIMEOUT
3502 #define USB_INTF_ERROR_RX_TIMEOUT_RESET  _u(0x0)
3503 #define USB_INTF_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
3504 #define USB_INTF_ERROR_RX_TIMEOUT_MSB    _u(6)
3505 #define USB_INTF_ERROR_RX_TIMEOUT_LSB    _u(6)
3506 #define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW"
3507 // -----------------------------------------------------------------------------
3508 // Field       : USB_INTF_ERROR_DATA_SEQ
3509 // Description : Source: SIE_STATUS.DATA_SEQ_ERROR
3510 #define USB_INTF_ERROR_DATA_SEQ_RESET  _u(0x0)
3511 #define USB_INTF_ERROR_DATA_SEQ_BITS   _u(0x00000020)
3512 #define USB_INTF_ERROR_DATA_SEQ_MSB    _u(5)
3513 #define USB_INTF_ERROR_DATA_SEQ_LSB    _u(5)
3514 #define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW"
3515 // -----------------------------------------------------------------------------
3516 // Field       : USB_INTF_BUFF_STATUS
3517 // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
3518 //               all bits in BUFF_STATUS.
3519 #define USB_INTF_BUFF_STATUS_RESET  _u(0x0)
3520 #define USB_INTF_BUFF_STATUS_BITS   _u(0x00000010)
3521 #define USB_INTF_BUFF_STATUS_MSB    _u(4)
3522 #define USB_INTF_BUFF_STATUS_LSB    _u(4)
3523 #define USB_INTF_BUFF_STATUS_ACCESS "RW"
3524 // -----------------------------------------------------------------------------
3525 // Field       : USB_INTF_TRANS_COMPLETE
3526 // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
3527 //               writing to this bit.
3528 #define USB_INTF_TRANS_COMPLETE_RESET  _u(0x0)
3529 #define USB_INTF_TRANS_COMPLETE_BITS   _u(0x00000008)
3530 #define USB_INTF_TRANS_COMPLETE_MSB    _u(3)
3531 #define USB_INTF_TRANS_COMPLETE_LSB    _u(3)
3532 #define USB_INTF_TRANS_COMPLETE_ACCESS "RW"
3533 // -----------------------------------------------------------------------------
3534 // Field       : USB_INTF_HOST_SOF
3535 // Description : Host: raised every time the host sends a SOF (Start of Frame).
3536 //               Cleared by reading SOF_RD
3537 #define USB_INTF_HOST_SOF_RESET  _u(0x0)
3538 #define USB_INTF_HOST_SOF_BITS   _u(0x00000004)
3539 #define USB_INTF_HOST_SOF_MSB    _u(2)
3540 #define USB_INTF_HOST_SOF_LSB    _u(2)
3541 #define USB_INTF_HOST_SOF_ACCESS "RW"
3542 // -----------------------------------------------------------------------------
3543 // Field       : USB_INTF_HOST_RESUME
3544 // Description : Host: raised when a device wakes up the host. Cleared by
3545 //               writing to SIE_STATUS.RESUME
3546 #define USB_INTF_HOST_RESUME_RESET  _u(0x0)
3547 #define USB_INTF_HOST_RESUME_BITS   _u(0x00000002)
3548 #define USB_INTF_HOST_RESUME_MSB    _u(1)
3549 #define USB_INTF_HOST_RESUME_LSB    _u(1)
3550 #define USB_INTF_HOST_RESUME_ACCESS "RW"
3551 // -----------------------------------------------------------------------------
3552 // Field       : USB_INTF_HOST_CONN_DIS
3553 // Description : Host: raised when a device is connected or disconnected (i.e.
3554 //               when SIE_STATUS.SPEED changes). Cleared by writing to
3555 //               SIE_STATUS.SPEED
3556 #define USB_INTF_HOST_CONN_DIS_RESET  _u(0x0)
3557 #define USB_INTF_HOST_CONN_DIS_BITS   _u(0x00000001)
3558 #define USB_INTF_HOST_CONN_DIS_MSB    _u(0)
3559 #define USB_INTF_HOST_CONN_DIS_LSB    _u(0)
3560 #define USB_INTF_HOST_CONN_DIS_ACCESS "RW"
3561 // =============================================================================
3562 // Register    : USB_INTS
3563 // Description : Interrupt status after masking & forcing
3564 #define USB_INTS_OFFSET _u(0x00000098)
3565 #define USB_INTS_BITS   _u(0x00ffffff)
3566 #define USB_INTS_RESET  _u(0x00000000)
3567 // -----------------------------------------------------------------------------
3568 // Field       : USB_INTS_EPX_STOPPED_ON_NAK
3569 // Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK
3570 #define USB_INTS_EPX_STOPPED_ON_NAK_RESET  _u(0x0)
3571 #define USB_INTS_EPX_STOPPED_ON_NAK_BITS   _u(0x00800000)
3572 #define USB_INTS_EPX_STOPPED_ON_NAK_MSB    _u(23)
3573 #define USB_INTS_EPX_STOPPED_ON_NAK_LSB    _u(23)
3574 #define USB_INTS_EPX_STOPPED_ON_NAK_ACCESS "RO"
3575 // -----------------------------------------------------------------------------
3576 // Field       : USB_INTS_DEV_SM_WATCHDOG_FIRED
3577 // Description : Source: DEV_SM_WATCHDOG.FIRED
3578 #define USB_INTS_DEV_SM_WATCHDOG_FIRED_RESET  _u(0x0)
3579 #define USB_INTS_DEV_SM_WATCHDOG_FIRED_BITS   _u(0x00400000)
3580 #define USB_INTS_DEV_SM_WATCHDOG_FIRED_MSB    _u(22)
3581 #define USB_INTS_DEV_SM_WATCHDOG_FIRED_LSB    _u(22)
3582 #define USB_INTS_DEV_SM_WATCHDOG_FIRED_ACCESS "RO"
3583 // -----------------------------------------------------------------------------
3584 // Field       : USB_INTS_ENDPOINT_ERROR
3585 // Description : Source: SIE_STATUS.ENDPOINT_ERROR
3586 #define USB_INTS_ENDPOINT_ERROR_RESET  _u(0x0)
3587 #define USB_INTS_ENDPOINT_ERROR_BITS   _u(0x00200000)
3588 #define USB_INTS_ENDPOINT_ERROR_MSB    _u(21)
3589 #define USB_INTS_ENDPOINT_ERROR_LSB    _u(21)
3590 #define USB_INTS_ENDPOINT_ERROR_ACCESS "RO"
3591 // -----------------------------------------------------------------------------
3592 // Field       : USB_INTS_RX_SHORT_PACKET
3593 // Description : Source: SIE_STATUS.RX_SHORT_PACKET
3594 #define USB_INTS_RX_SHORT_PACKET_RESET  _u(0x0)
3595 #define USB_INTS_RX_SHORT_PACKET_BITS   _u(0x00100000)
3596 #define USB_INTS_RX_SHORT_PACKET_MSB    _u(20)
3597 #define USB_INTS_RX_SHORT_PACKET_LSB    _u(20)
3598 #define USB_INTS_RX_SHORT_PACKET_ACCESS "RO"
3599 // -----------------------------------------------------------------------------
3600 // Field       : USB_INTS_EP_STALL_NAK
3601 // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
3602 //               clearing all bits in EP_STATUS_STALL_NAK.
3603 #define USB_INTS_EP_STALL_NAK_RESET  _u(0x0)
3604 #define USB_INTS_EP_STALL_NAK_BITS   _u(0x00080000)
3605 #define USB_INTS_EP_STALL_NAK_MSB    _u(19)
3606 #define USB_INTS_EP_STALL_NAK_LSB    _u(19)
3607 #define USB_INTS_EP_STALL_NAK_ACCESS "RO"
3608 // -----------------------------------------------------------------------------
3609 // Field       : USB_INTS_ABORT_DONE
3610 // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
3611 //               bits in ABORT_DONE.
3612 #define USB_INTS_ABORT_DONE_RESET  _u(0x0)
3613 #define USB_INTS_ABORT_DONE_BITS   _u(0x00040000)
3614 #define USB_INTS_ABORT_DONE_MSB    _u(18)
3615 #define USB_INTS_ABORT_DONE_LSB    _u(18)
3616 #define USB_INTS_ABORT_DONE_ACCESS "RO"
3617 // -----------------------------------------------------------------------------
3618 // Field       : USB_INTS_DEV_SOF
3619 // Description : Set every time the device receives a SOF (Start of Frame)
3620 //               packet. Cleared by reading SOF_RD
3621 #define USB_INTS_DEV_SOF_RESET  _u(0x0)
3622 #define USB_INTS_DEV_SOF_BITS   _u(0x00020000)
3623 #define USB_INTS_DEV_SOF_MSB    _u(17)
3624 #define USB_INTS_DEV_SOF_LSB    _u(17)
3625 #define USB_INTS_DEV_SOF_ACCESS "RO"
3626 // -----------------------------------------------------------------------------
3627 // Field       : USB_INTS_SETUP_REQ
3628 // Description : Device. Source: SIE_STATUS.SETUP_REC
3629 #define USB_INTS_SETUP_REQ_RESET  _u(0x0)
3630 #define USB_INTS_SETUP_REQ_BITS   _u(0x00010000)
3631 #define USB_INTS_SETUP_REQ_MSB    _u(16)
3632 #define USB_INTS_SETUP_REQ_LSB    _u(16)
3633 #define USB_INTS_SETUP_REQ_ACCESS "RO"
3634 // -----------------------------------------------------------------------------
3635 // Field       : USB_INTS_DEV_RESUME_FROM_HOST
3636 // Description : Set when the device receives a resume from the host. Cleared by
3637 //               writing to SIE_STATUS.RESUME
3638 #define USB_INTS_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
3639 #define USB_INTS_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
3640 #define USB_INTS_DEV_RESUME_FROM_HOST_MSB    _u(15)
3641 #define USB_INTS_DEV_RESUME_FROM_HOST_LSB    _u(15)
3642 #define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO"
3643 // -----------------------------------------------------------------------------
3644 // Field       : USB_INTS_DEV_SUSPEND
3645 // Description : Set when the device suspend state changes. Cleared by writing
3646 //               to SIE_STATUS.SUSPENDED
3647 #define USB_INTS_DEV_SUSPEND_RESET  _u(0x0)
3648 #define USB_INTS_DEV_SUSPEND_BITS   _u(0x00004000)
3649 #define USB_INTS_DEV_SUSPEND_MSB    _u(14)
3650 #define USB_INTS_DEV_SUSPEND_LSB    _u(14)
3651 #define USB_INTS_DEV_SUSPEND_ACCESS "RO"
3652 // -----------------------------------------------------------------------------
3653 // Field       : USB_INTS_DEV_CONN_DIS
3654 // Description : Set when the device connection state changes. Cleared by
3655 //               writing to SIE_STATUS.CONNECTED
3656 #define USB_INTS_DEV_CONN_DIS_RESET  _u(0x0)
3657 #define USB_INTS_DEV_CONN_DIS_BITS   _u(0x00002000)
3658 #define USB_INTS_DEV_CONN_DIS_MSB    _u(13)
3659 #define USB_INTS_DEV_CONN_DIS_LSB    _u(13)
3660 #define USB_INTS_DEV_CONN_DIS_ACCESS "RO"
3661 // -----------------------------------------------------------------------------
3662 // Field       : USB_INTS_BUS_RESET
3663 // Description : Source: SIE_STATUS.BUS_RESET
3664 #define USB_INTS_BUS_RESET_RESET  _u(0x0)
3665 #define USB_INTS_BUS_RESET_BITS   _u(0x00001000)
3666 #define USB_INTS_BUS_RESET_MSB    _u(12)
3667 #define USB_INTS_BUS_RESET_LSB    _u(12)
3668 #define USB_INTS_BUS_RESET_ACCESS "RO"
3669 // -----------------------------------------------------------------------------
3670 // Field       : USB_INTS_VBUS_DETECT
3671 // Description : Source: SIE_STATUS.VBUS_DETECTED
3672 #define USB_INTS_VBUS_DETECT_RESET  _u(0x0)
3673 #define USB_INTS_VBUS_DETECT_BITS   _u(0x00000800)
3674 #define USB_INTS_VBUS_DETECT_MSB    _u(11)
3675 #define USB_INTS_VBUS_DETECT_LSB    _u(11)
3676 #define USB_INTS_VBUS_DETECT_ACCESS "RO"
3677 // -----------------------------------------------------------------------------
3678 // Field       : USB_INTS_STALL
3679 // Description : Source: SIE_STATUS.STALL_REC
3680 #define USB_INTS_STALL_RESET  _u(0x0)
3681 #define USB_INTS_STALL_BITS   _u(0x00000400)
3682 #define USB_INTS_STALL_MSB    _u(10)
3683 #define USB_INTS_STALL_LSB    _u(10)
3684 #define USB_INTS_STALL_ACCESS "RO"
3685 // -----------------------------------------------------------------------------
3686 // Field       : USB_INTS_ERROR_CRC
3687 // Description : Source: SIE_STATUS.CRC_ERROR
3688 #define USB_INTS_ERROR_CRC_RESET  _u(0x0)
3689 #define USB_INTS_ERROR_CRC_BITS   _u(0x00000200)
3690 #define USB_INTS_ERROR_CRC_MSB    _u(9)
3691 #define USB_INTS_ERROR_CRC_LSB    _u(9)
3692 #define USB_INTS_ERROR_CRC_ACCESS "RO"
3693 // -----------------------------------------------------------------------------
3694 // Field       : USB_INTS_ERROR_BIT_STUFF
3695 // Description : Source: SIE_STATUS.BIT_STUFF_ERROR
3696 #define USB_INTS_ERROR_BIT_STUFF_RESET  _u(0x0)
3697 #define USB_INTS_ERROR_BIT_STUFF_BITS   _u(0x00000100)
3698 #define USB_INTS_ERROR_BIT_STUFF_MSB    _u(8)
3699 #define USB_INTS_ERROR_BIT_STUFF_LSB    _u(8)
3700 #define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO"
3701 // -----------------------------------------------------------------------------
3702 // Field       : USB_INTS_ERROR_RX_OVERFLOW
3703 // Description : Source: SIE_STATUS.RX_OVERFLOW
3704 #define USB_INTS_ERROR_RX_OVERFLOW_RESET  _u(0x0)
3705 #define USB_INTS_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
3706 #define USB_INTS_ERROR_RX_OVERFLOW_MSB    _u(7)
3707 #define USB_INTS_ERROR_RX_OVERFLOW_LSB    _u(7)
3708 #define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO"
3709 // -----------------------------------------------------------------------------
3710 // Field       : USB_INTS_ERROR_RX_TIMEOUT
3711 // Description : Source: SIE_STATUS.RX_TIMEOUT
3712 #define USB_INTS_ERROR_RX_TIMEOUT_RESET  _u(0x0)
3713 #define USB_INTS_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
3714 #define USB_INTS_ERROR_RX_TIMEOUT_MSB    _u(6)
3715 #define USB_INTS_ERROR_RX_TIMEOUT_LSB    _u(6)
3716 #define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO"
3717 // -----------------------------------------------------------------------------
3718 // Field       : USB_INTS_ERROR_DATA_SEQ
3719 // Description : Source: SIE_STATUS.DATA_SEQ_ERROR
3720 #define USB_INTS_ERROR_DATA_SEQ_RESET  _u(0x0)
3721 #define USB_INTS_ERROR_DATA_SEQ_BITS   _u(0x00000020)
3722 #define USB_INTS_ERROR_DATA_SEQ_MSB    _u(5)
3723 #define USB_INTS_ERROR_DATA_SEQ_LSB    _u(5)
3724 #define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO"
3725 // -----------------------------------------------------------------------------
3726 // Field       : USB_INTS_BUFF_STATUS
3727 // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
3728 //               all bits in BUFF_STATUS.
3729 #define USB_INTS_BUFF_STATUS_RESET  _u(0x0)
3730 #define USB_INTS_BUFF_STATUS_BITS   _u(0x00000010)
3731 #define USB_INTS_BUFF_STATUS_MSB    _u(4)
3732 #define USB_INTS_BUFF_STATUS_LSB    _u(4)
3733 #define USB_INTS_BUFF_STATUS_ACCESS "RO"
3734 // -----------------------------------------------------------------------------
3735 // Field       : USB_INTS_TRANS_COMPLETE
3736 // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
3737 //               writing to this bit.
3738 #define USB_INTS_TRANS_COMPLETE_RESET  _u(0x0)
3739 #define USB_INTS_TRANS_COMPLETE_BITS   _u(0x00000008)
3740 #define USB_INTS_TRANS_COMPLETE_MSB    _u(3)
3741 #define USB_INTS_TRANS_COMPLETE_LSB    _u(3)
3742 #define USB_INTS_TRANS_COMPLETE_ACCESS "RO"
3743 // -----------------------------------------------------------------------------
3744 // Field       : USB_INTS_HOST_SOF
3745 // Description : Host: raised every time the host sends a SOF (Start of Frame).
3746 //               Cleared by reading SOF_RD
3747 #define USB_INTS_HOST_SOF_RESET  _u(0x0)
3748 #define USB_INTS_HOST_SOF_BITS   _u(0x00000004)
3749 #define USB_INTS_HOST_SOF_MSB    _u(2)
3750 #define USB_INTS_HOST_SOF_LSB    _u(2)
3751 #define USB_INTS_HOST_SOF_ACCESS "RO"
3752 // -----------------------------------------------------------------------------
3753 // Field       : USB_INTS_HOST_RESUME
3754 // Description : Host: raised when a device wakes up the host. Cleared by
3755 //               writing to SIE_STATUS.RESUME
3756 #define USB_INTS_HOST_RESUME_RESET  _u(0x0)
3757 #define USB_INTS_HOST_RESUME_BITS   _u(0x00000002)
3758 #define USB_INTS_HOST_RESUME_MSB    _u(1)
3759 #define USB_INTS_HOST_RESUME_LSB    _u(1)
3760 #define USB_INTS_HOST_RESUME_ACCESS "RO"
3761 // -----------------------------------------------------------------------------
3762 // Field       : USB_INTS_HOST_CONN_DIS
3763 // Description : Host: raised when a device is connected or disconnected (i.e.
3764 //               when SIE_STATUS.SPEED changes). Cleared by writing to
3765 //               SIE_STATUS.SPEED
3766 #define USB_INTS_HOST_CONN_DIS_RESET  _u(0x0)
3767 #define USB_INTS_HOST_CONN_DIS_BITS   _u(0x00000001)
3768 #define USB_INTS_HOST_CONN_DIS_MSB    _u(0)
3769 #define USB_INTS_HOST_CONN_DIS_LSB    _u(0)
3770 #define USB_INTS_HOST_CONN_DIS_ACCESS "RO"
3771 // =============================================================================
3772 // Register    : USB_SOF_TIMESTAMP_RAW
3773 // Description : Device only. Raw value of free-running PHY clock counter
3774 //               @48MHz. Used to calculate time between SOF events.
3775 #define USB_SOF_TIMESTAMP_RAW_OFFSET _u(0x00000100)
3776 #define USB_SOF_TIMESTAMP_RAW_BITS   _u(0x001fffff)
3777 #define USB_SOF_TIMESTAMP_RAW_RESET  _u(0x00000000)
3778 #define USB_SOF_TIMESTAMP_RAW_MSB    _u(20)
3779 #define USB_SOF_TIMESTAMP_RAW_LSB    _u(0)
3780 #define USB_SOF_TIMESTAMP_RAW_ACCESS "RO"
3781 // =============================================================================
3782 // Register    : USB_SOF_TIMESTAMP_LAST
3783 // Description : Device only. Value of free-running PHY clock counter @48MHz
3784 //               when last SOF event occurred.
3785 #define USB_SOF_TIMESTAMP_LAST_OFFSET _u(0x00000104)
3786 #define USB_SOF_TIMESTAMP_LAST_BITS   _u(0x001fffff)
3787 #define USB_SOF_TIMESTAMP_LAST_RESET  _u(0x00000000)
3788 #define USB_SOF_TIMESTAMP_LAST_MSB    _u(20)
3789 #define USB_SOF_TIMESTAMP_LAST_LSB    _u(0)
3790 #define USB_SOF_TIMESTAMP_LAST_ACCESS "RO"
3791 // =============================================================================
3792 // Register    : USB_SM_STATE
3793 #define USB_SM_STATE_OFFSET _u(0x00000108)
3794 #define USB_SM_STATE_BITS   _u(0x00000fff)
3795 #define USB_SM_STATE_RESET  _u(0x00000000)
3796 // -----------------------------------------------------------------------------
3797 // Field       : USB_SM_STATE_RX_DASM
3798 #define USB_SM_STATE_RX_DASM_RESET  _u(0x0)
3799 #define USB_SM_STATE_RX_DASM_BITS   _u(0x00000f00)
3800 #define USB_SM_STATE_RX_DASM_MSB    _u(11)
3801 #define USB_SM_STATE_RX_DASM_LSB    _u(8)
3802 #define USB_SM_STATE_RX_DASM_ACCESS "RO"
3803 // -----------------------------------------------------------------------------
3804 // Field       : USB_SM_STATE_BC_STATE
3805 #define USB_SM_STATE_BC_STATE_RESET  _u(0x0)
3806 #define USB_SM_STATE_BC_STATE_BITS   _u(0x000000e0)
3807 #define USB_SM_STATE_BC_STATE_MSB    _u(7)
3808 #define USB_SM_STATE_BC_STATE_LSB    _u(5)
3809 #define USB_SM_STATE_BC_STATE_ACCESS "RO"
3810 // -----------------------------------------------------------------------------
3811 // Field       : USB_SM_STATE_STATE
3812 #define USB_SM_STATE_STATE_RESET  _u(0x00)
3813 #define USB_SM_STATE_STATE_BITS   _u(0x0000001f)
3814 #define USB_SM_STATE_STATE_MSB    _u(4)
3815 #define USB_SM_STATE_STATE_LSB    _u(0)
3816 #define USB_SM_STATE_STATE_ACCESS "RO"
3817 // =============================================================================
3818 // Register    : USB_EP_TX_ERROR
3819 // Description : TX error count for each endpoint. Write to each field to reset
3820 //               the counter to 0.
3821 #define USB_EP_TX_ERROR_OFFSET _u(0x0000010c)
3822 #define USB_EP_TX_ERROR_BITS   _u(0xffffffff)
3823 #define USB_EP_TX_ERROR_RESET  _u(0x00000000)
3824 // -----------------------------------------------------------------------------
3825 // Field       : USB_EP_TX_ERROR_EP15
3826 #define USB_EP_TX_ERROR_EP15_RESET  _u(0x0)
3827 #define USB_EP_TX_ERROR_EP15_BITS   _u(0xc0000000)
3828 #define USB_EP_TX_ERROR_EP15_MSB    _u(31)
3829 #define USB_EP_TX_ERROR_EP15_LSB    _u(30)
3830 #define USB_EP_TX_ERROR_EP15_ACCESS "WC"
3831 // -----------------------------------------------------------------------------
3832 // Field       : USB_EP_TX_ERROR_EP14
3833 #define USB_EP_TX_ERROR_EP14_RESET  _u(0x0)
3834 #define USB_EP_TX_ERROR_EP14_BITS   _u(0x30000000)
3835 #define USB_EP_TX_ERROR_EP14_MSB    _u(29)
3836 #define USB_EP_TX_ERROR_EP14_LSB    _u(28)
3837 #define USB_EP_TX_ERROR_EP14_ACCESS "WC"
3838 // -----------------------------------------------------------------------------
3839 // Field       : USB_EP_TX_ERROR_EP13
3840 #define USB_EP_TX_ERROR_EP13_RESET  _u(0x0)
3841 #define USB_EP_TX_ERROR_EP13_BITS   _u(0x0c000000)
3842 #define USB_EP_TX_ERROR_EP13_MSB    _u(27)
3843 #define USB_EP_TX_ERROR_EP13_LSB    _u(26)
3844 #define USB_EP_TX_ERROR_EP13_ACCESS "WC"
3845 // -----------------------------------------------------------------------------
3846 // Field       : USB_EP_TX_ERROR_EP12
3847 #define USB_EP_TX_ERROR_EP12_RESET  _u(0x0)
3848 #define USB_EP_TX_ERROR_EP12_BITS   _u(0x03000000)
3849 #define USB_EP_TX_ERROR_EP12_MSB    _u(25)
3850 #define USB_EP_TX_ERROR_EP12_LSB    _u(24)
3851 #define USB_EP_TX_ERROR_EP12_ACCESS "WC"
3852 // -----------------------------------------------------------------------------
3853 // Field       : USB_EP_TX_ERROR_EP11
3854 #define USB_EP_TX_ERROR_EP11_RESET  _u(0x0)
3855 #define USB_EP_TX_ERROR_EP11_BITS   _u(0x00c00000)
3856 #define USB_EP_TX_ERROR_EP11_MSB    _u(23)
3857 #define USB_EP_TX_ERROR_EP11_LSB    _u(22)
3858 #define USB_EP_TX_ERROR_EP11_ACCESS "WC"
3859 // -----------------------------------------------------------------------------
3860 // Field       : USB_EP_TX_ERROR_EP10
3861 #define USB_EP_TX_ERROR_EP10_RESET  _u(0x0)
3862 #define USB_EP_TX_ERROR_EP10_BITS   _u(0x00300000)
3863 #define USB_EP_TX_ERROR_EP10_MSB    _u(21)
3864 #define USB_EP_TX_ERROR_EP10_LSB    _u(20)
3865 #define USB_EP_TX_ERROR_EP10_ACCESS "WC"
3866 // -----------------------------------------------------------------------------
3867 // Field       : USB_EP_TX_ERROR_EP9
3868 #define USB_EP_TX_ERROR_EP9_RESET  _u(0x0)
3869 #define USB_EP_TX_ERROR_EP9_BITS   _u(0x000c0000)
3870 #define USB_EP_TX_ERROR_EP9_MSB    _u(19)
3871 #define USB_EP_TX_ERROR_EP9_LSB    _u(18)
3872 #define USB_EP_TX_ERROR_EP9_ACCESS "WC"
3873 // -----------------------------------------------------------------------------
3874 // Field       : USB_EP_TX_ERROR_EP8
3875 #define USB_EP_TX_ERROR_EP8_RESET  _u(0x0)
3876 #define USB_EP_TX_ERROR_EP8_BITS   _u(0x00030000)
3877 #define USB_EP_TX_ERROR_EP8_MSB    _u(17)
3878 #define USB_EP_TX_ERROR_EP8_LSB    _u(16)
3879 #define USB_EP_TX_ERROR_EP8_ACCESS "WC"
3880 // -----------------------------------------------------------------------------
3881 // Field       : USB_EP_TX_ERROR_EP7
3882 #define USB_EP_TX_ERROR_EP7_RESET  _u(0x0)
3883 #define USB_EP_TX_ERROR_EP7_BITS   _u(0x0000c000)
3884 #define USB_EP_TX_ERROR_EP7_MSB    _u(15)
3885 #define USB_EP_TX_ERROR_EP7_LSB    _u(14)
3886 #define USB_EP_TX_ERROR_EP7_ACCESS "WC"
3887 // -----------------------------------------------------------------------------
3888 // Field       : USB_EP_TX_ERROR_EP6
3889 #define USB_EP_TX_ERROR_EP6_RESET  _u(0x0)
3890 #define USB_EP_TX_ERROR_EP6_BITS   _u(0x00003000)
3891 #define USB_EP_TX_ERROR_EP6_MSB    _u(13)
3892 #define USB_EP_TX_ERROR_EP6_LSB    _u(12)
3893 #define USB_EP_TX_ERROR_EP6_ACCESS "WC"
3894 // -----------------------------------------------------------------------------
3895 // Field       : USB_EP_TX_ERROR_EP5
3896 #define USB_EP_TX_ERROR_EP5_RESET  _u(0x0)
3897 #define USB_EP_TX_ERROR_EP5_BITS   _u(0x00000c00)
3898 #define USB_EP_TX_ERROR_EP5_MSB    _u(11)
3899 #define USB_EP_TX_ERROR_EP5_LSB    _u(10)
3900 #define USB_EP_TX_ERROR_EP5_ACCESS "WC"
3901 // -----------------------------------------------------------------------------
3902 // Field       : USB_EP_TX_ERROR_EP4
3903 #define USB_EP_TX_ERROR_EP4_RESET  _u(0x0)
3904 #define USB_EP_TX_ERROR_EP4_BITS   _u(0x00000300)
3905 #define USB_EP_TX_ERROR_EP4_MSB    _u(9)
3906 #define USB_EP_TX_ERROR_EP4_LSB    _u(8)
3907 #define USB_EP_TX_ERROR_EP4_ACCESS "WC"
3908 // -----------------------------------------------------------------------------
3909 // Field       : USB_EP_TX_ERROR_EP3
3910 #define USB_EP_TX_ERROR_EP3_RESET  _u(0x0)
3911 #define USB_EP_TX_ERROR_EP3_BITS   _u(0x000000c0)
3912 #define USB_EP_TX_ERROR_EP3_MSB    _u(7)
3913 #define USB_EP_TX_ERROR_EP3_LSB    _u(6)
3914 #define USB_EP_TX_ERROR_EP3_ACCESS "WC"
3915 // -----------------------------------------------------------------------------
3916 // Field       : USB_EP_TX_ERROR_EP2
3917 #define USB_EP_TX_ERROR_EP2_RESET  _u(0x0)
3918 #define USB_EP_TX_ERROR_EP2_BITS   _u(0x00000030)
3919 #define USB_EP_TX_ERROR_EP2_MSB    _u(5)
3920 #define USB_EP_TX_ERROR_EP2_LSB    _u(4)
3921 #define USB_EP_TX_ERROR_EP2_ACCESS "WC"
3922 // -----------------------------------------------------------------------------
3923 // Field       : USB_EP_TX_ERROR_EP1
3924 #define USB_EP_TX_ERROR_EP1_RESET  _u(0x0)
3925 #define USB_EP_TX_ERROR_EP1_BITS   _u(0x0000000c)
3926 #define USB_EP_TX_ERROR_EP1_MSB    _u(3)
3927 #define USB_EP_TX_ERROR_EP1_LSB    _u(2)
3928 #define USB_EP_TX_ERROR_EP1_ACCESS "WC"
3929 // -----------------------------------------------------------------------------
3930 // Field       : USB_EP_TX_ERROR_EP0
3931 #define USB_EP_TX_ERROR_EP0_RESET  _u(0x0)
3932 #define USB_EP_TX_ERROR_EP0_BITS   _u(0x00000003)
3933 #define USB_EP_TX_ERROR_EP0_MSB    _u(1)
3934 #define USB_EP_TX_ERROR_EP0_LSB    _u(0)
3935 #define USB_EP_TX_ERROR_EP0_ACCESS "WC"
3936 // =============================================================================
3937 // Register    : USB_EP_RX_ERROR
3938 // Description : RX error count for each endpoint. Write to each field to reset
3939 //               the counter to 0.
3940 #define USB_EP_RX_ERROR_OFFSET _u(0x00000110)
3941 #define USB_EP_RX_ERROR_BITS   _u(0xffffffff)
3942 #define USB_EP_RX_ERROR_RESET  _u(0x00000000)
3943 // -----------------------------------------------------------------------------
3944 // Field       : USB_EP_RX_ERROR_EP15_SEQ
3945 #define USB_EP_RX_ERROR_EP15_SEQ_RESET  _u(0x0)
3946 #define USB_EP_RX_ERROR_EP15_SEQ_BITS   _u(0x80000000)
3947 #define USB_EP_RX_ERROR_EP15_SEQ_MSB    _u(31)
3948 #define USB_EP_RX_ERROR_EP15_SEQ_LSB    _u(31)
3949 #define USB_EP_RX_ERROR_EP15_SEQ_ACCESS "WC"
3950 // -----------------------------------------------------------------------------
3951 // Field       : USB_EP_RX_ERROR_EP15_TRANSACTION
3952 #define USB_EP_RX_ERROR_EP15_TRANSACTION_RESET  _u(0x0)
3953 #define USB_EP_RX_ERROR_EP15_TRANSACTION_BITS   _u(0x40000000)
3954 #define USB_EP_RX_ERROR_EP15_TRANSACTION_MSB    _u(30)
3955 #define USB_EP_RX_ERROR_EP15_TRANSACTION_LSB    _u(30)
3956 #define USB_EP_RX_ERROR_EP15_TRANSACTION_ACCESS "WC"
3957 // -----------------------------------------------------------------------------
3958 // Field       : USB_EP_RX_ERROR_EP14_SEQ
3959 #define USB_EP_RX_ERROR_EP14_SEQ_RESET  _u(0x0)
3960 #define USB_EP_RX_ERROR_EP14_SEQ_BITS   _u(0x20000000)
3961 #define USB_EP_RX_ERROR_EP14_SEQ_MSB    _u(29)
3962 #define USB_EP_RX_ERROR_EP14_SEQ_LSB    _u(29)
3963 #define USB_EP_RX_ERROR_EP14_SEQ_ACCESS "WC"
3964 // -----------------------------------------------------------------------------
3965 // Field       : USB_EP_RX_ERROR_EP14_TRANSACTION
3966 #define USB_EP_RX_ERROR_EP14_TRANSACTION_RESET  _u(0x0)
3967 #define USB_EP_RX_ERROR_EP14_TRANSACTION_BITS   _u(0x10000000)
3968 #define USB_EP_RX_ERROR_EP14_TRANSACTION_MSB    _u(28)
3969 #define USB_EP_RX_ERROR_EP14_TRANSACTION_LSB    _u(28)
3970 #define USB_EP_RX_ERROR_EP14_TRANSACTION_ACCESS "WC"
3971 // -----------------------------------------------------------------------------
3972 // Field       : USB_EP_RX_ERROR_EP13_SEQ
3973 #define USB_EP_RX_ERROR_EP13_SEQ_RESET  _u(0x0)
3974 #define USB_EP_RX_ERROR_EP13_SEQ_BITS   _u(0x08000000)
3975 #define USB_EP_RX_ERROR_EP13_SEQ_MSB    _u(27)
3976 #define USB_EP_RX_ERROR_EP13_SEQ_LSB    _u(27)
3977 #define USB_EP_RX_ERROR_EP13_SEQ_ACCESS "WC"
3978 // -----------------------------------------------------------------------------
3979 // Field       : USB_EP_RX_ERROR_EP13_TRANSACTION
3980 #define USB_EP_RX_ERROR_EP13_TRANSACTION_RESET  _u(0x0)
3981 #define USB_EP_RX_ERROR_EP13_TRANSACTION_BITS   _u(0x04000000)
3982 #define USB_EP_RX_ERROR_EP13_TRANSACTION_MSB    _u(26)
3983 #define USB_EP_RX_ERROR_EP13_TRANSACTION_LSB    _u(26)
3984 #define USB_EP_RX_ERROR_EP13_TRANSACTION_ACCESS "WC"
3985 // -----------------------------------------------------------------------------
3986 // Field       : USB_EP_RX_ERROR_EP12_SEQ
3987 #define USB_EP_RX_ERROR_EP12_SEQ_RESET  _u(0x0)
3988 #define USB_EP_RX_ERROR_EP12_SEQ_BITS   _u(0x02000000)
3989 #define USB_EP_RX_ERROR_EP12_SEQ_MSB    _u(25)
3990 #define USB_EP_RX_ERROR_EP12_SEQ_LSB    _u(25)
3991 #define USB_EP_RX_ERROR_EP12_SEQ_ACCESS "WC"
3992 // -----------------------------------------------------------------------------
3993 // Field       : USB_EP_RX_ERROR_EP12_TRANSACTION
3994 #define USB_EP_RX_ERROR_EP12_TRANSACTION_RESET  _u(0x0)
3995 #define USB_EP_RX_ERROR_EP12_TRANSACTION_BITS   _u(0x01000000)
3996 #define USB_EP_RX_ERROR_EP12_TRANSACTION_MSB    _u(24)
3997 #define USB_EP_RX_ERROR_EP12_TRANSACTION_LSB    _u(24)
3998 #define USB_EP_RX_ERROR_EP12_TRANSACTION_ACCESS "WC"
3999 // -----------------------------------------------------------------------------
4000 // Field       : USB_EP_RX_ERROR_EP11_SEQ
4001 #define USB_EP_RX_ERROR_EP11_SEQ_RESET  _u(0x0)
4002 #define USB_EP_RX_ERROR_EP11_SEQ_BITS   _u(0x00800000)
4003 #define USB_EP_RX_ERROR_EP11_SEQ_MSB    _u(23)
4004 #define USB_EP_RX_ERROR_EP11_SEQ_LSB    _u(23)
4005 #define USB_EP_RX_ERROR_EP11_SEQ_ACCESS "WC"
4006 // -----------------------------------------------------------------------------
4007 // Field       : USB_EP_RX_ERROR_EP11_TRANSACTION
4008 #define USB_EP_RX_ERROR_EP11_TRANSACTION_RESET  _u(0x0)
4009 #define USB_EP_RX_ERROR_EP11_TRANSACTION_BITS   _u(0x00400000)
4010 #define USB_EP_RX_ERROR_EP11_TRANSACTION_MSB    _u(22)
4011 #define USB_EP_RX_ERROR_EP11_TRANSACTION_LSB    _u(22)
4012 #define USB_EP_RX_ERROR_EP11_TRANSACTION_ACCESS "WC"
4013 // -----------------------------------------------------------------------------
4014 // Field       : USB_EP_RX_ERROR_EP10_SEQ
4015 #define USB_EP_RX_ERROR_EP10_SEQ_RESET  _u(0x0)
4016 #define USB_EP_RX_ERROR_EP10_SEQ_BITS   _u(0x00200000)
4017 #define USB_EP_RX_ERROR_EP10_SEQ_MSB    _u(21)
4018 #define USB_EP_RX_ERROR_EP10_SEQ_LSB    _u(21)
4019 #define USB_EP_RX_ERROR_EP10_SEQ_ACCESS "WC"
4020 // -----------------------------------------------------------------------------
4021 // Field       : USB_EP_RX_ERROR_EP10_TRANSACTION
4022 #define USB_EP_RX_ERROR_EP10_TRANSACTION_RESET  _u(0x0)
4023 #define USB_EP_RX_ERROR_EP10_TRANSACTION_BITS   _u(0x00100000)
4024 #define USB_EP_RX_ERROR_EP10_TRANSACTION_MSB    _u(20)
4025 #define USB_EP_RX_ERROR_EP10_TRANSACTION_LSB    _u(20)
4026 #define USB_EP_RX_ERROR_EP10_TRANSACTION_ACCESS "WC"
4027 // -----------------------------------------------------------------------------
4028 // Field       : USB_EP_RX_ERROR_EP9_SEQ
4029 #define USB_EP_RX_ERROR_EP9_SEQ_RESET  _u(0x0)
4030 #define USB_EP_RX_ERROR_EP9_SEQ_BITS   _u(0x00080000)
4031 #define USB_EP_RX_ERROR_EP9_SEQ_MSB    _u(19)
4032 #define USB_EP_RX_ERROR_EP9_SEQ_LSB    _u(19)
4033 #define USB_EP_RX_ERROR_EP9_SEQ_ACCESS "WC"
4034 // -----------------------------------------------------------------------------
4035 // Field       : USB_EP_RX_ERROR_EP9_TRANSACTION
4036 #define USB_EP_RX_ERROR_EP9_TRANSACTION_RESET  _u(0x0)
4037 #define USB_EP_RX_ERROR_EP9_TRANSACTION_BITS   _u(0x00040000)
4038 #define USB_EP_RX_ERROR_EP9_TRANSACTION_MSB    _u(18)
4039 #define USB_EP_RX_ERROR_EP9_TRANSACTION_LSB    _u(18)
4040 #define USB_EP_RX_ERROR_EP9_TRANSACTION_ACCESS "WC"
4041 // -----------------------------------------------------------------------------
4042 // Field       : USB_EP_RX_ERROR_EP8_SEQ
4043 #define USB_EP_RX_ERROR_EP8_SEQ_RESET  _u(0x0)
4044 #define USB_EP_RX_ERROR_EP8_SEQ_BITS   _u(0x00020000)
4045 #define USB_EP_RX_ERROR_EP8_SEQ_MSB    _u(17)
4046 #define USB_EP_RX_ERROR_EP8_SEQ_LSB    _u(17)
4047 #define USB_EP_RX_ERROR_EP8_SEQ_ACCESS "WC"
4048 // -----------------------------------------------------------------------------
4049 // Field       : USB_EP_RX_ERROR_EP8_TRANSACTION
4050 #define USB_EP_RX_ERROR_EP8_TRANSACTION_RESET  _u(0x0)
4051 #define USB_EP_RX_ERROR_EP8_TRANSACTION_BITS   _u(0x00010000)
4052 #define USB_EP_RX_ERROR_EP8_TRANSACTION_MSB    _u(16)
4053 #define USB_EP_RX_ERROR_EP8_TRANSACTION_LSB    _u(16)
4054 #define USB_EP_RX_ERROR_EP8_TRANSACTION_ACCESS "WC"
4055 // -----------------------------------------------------------------------------
4056 // Field       : USB_EP_RX_ERROR_EP7_SEQ
4057 #define USB_EP_RX_ERROR_EP7_SEQ_RESET  _u(0x0)
4058 #define USB_EP_RX_ERROR_EP7_SEQ_BITS   _u(0x00008000)
4059 #define USB_EP_RX_ERROR_EP7_SEQ_MSB    _u(15)
4060 #define USB_EP_RX_ERROR_EP7_SEQ_LSB    _u(15)
4061 #define USB_EP_RX_ERROR_EP7_SEQ_ACCESS "WC"
4062 // -----------------------------------------------------------------------------
4063 // Field       : USB_EP_RX_ERROR_EP7_TRANSACTION
4064 #define USB_EP_RX_ERROR_EP7_TRANSACTION_RESET  _u(0x0)
4065 #define USB_EP_RX_ERROR_EP7_TRANSACTION_BITS   _u(0x00004000)
4066 #define USB_EP_RX_ERROR_EP7_TRANSACTION_MSB    _u(14)
4067 #define USB_EP_RX_ERROR_EP7_TRANSACTION_LSB    _u(14)
4068 #define USB_EP_RX_ERROR_EP7_TRANSACTION_ACCESS "WC"
4069 // -----------------------------------------------------------------------------
4070 // Field       : USB_EP_RX_ERROR_EP6_SEQ
4071 #define USB_EP_RX_ERROR_EP6_SEQ_RESET  _u(0x0)
4072 #define USB_EP_RX_ERROR_EP6_SEQ_BITS   _u(0x00002000)
4073 #define USB_EP_RX_ERROR_EP6_SEQ_MSB    _u(13)
4074 #define USB_EP_RX_ERROR_EP6_SEQ_LSB    _u(13)
4075 #define USB_EP_RX_ERROR_EP6_SEQ_ACCESS "WC"
4076 // -----------------------------------------------------------------------------
4077 // Field       : USB_EP_RX_ERROR_EP6_TRANSACTION
4078 #define USB_EP_RX_ERROR_EP6_TRANSACTION_RESET  _u(0x0)
4079 #define USB_EP_RX_ERROR_EP6_TRANSACTION_BITS   _u(0x00001000)
4080 #define USB_EP_RX_ERROR_EP6_TRANSACTION_MSB    _u(12)
4081 #define USB_EP_RX_ERROR_EP6_TRANSACTION_LSB    _u(12)
4082 #define USB_EP_RX_ERROR_EP6_TRANSACTION_ACCESS "WC"
4083 // -----------------------------------------------------------------------------
4084 // Field       : USB_EP_RX_ERROR_EP5_SEQ
4085 #define USB_EP_RX_ERROR_EP5_SEQ_RESET  _u(0x0)
4086 #define USB_EP_RX_ERROR_EP5_SEQ_BITS   _u(0x00000800)
4087 #define USB_EP_RX_ERROR_EP5_SEQ_MSB    _u(11)
4088 #define USB_EP_RX_ERROR_EP5_SEQ_LSB    _u(11)
4089 #define USB_EP_RX_ERROR_EP5_SEQ_ACCESS "WC"
4090 // -----------------------------------------------------------------------------
4091 // Field       : USB_EP_RX_ERROR_EP5_TRANSACTION
4092 #define USB_EP_RX_ERROR_EP5_TRANSACTION_RESET  _u(0x0)
4093 #define USB_EP_RX_ERROR_EP5_TRANSACTION_BITS   _u(0x00000400)
4094 #define USB_EP_RX_ERROR_EP5_TRANSACTION_MSB    _u(10)
4095 #define USB_EP_RX_ERROR_EP5_TRANSACTION_LSB    _u(10)
4096 #define USB_EP_RX_ERROR_EP5_TRANSACTION_ACCESS "WC"
4097 // -----------------------------------------------------------------------------
4098 // Field       : USB_EP_RX_ERROR_EP4_SEQ
4099 #define USB_EP_RX_ERROR_EP4_SEQ_RESET  _u(0x0)
4100 #define USB_EP_RX_ERROR_EP4_SEQ_BITS   _u(0x00000200)
4101 #define USB_EP_RX_ERROR_EP4_SEQ_MSB    _u(9)
4102 #define USB_EP_RX_ERROR_EP4_SEQ_LSB    _u(9)
4103 #define USB_EP_RX_ERROR_EP4_SEQ_ACCESS "WC"
4104 // -----------------------------------------------------------------------------
4105 // Field       : USB_EP_RX_ERROR_EP4_TRANSACTION
4106 #define USB_EP_RX_ERROR_EP4_TRANSACTION_RESET  _u(0x0)
4107 #define USB_EP_RX_ERROR_EP4_TRANSACTION_BITS   _u(0x00000100)
4108 #define USB_EP_RX_ERROR_EP4_TRANSACTION_MSB    _u(8)
4109 #define USB_EP_RX_ERROR_EP4_TRANSACTION_LSB    _u(8)
4110 #define USB_EP_RX_ERROR_EP4_TRANSACTION_ACCESS "WC"
4111 // -----------------------------------------------------------------------------
4112 // Field       : USB_EP_RX_ERROR_EP3_SEQ
4113 #define USB_EP_RX_ERROR_EP3_SEQ_RESET  _u(0x0)
4114 #define USB_EP_RX_ERROR_EP3_SEQ_BITS   _u(0x00000080)
4115 #define USB_EP_RX_ERROR_EP3_SEQ_MSB    _u(7)
4116 #define USB_EP_RX_ERROR_EP3_SEQ_LSB    _u(7)
4117 #define USB_EP_RX_ERROR_EP3_SEQ_ACCESS "WC"
4118 // -----------------------------------------------------------------------------
4119 // Field       : USB_EP_RX_ERROR_EP3_TRANSACTION
4120 #define USB_EP_RX_ERROR_EP3_TRANSACTION_RESET  _u(0x0)
4121 #define USB_EP_RX_ERROR_EP3_TRANSACTION_BITS   _u(0x00000040)
4122 #define USB_EP_RX_ERROR_EP3_TRANSACTION_MSB    _u(6)
4123 #define USB_EP_RX_ERROR_EP3_TRANSACTION_LSB    _u(6)
4124 #define USB_EP_RX_ERROR_EP3_TRANSACTION_ACCESS "WC"
4125 // -----------------------------------------------------------------------------
4126 // Field       : USB_EP_RX_ERROR_EP2_SEQ
4127 #define USB_EP_RX_ERROR_EP2_SEQ_RESET  _u(0x0)
4128 #define USB_EP_RX_ERROR_EP2_SEQ_BITS   _u(0x00000020)
4129 #define USB_EP_RX_ERROR_EP2_SEQ_MSB    _u(5)
4130 #define USB_EP_RX_ERROR_EP2_SEQ_LSB    _u(5)
4131 #define USB_EP_RX_ERROR_EP2_SEQ_ACCESS "WC"
4132 // -----------------------------------------------------------------------------
4133 // Field       : USB_EP_RX_ERROR_EP2_TRANSACTION
4134 #define USB_EP_RX_ERROR_EP2_TRANSACTION_RESET  _u(0x0)
4135 #define USB_EP_RX_ERROR_EP2_TRANSACTION_BITS   _u(0x00000010)
4136 #define USB_EP_RX_ERROR_EP2_TRANSACTION_MSB    _u(4)
4137 #define USB_EP_RX_ERROR_EP2_TRANSACTION_LSB    _u(4)
4138 #define USB_EP_RX_ERROR_EP2_TRANSACTION_ACCESS "WC"
4139 // -----------------------------------------------------------------------------
4140 // Field       : USB_EP_RX_ERROR_EP1_SEQ
4141 #define USB_EP_RX_ERROR_EP1_SEQ_RESET  _u(0x0)
4142 #define USB_EP_RX_ERROR_EP1_SEQ_BITS   _u(0x00000008)
4143 #define USB_EP_RX_ERROR_EP1_SEQ_MSB    _u(3)
4144 #define USB_EP_RX_ERROR_EP1_SEQ_LSB    _u(3)
4145 #define USB_EP_RX_ERROR_EP1_SEQ_ACCESS "WC"
4146 // -----------------------------------------------------------------------------
4147 // Field       : USB_EP_RX_ERROR_EP1_TRANSACTION
4148 #define USB_EP_RX_ERROR_EP1_TRANSACTION_RESET  _u(0x0)
4149 #define USB_EP_RX_ERROR_EP1_TRANSACTION_BITS   _u(0x00000004)
4150 #define USB_EP_RX_ERROR_EP1_TRANSACTION_MSB    _u(2)
4151 #define USB_EP_RX_ERROR_EP1_TRANSACTION_LSB    _u(2)
4152 #define USB_EP_RX_ERROR_EP1_TRANSACTION_ACCESS "WC"
4153 // -----------------------------------------------------------------------------
4154 // Field       : USB_EP_RX_ERROR_EP0_SEQ
4155 #define USB_EP_RX_ERROR_EP0_SEQ_RESET  _u(0x0)
4156 #define USB_EP_RX_ERROR_EP0_SEQ_BITS   _u(0x00000002)
4157 #define USB_EP_RX_ERROR_EP0_SEQ_MSB    _u(1)
4158 #define USB_EP_RX_ERROR_EP0_SEQ_LSB    _u(1)
4159 #define USB_EP_RX_ERROR_EP0_SEQ_ACCESS "WC"
4160 // -----------------------------------------------------------------------------
4161 // Field       : USB_EP_RX_ERROR_EP0_TRANSACTION
4162 #define USB_EP_RX_ERROR_EP0_TRANSACTION_RESET  _u(0x0)
4163 #define USB_EP_RX_ERROR_EP0_TRANSACTION_BITS   _u(0x00000001)
4164 #define USB_EP_RX_ERROR_EP0_TRANSACTION_MSB    _u(0)
4165 #define USB_EP_RX_ERROR_EP0_TRANSACTION_LSB    _u(0)
4166 #define USB_EP_RX_ERROR_EP0_TRANSACTION_ACCESS "WC"
4167 // =============================================================================
4168 // Register    : USB_DEV_SM_WATCHDOG
4169 // Description : Watchdog that forces the device state machine to idle and
4170 //               raises an interrupt if the device stays in a state that isn't
4171 //               idle for the configured limit. The counter is reset on every
4172 //               state transition.
4173 //               Set limit while enable is low and then set the enable.
4174 #define USB_DEV_SM_WATCHDOG_OFFSET _u(0x00000114)
4175 #define USB_DEV_SM_WATCHDOG_BITS   _u(0x001fffff)
4176 #define USB_DEV_SM_WATCHDOG_RESET  _u(0x00000000)
4177 // -----------------------------------------------------------------------------
4178 // Field       : USB_DEV_SM_WATCHDOG_FIRED
4179 #define USB_DEV_SM_WATCHDOG_FIRED_RESET  _u(0x0)
4180 #define USB_DEV_SM_WATCHDOG_FIRED_BITS   _u(0x00100000)
4181 #define USB_DEV_SM_WATCHDOG_FIRED_MSB    _u(20)
4182 #define USB_DEV_SM_WATCHDOG_FIRED_LSB    _u(20)
4183 #define USB_DEV_SM_WATCHDOG_FIRED_ACCESS "WC"
4184 // -----------------------------------------------------------------------------
4185 // Field       : USB_DEV_SM_WATCHDOG_RESET
4186 // Description : Set to 1 to forcibly reset the device state machine on watchdog
4187 //               expiry
4188 #define USB_DEV_SM_WATCHDOG_RESET_RESET  _u(0x0)
4189 #define USB_DEV_SM_WATCHDOG_RESET_BITS   _u(0x00080000)
4190 #define USB_DEV_SM_WATCHDOG_RESET_MSB    _u(19)
4191 #define USB_DEV_SM_WATCHDOG_RESET_LSB    _u(19)
4192 #define USB_DEV_SM_WATCHDOG_RESET_ACCESS "RW"
4193 // -----------------------------------------------------------------------------
4194 // Field       : USB_DEV_SM_WATCHDOG_ENABLE
4195 #define USB_DEV_SM_WATCHDOG_ENABLE_RESET  _u(0x0)
4196 #define USB_DEV_SM_WATCHDOG_ENABLE_BITS   _u(0x00040000)
4197 #define USB_DEV_SM_WATCHDOG_ENABLE_MSB    _u(18)
4198 #define USB_DEV_SM_WATCHDOG_ENABLE_LSB    _u(18)
4199 #define USB_DEV_SM_WATCHDOG_ENABLE_ACCESS "RW"
4200 // -----------------------------------------------------------------------------
4201 // Field       : USB_DEV_SM_WATCHDOG_LIMIT
4202 #define USB_DEV_SM_WATCHDOG_LIMIT_RESET  _u(0x00000)
4203 #define USB_DEV_SM_WATCHDOG_LIMIT_BITS   _u(0x0003ffff)
4204 #define USB_DEV_SM_WATCHDOG_LIMIT_MSB    _u(17)
4205 #define USB_DEV_SM_WATCHDOG_LIMIT_LSB    _u(0)
4206 #define USB_DEV_SM_WATCHDOG_LIMIT_ACCESS "RW"
4207 // =============================================================================
4208 #endif // _HARDWARE_REGS_USB_H
4209