src/platform/STM32/timer_stm32f4xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "platform.h"
  22
  23 #ifdef USE_TIMER
  24
  25 #include "common/utils.h"
  26
  27 #include "drivers/dma.h"
  28 #include "drivers/io.h"
  29 #include "timer_def.h"
  30
  31 #include "stm32f4xx.h"
  32 #include "drivers/rcc.h"
  33 #include "drivers/timer.h"
  34
  35 const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
  36     { .TIMx = TIM1,  .rcc = RCC_APB2(TIM1),  .inputIrq = TIM1_CC_IRQn},
  37     { .TIMx = TIM2,  .rcc = RCC_APB1(TIM2),  .inputIrq = TIM2_IRQn},
  38     { .TIMx = TIM3,  .rcc = RCC_APB1(TIM3),  .inputIrq = TIM3_IRQn},
  39     { .TIMx = TIM4,  .rcc = RCC_APB1(TIM4),  .inputIrq = TIM4_IRQn},
  40     { .TIMx = TIM5,  .rcc = RCC_APB1(TIM5),  .inputIrq = TIM5_IRQn},
  41     { .TIMx = TIM6,  .rcc = RCC_APB1(TIM6),  .inputIrq = 0},
  42     { .TIMx = TIM7,  .rcc = RCC_APB1(TIM7),  .inputIrq = 0},
  43 #if defined(STM32F446xx)
  44     { .TIMx = TIM8,  .rcc = RCC_APB2(TIM8),  .inputIrq = 0},
  45 #elif !defined(STM32F411xE)
  46     { .TIMx = TIM8,  .rcc = RCC_APB2(TIM8),  .inputIrq = TIM8_CC_IRQn},
  47 #endif
  48     { .TIMx = TIM9,  .rcc = RCC_APB2(TIM9),  .inputIrq = TIM1_BRK_TIM9_IRQn},
  49     { .TIMx = TIM10, .rcc = RCC_APB2(TIM10), .inputIrq = TIM1_UP_TIM10_IRQn},
  50     { .TIMx = TIM11, .rcc = RCC_APB2(TIM11), .inputIrq = TIM1_TRG_COM_TIM11_IRQn},
  51 #ifndef STM32F411xE
  52     { .TIMx = TIM12, .rcc = RCC_APB1(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
  53     { .TIMx = TIM13, .rcc = RCC_APB1(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
  54     { .TIMx = TIM14, .rcc = RCC_APB1(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
  55 #endif
  56 };
  57
  58 #if defined(USE_TIMER_MGMT)
  59 const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
  60     // Auto-generated from 'timer_def.h'
  61 //PORTA
  62     DEF_TIM(TIM2, CH1,  PA0, 0, 0),
  63     DEF_TIM(TIM2, CH2,  PA1, 0, 0),
  64     DEF_TIM(TIM2, CH3,  PA2, 0, 0),
  65     DEF_TIM(TIM2, CH4,  PA3, 0, 0),
  66     DEF_TIM(TIM2, CH1,  PA5, 0, 0),
  67     DEF_TIM(TIM1, CH1N, PA7, 0, 0),
  68     DEF_TIM(TIM1, CH1,  PA8, 0, 0),
  69     DEF_TIM(TIM1, CH2,  PA9, 0, 0),
  70     DEF_TIM(TIM1, CH3,  PA10, 0, 0),
  71     DEF_TIM(TIM1, CH1N, PA11, 0, 0),
  72     DEF_TIM(TIM2, CH1,  PA15, 0, 0),
  73
  74     DEF_TIM(TIM5, CH1,  PA0, 0, 0),
  75     DEF_TIM(TIM5, CH2,  PA1, 0, 0),
  76     DEF_TIM(TIM5, CH3,  PA2, 0, 0),
  77     DEF_TIM(TIM5, CH4,  PA3, 0, 0),
  78     DEF_TIM(TIM3, CH1,  PA6, 0, 0),
  79     DEF_TIM(TIM3, CH2,  PA7, 0, 0),
  80
  81     DEF_TIM(TIM9, CH1,  PA2, 0, 0),
  82     DEF_TIM(TIM9, CH2,  PA3, 0, 0),
  83 #if !defined(STM32F411xE)
  84     DEF_TIM(TIM8, CH1N, PA5, 0, 0),
  85     DEF_TIM(TIM8, CH1N, PA7, 0, 0),
  86
  87     DEF_TIM(TIM13, CH1, PA6, 0, 0),
  88     DEF_TIM(TIM14, CH1, PA7, 0, 0),
  89 #endif
  90
  91 //PORTB
  92     DEF_TIM(TIM1, CH2N, PB0, 0, 0),
  93     DEF_TIM(TIM1, CH3N, PB1, 0, 0),
  94     DEF_TIM(TIM2, CH2,  PB3, 0, 0),
  95     DEF_TIM(TIM2, CH3,  PB10, 0, 0),
  96     DEF_TIM(TIM2, CH4,  PB11, 0, 0),
  97     DEF_TIM(TIM1, CH1N, PB13, 0, 0),
  98     DEF_TIM(TIM1, CH2N, PB14, 0, 0),
  99     DEF_TIM(TIM1, CH3N, PB15, 0, 0),
 100
 101     DEF_TIM(TIM3, CH3,  PB0, 0, 0),
 102     DEF_TIM(TIM3, CH4,  PB1, 0, 0),
 103     DEF_TIM(TIM3, CH1,  PB4, 0, 0),
 104     DEF_TIM(TIM3, CH2,  PB5, 0, 0),
 105     DEF_TIM(TIM4, CH1,  PB6, 0, 0),
 106     DEF_TIM(TIM4, CH2,  PB7, 0, 0),
 107     DEF_TIM(TIM4, CH3,  PB8, 0, 0),
 108     DEF_TIM(TIM4, CH4,  PB9, 0, 0),
 109
 110 #if !defined(STM32F411xE)
 111     DEF_TIM(TIM8, CH2N, PB0, 0, 0),
 112     DEF_TIM(TIM8, CH3N, PB1, 0, 0),
 113 #endif
 114     DEF_TIM(TIM10, CH1, PB8, 0, 0),
 115     DEF_TIM(TIM11, CH1, PB9, 0, 0),
 116 #if !defined(STM32F411xE)
 117     DEF_TIM(TIM8, CH2N, PB14, 0, 0),
 118     DEF_TIM(TIM8, CH3N, PB15, 0, 0),
 119
 120     DEF_TIM(TIM12, CH1, PB14, 0, 0),
 121     DEF_TIM(TIM12, CH2, PB15, 0, 0),
 122 #endif
 123
 124 //PORTC
 125     DEF_TIM(TIM3, CH1, PC6, 0, 0),
 126     DEF_TIM(TIM3, CH2, PC7, 0, 0),
 127     DEF_TIM(TIM3, CH3, PC8, 0, 0),
 128     DEF_TIM(TIM3, CH4, PC9, 0, 0),
 129
 130 #if !defined(STM32F411xE)
 131     DEF_TIM(TIM8, CH1, PC6, 0, 0),
 132     DEF_TIM(TIM8, CH2, PC7, 0, 0),
 133     DEF_TIM(TIM8, CH3, PC8, 0, 0),
 134     DEF_TIM(TIM8, CH4, PC9, 0, 0),
 135 #endif
 136
 137 //PORTD
 138     DEF_TIM(TIM4, CH1, PD12, 0, 0),
 139     DEF_TIM(TIM4, CH2, PD13, 0, 0),
 140     DEF_TIM(TIM4, CH3, PD14, 0, 0),
 141     DEF_TIM(TIM4, CH4, PD15, 0, 0),
 142
 143 //PORTE
 144     DEF_TIM(TIM1, CH1N, PE8, 0, 0),
 145     DEF_TIM(TIM1, CH1,  PE9, 0, 0),
 146     DEF_TIM(TIM1, CH2N, PE10, 0, 0),
 147     DEF_TIM(TIM1, CH2,  PE11, 0, 0),
 148     DEF_TIM(TIM1, CH3N, PE12, 0, 0),
 149     DEF_TIM(TIM1, CH3,  PE13, 0, 0),
 150     DEF_TIM(TIM1, CH4,  PE14, 0, 0),
 151
 152     DEF_TIM(TIM9, CH1,  PE5, 0, 0),
 153     DEF_TIM(TIM9, CH2,  PE6, 0, 0),
 154
 155 //PORTF
 156 #if !defined(STM32F411xE)
 157     DEF_TIM(TIM10, CH1, PF6, 0, 0),
 158     DEF_TIM(TIM11, CH1, PF7, 0, 0),
 159 #endif
 160
 161 //PORTH
 162 // Port H is not available for LPQFP-100 or 144 package
 163 //    DEF_TIM(TIM5, CH1, PH10, 0, 0),
 164 //    DEF_TIM(TIM5, CH2, PH11, 0, 0),
 165 //    DEF_TIM(TIM5, CH3, PH12, 0, 0),
 166 //
 167 //#if !defined(STM32F411xE)
 168 //    DEF_TIM(TIM8, CH1N, PH13, 0, 0),
 169 //    DEF_TIM(TIM8, CH2N, PH14, 0, 0),
 170 //    DEF_TIM(TIM8, CH3N, PH15, 0, 0),
 171 //
 172 //    DEF_TIM(TIM12, CH1, PH6, 0, 0),
 173 //    DEF_TIM(TIM12, CH2, PH9, 0, 0),
 174 //#endif
 175
 176 //PORTI
 177 // Port I is not available for LPQFP-100 or 144 package
 178 //    DEF_TIM(TIM5, CH4, PI0, 0, 0),
 179 //
 180 //#if !defined(STM32F411xE)
 181 //    DEF_TIM(TIM8, CH4, PI2, 0, 0),
 182 //    DEF_TIM(TIM8, CH1, PI5, 0, 0),
 183 //    DEF_TIM(TIM8, CH2, PI6, 0, 0),
 184 //    DEF_TIM(TIM8, CH3, PI7, 0, 0),
 185 //#endif
 186 };
 187 #endif
 188
 189 /*
 190     need a mapping from dma and timers to pins, and the values should all be set here to the dmaMotors array.
 191     this mapping could be used for both these motors and for led strip.
 192
 193     only certain pins have OC output (already used in normal PWM et al) but then
 194     there are only certain DMA streams/channels available for certain timers and channels.
 195      *** (this may highlight some hardware limitations on some targets) ***
 196
 197     DMA1
 198
 199     Channel Stream0     Stream1     Stream2     Stream3     Stream4     Stream5     Stream6     Stream7
 200     0
 201     1
 202     2       TIM4_CH1                            TIM4_CH2                                        TIM4_CH3
 203     3                   TIM2_CH3                                        TIM2_CH1    TIM2_CH1    TIM2_CH4
 204                                                                                     TIM2_CH4
 205     4
 206     5                               TIM3_CH4                TIM3_CH1    TIM3_CH2                TIM3_CH3
 207     6       TIM5_CH3    TIM5_CH4    TIM5_CH1    TIM5_CH4    TIM5_CH2
 208     7
 209
 210     DMA2
 211
 212     Channel Stream0     Stream1     Stream2     Stream3     Stream4     Stream5     Stream6     Stream7
 213     0                               TIM8_CH1                                        TIM1_CH1
 214                                     TIM8_CH2                                        TIM1_CH2
 215                                     TIM8_CH3                                        TIM1_CH3
 216     1
 217     2
 218     3
 219     4
 220     5
 221     6       TIM1_CH1    TIM1_CH2    TIM1_CH1                TIM1_CH4                TIM1_CH3
 222     7                   TIM8_CH1    TIM8_CH2    TIM8_CH3                                        TIM8_CH4
 223 */
 224
 225 uint32_t timerClock(const TIM_TypeDef *tim)
 226 {
 227 #if defined(STM32F411xE)
 228     UNUSED(tim);
 229     return SystemCoreClock;
 230 #elif defined(STM32F40_41xxx) || defined(STM32F446xx)
 231     if (tim == TIM8 || tim == TIM1 || tim == TIM9 || tim == TIM10 || tim == TIM11) {
 232         return SystemCoreClock;
 233     } else {
 234         return SystemCoreClock / 2;
 235     }
 236 #else
 237     #error "No timer clock defined correctly for MCU"
 238 #endif
 239 }
 240 #endif