opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2024 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 typedef struct instr_info instr_info;
  43
  44 static bool dofloat (instr_info *, int);
  45 static int putop (instr_info *, const char *, int);
  46 static void oappend_with_style (instr_info *, const char *,
  47                                 enum disassembler_style);
  48
  49 static bool OP_E (instr_info *, int, int);
  50 static bool OP_E_memory (instr_info *, int, int);
  51 static bool OP_indirE (instr_info *, int, int);
  52 static bool OP_G (instr_info *, int, int);
  53 static bool OP_ST (instr_info *, int, int);
  54 static bool OP_STi (instr_info *, int, int);
  55 static bool OP_Skip_MODRM (instr_info *, int, int);
  56 static bool OP_REG (instr_info *, int, int);
  57 static bool OP_IMREG (instr_info *, int, int);
  58 static bool OP_I (instr_info *, int, int);
  59 static bool OP_I64 (instr_info *, int, int);
  60 static bool OP_sI (instr_info *, int, int);
  61 static bool OP_J (instr_info *, int, int);
  62 static bool OP_SEG (instr_info *, int, int);
  63 static bool OP_DIR (instr_info *, int, int);
  64 static bool OP_OFF (instr_info *, int, int);
  65 static bool OP_OFF64 (instr_info *, int, int);
  66 static bool OP_ESreg (instr_info *, int, int);
  67 static bool OP_DSreg (instr_info *, int, int);
  68 static bool OP_C (instr_info *, int, int);
  69 static bool OP_D (instr_info *, int, int);
  70 static bool OP_T (instr_info *, int, int);
  71 static bool OP_MMX (instr_info *, int, int);
  72 static bool OP_XMM (instr_info *, int, int);
  73 static bool OP_EM (instr_info *, int, int);
  74 static bool OP_EX (instr_info *, int, int);
  75 static bool OP_EMC (instr_info *, int,int);
  76 static bool OP_MXC (instr_info *, int,int);
  77 static bool OP_R (instr_info *, int, int);
  78 static bool OP_M (instr_info *, int, int);
  79 static bool OP_VEX (instr_info *, int, int);
  80 static bool OP_VexR (instr_info *, int, int);
  81 static bool OP_VexW (instr_info *, int, int);
  82 static bool OP_Rounding (instr_info *, int, int);
  83 static bool OP_REG_VexI4 (instr_info *, int, int);
  84 static bool OP_VexI4 (instr_info *, int, int);
  85 static bool OP_0f07 (instr_info *, int, int);
  86 static bool OP_Monitor (instr_info *, int, int);
  87 static bool OP_Mwait (instr_info *, int, int);
  88
  89 static bool PCLMUL_Fixup (instr_info *, int, int);
  90 static bool VPCMP_Fixup (instr_info *, int, int);
  91 static bool VPCOM_Fixup (instr_info *, int, int);
  92 static bool NOP_Fixup (instr_info *, int, int);
  93 static bool MONTMUL_Fixup (instr_info *, int, int);
  94 static bool OP_3DNowSuffix (instr_info *, int, int);
  95 static bool CMP_Fixup (instr_info *, int, int);
  96 static bool REP_Fixup (instr_info *, int, int);
  97 static bool SEP_Fixup (instr_info *, int, int);
  98 static bool BND_Fixup (instr_info *, int, int);
  99 static bool NOTRACK_Fixup (instr_info *, int, int);
 100 static bool HLE_Fixup1 (instr_info *, int, int);
 101 static bool HLE_Fixup2 (instr_info *, int, int);
 102 static bool HLE_Fixup3 (instr_info *, int, int);
 103 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
 104 static bool XMM_Fixup (instr_info *, int, int);
 105 static bool FXSAVE_Fixup (instr_info *, int, int);
 106 static bool MOVSXD_Fixup (instr_info *, int, int);
 107 static bool DistinctDest_Fixup (instr_info *, int, int);
 108 static bool PREFETCHI_Fixup (instr_info *, int, int);
 109 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
 110 static bool JMPABS_Fixup (instr_info *, int, int);
 111 static bool CFCMOV_Fixup (instr_info *, int, int);
 112
 113 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
 114                                                 enum disassembler_style,
 115                                                 const char *, ...);
 116
 117 /* This character is used to encode style information within the output
 118    buffers.  See oappend_insert_style for more details.  */
 119 #define STYLE_MARKER_CHAR '\002'
 120
 121 /* The maximum operand buffer size.  */
 122 #define MAX_OPERAND_BUFFER_SIZE 128
 123
 124 enum address_mode
 125 {
 126   mode_16bit,
 127   mode_32bit,
 128   mode_64bit
 129 };
 130
 131 static const char *prefix_name (enum address_mode, uint8_t, int);
 132
 133 enum x86_64_isa
 134 {
 135   amd64 = 1,
 136   intel64
 137 };
 138
 139 enum evex_type
 140 {
 141   evex_default = 0,
 142   evex_from_legacy,
 143   evex_from_vex,
 144 };
 145
 146 struct instr_info
 147 {
 148   enum address_mode address_mode;
 149
 150   /* Flags for the prefixes for the current instruction.  See below.  */
 151   int prefixes;
 152
 153   /* REX prefix the current instruction.  See below.  */
 154   uint8_t rex;
 155   /* Bits of REX we've already used.  */
 156   uint8_t rex_used;
 157
 158   /* Record W R4 X4 B4 bits for rex2.  */
 159   unsigned char rex2;
 160   /* Bits of rex2 we've already used.  */
 161   unsigned char rex2_used;
 162   unsigned char rex2_payload;
 163
 164   bool need_modrm;
 165   unsigned char condition_code;
 166   unsigned char need_vex;
 167   bool has_sib;
 168
 169   /* Flags for ins->prefixes which we somehow handled when printing the
 170      current instruction.  */
 171   int used_prefixes;
 172
 173   /* Flags for EVEX bits which we somehow handled when printing the
 174      current instruction.  */
 175   int evex_used;
 176
 177   char obuf[MAX_OPERAND_BUFFER_SIZE];
 178   char *obufp;
 179   char *mnemonicendp;
 180   const uint8_t *start_codep;
 181   uint8_t *codep;
 182   const uint8_t *end_codep;
 183   unsigned char nr_prefixes;
 184   signed char last_lock_prefix;
 185   signed char last_repz_prefix;
 186   signed char last_repnz_prefix;
 187   signed char last_data_prefix;
 188   signed char last_addr_prefix;
 189   signed char last_rex_prefix;
 190   signed char last_rex2_prefix;
 191   signed char last_seg_prefix;
 192   signed char fwait_prefix;
 193   /* The active segment register prefix.  */
 194   unsigned char active_seg_prefix;
 195
 196 #define MAX_CODE_LENGTH 15
 197   /* We can up to 14 ins->prefixes since the maximum instruction length is
 198      15bytes.  */
 199   uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
 200   disassemble_info *info;
 201
 202   struct
 203   {
 204     int mod;
 205     int reg;
 206     int rm;
 207   }
 208   modrm;
 209
 210   struct
 211   {
 212     int scale;
 213     int index;
 214     int base;
 215   }
 216   sib;
 217
 218   struct
 219   {
 220     int register_specifier;
 221     int length;
 222     int prefix;
 223     int mask_register_specifier;
 224     int scc;
 225     int ll;
 226     bool w;
 227     bool evex;
 228     bool v;
 229     bool zeroing;
 230     bool b;
 231     bool no_broadcast;
 232     bool nf;
 233     bool u;
 234   }
 235   vex;
 236
 237 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b.  */
 238 #define nd b
 239
 240   enum evex_type evex_type;
 241
 242   /* Remember if the current op is a jump instruction.  */
 243   bool op_is_jump;
 244
 245   bool two_source_ops;
 246
 247   /* Record whether EVEX masking is used incorrectly.  */
 248   bool illegal_masking;
 249
 250   /* Record whether the modrm byte has been skipped.  */
 251   bool has_skipped_modrm;
 252
 253   unsigned char op_ad;
 254   signed char op_index[MAX_OPERANDS];
 255   bool op_riprel[MAX_OPERANDS];
 256   char *op_out[MAX_OPERANDS];
 257   bfd_vma op_address[MAX_OPERANDS];
 258   bfd_vma start_pc;
 259
 260   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 261    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 262    *   section of the "Virtual 8086 Mode" chapter.)
 263    * 'pc' should be the address of this instruction, it will
 264    *   be used to print the target address if this is a relative jump or call
 265    * The function returns the length of this instruction in bytes.
 266    */
 267   char intel_syntax;
 268   bool intel_mnemonic;
 269   char open_char;
 270   char close_char;
 271   char separator_char;
 272   char scale_char;
 273
 274   enum x86_64_isa isa64;
 275 };
 276
 277 struct dis_private {
 278   bfd_vma insn_start;
 279   int orig_sizeflag;
 280
 281   /* Indexes first byte not fetched.  */
 282   unsigned int fetched;
 283   uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
 284 };
 285
 286 /* Mark parts used in the REX prefix.  When we are testing for
 287    empty prefix (for 8bit register REX extension), just mask it
 288    out.  Otherwise test for REX bit is excuse for existence of REX
 289    only in case value is nonzero.  */
 290 #define USED_REX(value)                                 \
 291   {                                                     \
 292     if (value)                                          \
 293       {                                                 \
 294         if (ins->rex & value)                           \
 295           ins->rex_used |= (value) | REX_OPCODE;        \
 296         if (ins->rex2 & value)                          \
 297           {                                             \
 298             ins->rex2_used |= (value);                  \
 299             ins->rex_used |= REX_OPCODE;                \
 300           }                                             \
 301       }                                                 \
 302     else                                                \
 303       ins->rex_used |= REX_OPCODE;                      \
 304   }
 305
 306
 307 #define EVEX_b_used 1
 308 #define EVEX_len_used 2
 309
 310
 311 /* {rex2} is not printed when the REX2_SPECIAL is set.  */
 312 #define REX2_SPECIAL 16
 313
 314 /* Flags stored in PREFIXES.  */
 315 #define PREFIX_REPZ 1
 316 #define PREFIX_REPNZ 2
 317 #define PREFIX_CS 4
 318 #define PREFIX_SS 8
 319 #define PREFIX_DS 0x10
 320 #define PREFIX_ES 0x20
 321 #define PREFIX_FS 0x40
 322 #define PREFIX_GS 0x80
 323 #define PREFIX_LOCK 0x100
 324 #define PREFIX_DATA 0x200
 325 #define PREFIX_ADDR 0x400
 326 #define PREFIX_FWAIT 0x800
 327 #define PREFIX_REX2 0x1000
 328 #define PREFIX_NP_OR_DATA 0x2000
 329 #define NO_PREFIX   0x4000
 330
 331 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 332    to ADDR (exclusive) are valid.  Returns true for success, false
 333    on error.  */
 334 static bool
 335 fetch_code (struct disassemble_info *info, const uint8_t *until)
 336 {
 337   int status = -1;
 338   struct dis_private *priv = info->private_data;
 339   bfd_vma start = priv->insn_start + priv->fetched;
 340   uint8_t *fetch_end = priv->the_buffer + priv->fetched;
 341   ptrdiff_t needed = until - fetch_end;
 342
 343   if (needed <= 0)
 344     return true;
 345
 346   if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
 347     status = (*info->read_memory_func) (start, fetch_end, needed, info);
 348   if (status != 0)
 349     {
 350       /* If we did manage to read at least one byte, then
 351          print_insn_i386 will do something sensible.  Otherwise, print
 352          an error.  We do that here because this is where we know
 353          STATUS.  */
 354       if (!priv->fetched)
 355         (*info->memory_error_func) (status, start, info);
 356       return false;
 357     }
 358
 359   priv->fetched += needed;
 360   return true;
 361 }
 362
 363 static bool
 364 fetch_modrm (instr_info *ins)
 365 {
 366   if (!fetch_code (ins->info, ins->codep + 1))
 367     return false;
 368
 369   ins->modrm.mod = (*ins->codep >> 6) & 3;
 370   ins->modrm.reg = (*ins->codep >> 3) & 7;
 371   ins->modrm.rm = *ins->codep & 7;
 372
 373   return true;
 374 }
 375
 376 static int
 377 fetch_error (const instr_info *ins)
 378 {
 379   /* Getting here means we tried for data but didn't get it.  That
 380      means we have an incomplete instruction of some sort.  Just
 381      print the first byte as a prefix or a .byte pseudo-op.  */
 382   const struct dis_private *priv = ins->info->private_data;
 383   const char *name = NULL;
 384
 385   if (ins->codep <= priv->the_buffer)
 386     return -1;
 387
 388   if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
 389     name = prefix_name (ins->address_mode, priv->the_buffer[0],
 390                         priv->orig_sizeflag);
 391   if (name != NULL)
 392     i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
 393   else
 394     {
 395       /* Just print the first byte as a .byte instruction.  */
 396       i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
 397       i386_dis_printf (ins->info, dis_style_immediate, "%#x",
 398                        (unsigned int) priv->the_buffer[0]);
 399     }
 400
 401   return 1;
 402 }
 403
 404 /* Possible values for prefix requirement.  */
 405 #define PREFIX_IGNORED_SHIFT    16
 406 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 407 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 408 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 409 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 410 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 411 #define PREFIX_REX2_ILLEGAL     (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
 412
 413 /* Opcode prefixes.  */
 414 #define PREFIX_OPCODE           (PREFIX_REPZ \
 415                                  | PREFIX_REPNZ \
 416                                  | PREFIX_DATA)
 417
 418 /* Prefixes ignored.  */
 419 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 420                                  | PREFIX_IGNORED_REPNZ \
 421                                  | PREFIX_IGNORED_DATA)
 422
 423 #define XX { NULL, 0 }
 424 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 425
 426 #define Eb { OP_E, b_mode }
 427 #define Ebnd { OP_E, bnd_mode }
 428 #define EbS { OP_E, b_swap_mode }
 429 #define EbndS { OP_E, bnd_swap_mode }
 430 #define Ev { OP_E, v_mode }
 431 #define Eva { OP_E, va_mode }
 432 #define Ev_bnd { OP_E, v_bnd_mode }
 433 #define EvS { OP_E, v_swap_mode }
 434 #define Ed { OP_E, d_mode }
 435 #define Edq { OP_E, dq_mode }
 436 #define Edb { OP_E, db_mode }
 437 #define Edw { OP_E, dw_mode }
 438 #define Eq { OP_E, q_mode }
 439 #define indirEv { OP_indirE, indir_v_mode }
 440 #define indirEp { OP_indirE, f_mode }
 441 #define stackEv { OP_E, stack_v_mode }
 442 #define Em { OP_E, m_mode }
 443 #define Ew { OP_E, w_mode }
 444 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 445 #define Ma { OP_M, a_mode }
 446 #define Mb { OP_M, b_mode }
 447 #define Md { OP_M, d_mode }
 448 #define Mdq { OP_M, dq_mode }
 449 #define Mo { OP_M, o_mode }
 450 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 451 #define Mq { OP_M, q_mode }
 452 #define Mv { OP_M, v_mode }
 453 #define Mv_bnd { OP_M, v_bndmk_mode }
 454 #define Mw { OP_M, w_mode }
 455 #define Mx { OP_M, x_mode }
 456 #define Mxmm { OP_M, xmm_mode }
 457 #define Mymm { OP_M, ymm_mode }
 458 #define Gb { OP_G, b_mode }
 459 #define Gbnd { OP_G, bnd_mode }
 460 #define Gv { OP_G, v_mode }
 461 #define Gd { OP_G, d_mode }
 462 #define Gdq { OP_G, dq_mode }
 463 #define Gq { OP_G, q_mode }
 464 #define Gm { OP_G, m_mode }
 465 #define Gva { OP_G, va_mode }
 466 #define Gw { OP_G, w_mode }
 467 #define Ib { OP_I, b_mode }
 468 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 469 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 470 #define Iv { OP_I, v_mode }
 471 #define sIv { OP_sI, v_mode }
 472 #define Iv64 { OP_I64, v_mode }
 473 #define Id { OP_I, d_mode }
 474 #define Iw { OP_I, w_mode }
 475 #define I1 { OP_I, const_1_mode }
 476 #define Jb { OP_J, b_mode }
 477 #define Jv { OP_J, v_mode }
 478 #define Jdqw { OP_J, dqw_mode }
 479 #define Cm { OP_C, m_mode }
 480 #define Dm { OP_D, m_mode }
 481 #define Td { OP_T, d_mode }
 482 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 483
 484 #define RMeAX { OP_REG, eAX_reg }
 485 #define RMeBX { OP_REG, eBX_reg }
 486 #define RMeCX { OP_REG, eCX_reg }
 487 #define RMeDX { OP_REG, eDX_reg }
 488 #define RMeSP { OP_REG, eSP_reg }
 489 #define RMeBP { OP_REG, eBP_reg }
 490 #define RMeSI { OP_REG, eSI_reg }
 491 #define RMeDI { OP_REG, eDI_reg }
 492 #define RMrAX { OP_REG, rAX_reg }
 493 #define RMrBX { OP_REG, rBX_reg }
 494 #define RMrCX { OP_REG, rCX_reg }
 495 #define RMrDX { OP_REG, rDX_reg }
 496 #define RMrSP { OP_REG, rSP_reg }
 497 #define RMrBP { OP_REG, rBP_reg }
 498 #define RMrSI { OP_REG, rSI_reg }
 499 #define RMrDI { OP_REG, rDI_reg }
 500 #define RMAL { OP_REG, al_reg }
 501 #define RMCL { OP_REG, cl_reg }
 502 #define RMDL { OP_REG, dl_reg }
 503 #define RMBL { OP_REG, bl_reg }
 504 #define RMAH { OP_REG, ah_reg }
 505 #define RMCH { OP_REG, ch_reg }
 506 #define RMDH { OP_REG, dh_reg }
 507 #define RMBH { OP_REG, bh_reg }
 508 #define RMAX { OP_REG, ax_reg }
 509 #define RMDX { OP_REG, dx_reg }
 510
 511 #define eAX { OP_IMREG, eAX_reg }
 512 #define AL { OP_IMREG, al_reg }
 513 #define CL { OP_IMREG, cl_reg }
 514 #define zAX { OP_IMREG, z_mode_ax_reg }
 515 #define indirDX { OP_IMREG, indir_dx_reg }
 516
 517 #define Sw { OP_SEG, w_mode }
 518 #define Sv { OP_SEG, v_mode }
 519 #define Ap { OP_DIR, 0 }
 520 #define Ob { OP_OFF64, b_mode }
 521 #define Ov { OP_OFF64, v_mode }
 522 #define Xb { OP_DSreg, eSI_reg }
 523 #define Xv { OP_DSreg, eSI_reg }
 524 #define Xz { OP_DSreg, eSI_reg }
 525 #define Yb { OP_ESreg, eDI_reg }
 526 #define Yv { OP_ESreg, eDI_reg }
 527 #define DSBX { OP_DSreg, eBX_reg }
 528
 529 #define es { OP_REG, es_reg }
 530 #define ss { OP_REG, ss_reg }
 531 #define cs { OP_REG, cs_reg }
 532 #define ds { OP_REG, ds_reg }
 533 #define fs { OP_REG, fs_reg }
 534 #define gs { OP_REG, gs_reg }
 535
 536 #define MX { OP_MMX, 0 }
 537 #define XM { OP_XMM, 0 }
 538 #define XMScalar { OP_XMM, scalar_mode }
 539 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 540 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 541 #define XMM { OP_XMM, xmm_mode }
 542 #define TMM { OP_XMM, tmm_mode }
 543 #define XMxmmq { OP_XMM, xmmq_mode }
 544 #define EM { OP_EM, v_mode }
 545 #define EMS { OP_EM, v_swap_mode }
 546 #define EMd { OP_EM, d_mode }
 547 #define EMx { OP_EM, x_mode }
 548 #define EXbwUnit { OP_EX, bw_unit_mode }
 549 #define EXb { OP_EX, b_mode }
 550 #define EXw { OP_EX, w_mode }
 551 #define EXd { OP_EX, d_mode }
 552 #define EXdS { OP_EX, d_swap_mode }
 553 #define EXwS { OP_EX, w_swap_mode }
 554 #define EXq { OP_EX, q_mode }
 555 #define EXqS { OP_EX, q_swap_mode }
 556 #define EXdq { OP_EX, dq_mode }
 557 #define EXx { OP_EX, x_mode }
 558 #define EXxh { OP_EX, xh_mode }
 559 #define EXxS { OP_EX, x_swap_mode }
 560 #define EXxmm { OP_EX, xmm_mode }
 561 #define EXymm { OP_EX, ymm_mode }
 562 #define EXxmmq { OP_EX, xmmq_mode }
 563 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 564 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 565 #define EXxmmdw { OP_EX, xmmdw_mode }
 566 #define EXxmmqd { OP_EX, xmmqd_mode }
 567 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 568 #define EXymmq { OP_EX, ymmq_mode }
 569 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 570 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 571 #define Rd { OP_R, d_mode }
 572 #define Rdq { OP_R, dq_mode }
 573 #define Rq { OP_R, q_mode }
 574 #define Nq { OP_R, q_mm_mode }
 575 #define Ux { OP_R, x_mode }
 576 #define Uxmm { OP_R, xmm_mode }
 577 #define Rxmmq { OP_R, xmmq_mode }
 578 #define Rymm { OP_R, ymm_mode }
 579 #define Rtmm { OP_R, tmm_mode }
 580 #define EMCq { OP_EMC, q_mode }
 581 #define MXC { OP_MXC, 0 }
 582 #define OPSUF { OP_3DNowSuffix, 0 }
 583 #define SEP { SEP_Fixup, 0 }
 584 #define CMP { CMP_Fixup, 0 }
 585 #define XMM0 { XMM_Fixup, 0 }
 586 #define FXSAVE { FXSAVE_Fixup, 0 }
 587
 588 #define Vex { OP_VEX, x_mode }
 589 #define VexW { OP_VexW, x_mode }
 590 #define VexScalar { OP_VEX, scalar_mode }
 591 #define VexScalarR { OP_VexR, scalar_mode }
 592 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 593 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 594 #define VexGdq { OP_VEX, dq_mode }
 595 #define VexGb { OP_VEX, b_mode }
 596 #define VexGv { OP_VEX, v_mode }
 597 #define VexTmm { OP_VEX, tmm_mode }
 598 #define XMVexI4 { OP_REG_VexI4, x_mode }
 599 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 600 #define VexI4 { OP_VexI4, 0 }
 601 #define PCLMUL { PCLMUL_Fixup, 0 }
 602 #define VPCMP { VPCMP_Fixup, 0 }
 603 #define VPCOM { VPCOM_Fixup, 0 }
 604
 605 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 606 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 607 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 608
 609 #define MaskG { OP_G, mask_mode }
 610 #define MaskE { OP_E, mask_mode }
 611 #define MaskR { OP_R, mask_mode }
 612 #define MaskBDE { OP_E, mask_bd_mode }
 613 #define MaskVex { OP_VEX, mask_mode }
 614
 615 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 616 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 617
 618 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 619
 620 /* Used handle "rep" prefix for string instructions.  */
 621 #define Xbr { REP_Fixup, eSI_reg }
 622 #define Xvr { REP_Fixup, eSI_reg }
 623 #define Ybr { REP_Fixup, eDI_reg }
 624 #define Yvr { REP_Fixup, eDI_reg }
 625 #define Yzr { REP_Fixup, eDI_reg }
 626 #define indirDXr { REP_Fixup, indir_dx_reg }
 627 #define ALr { REP_Fixup, al_reg }
 628 #define eAXr { REP_Fixup, eAX_reg }
 629
 630 /* Used handle HLE prefix for lockable instructions.  */
 631 #define Ebh1 { HLE_Fixup1, b_mode }
 632 #define Evh1 { HLE_Fixup1, v_mode }
 633 #define Ebh2 { HLE_Fixup2, b_mode }
 634 #define Evh2 { HLE_Fixup2, v_mode }
 635 #define Ebh3 { HLE_Fixup3, b_mode }
 636 #define Evh3 { HLE_Fixup3, v_mode }
 637
 638 #define BND { BND_Fixup, 0 }
 639 #define NOTRACK { NOTRACK_Fixup, 0 }
 640
 641 #define cond_jump_flag { NULL, cond_jump_mode }
 642 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 643
 644 /* bits in sizeflag */
 645 #define SUFFIX_ALWAYS 4
 646 #define AFLAG 2
 647 #define DFLAG 1
 648
 649 enum
 650 {
 651   /* byte operand */
 652   b_mode = 1,
 653   /* byte operand with operand swapped */
 654   b_swap_mode,
 655   /* byte operand, sign extend like 'T' suffix */
 656   b_T_mode,
 657   /* operand size depends on prefixes */
 658   v_mode,
 659   /* operand size depends on prefixes with operand swapped */
 660   v_swap_mode,
 661   /* operand size depends on address prefix */
 662   va_mode,
 663   /* word operand */
 664   w_mode,
 665   /* double word operand  */
 666   d_mode,
 667   /* word operand with operand swapped  */
 668   w_swap_mode,
 669   /* double word operand with operand swapped */
 670   d_swap_mode,
 671   /* quad word operand */
 672   q_mode,
 673   /* 8-byte MM operand */
 674   q_mm_mode,
 675   /* quad word operand with operand swapped */
 676   q_swap_mode,
 677   /* ten-byte operand */
 678   t_mode,
 679   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 680      broadcast enabled.  */
 681   x_mode,
 682   /* Similar to x_mode, but with different EVEX mem shifts.  */
 683   evex_x_gscat_mode,
 684   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 685   bw_unit_mode,
 686   /* Similar to x_mode, but with disabled broadcast.  */
 687   evex_x_nobcst_mode,
 688   /* Similar to x_mode, but with operands swapped and disabled broadcast
 689      in EVEX.  */
 690   x_swap_mode,
 691   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 692      broadcast of 16bit enabled.  */
 693   xh_mode,
 694   /* 16-byte XMM operand */
 695   xmm_mode,
 696   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 697      memory operand (depending on vector length).  Broadcast isn't
 698      allowed.  */
 699   xmmq_mode,
 700   /* Same as xmmq_mode, but broadcast is allowed.  */
 701   evex_half_bcst_xmmq_mode,
 702   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 703      memory operand (depending on vector length).  16bit broadcast.  */
 704   evex_half_bcst_xmmqh_mode,
 705   /* 16-byte XMM, word, double word or quad word operand.  */
 706   xmmdw_mode,
 707   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 708   xmmqd_mode,
 709   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 710      16bit broadcast.  */
 711   evex_half_bcst_xmmqdh_mode,
 712   /* 32-byte YMM operand */
 713   ymm_mode,
 714   /* quad word, ymmword or zmmword memory operand.  */
 715   ymmq_mode,
 716   /* TMM operand */
 717   tmm_mode,
 718   /* d_mode in 32bit, q_mode in 64bit mode.  */
 719   m_mode,
 720   /* pair of v_mode operands */
 721   a_mode,
 722   cond_jump_mode,
 723   loop_jcxz_mode,
 724   movsxd_mode,
 725   v_bnd_mode,
 726   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 727   v_bndmk_mode,
 728   /* operand size depends on REX.W / VEX.W.  */
 729   dq_mode,
 730   /* Displacements like v_mode without considering Intel64 ISA.  */
 731   dqw_mode,
 732   /* bounds operand */
 733   bnd_mode,
 734   /* bounds operand with operand swapped */
 735   bnd_swap_mode,
 736   /* 4- or 6-byte pointer operand */
 737   f_mode,
 738   const_1_mode,
 739   /* v_mode for indirect branch opcodes.  */
 740   indir_v_mode,
 741   /* v_mode for stack-related opcodes.  */
 742   stack_v_mode,
 743   /* non-quad operand size depends on prefixes */
 744   z_mode,
 745   /* 16-byte operand */
 746   o_mode,
 747   /* registers like d_mode, memory like b_mode.  */
 748   db_mode,
 749   /* registers like d_mode, memory like w_mode.  */
 750   dw_mode,
 751
 752   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 753   vex_vsib_d_w_dq_mode,
 754   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 755   vex_vsib_q_w_dq_mode,
 756   /* mandatory non-vector SIB.  */
 757   vex_sibmem_mode,
 758
 759   /* scalar, ignore vector length.  */
 760   scalar_mode,
 761
 762   /* Static rounding.  */
 763   evex_rounding_mode,
 764   /* Static rounding, 64-bit mode only.  */
 765   evex_rounding_64_mode,
 766   /* Supress all exceptions.  */
 767   evex_sae_mode,
 768
 769   /* Mask register operand.  */
 770   mask_mode,
 771   /* Mask register operand.  */
 772   mask_bd_mode,
 773
 774   es_reg,
 775   cs_reg,
 776   ss_reg,
 777   ds_reg,
 778   fs_reg,
 779   gs_reg,
 780
 781   eAX_reg,
 782   eCX_reg,
 783   eDX_reg,
 784   eBX_reg,
 785   eSP_reg,
 786   eBP_reg,
 787   eSI_reg,
 788   eDI_reg,
 789
 790   al_reg,
 791   cl_reg,
 792   dl_reg,
 793   bl_reg,
 794   ah_reg,
 795   ch_reg,
 796   dh_reg,
 797   bh_reg,
 798
 799   ax_reg,
 800   cx_reg,
 801   dx_reg,
 802   bx_reg,
 803   sp_reg,
 804   bp_reg,
 805   si_reg,
 806   di_reg,
 807
 808   rAX_reg,
 809   rCX_reg,
 810   rDX_reg,
 811   rBX_reg,
 812   rSP_reg,
 813   rBP_reg,
 814   rSI_reg,
 815   rDI_reg,
 816
 817   z_mode_ax_reg,
 818   indir_dx_reg
 819 };
 820
 821 enum
 822 {
 823   FLOATCODE = 1,
 824   USE_REG_TABLE,
 825   USE_MOD_TABLE,
 826   USE_RM_TABLE,
 827   USE_PREFIX_TABLE,
 828   USE_X86_64_TABLE,
 829   USE_X86_64_EVEX_FROM_VEX_TABLE,
 830   USE_X86_64_EVEX_PFX_TABLE,
 831   USE_X86_64_EVEX_W_TABLE,
 832   USE_X86_64_EVEX_MEM_W_TABLE,
 833   USE_3BYTE_TABLE,
 834   USE_XOP_8F_TABLE,
 835   USE_VEX_C4_TABLE,
 836   USE_VEX_C5_TABLE,
 837   USE_VEX_LEN_TABLE,
 838   USE_VEX_W_TABLE,
 839   USE_EVEX_TABLE,
 840   USE_EVEX_LEN_TABLE
 841 };
 842
 843 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 844
 845 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 846 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 847 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 848 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 849 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 850 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 851 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
 852   DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
 853 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
 854 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
 855 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
 856 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 857 #define XOP_8F_TABLE()          DIS386 (USE_XOP_8F_TABLE, 0)
 858 #define VEX_C4_TABLE()          DIS386 (USE_VEX_C4_TABLE, 0)
 859 #define VEX_C5_TABLE()          DIS386 (USE_VEX_C5_TABLE, 0)
 860 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 861 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 862 #define EVEX_TABLE()            DIS386 (USE_EVEX_TABLE, 0)
 863 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 864
 865 enum
 866 {
 867   REG_80 = 0,
 868   REG_81,
 869   REG_83,
 870   REG_8F,
 871   REG_C0,
 872   REG_C1,
 873   REG_C6,
 874   REG_C7,
 875   REG_D0,
 876   REG_D1,
 877   REG_D2,
 878   REG_D3,
 879   REG_F6,
 880   REG_F7,
 881   REG_FE,
 882   REG_FF,
 883   REG_0F00,
 884   REG_0F01,
 885   REG_0F0D,
 886   REG_0F18,
 887   REG_0F1C_P_0_MOD_0,
 888   REG_0F1E_P_1_MOD_3,
 889   REG_0F38D8_PREFIX_1,
 890   REG_0F3A0F_P_1,
 891   REG_0F71,
 892   REG_0F72,
 893   REG_0F73,
 894   REG_0FA6,
 895   REG_0FA7,
 896   REG_0FAE,
 897   REG_0FBA,
 898   REG_0FC7,
 899   REG_VEX_0F71,
 900   REG_VEX_0F72,
 901   REG_VEX_0F73,
 902   REG_VEX_0FAE,
 903   REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
 904   REG_VEX_0F38F3_L_0_P_0,
 905   REG_VEX_MAP7_F8_L_0_W_0,
 906
 907   REG_XOP_09_01_L_0,
 908   REG_XOP_09_02_L_0,
 909   REG_XOP_09_12_L_0,
 910   REG_XOP_0A_12_L_0,
 911
 912   REG_EVEX_0F71,
 913   REG_EVEX_0F72,
 914   REG_EVEX_0F73,
 915   REG_EVEX_0F38C6_L_2,
 916   REG_EVEX_0F38C7_L_2,
 917   REG_EVEX_MAP4_80,
 918   REG_EVEX_MAP4_81,
 919   REG_EVEX_MAP4_83,
 920   REG_EVEX_MAP4_8F,
 921   REG_EVEX_MAP4_F6,
 922   REG_EVEX_MAP4_F7,
 923   REG_EVEX_MAP4_FE,
 924   REG_EVEX_MAP4_FF,
 925 };
 926
 927 enum
 928 {
 929   MOD_62_32BIT = 0,
 930   MOD_C4_32BIT,
 931   MOD_C5_32BIT,
 932   MOD_0F01_REG_0,
 933   MOD_0F01_REG_1,
 934   MOD_0F01_REG_2,
 935   MOD_0F01_REG_3,
 936   MOD_0F01_REG_5,
 937   MOD_0F01_REG_7,
 938   MOD_0F12_PREFIX_0,
 939   MOD_0F16_PREFIX_0,
 940   MOD_0F18_REG_0,
 941   MOD_0F18_REG_1,
 942   MOD_0F18_REG_2,
 943   MOD_0F18_REG_3,
 944   MOD_0F18_REG_6,
 945   MOD_0F18_REG_7,
 946   MOD_0F1A_PREFIX_0,
 947   MOD_0F1B_PREFIX_0,
 948   MOD_0F1B_PREFIX_1,
 949   MOD_0F1C_PREFIX_0,
 950   MOD_0F1E_PREFIX_1,
 951   MOD_0FAE_REG_0,
 952   MOD_0FAE_REG_1,
 953   MOD_0FAE_REG_2,
 954   MOD_0FAE_REG_3,
 955   MOD_0FAE_REG_4,
 956   MOD_0FAE_REG_5,
 957   MOD_0FAE_REG_6,
 958   MOD_0FAE_REG_7,
 959   MOD_0FC7_REG_6,
 960   MOD_0FC7_REG_7,
 961   MOD_0F38DC_PREFIX_1,
 962   MOD_0F38F8,
 963
 964   MOD_VEX_0F3849_X86_64_L_0_W_0,
 965
 966   MOD_EVEX_MAP4_60,
 967   MOD_EVEX_MAP4_61,
 968   MOD_EVEX_MAP4_F8_P_1,
 969   MOD_EVEX_MAP4_F8_P_3,
 970 };
 971
 972 enum
 973 {
 974   RM_C6_REG_7 = 0,
 975   RM_C7_REG_7,
 976   RM_0F01_REG_0,
 977   RM_0F01_REG_1,
 978   RM_0F01_REG_2,
 979   RM_0F01_REG_3,
 980   RM_0F01_REG_5_MOD_3,
 981   RM_0F01_REG_7_MOD_3,
 982   RM_0F1E_P_1_MOD_3_REG_7,
 983   RM_0FAE_REG_6_MOD_3_P_0,
 984   RM_0FAE_REG_7_MOD_3,
 985   RM_0F3A0F_P_1_R_0,
 986
 987   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
 988   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
 989 };
 990
 991 enum
 992 {
 993   PREFIX_90 = 0,
 994   PREFIX_0F00_REG_6_X86_64,
 995   PREFIX_0F01_REG_0_MOD_3_RM_6,
 996   PREFIX_0F01_REG_0_MOD_3_RM_7,
 997   PREFIX_0F01_REG_1_RM_2,
 998   PREFIX_0F01_REG_1_RM_4,
 999   PREFIX_0F01_REG_1_RM_5,
1000   PREFIX_0F01_REG_1_RM_6,
1001   PREFIX_0F01_REG_1_RM_7,
1002   PREFIX_0F01_REG_3_RM_1,
1003   PREFIX_0F01_REG_5_MOD_0,
1004   PREFIX_0F01_REG_5_MOD_3_RM_0,
1005   PREFIX_0F01_REG_5_MOD_3_RM_1,
1006   PREFIX_0F01_REG_5_MOD_3_RM_2,
1007   PREFIX_0F01_REG_5_MOD_3_RM_4,
1008   PREFIX_0F01_REG_5_MOD_3_RM_5,
1009   PREFIX_0F01_REG_5_MOD_3_RM_6,
1010   PREFIX_0F01_REG_5_MOD_3_RM_7,
1011   PREFIX_0F01_REG_7_MOD_3_RM_2,
1012   PREFIX_0F01_REG_7_MOD_3_RM_5,
1013   PREFIX_0F01_REG_7_MOD_3_RM_6,
1014   PREFIX_0F01_REG_7_MOD_3_RM_7,
1015   PREFIX_0F09,
1016   PREFIX_0F10,
1017   PREFIX_0F11,
1018   PREFIX_0F12,
1019   PREFIX_0F16,
1020   PREFIX_0F18_REG_6_MOD_0_X86_64,
1021   PREFIX_0F18_REG_7_MOD_0_X86_64,
1022   PREFIX_0F1A,
1023   PREFIX_0F1B,
1024   PREFIX_0F1C,
1025   PREFIX_0F1E,
1026   PREFIX_0F2A,
1027   PREFIX_0F2B,
1028   PREFIX_0F2C,
1029   PREFIX_0F2D,
1030   PREFIX_0F2E,
1031   PREFIX_0F2F,
1032   PREFIX_0F51,
1033   PREFIX_0F52,
1034   PREFIX_0F53,
1035   PREFIX_0F58,
1036   PREFIX_0F59,
1037   PREFIX_0F5A,
1038   PREFIX_0F5B,
1039   PREFIX_0F5C,
1040   PREFIX_0F5D,
1041   PREFIX_0F5E,
1042   PREFIX_0F5F,
1043   PREFIX_0F60,
1044   PREFIX_0F61,
1045   PREFIX_0F62,
1046   PREFIX_0F6F,
1047   PREFIX_0F70,
1048   PREFIX_0F78,
1049   PREFIX_0F79,
1050   PREFIX_0F7C,
1051   PREFIX_0F7D,
1052   PREFIX_0F7E,
1053   PREFIX_0F7F,
1054   PREFIX_0FA6_REG_0,
1055   PREFIX_0FA6_REG_5,
1056   PREFIX_0FA7_REG_6,
1057   PREFIX_0FAE_REG_0_MOD_3,
1058   PREFIX_0FAE_REG_1_MOD_3,
1059   PREFIX_0FAE_REG_2_MOD_3,
1060   PREFIX_0FAE_REG_3_MOD_3,
1061   PREFIX_0FAE_REG_4_MOD_0,
1062   PREFIX_0FAE_REG_4_MOD_3,
1063   PREFIX_0FAE_REG_5_MOD_3,
1064   PREFIX_0FAE_REG_6_MOD_0,
1065   PREFIX_0FAE_REG_6_MOD_3,
1066   PREFIX_0FAE_REG_7_MOD_0,
1067   PREFIX_0FB8,
1068   PREFIX_0FBC,
1069   PREFIX_0FBD,
1070   PREFIX_0FC2,
1071   PREFIX_0FC7_REG_6_MOD_0,
1072   PREFIX_0FC7_REG_6_MOD_3,
1073   PREFIX_0FC7_REG_7_MOD_3,
1074   PREFIX_0FD0,
1075   PREFIX_0FD6,
1076   PREFIX_0FE6,
1077   PREFIX_0FE7,
1078   PREFIX_0FF0,
1079   PREFIX_0FF7,
1080   PREFIX_0F38D8,
1081   PREFIX_0F38DC,
1082   PREFIX_0F38DD,
1083   PREFIX_0F38DE,
1084   PREFIX_0F38DF,
1085   PREFIX_0F38F0,
1086   PREFIX_0F38F1,
1087   PREFIX_0F38F6,
1088   PREFIX_0F38F8_M_0,
1089   PREFIX_0F38F8_M_1_X86_64,
1090   PREFIX_0F38FA,
1091   PREFIX_0F38FB,
1092   PREFIX_0F38FC,
1093   PREFIX_0F3A0F,
1094   PREFIX_VEX_0F12,
1095   PREFIX_VEX_0F16,
1096   PREFIX_VEX_0F2A,
1097   PREFIX_VEX_0F2C,
1098   PREFIX_VEX_0F2D,
1099   PREFIX_VEX_0F41_L_1_W_0,
1100   PREFIX_VEX_0F41_L_1_W_1,
1101   PREFIX_VEX_0F42_L_1_W_0,
1102   PREFIX_VEX_0F42_L_1_W_1,
1103   PREFIX_VEX_0F44_L_0_W_0,
1104   PREFIX_VEX_0F44_L_0_W_1,
1105   PREFIX_VEX_0F45_L_1_W_0,
1106   PREFIX_VEX_0F45_L_1_W_1,
1107   PREFIX_VEX_0F46_L_1_W_0,
1108   PREFIX_VEX_0F46_L_1_W_1,
1109   PREFIX_VEX_0F47_L_1_W_0,
1110   PREFIX_VEX_0F47_L_1_W_1,
1111   PREFIX_VEX_0F4A_L_1_W_0,
1112   PREFIX_VEX_0F4A_L_1_W_1,
1113   PREFIX_VEX_0F4B_L_1_W_0,
1114   PREFIX_VEX_0F4B_L_1_W_1,
1115   PREFIX_VEX_0F6F,
1116   PREFIX_VEX_0F70,
1117   PREFIX_VEX_0F7E,
1118   PREFIX_VEX_0F7F,
1119   PREFIX_VEX_0F90_L_0_W_0,
1120   PREFIX_VEX_0F90_L_0_W_1,
1121   PREFIX_VEX_0F91_L_0_W_0,
1122   PREFIX_VEX_0F91_L_0_W_1,
1123   PREFIX_VEX_0F92_L_0_W_0,
1124   PREFIX_VEX_0F92_L_0_W_1,
1125   PREFIX_VEX_0F93_L_0_W_0,
1126   PREFIX_VEX_0F93_L_0_W_1,
1127   PREFIX_VEX_0F98_L_0_W_0,
1128   PREFIX_VEX_0F98_L_0_W_1,
1129   PREFIX_VEX_0F99_L_0_W_0,
1130   PREFIX_VEX_0F99_L_0_W_1,
1131   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1132   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1133   PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1134   PREFIX_VEX_0F3850_W_0,
1135   PREFIX_VEX_0F3851_W_0,
1136   PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1137   PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1138   PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1139   PREFIX_VEX_0F3872,
1140   PREFIX_VEX_0F38B0_W_0,
1141   PREFIX_VEX_0F38B1_W_0,
1142   PREFIX_VEX_0F38D2_W_0,
1143   PREFIX_VEX_0F38D3_W_0,
1144   PREFIX_VEX_0F38CB,
1145   PREFIX_VEX_0F38CC,
1146   PREFIX_VEX_0F38CD,
1147   PREFIX_VEX_0F38DA_W_0,
1148   PREFIX_VEX_0F38F2_L_0,
1149   PREFIX_VEX_0F38F3_L_0,
1150   PREFIX_VEX_0F38F5_L_0,
1151   PREFIX_VEX_0F38F6_L_0,
1152   PREFIX_VEX_0F38F7_L_0,
1153   PREFIX_VEX_0F3AF0_L_0,
1154   PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1155
1156   PREFIX_EVEX_0F5B,
1157   PREFIX_EVEX_0F6F,
1158   PREFIX_EVEX_0F70,
1159   PREFIX_EVEX_0F78,
1160   PREFIX_EVEX_0F79,
1161   PREFIX_EVEX_0F7A,
1162   PREFIX_EVEX_0F7B,
1163   PREFIX_EVEX_0F7E,
1164   PREFIX_EVEX_0F7F,
1165   PREFIX_EVEX_0FC2,
1166   PREFIX_EVEX_0FE6,
1167   PREFIX_EVEX_0F3810,
1168   PREFIX_EVEX_0F3811,
1169   PREFIX_EVEX_0F3812,
1170   PREFIX_EVEX_0F3813,
1171   PREFIX_EVEX_0F3814,
1172   PREFIX_EVEX_0F3815,
1173   PREFIX_EVEX_0F3820,
1174   PREFIX_EVEX_0F3821,
1175   PREFIX_EVEX_0F3822,
1176   PREFIX_EVEX_0F3823,
1177   PREFIX_EVEX_0F3824,
1178   PREFIX_EVEX_0F3825,
1179   PREFIX_EVEX_0F3826,
1180   PREFIX_EVEX_0F3827,
1181   PREFIX_EVEX_0F3828,
1182   PREFIX_EVEX_0F3829,
1183   PREFIX_EVEX_0F382A,
1184   PREFIX_EVEX_0F3830,
1185   PREFIX_EVEX_0F3831,
1186   PREFIX_EVEX_0F3832,
1187   PREFIX_EVEX_0F3833,
1188   PREFIX_EVEX_0F3834,
1189   PREFIX_EVEX_0F3835,
1190   PREFIX_EVEX_0F3838,
1191   PREFIX_EVEX_0F3839,
1192   PREFIX_EVEX_0F383A,
1193   PREFIX_EVEX_0F3852,
1194   PREFIX_EVEX_0F3853,
1195   PREFIX_EVEX_0F3868,
1196   PREFIX_EVEX_0F3872,
1197   PREFIX_EVEX_0F3874,
1198   PREFIX_EVEX_0F389A,
1199   PREFIX_EVEX_0F389B,
1200   PREFIX_EVEX_0F38AA,
1201   PREFIX_EVEX_0F38AB,
1202
1203   PREFIX_EVEX_0F3A08,
1204   PREFIX_EVEX_0F3A0A,
1205   PREFIX_EVEX_0F3A26,
1206   PREFIX_EVEX_0F3A27,
1207   PREFIX_EVEX_0F3A42_W_0,
1208   PREFIX_EVEX_0F3A56,
1209   PREFIX_EVEX_0F3A57,
1210   PREFIX_EVEX_0F3A66,
1211   PREFIX_EVEX_0F3A67,
1212   PREFIX_EVEX_0F3AC2,
1213
1214   PREFIX_EVEX_MAP4_4x,
1215   PREFIX_EVEX_MAP4_F0,
1216   PREFIX_EVEX_MAP4_F1,
1217   PREFIX_EVEX_MAP4_F2,
1218   PREFIX_EVEX_MAP4_F8,
1219
1220   PREFIX_EVEX_MAP5_10,
1221   PREFIX_EVEX_MAP5_11,
1222   PREFIX_EVEX_MAP5_18,
1223   PREFIX_EVEX_MAP5_1B,
1224   PREFIX_EVEX_MAP5_1D,
1225   PREFIX_EVEX_MAP5_1E,
1226   PREFIX_EVEX_MAP5_2A,
1227   PREFIX_EVEX_MAP5_2C,
1228   PREFIX_EVEX_MAP5_2D,
1229   PREFIX_EVEX_MAP5_2E,
1230   PREFIX_EVEX_MAP5_2F,
1231   PREFIX_EVEX_MAP5_51,
1232   PREFIX_EVEX_MAP5_58,
1233   PREFIX_EVEX_MAP5_59,
1234   PREFIX_EVEX_MAP5_5A,
1235   PREFIX_EVEX_MAP5_5B,
1236   PREFIX_EVEX_MAP5_5C,
1237   PREFIX_EVEX_MAP5_5D,
1238   PREFIX_EVEX_MAP5_5E,
1239   PREFIX_EVEX_MAP5_5F,
1240   PREFIX_EVEX_MAP5_74,
1241   PREFIX_EVEX_MAP5_78,
1242   PREFIX_EVEX_MAP5_79,
1243   PREFIX_EVEX_MAP5_7A,
1244   PREFIX_EVEX_MAP5_7B,
1245   PREFIX_EVEX_MAP5_7C,
1246   PREFIX_EVEX_MAP5_7D,
1247
1248   PREFIX_EVEX_MAP6_13,
1249   PREFIX_EVEX_MAP6_56,
1250   PREFIX_EVEX_MAP6_57,
1251   PREFIX_EVEX_MAP6_D6,
1252   PREFIX_EVEX_MAP6_D7,
1253 };
1254
1255 enum
1256 {
1257   X86_64_06 = 0,
1258   X86_64_07,
1259   X86_64_0E,
1260   X86_64_16,
1261   X86_64_17,
1262   X86_64_1E,
1263   X86_64_1F,
1264   X86_64_27,
1265   X86_64_2F,
1266   X86_64_37,
1267   X86_64_3F,
1268   X86_64_60,
1269   X86_64_61,
1270   X86_64_62,
1271   X86_64_63,
1272   X86_64_6D,
1273   X86_64_6F,
1274   X86_64_82,
1275   X86_64_9A,
1276   X86_64_C2,
1277   X86_64_C3,
1278   X86_64_C4,
1279   X86_64_C5,
1280   X86_64_CE,
1281   X86_64_D4,
1282   X86_64_D5,
1283   X86_64_E8,
1284   X86_64_E9,
1285   X86_64_EA,
1286   X86_64_0F00_REG_6,
1287   X86_64_0F01_REG_0,
1288   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1289   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1290   X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1291   X86_64_0F01_REG_1,
1292   X86_64_0F01_REG_1_RM_2_PREFIX_1,
1293   X86_64_0F01_REG_1_RM_2_PREFIX_3,
1294   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1295   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1296   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1297   X86_64_0F01_REG_2,
1298   X86_64_0F01_REG_3,
1299   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1300   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1301   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1302   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1303   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1304   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1305   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1306   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1307   X86_64_0F18_REG_6_MOD_0,
1308   X86_64_0F18_REG_7_MOD_0,
1309   X86_64_0F24,
1310   X86_64_0F26,
1311   X86_64_0F38F8_M_1,
1312   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1313
1314   X86_64_VEX_0F3849,
1315   X86_64_VEX_0F384B,
1316   X86_64_VEX_0F385C,
1317   X86_64_VEX_0F385E,
1318   X86_64_VEX_0F386C,
1319   X86_64_VEX_0F38Ex,
1320
1321   X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1322 };
1323
1324 enum
1325 {
1326   THREE_BYTE_0F38 = 0,
1327   THREE_BYTE_0F3A
1328 };
1329
1330 enum
1331 {
1332   XOP_08 = 0,
1333   XOP_09,
1334   XOP_0A
1335 };
1336
1337 enum
1338 {
1339   VEX_0F = 0,
1340   VEX_0F38,
1341   VEX_0F3A,
1342   VEX_MAP7,
1343 };
1344
1345 enum
1346 {
1347   EVEX_0F = 0,
1348   EVEX_0F38,
1349   EVEX_0F3A,
1350   EVEX_MAP4,
1351   EVEX_MAP5,
1352   EVEX_MAP6,
1353   EVEX_MAP7,
1354 };
1355
1356 enum
1357 {
1358   VEX_LEN_0F12_P_0 = 0,
1359   VEX_LEN_0F12_P_2,
1360   VEX_LEN_0F13,
1361   VEX_LEN_0F16_P_0,
1362   VEX_LEN_0F16_P_2,
1363   VEX_LEN_0F17,
1364   VEX_LEN_0F41,
1365   VEX_LEN_0F42,
1366   VEX_LEN_0F44,
1367   VEX_LEN_0F45,
1368   VEX_LEN_0F46,
1369   VEX_LEN_0F47,
1370   VEX_LEN_0F4A,
1371   VEX_LEN_0F4B,
1372   VEX_LEN_0F6E,
1373   VEX_LEN_0F77,
1374   VEX_LEN_0F7E_P_1,
1375   VEX_LEN_0F7E_P_2,
1376   VEX_LEN_0F90,
1377   VEX_LEN_0F91,
1378   VEX_LEN_0F92,
1379   VEX_LEN_0F93,
1380   VEX_LEN_0F98,
1381   VEX_LEN_0F99,
1382   VEX_LEN_0FAE_R_2,
1383   VEX_LEN_0FAE_R_3,
1384   VEX_LEN_0FC4,
1385   VEX_LEN_0FD6,
1386   VEX_LEN_0F3816,
1387   VEX_LEN_0F3819,
1388   VEX_LEN_0F381A,
1389   VEX_LEN_0F3836,
1390   VEX_LEN_0F3841,
1391   VEX_LEN_0F3849_X86_64,
1392   VEX_LEN_0F384B_X86_64,
1393   VEX_LEN_0F385A,
1394   VEX_LEN_0F385C_X86_64,
1395   VEX_LEN_0F385E_X86_64,
1396   VEX_LEN_0F386C_X86_64,
1397   VEX_LEN_0F38CB_P_3_W_0,
1398   VEX_LEN_0F38CC_P_3_W_0,
1399   VEX_LEN_0F38CD_P_3_W_0,
1400   VEX_LEN_0F38DA_W_0_P_0,
1401   VEX_LEN_0F38DA_W_0_P_2,
1402   VEX_LEN_0F38DB,
1403   VEX_LEN_0F38F2,
1404   VEX_LEN_0F38F3,
1405   VEX_LEN_0F38F5,
1406   VEX_LEN_0F38F6,
1407   VEX_LEN_0F38F7,
1408   VEX_LEN_0F3A00,
1409   VEX_LEN_0F3A01,
1410   VEX_LEN_0F3A06,
1411   VEX_LEN_0F3A14,
1412   VEX_LEN_0F3A15,
1413   VEX_LEN_0F3A16,
1414   VEX_LEN_0F3A17,
1415   VEX_LEN_0F3A18,
1416   VEX_LEN_0F3A19,
1417   VEX_LEN_0F3A20,
1418   VEX_LEN_0F3A21,
1419   VEX_LEN_0F3A22,
1420   VEX_LEN_0F3A30,
1421   VEX_LEN_0F3A31,
1422   VEX_LEN_0F3A32,
1423   VEX_LEN_0F3A33,
1424   VEX_LEN_0F3A38,
1425   VEX_LEN_0F3A39,
1426   VEX_LEN_0F3A41,
1427   VEX_LEN_0F3A46,
1428   VEX_LEN_0F3A60,
1429   VEX_LEN_0F3A61,
1430   VEX_LEN_0F3A62,
1431   VEX_LEN_0F3A63,
1432   VEX_LEN_0F3ADE_W_0,
1433   VEX_LEN_0F3ADF,
1434   VEX_LEN_0F3AF0,
1435   VEX_LEN_MAP7_F8,
1436   VEX_LEN_XOP_08_85,
1437   VEX_LEN_XOP_08_86,
1438   VEX_LEN_XOP_08_87,
1439   VEX_LEN_XOP_08_8E,
1440   VEX_LEN_XOP_08_8F,
1441   VEX_LEN_XOP_08_95,
1442   VEX_LEN_XOP_08_96,
1443   VEX_LEN_XOP_08_97,
1444   VEX_LEN_XOP_08_9E,
1445   VEX_LEN_XOP_08_9F,
1446   VEX_LEN_XOP_08_A3,
1447   VEX_LEN_XOP_08_A6,
1448   VEX_LEN_XOP_08_B6,
1449   VEX_LEN_XOP_08_C0,
1450   VEX_LEN_XOP_08_C1,
1451   VEX_LEN_XOP_08_C2,
1452   VEX_LEN_XOP_08_C3,
1453   VEX_LEN_XOP_08_CC,
1454   VEX_LEN_XOP_08_CD,
1455   VEX_LEN_XOP_08_CE,
1456   VEX_LEN_XOP_08_CF,
1457   VEX_LEN_XOP_08_EC,
1458   VEX_LEN_XOP_08_ED,
1459   VEX_LEN_XOP_08_EE,
1460   VEX_LEN_XOP_08_EF,
1461   VEX_LEN_XOP_09_01,
1462   VEX_LEN_XOP_09_02,
1463   VEX_LEN_XOP_09_12,
1464   VEX_LEN_XOP_09_82_W_0,
1465   VEX_LEN_XOP_09_83_W_0,
1466   VEX_LEN_XOP_09_90,
1467   VEX_LEN_XOP_09_91,
1468   VEX_LEN_XOP_09_92,
1469   VEX_LEN_XOP_09_93,
1470   VEX_LEN_XOP_09_94,
1471   VEX_LEN_XOP_09_95,
1472   VEX_LEN_XOP_09_96,
1473   VEX_LEN_XOP_09_97,
1474   VEX_LEN_XOP_09_98,
1475   VEX_LEN_XOP_09_99,
1476   VEX_LEN_XOP_09_9A,
1477   VEX_LEN_XOP_09_9B,
1478   VEX_LEN_XOP_09_C1,
1479   VEX_LEN_XOP_09_C2,
1480   VEX_LEN_XOP_09_C3,
1481   VEX_LEN_XOP_09_C6,
1482   VEX_LEN_XOP_09_C7,
1483   VEX_LEN_XOP_09_CB,
1484   VEX_LEN_XOP_09_D1,
1485   VEX_LEN_XOP_09_D2,
1486   VEX_LEN_XOP_09_D3,
1487   VEX_LEN_XOP_09_D6,
1488   VEX_LEN_XOP_09_D7,
1489   VEX_LEN_XOP_09_DB,
1490   VEX_LEN_XOP_09_E1,
1491   VEX_LEN_XOP_09_E2,
1492   VEX_LEN_XOP_09_E3,
1493   VEX_LEN_XOP_0A_12,
1494 };
1495
1496 enum
1497 {
1498   EVEX_LEN_0F3816 = 0,
1499   EVEX_LEN_0F3819,
1500   EVEX_LEN_0F381A,
1501   EVEX_LEN_0F381B,
1502   EVEX_LEN_0F3836,
1503   EVEX_LEN_0F385A,
1504   EVEX_LEN_0F385B,
1505   EVEX_LEN_0F38C6,
1506   EVEX_LEN_0F38C7,
1507   EVEX_LEN_0F3A00,
1508   EVEX_LEN_0F3A01,
1509   EVEX_LEN_0F3A18,
1510   EVEX_LEN_0F3A19,
1511   EVEX_LEN_0F3A1A,
1512   EVEX_LEN_0F3A1B,
1513   EVEX_LEN_0F3A23,
1514   EVEX_LEN_0F3A38,
1515   EVEX_LEN_0F3A39,
1516   EVEX_LEN_0F3A3A,
1517   EVEX_LEN_0F3A3B,
1518   EVEX_LEN_0F3A43
1519 };
1520
1521 enum
1522 {
1523   VEX_W_0F41_L_1 = 0,
1524   VEX_W_0F42_L_1,
1525   VEX_W_0F44_L_0,
1526   VEX_W_0F45_L_1,
1527   VEX_W_0F46_L_1,
1528   VEX_W_0F47_L_1,
1529   VEX_W_0F4A_L_1,
1530   VEX_W_0F4B_L_1,
1531   VEX_W_0F90_L_0,
1532   VEX_W_0F91_L_0,
1533   VEX_W_0F92_L_0,
1534   VEX_W_0F93_L_0,
1535   VEX_W_0F98_L_0,
1536   VEX_W_0F99_L_0,
1537   VEX_W_0F380C,
1538   VEX_W_0F380D,
1539   VEX_W_0F380E,
1540   VEX_W_0F380F,
1541   VEX_W_0F3813,
1542   VEX_W_0F3816_L_1,
1543   VEX_W_0F3818,
1544   VEX_W_0F3819_L_1,
1545   VEX_W_0F381A_L_1,
1546   VEX_W_0F382C,
1547   VEX_W_0F382D,
1548   VEX_W_0F382E,
1549   VEX_W_0F382F,
1550   VEX_W_0F3836,
1551   VEX_W_0F3846,
1552   VEX_W_0F3849_X86_64_L_0,
1553   VEX_W_0F384B_X86_64_L_0,
1554   VEX_W_0F3850,
1555   VEX_W_0F3851,
1556   VEX_W_0F3852,
1557   VEX_W_0F3853,
1558   VEX_W_0F3858,
1559   VEX_W_0F3859,
1560   VEX_W_0F385A_L_0,
1561   VEX_W_0F385C_X86_64_L_0,
1562   VEX_W_0F385E_X86_64_L_0,
1563   VEX_W_0F386C_X86_64_L_0,
1564   VEX_W_0F3872_P_1,
1565   VEX_W_0F3878,
1566   VEX_W_0F3879,
1567   VEX_W_0F38B0,
1568   VEX_W_0F38B1,
1569   VEX_W_0F38B4,
1570   VEX_W_0F38B5,
1571   VEX_W_0F38CB_P_3,
1572   VEX_W_0F38CC_P_3,
1573   VEX_W_0F38CD_P_3,
1574   VEX_W_0F38CF,
1575   VEX_W_0F38D2,
1576   VEX_W_0F38D3,
1577   VEX_W_0F38DA,
1578   VEX_W_0F3A00_L_1,
1579   VEX_W_0F3A01_L_1,
1580   VEX_W_0F3A02,
1581   VEX_W_0F3A04,
1582   VEX_W_0F3A05,
1583   VEX_W_0F3A06_L_1,
1584   VEX_W_0F3A18_L_1,
1585   VEX_W_0F3A19_L_1,
1586   VEX_W_0F3A1D,
1587   VEX_W_0F3A38_L_1,
1588   VEX_W_0F3A39_L_1,
1589   VEX_W_0F3A46_L_1,
1590   VEX_W_0F3A4A,
1591   VEX_W_0F3A4B,
1592   VEX_W_0F3A4C,
1593   VEX_W_0F3ACE,
1594   VEX_W_0F3ACF,
1595   VEX_W_0F3ADE,
1596   VEX_W_MAP7_F8_L_0,
1597
1598   VEX_W_XOP_08_85_L_0,
1599   VEX_W_XOP_08_86_L_0,
1600   VEX_W_XOP_08_87_L_0,
1601   VEX_W_XOP_08_8E_L_0,
1602   VEX_W_XOP_08_8F_L_0,
1603   VEX_W_XOP_08_95_L_0,
1604   VEX_W_XOP_08_96_L_0,
1605   VEX_W_XOP_08_97_L_0,
1606   VEX_W_XOP_08_9E_L_0,
1607   VEX_W_XOP_08_9F_L_0,
1608   VEX_W_XOP_08_A6_L_0,
1609   VEX_W_XOP_08_B6_L_0,
1610   VEX_W_XOP_08_C0_L_0,
1611   VEX_W_XOP_08_C1_L_0,
1612   VEX_W_XOP_08_C2_L_0,
1613   VEX_W_XOP_08_C3_L_0,
1614   VEX_W_XOP_08_CC_L_0,
1615   VEX_W_XOP_08_CD_L_0,
1616   VEX_W_XOP_08_CE_L_0,
1617   VEX_W_XOP_08_CF_L_0,
1618   VEX_W_XOP_08_EC_L_0,
1619   VEX_W_XOP_08_ED_L_0,
1620   VEX_W_XOP_08_EE_L_0,
1621   VEX_W_XOP_08_EF_L_0,
1622
1623   VEX_W_XOP_09_80,
1624   VEX_W_XOP_09_81,
1625   VEX_W_XOP_09_82,
1626   VEX_W_XOP_09_83,
1627   VEX_W_XOP_09_C1_L_0,
1628   VEX_W_XOP_09_C2_L_0,
1629   VEX_W_XOP_09_C3_L_0,
1630   VEX_W_XOP_09_C6_L_0,
1631   VEX_W_XOP_09_C7_L_0,
1632   VEX_W_XOP_09_CB_L_0,
1633   VEX_W_XOP_09_D1_L_0,
1634   VEX_W_XOP_09_D2_L_0,
1635   VEX_W_XOP_09_D3_L_0,
1636   VEX_W_XOP_09_D6_L_0,
1637   VEX_W_XOP_09_D7_L_0,
1638   VEX_W_XOP_09_DB_L_0,
1639   VEX_W_XOP_09_E1_L_0,
1640   VEX_W_XOP_09_E2_L_0,
1641   VEX_W_XOP_09_E3_L_0,
1642
1643   EVEX_W_0F5B_P_0,
1644   EVEX_W_0F62,
1645   EVEX_W_0F66,
1646   EVEX_W_0F6A,
1647   EVEX_W_0F6B,
1648   EVEX_W_0F6C,
1649   EVEX_W_0F6D,
1650   EVEX_W_0F6F_P_1,
1651   EVEX_W_0F6F_P_2,
1652   EVEX_W_0F6F_P_3,
1653   EVEX_W_0F70_P_2,
1654   EVEX_W_0F72_R_2,
1655   EVEX_W_0F72_R_6,
1656   EVEX_W_0F73_R_2,
1657   EVEX_W_0F73_R_6,
1658   EVEX_W_0F76,
1659   EVEX_W_0F78_P_0,
1660   EVEX_W_0F78_P_2,
1661   EVEX_W_0F79_P_0,
1662   EVEX_W_0F79_P_2,
1663   EVEX_W_0F7A_P_1,
1664   EVEX_W_0F7A_P_2,
1665   EVEX_W_0F7A_P_3,
1666   EVEX_W_0F7B_P_2,
1667   EVEX_W_0F7E_P_1,
1668   EVEX_W_0F7F_P_1,
1669   EVEX_W_0F7F_P_2,
1670   EVEX_W_0F7F_P_3,
1671   EVEX_W_0FD2,
1672   EVEX_W_0FD3,
1673   EVEX_W_0FD4,
1674   EVEX_W_0FD6,
1675   EVEX_W_0FE6_P_1,
1676   EVEX_W_0FE7,
1677   EVEX_W_0FF2,
1678   EVEX_W_0FF3,
1679   EVEX_W_0FF4,
1680   EVEX_W_0FFA,
1681   EVEX_W_0FFB,
1682   EVEX_W_0FFE,
1683
1684   EVEX_W_0F3810_P_1,
1685   EVEX_W_0F3810_P_2,
1686   EVEX_W_0F3811_P_1,
1687   EVEX_W_0F3811_P_2,
1688   EVEX_W_0F3812_P_1,
1689   EVEX_W_0F3812_P_2,
1690   EVEX_W_0F3813_P_1,
1691   EVEX_W_0F3814_P_1,
1692   EVEX_W_0F3815_P_1,
1693   EVEX_W_0F3819_L_n,
1694   EVEX_W_0F381A_L_n,
1695   EVEX_W_0F381B_L_2,
1696   EVEX_W_0F381E,
1697   EVEX_W_0F381F,
1698   EVEX_W_0F3820_P_1,
1699   EVEX_W_0F3821_P_1,
1700   EVEX_W_0F3822_P_1,
1701   EVEX_W_0F3823_P_1,
1702   EVEX_W_0F3824_P_1,
1703   EVEX_W_0F3825_P_1,
1704   EVEX_W_0F3825_P_2,
1705   EVEX_W_0F3828_P_2,
1706   EVEX_W_0F3829_P_2,
1707   EVEX_W_0F382A_P_1,
1708   EVEX_W_0F382A_P_2,
1709   EVEX_W_0F382B,
1710   EVEX_W_0F3830_P_1,
1711   EVEX_W_0F3831_P_1,
1712   EVEX_W_0F3832_P_1,
1713   EVEX_W_0F3833_P_1,
1714   EVEX_W_0F3834_P_1,
1715   EVEX_W_0F3835_P_1,
1716   EVEX_W_0F3835_P_2,
1717   EVEX_W_0F3837,
1718   EVEX_W_0F383A_P_1,
1719   EVEX_W_0F3859,
1720   EVEX_W_0F385A_L_n,
1721   EVEX_W_0F385B_L_2,
1722   EVEX_W_0F3870,
1723   EVEX_W_0F3872_P_2,
1724   EVEX_W_0F387A,
1725   EVEX_W_0F387B,
1726   EVEX_W_0F3883,
1727
1728   EVEX_W_0F3A18_L_n,
1729   EVEX_W_0F3A19_L_n,
1730   EVEX_W_0F3A1A_L_2,
1731   EVEX_W_0F3A1B_L_2,
1732   EVEX_W_0F3A21,
1733   EVEX_W_0F3A23_L_n,
1734   EVEX_W_0F3A38_L_n,
1735   EVEX_W_0F3A39_L_n,
1736   EVEX_W_0F3A3A_L_2,
1737   EVEX_W_0F3A3B_L_2,
1738   EVEX_W_0F3A42,
1739   EVEX_W_0F3A43_L_n,
1740   EVEX_W_0F3A70,
1741   EVEX_W_0F3A72,
1742
1743   EVEX_W_MAP4_8F_R_0,
1744   EVEX_W_MAP4_F8_P1_M_1,
1745   EVEX_W_MAP4_F8_P3_M_1,
1746   EVEX_W_MAP4_FF_R_6,
1747
1748   EVEX_W_MAP5_5B_P_0,
1749   EVEX_W_MAP5_7A_P_3,
1750 };
1751
1752 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1753
1754 struct dis386 {
1755   const char *name;
1756   struct
1757     {
1758       op_rtn rtn;
1759       int bytemode;
1760     } op[MAX_OPERANDS];
1761   unsigned int prefix_requirement;
1762 };
1763
1764 /* Upper case letters in the instruction names here are macros.
1765    'A' => print 'b' if no (suitable) register operand or suffix_always is true
1766    'B' => print 'b' if suffix_always is true
1767    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1768           size prefix
1769    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1770           suffix_always is true
1771    'E' => print 'e' if 32-bit form of jcxz
1772    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1773    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1774    'H' => print ",pt" or ",pn" branch hint
1775    'I' unused.
1776    'J' unused.
1777    'K' => print 'd' or 'q' if rex prefix is present.
1778    'L' => print 'l' or 'q' if suffix_always is true
1779    'M' => print 'r' if intel_mnemonic is false.
1780    'N' => print 'n' if instruction has no wait "prefix"
1781    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1782    'P' => behave as 'T' except with register operand outside of suffix_always
1783           mode
1784    'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1785           suffix_always is true
1786    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1787    'S' => print 'w', 'l' or 'q' if suffix_always is true
1788    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1789           prefix or if suffix_always is true.
1790    'U' unused.
1791    'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1792    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1793    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1794    'Y' => no output, mark EVEX.aaa != 0 as bad.
1795    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1796    '!' => change condition from true to false or from false to true.
1797    '%' => add 1 upper case letter to the macro.
1798    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1799           prefix or suffix_always is true (lcall/ljmp).
1800    '@' => in 64bit mode for Intel64 ISA or if instruction
1801           has no operand sizing prefix, print 'q' if suffix_always is true or
1802           nothing otherwise; behave as 'P' in all other cases
1803
1804    2 upper case letter macros:
1805    "CC" => print condition code
1806    "XY" => print 'x' or 'y' if suffix_always is true or no register
1807            operands and no broadcast.
1808    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1809            register operands and no broadcast.
1810    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1811    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1812    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1813    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1814    "XV" => print "{vex} " pseudo prefix
1815    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1816            is used by an EVEX-encoded (AVX512VL) instruction.
1817    "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1818            pseudo prefix when instructions without NF, EGPR and VVVV,
1819    "NE" => don't print "{evex} " pseudo prefix for some special instructions
1820            in MAP4.
1821    "ZU" => print 'zu' if EVEX.ZU=1.
1822    "SC" => print suffix SCC for SCC insns
1823    "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1824    "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1825    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1826            being false, or no operand at all in 64bit mode, or if suffix_always
1827            is true.
1828    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1829    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1830    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1831    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1832    "DF" => print default flag value for SCC insns
1833    "BW" => print 'b' or 'w' depending on the VEX.W bit
1834    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1835            an operand size prefix, or suffix_always is true.  print
1836            'q' if rex prefix is present.
1837
1838    Many of the above letters print nothing in Intel mode.  See "putop"
1839    for the details.
1840
1841    Braces '{' and '}', and vertical bars '|', indicate alternative
1842    mnemonic strings for AT&T and Intel.  */
1843
1844 static const struct dis386 dis386[] = {
1845   /* 00 */
1846   { "addB",             { Ebh1, Gb }, 0 },
1847   { "addS",             { Evh1, Gv }, 0 },
1848   { "addB",             { Gb, EbS }, 0 },
1849   { "addS",             { Gv, EvS }, 0 },
1850   { "addB",             { AL, Ib }, 0 },
1851   { "addS",             { eAX, Iv }, 0 },
1852   { X86_64_TABLE (X86_64_06) },
1853   { X86_64_TABLE (X86_64_07) },
1854   /* 08 */
1855   { "orB",              { Ebh1, Gb }, 0 },
1856   { "orS",              { Evh1, Gv }, 0 },
1857   { "orB",              { Gb, EbS }, 0 },
1858   { "orS",              { Gv, EvS }, 0 },
1859   { "orB",              { AL, Ib }, 0 },
1860   { "orS",              { eAX, Iv }, 0 },
1861   { X86_64_TABLE (X86_64_0E) },
1862   { Bad_Opcode },       /* 0x0f extended opcode escape */
1863   /* 10 */
1864   { "adcB",             { Ebh1, Gb }, 0 },
1865   { "adcS",             { Evh1, Gv }, 0 },
1866   { "adcB",             { Gb, EbS }, 0 },
1867   { "adcS",             { Gv, EvS }, 0 },
1868   { "adcB",             { AL, Ib }, 0 },
1869   { "adcS",             { eAX, Iv }, 0 },
1870   { X86_64_TABLE (X86_64_16) },
1871   { X86_64_TABLE (X86_64_17) },
1872   /* 18 */
1873   { "sbbB",             { Ebh1, Gb }, 0 },
1874   { "sbbS",             { Evh1, Gv }, 0 },
1875   { "sbbB",             { Gb, EbS }, 0 },
1876   { "sbbS",             { Gv, EvS }, 0 },
1877   { "sbbB",             { AL, Ib }, 0 },
1878   { "sbbS",             { eAX, Iv }, 0 },
1879   { X86_64_TABLE (X86_64_1E) },
1880   { X86_64_TABLE (X86_64_1F) },
1881   /* 20 */
1882   { "andB",             { Ebh1, Gb }, 0 },
1883   { "andS",             { Evh1, Gv }, 0 },
1884   { "andB",             { Gb, EbS }, 0 },
1885   { "andS",             { Gv, EvS }, 0 },
1886   { "andB",             { AL, Ib }, 0 },
1887   { "andS",             { eAX, Iv }, 0 },
1888   { Bad_Opcode },       /* SEG ES prefix */
1889   { X86_64_TABLE (X86_64_27) },
1890   /* 28 */
1891   { "subB",             { Ebh1, Gb }, 0 },
1892   { "subS",             { Evh1, Gv }, 0 },
1893   { "subB",             { Gb, EbS }, 0 },
1894   { "subS",             { Gv, EvS }, 0 },
1895   { "subB",             { AL, Ib }, 0 },
1896   { "subS",             { eAX, Iv }, 0 },
1897   { Bad_Opcode },       /* SEG CS prefix */
1898   { X86_64_TABLE (X86_64_2F) },
1899   /* 30 */
1900   { "xorB",             { Ebh1, Gb }, 0 },
1901   { "xorS",             { Evh1, Gv }, 0 },
1902   { "xorB",             { Gb, EbS }, 0 },
1903   { "xorS",             { Gv, EvS }, 0 },
1904   { "xorB",             { AL, Ib }, 0 },
1905   { "xorS",             { eAX, Iv }, 0 },
1906   { Bad_Opcode },       /* SEG SS prefix */
1907   { X86_64_TABLE (X86_64_37) },
1908   /* 38 */
1909   { "cmpB",             { Eb, Gb }, 0 },
1910   { "cmpS",             { Ev, Gv }, 0 },
1911   { "cmpB",             { Gb, EbS }, 0 },
1912   { "cmpS",             { Gv, EvS }, 0 },
1913   { "cmpB",             { AL, Ib }, 0 },
1914   { "cmpS",             { eAX, Iv }, 0 },
1915   { Bad_Opcode },       /* SEG DS prefix */
1916   { X86_64_TABLE (X86_64_3F) },
1917   /* 40 */
1918   { "inc{S|}",          { RMeAX }, 0 },
1919   { "inc{S|}",          { RMeCX }, 0 },
1920   { "inc{S|}",          { RMeDX }, 0 },
1921   { "inc{S|}",          { RMeBX }, 0 },
1922   { "inc{S|}",          { RMeSP }, 0 },
1923   { "inc{S|}",          { RMeBP }, 0 },
1924   { "inc{S|}",          { RMeSI }, 0 },
1925   { "inc{S|}",          { RMeDI }, 0 },
1926   /* 48 */
1927   { "dec{S|}",          { RMeAX }, 0 },
1928   { "dec{S|}",          { RMeCX }, 0 },
1929   { "dec{S|}",          { RMeDX }, 0 },
1930   { "dec{S|}",          { RMeBX }, 0 },
1931   { "dec{S|}",          { RMeSP }, 0 },
1932   { "dec{S|}",          { RMeBP }, 0 },
1933   { "dec{S|}",          { RMeSI }, 0 },
1934   { "dec{S|}",          { RMeDI }, 0 },
1935   /* 50 */
1936   { "push!P",           { RMrAX }, 0 },
1937   { "push!P",           { RMrCX }, 0 },
1938   { "push!P",           { RMrDX }, 0 },
1939   { "push!P",           { RMrBX }, 0 },
1940   { "push!P",           { RMrSP }, 0 },
1941   { "push!P",           { RMrBP }, 0 },
1942   { "push!P",           { RMrSI }, 0 },
1943   { "push!P",           { RMrDI }, 0 },
1944   /* 58 */
1945   { "pop!P",            { RMrAX }, 0 },
1946   { "pop!P",            { RMrCX }, 0 },
1947   { "pop!P",            { RMrDX }, 0 },
1948   { "pop!P",            { RMrBX }, 0 },
1949   { "pop!P",            { RMrSP }, 0 },
1950   { "pop!P",            { RMrBP }, 0 },
1951   { "pop!P",            { RMrSI }, 0 },
1952   { "pop!P",            { RMrDI }, 0 },
1953   /* 60 */
1954   { X86_64_TABLE (X86_64_60) },
1955   { X86_64_TABLE (X86_64_61) },
1956   { X86_64_TABLE (X86_64_62) },
1957   { X86_64_TABLE (X86_64_63) },
1958   { Bad_Opcode },       /* seg fs */
1959   { Bad_Opcode },       /* seg gs */
1960   { Bad_Opcode },       /* op size prefix */
1961   { Bad_Opcode },       /* adr size prefix */
1962   /* 68 */
1963   { "pushP",            { sIv }, 0 },
1964   { "imulS",            { Gv, Ev, Iv }, 0 },
1965   { "pushP",            { sIbT }, 0 },
1966   { "imulS",            { Gv, Ev, sIb }, 0 },
1967   { "ins{b|}",          { Ybr, indirDX }, 0 },
1968   { X86_64_TABLE (X86_64_6D) },
1969   { "outs{b|}",         { indirDXr, Xb }, 0 },
1970   { X86_64_TABLE (X86_64_6F) },
1971   /* 70 */
1972   { "joH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1973   { "jnoH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1974   { "jbH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1975   { "jaeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1976   { "jeH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1977   { "jneH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978   { "jbeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979   { "jaH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1980   /* 78 */
1981   { "jsH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1982   { "jnsH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1983   { "jpH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1984   { "jnpH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1985   { "jlH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1986   { "jgeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1987   { "jleH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1988   { "jgH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1989   /* 80 */
1990   { REG_TABLE (REG_80) },
1991   { REG_TABLE (REG_81) },
1992   { X86_64_TABLE (X86_64_82) },
1993   { REG_TABLE (REG_83) },
1994   { "testB",            { Eb, Gb }, 0 },
1995   { "testS",            { Ev, Gv }, 0 },
1996   { "xchgB",            { Ebh2, Gb }, 0 },
1997   { "xchgS",            { Evh2, Gv }, 0 },
1998   /* 88 */
1999   { "movB",             { Ebh3, Gb }, 0 },
2000   { "movS",             { Evh3, Gv }, 0 },
2001   { "movB",             { Gb, EbS }, 0 },
2002   { "movS",             { Gv, EvS }, 0 },
2003   { "movD",             { Sv, Sw }, 0 },
2004   { "leaS",             { Gv, M }, 0 },
2005   { "movD",             { Sw, Sv }, 0 },
2006   { REG_TABLE (REG_8F) },
2007   /* 90 */
2008   { PREFIX_TABLE (PREFIX_90) },
2009   { "xchgS",            { RMeCX, eAX }, 0 },
2010   { "xchgS",            { RMeDX, eAX }, 0 },
2011   { "xchgS",            { RMeBX, eAX }, 0 },
2012   { "xchgS",            { RMeSP, eAX }, 0 },
2013   { "xchgS",            { RMeBP, eAX }, 0 },
2014   { "xchgS",            { RMeSI, eAX }, 0 },
2015   { "xchgS",            { RMeDI, eAX }, 0 },
2016   /* 98 */
2017   { "cW{t|}R",          { XX }, 0 },
2018   { "cR{t|}O",          { XX }, 0 },
2019   { X86_64_TABLE (X86_64_9A) },
2020   { Bad_Opcode },       /* fwait */
2021   { "pushfP",           { XX }, 0 },
2022   { "popfP",            { XX }, 0 },
2023   { "sahf",             { XX }, 0 },
2024   { "lahf",             { XX }, 0 },
2025   /* a0 */
2026   { "mov%LB",           { AL, Ob }, PREFIX_REX2_ILLEGAL },
2027   { "mov%LS",           { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2028   { "mov%LB",           { Ob, AL }, PREFIX_REX2_ILLEGAL },
2029   { "mov%LS",           { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2030   { "movs{b|}",         { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2031   { "movs{R|}",         { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2032   { "cmps{b|}",         { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2033   { "cmps{R|}",         { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2034   /* a8 */
2035   { "testB",            { AL, Ib }, PREFIX_REX2_ILLEGAL },
2036   { "testS",            { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2037   { "stosB",            { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2038   { "stosS",            { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2039   { "lodsB",            { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2040   { "lodsS",            { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2041   { "scasB",            { AL, Yb }, PREFIX_REX2_ILLEGAL },
2042   { "scasS",            { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2043   /* b0 */
2044   { "movB",             { RMAL, Ib }, 0 },
2045   { "movB",             { RMCL, Ib }, 0 },
2046   { "movB",             { RMDL, Ib }, 0 },
2047   { "movB",             { RMBL, Ib }, 0 },
2048   { "movB",             { RMAH, Ib }, 0 },
2049   { "movB",             { RMCH, Ib }, 0 },
2050   { "movB",             { RMDH, Ib }, 0 },
2051   { "movB",             { RMBH, Ib }, 0 },
2052   /* b8 */
2053   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2054   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2055   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2056   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2057   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2058   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2059   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2060   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2061   /* c0 */
2062   { REG_TABLE (REG_C0) },
2063   { REG_TABLE (REG_C1) },
2064   { X86_64_TABLE (X86_64_C2) },
2065   { X86_64_TABLE (X86_64_C3) },
2066   { X86_64_TABLE (X86_64_C4) },
2067   { X86_64_TABLE (X86_64_C5) },
2068   { REG_TABLE (REG_C6) },
2069   { REG_TABLE (REG_C7) },
2070   /* c8 */
2071   { "enterP",           { Iw, Ib }, 0 },
2072   { "leaveP",           { XX }, 0 },
2073   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2074   { "{l|}ret{|f}%LP",   { XX }, 0 },
2075   { "int3",             { XX }, 0 },
2076   { "int",              { Ib }, 0 },
2077   { X86_64_TABLE (X86_64_CE) },
2078   { "iret%LP",          { XX }, 0 },
2079   /* d0 */
2080   { REG_TABLE (REG_D0) },
2081   { REG_TABLE (REG_D1) },
2082   { REG_TABLE (REG_D2) },
2083   { REG_TABLE (REG_D3) },
2084   { X86_64_TABLE (X86_64_D4) },
2085   { X86_64_TABLE (X86_64_D5) },
2086   { Bad_Opcode },
2087   { "xlat",             { DSBX }, 0 },
2088   /* d8 */
2089   { FLOAT },
2090   { FLOAT },
2091   { FLOAT },
2092   { FLOAT },
2093   { FLOAT },
2094   { FLOAT },
2095   { FLOAT },
2096   { FLOAT },
2097   /* e0 */
2098   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2099   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2100   { "loopFH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2101   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2102   { "inB",              { AL, Ib }, PREFIX_REX2_ILLEGAL },
2103   { "inG",              { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2104   { "outB",             { Ib, AL }, PREFIX_REX2_ILLEGAL },
2105   { "outG",             { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2106   /* e8 */
2107   { X86_64_TABLE (X86_64_E8) },
2108   { X86_64_TABLE (X86_64_E9) },
2109   { X86_64_TABLE (X86_64_EA) },
2110   { "jmp",              { Jb, BND }, PREFIX_REX2_ILLEGAL },
2111   { "inB",              { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2112   { "inG",              { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2113   { "outB",             { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2114   { "outG",             { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2115   /* f0 */
2116   { Bad_Opcode },       /* lock prefix */
2117   { "int1",             { XX }, 0 },
2118   { Bad_Opcode },       /* repne */
2119   { Bad_Opcode },       /* repz */
2120   { "hlt",              { XX }, 0 },
2121   { "cmc",              { XX }, 0 },
2122   { REG_TABLE (REG_F6) },
2123   { REG_TABLE (REG_F7) },
2124   /* f8 */
2125   { "clc",              { XX }, 0 },
2126   { "stc",              { XX }, 0 },
2127   { "cli",              { XX }, 0 },
2128   { "sti",              { XX }, 0 },
2129   { "cld",              { XX }, 0 },
2130   { "std",              { XX }, 0 },
2131   { REG_TABLE (REG_FE) },
2132   { REG_TABLE (REG_FF) },
2133 };
2134
2135 static const struct dis386 dis386_twobyte[] = {
2136   /* 00 */
2137   { REG_TABLE (REG_0F00 ) },
2138   { REG_TABLE (REG_0F01 ) },
2139   { "larS",             { Gv, Sv }, 0 },
2140   { "lslS",             { Gv, Sv }, 0 },
2141   { Bad_Opcode },
2142   { "syscall",          { XX }, 0 },
2143   { "clts",             { XX }, 0 },
2144   { "sysret%LQ",                { XX }, 0 },
2145   /* 08 */
2146   { "invd",             { XX }, 0 },
2147   { PREFIX_TABLE (PREFIX_0F09) },
2148   { Bad_Opcode },
2149   { "ud2",              { XX }, 0 },
2150   { Bad_Opcode },
2151   { REG_TABLE (REG_0F0D) },
2152   { "femms",            { XX }, 0 },
2153   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2154   /* 10 */
2155   { PREFIX_TABLE (PREFIX_0F10) },
2156   { PREFIX_TABLE (PREFIX_0F11) },
2157   { PREFIX_TABLE (PREFIX_0F12) },
2158   { "movlpX",           { Mq, XM }, PREFIX_OPCODE },
2159   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2160   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2161   { PREFIX_TABLE (PREFIX_0F16) },
2162   { "movhpX",           { Mq, XM }, PREFIX_OPCODE },
2163   /* 18 */
2164   { REG_TABLE (REG_0F18) },
2165   { "nopQ",             { Ev }, 0 },
2166   { PREFIX_TABLE (PREFIX_0F1A) },
2167   { PREFIX_TABLE (PREFIX_0F1B) },
2168   { PREFIX_TABLE (PREFIX_0F1C) },
2169   { "nopQ",             { Ev }, 0 },
2170   { PREFIX_TABLE (PREFIX_0F1E) },
2171   { "nopQ",             { Ev }, 0 },
2172   /* 20 */
2173   { "movZ",             { Em, Cm }, 0 },
2174   { "movZ",             { Em, Dm }, 0 },
2175   { "movZ",             { Cm, Em }, 0 },
2176   { "movZ",             { Dm, Em }, 0 },
2177   { X86_64_TABLE (X86_64_0F24) },
2178   { Bad_Opcode },
2179   { X86_64_TABLE (X86_64_0F26) },
2180   { Bad_Opcode },
2181   /* 28 */
2182   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2183   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2184   { PREFIX_TABLE (PREFIX_0F2A) },
2185   { PREFIX_TABLE (PREFIX_0F2B) },
2186   { PREFIX_TABLE (PREFIX_0F2C) },
2187   { PREFIX_TABLE (PREFIX_0F2D) },
2188   { PREFIX_TABLE (PREFIX_0F2E) },
2189   { PREFIX_TABLE (PREFIX_0F2F) },
2190   /* 30 */
2191   { "wrmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2192   { "rdtsc",            { XX }, PREFIX_REX2_ILLEGAL },
2193   { "rdmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2194   { "rdpmc",            { XX }, PREFIX_REX2_ILLEGAL },
2195   { "sysenter",         { SEP }, PREFIX_REX2_ILLEGAL },
2196   { "sysexit%LQ",       { SEP }, PREFIX_REX2_ILLEGAL },
2197   { Bad_Opcode },
2198   { "getsec",           { XX }, 0 },
2199   /* 38 */
2200   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2201   { Bad_Opcode },
2202   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2203   { Bad_Opcode },
2204   { Bad_Opcode },
2205   { Bad_Opcode },
2206   { Bad_Opcode },
2207   { Bad_Opcode },
2208   /* 40 */
2209   { "cmovoS",           { Gv, Ev }, 0 },
2210   { "cmovnoS",          { Gv, Ev }, 0 },
2211   { "cmovbS",           { Gv, Ev }, 0 },
2212   { "cmovaeS",          { Gv, Ev }, 0 },
2213   { "cmoveS",           { Gv, Ev }, 0 },
2214   { "cmovneS",          { Gv, Ev }, 0 },
2215   { "cmovbeS",          { Gv, Ev }, 0 },
2216   { "cmovaS",           { Gv, Ev }, 0 },
2217   /* 48 */
2218   { "cmovsS",           { Gv, Ev }, 0 },
2219   { "cmovnsS",          { Gv, Ev }, 0 },
2220   { "cmovpS",           { Gv, Ev }, 0 },
2221   { "cmovnpS",          { Gv, Ev }, 0 },
2222   { "cmovlS",           { Gv, Ev }, 0 },
2223   { "cmovgeS",          { Gv, Ev }, 0 },
2224   { "cmovleS",          { Gv, Ev }, 0 },
2225   { "cmovgS",           { Gv, Ev }, 0 },
2226   /* 50 */
2227   { "movmskpX",         { Gdq, Ux }, PREFIX_OPCODE },
2228   { PREFIX_TABLE (PREFIX_0F51) },
2229   { PREFIX_TABLE (PREFIX_0F52) },
2230   { PREFIX_TABLE (PREFIX_0F53) },
2231   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2232   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2233   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2234   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2235   /* 58 */
2236   { PREFIX_TABLE (PREFIX_0F58) },
2237   { PREFIX_TABLE (PREFIX_0F59) },
2238   { PREFIX_TABLE (PREFIX_0F5A) },
2239   { PREFIX_TABLE (PREFIX_0F5B) },
2240   { PREFIX_TABLE (PREFIX_0F5C) },
2241   { PREFIX_TABLE (PREFIX_0F5D) },
2242   { PREFIX_TABLE (PREFIX_0F5E) },
2243   { PREFIX_TABLE (PREFIX_0F5F) },
2244   /* 60 */
2245   { PREFIX_TABLE (PREFIX_0F60) },
2246   { PREFIX_TABLE (PREFIX_0F61) },
2247   { PREFIX_TABLE (PREFIX_0F62) },
2248   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2249   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2250   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2251   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2252   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2253   /* 68 */
2254   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2255   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2256   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2257   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2258   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2259   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2260   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2261   { PREFIX_TABLE (PREFIX_0F6F) },
2262   /* 70 */
2263   { PREFIX_TABLE (PREFIX_0F70) },
2264   { REG_TABLE (REG_0F71) },
2265   { REG_TABLE (REG_0F72) },
2266   { REG_TABLE (REG_0F73) },
2267   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2268   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2269   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2270   { "emms",             { XX }, PREFIX_OPCODE },
2271   /* 78 */
2272   { PREFIX_TABLE (PREFIX_0F78) },
2273   { PREFIX_TABLE (PREFIX_0F79) },
2274   { Bad_Opcode },
2275   { Bad_Opcode },
2276   { PREFIX_TABLE (PREFIX_0F7C) },
2277   { PREFIX_TABLE (PREFIX_0F7D) },
2278   { PREFIX_TABLE (PREFIX_0F7E) },
2279   { PREFIX_TABLE (PREFIX_0F7F) },
2280   /* 80 */
2281   { "joH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2282   { "jnoH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2283   { "jbH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2284   { "jaeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2285   { "jeH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2286   { "jneH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287   { "jbeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288   { "jaH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2289   /* 88 */
2290   { "jsH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2291   { "jnsH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2292   { "jpH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2293   { "jnpH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2294   { "jlH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2295   { "jgeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2296   { "jleH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2297   { "jgH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2298   /* 90 */
2299   { "seto",             { Eb }, 0 },
2300   { "setno",            { Eb }, 0 },
2301   { "setb",             { Eb }, 0 },
2302   { "setae",            { Eb }, 0 },
2303   { "sete",             { Eb }, 0 },
2304   { "setne",            { Eb }, 0 },
2305   { "setbe",            { Eb }, 0 },
2306   { "seta",             { Eb }, 0 },
2307   /* 98 */
2308   { "sets",             { Eb }, 0 },
2309   { "setns",            { Eb }, 0 },
2310   { "setp",             { Eb }, 0 },
2311   { "setnp",            { Eb }, 0 },
2312   { "setl",             { Eb }, 0 },
2313   { "setge",            { Eb }, 0 },
2314   { "setle",            { Eb }, 0 },
2315   { "setg",             { Eb }, 0 },
2316   /* a0 */
2317   { "pushP",            { fs }, 0 },
2318   { "popP",             { fs }, 0 },
2319   { "cpuid",            { XX }, 0 },
2320   { "btS",              { Ev, Gv }, 0 },
2321   { "shldS",            { Ev, Gv, Ib }, 0 },
2322   { "shldS",            { Ev, Gv, CL }, 0 },
2323   { REG_TABLE (REG_0FA6) },
2324   { REG_TABLE (REG_0FA7) },
2325   /* a8 */
2326   { "pushP",            { gs }, 0 },
2327   { "popP",             { gs }, 0 },
2328   { "rsm",              { XX }, 0 },
2329   { "btsS",             { Evh1, Gv }, 0 },
2330   { "shrdS",            { Ev, Gv, Ib }, 0 },
2331   { "shrdS",            { Ev, Gv, CL }, 0 },
2332   { REG_TABLE (REG_0FAE) },
2333   { "imulS",            { Gv, Ev }, 0 },
2334   /* b0 */
2335   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2336   { "cmpxchgS",         { Evh1, Gv }, 0 },
2337   { "lssS",             { Gv, Mp }, 0 },
2338   { "btrS",             { Evh1, Gv }, 0 },
2339   { "lfsS",             { Gv, Mp }, 0 },
2340   { "lgsS",             { Gv, Mp }, 0 },
2341   { "movz{bR|x}",       { Gv, Eb }, 0 },
2342   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2343   /* b8 */
2344   { PREFIX_TABLE (PREFIX_0FB8) },
2345   { "ud1S",             { Gv, Ev }, 0 },
2346   { REG_TABLE (REG_0FBA) },
2347   { "btcS",             { Evh1, Gv }, 0 },
2348   { PREFIX_TABLE (PREFIX_0FBC) },
2349   { PREFIX_TABLE (PREFIX_0FBD) },
2350   { "movs{bR|x}",       { Gv, Eb }, 0 },
2351   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2352   /* c0 */
2353   { "xaddB",            { Ebh1, Gb }, 0 },
2354   { "xaddS",            { Evh1, Gv }, 0 },
2355   { PREFIX_TABLE (PREFIX_0FC2) },
2356   { "movntiS",          { Mdq, Gdq }, PREFIX_OPCODE },
2357   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2358   { "pextrw",           { Gd, Nq, Ib }, PREFIX_OPCODE },
2359   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2360   { REG_TABLE (REG_0FC7) },
2361   /* c8 */
2362   { "bswap",            { RMeAX }, 0 },
2363   { "bswap",            { RMeCX }, 0 },
2364   { "bswap",            { RMeDX }, 0 },
2365   { "bswap",            { RMeBX }, 0 },
2366   { "bswap",            { RMeSP }, 0 },
2367   { "bswap",            { RMeBP }, 0 },
2368   { "bswap",            { RMeSI }, 0 },
2369   { "bswap",            { RMeDI }, 0 },
2370   /* d0 */
2371   { PREFIX_TABLE (PREFIX_0FD0) },
2372   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2373   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2374   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2375   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2376   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2377   { PREFIX_TABLE (PREFIX_0FD6) },
2378   { "pmovmskb",         { Gdq, Nq }, PREFIX_OPCODE },
2379   /* d8 */
2380   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2381   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2382   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2383   { "pand",             { MX, EM }, PREFIX_OPCODE },
2384   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2385   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2386   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2387   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2388   /* e0 */
2389   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2390   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2391   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2392   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2393   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2394   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2395   { PREFIX_TABLE (PREFIX_0FE6) },
2396   { PREFIX_TABLE (PREFIX_0FE7) },
2397   /* e8 */
2398   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2399   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2400   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2401   { "por",              { MX, EM }, PREFIX_OPCODE },
2402   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2403   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2404   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2405   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2406   /* f0 */
2407   { PREFIX_TABLE (PREFIX_0FF0) },
2408   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2409   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2410   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2411   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2412   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2413   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2414   { PREFIX_TABLE (PREFIX_0FF7) },
2415   /* f8 */
2416   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2417   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2418   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2419   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2420   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2421   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2422   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2423   { "ud0S",             { Gv, Ev }, 0 },
2424 };
2425
2426 static const bool onebyte_has_modrm[256] = {
2427   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2428   /*       -------------------------------        */
2429   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2430   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2431   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2432   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2433   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2434   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2435   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2436   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2437   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2438   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2439   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2440   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2441   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2442   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2443   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2444   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2445   /*       -------------------------------        */
2446   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2447 };
2448
2449 static const bool twobyte_has_modrm[256] = {
2450   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2451   /*       -------------------------------        */
2452   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2453   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2454   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2455   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2456   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2457   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2458   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2459   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2460   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2461   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2462   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2463   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2464   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2465   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2466   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2467   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2468   /*       -------------------------------        */
2469   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2470 };
2471
2472
2473 struct op
2474   {
2475     const char *name;
2476     unsigned int len;
2477   };
2478
2479 /* If we are accessing mod/rm/reg without need_modrm set, then the
2480    values are stale.  Hitting this abort likely indicates that you
2481    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2482 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2483
2484 static const char intel_index16[][6] = {
2485   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2486 };
2487
2488 static const char att_names64[][8] = {
2489   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2490   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2491   "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2492   "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2493 };
2494 static const char att_names32[][8] = {
2495   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2496   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2497   "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2498   "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2499 };
2500 static const char att_names16[][8] = {
2501   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2502   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2503   "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2504   "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2505 };
2506 static const char att_names8[][8] = {
2507   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2508 };
2509 static const char att_names8rex[][8] = {
2510   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2511   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2512   "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2513   "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2514 };
2515 static const char att_names_seg[][4] = {
2516   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2517 };
2518 static const char att_index64[] = "%riz";
2519 static const char att_index32[] = "%eiz";
2520 static const char att_index16[][8] = {
2521   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2522 };
2523
2524 static const char att_names_mm[][8] = {
2525   "%mm0", "%mm1", "%mm2", "%mm3",
2526   "%mm4", "%mm5", "%mm6", "%mm7"
2527 };
2528
2529 static const char att_names_bnd[][8] = {
2530   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2531 };
2532
2533 static const char att_names_xmm[][8] = {
2534   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2535   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2536   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2537   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2538   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2539   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2540   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2541   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2542 };
2543
2544 static const char att_names_ymm[][8] = {
2545   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2546   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2547   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2548   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2549   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2550   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2551   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2552   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2553 };
2554
2555 static const char att_names_zmm[][8] = {
2556   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2557   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2558   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2559   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2560   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2561   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2562   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2563   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2564 };
2565
2566 static const char att_names_tmm[][8] = {
2567   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2568   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2569 };
2570
2571 static const char att_names_mask[][8] = {
2572   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2573 };
2574
2575 static const char *const names_rounding[] =
2576 {
2577   "{rn-",
2578   "{rd-",
2579   "{ru-",
2580   "{rz-"
2581 };
2582
2583 static const struct dis386 reg_table[][8] = {
2584   /* REG_80 */
2585   {
2586     { "addA",   { Ebh1, Ib }, 0 },
2587     { "orA",    { Ebh1, Ib }, 0 },
2588     { "adcA",   { Ebh1, Ib }, 0 },
2589     { "sbbA",   { Ebh1, Ib }, 0 },
2590     { "andA",   { Ebh1, Ib }, 0 },
2591     { "subA",   { Ebh1, Ib }, 0 },
2592     { "xorA",   { Ebh1, Ib }, 0 },
2593     { "cmpA",   { Eb, Ib }, 0 },
2594   },
2595   /* REG_81 */
2596   {
2597     { "addQ",   { Evh1, Iv }, 0 },
2598     { "orQ",    { Evh1, Iv }, 0 },
2599     { "adcQ",   { Evh1, Iv }, 0 },
2600     { "sbbQ",   { Evh1, Iv }, 0 },
2601     { "andQ",   { Evh1, Iv }, 0 },
2602     { "subQ",   { Evh1, Iv }, 0 },
2603     { "xorQ",   { Evh1, Iv }, 0 },
2604     { "cmpQ",   { Ev, Iv }, 0 },
2605   },
2606   /* REG_83 */
2607   {
2608     { "addQ",   { Evh1, sIb }, 0 },
2609     { "orQ",    { Evh1, sIb }, 0 },
2610     { "adcQ",   { Evh1, sIb }, 0 },
2611     { "sbbQ",   { Evh1, sIb }, 0 },
2612     { "andQ",   { Evh1, sIb }, 0 },
2613     { "subQ",   { Evh1, sIb }, 0 },
2614     { "xorQ",   { Evh1, sIb }, 0 },
2615     { "cmpQ",   { Ev, sIb }, 0 },
2616   },
2617   /* REG_8F */
2618   {
2619     { "pop{P|}", { stackEv }, 0 },
2620     { XOP_8F_TABLE () },
2621     { Bad_Opcode },
2622     { Bad_Opcode },
2623     { Bad_Opcode },
2624     { XOP_8F_TABLE () },
2625   },
2626   /* REG_C0 */
2627   {
2628     { "%NFrolA",        { VexGb, Eb, Ib }, NO_PREFIX },
2629     { "%NFrorA",        { VexGb, Eb, Ib }, NO_PREFIX },
2630     { "rclA",   { VexGb, Eb, Ib }, NO_PREFIX },
2631     { "rcrA",   { VexGb, Eb, Ib }, NO_PREFIX },
2632     { "%NFshlA",        { VexGb, Eb, Ib }, NO_PREFIX },
2633     { "%NFshrA",        { VexGb, Eb, Ib }, NO_PREFIX },
2634     { "%NFshlA",        { VexGb, Eb, Ib }, NO_PREFIX },
2635     { "%NFsarA",        { VexGb, Eb, Ib }, NO_PREFIX },
2636   },
2637   /* REG_C1 */
2638   {
2639     { "%NFrolQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2640     { "%NFrorQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2641     { "rclQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2642     { "rcrQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2643     { "%NFshlQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2644     { "%NFshrQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2645     { "%NFshlQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2646     { "%NFsarQ",        { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2647   },
2648   /* REG_C6 */
2649   {
2650     { "movA",   { Ebh3, Ib }, 0 },
2651     { Bad_Opcode },
2652     { Bad_Opcode },
2653     { Bad_Opcode },
2654     { Bad_Opcode },
2655     { Bad_Opcode },
2656     { Bad_Opcode },
2657     { RM_TABLE (RM_C6_REG_7) },
2658   },
2659   /* REG_C7 */
2660   {
2661     { "movQ",   { Evh3, Iv }, 0 },
2662     { Bad_Opcode },
2663     { Bad_Opcode },
2664     { Bad_Opcode },
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { Bad_Opcode },
2668     { RM_TABLE (RM_C7_REG_7) },
2669   },
2670   /* REG_D0 */
2671   {
2672     { "%NFrolA",        { VexGb, Eb, I1 }, NO_PREFIX },
2673     { "%NFrorA",        { VexGb, Eb, I1 }, NO_PREFIX },
2674     { "rclA",   { VexGb, Eb, I1 }, NO_PREFIX },
2675     { "rcrA",   { VexGb, Eb, I1 }, NO_PREFIX },
2676     { "%NFshlA",        { VexGb, Eb, I1 }, NO_PREFIX },
2677     { "%NFshrA",        { VexGb, Eb, I1 }, NO_PREFIX },
2678     { "%NFshlA",        { VexGb, Eb, I1 }, NO_PREFIX },
2679     { "%NFsarA",        { VexGb, Eb, I1 }, NO_PREFIX },
2680   },
2681   /* REG_D1 */
2682   {
2683     { "%NFrolQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2684     { "%NFrorQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2685     { "rclQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2686     { "rcrQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2687     { "%NFshlQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2688     { "%NFshrQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2689     { "%NFshlQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2690     { "%NFsarQ",        { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2691   },
2692   /* REG_D2 */
2693   {
2694     { "%NFrolA",        { VexGb, Eb, CL }, NO_PREFIX },
2695     { "%NFrorA",        { VexGb, Eb, CL }, NO_PREFIX },
2696     { "rclA",   { VexGb, Eb, CL }, NO_PREFIX },
2697     { "rcrA",   { VexGb, Eb, CL }, NO_PREFIX },
2698     { "%NFshlA",        { VexGb, Eb, CL }, NO_PREFIX },
2699     { "%NFshrA",        { VexGb, Eb, CL }, NO_PREFIX },
2700     { "%NFshlA",        { VexGb, Eb, CL }, NO_PREFIX },
2701     { "%NFsarA",        { VexGb, Eb, CL }, NO_PREFIX },
2702   },
2703   /* REG_D3 */
2704   {
2705     { "%NFrolQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2706     { "%NFrorQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2707     { "rclQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2708     { "rcrQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2709     { "%NFshlQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2710     { "%NFshrQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2711     { "%NFshlQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2712     { "%NFsarQ",        { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2713   },
2714   /* REG_F6 */
2715   {
2716     { "testA",  { Eb, Ib }, 0 },
2717     { "testA",  { Eb, Ib }, 0 },
2718     { "notA",   { Ebh1 }, 0 },
2719     { "negA",   { Ebh1 }, 0 },
2720     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2721     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2722     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2723     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2724   },
2725   /* REG_F7 */
2726   {
2727     { "testQ",  { Ev, Iv }, 0 },
2728     { "testQ",  { Ev, Iv }, 0 },
2729     { "notQ",   { Evh1 }, 0 },
2730     { "negQ",   { Evh1 }, 0 },
2731     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2732     { "imulQ",  { Ev }, 0 },
2733     { "divQ",   { Ev }, 0 },
2734     { "idivQ",  { Ev }, 0 },
2735   },
2736   /* REG_FE */
2737   {
2738     { "incA",   { Ebh1 }, 0 },
2739     { "decA",   { Ebh1 }, 0 },
2740   },
2741   /* REG_FF */
2742   {
2743     { "incQ",   { Evh1 }, 0 },
2744     { "decQ",   { Evh1 }, 0 },
2745     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2746     { "{l|}call^", { indirEp }, 0 },
2747     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2748     { "{l|}jmp^", { indirEp }, 0 },
2749     { "push{P|}", { stackEv }, 0 },
2750     { Bad_Opcode },
2751   },
2752   /* REG_0F00 */
2753   {
2754     { "sldtD",  { Sv }, 0 },
2755     { "strD",   { Sv }, 0 },
2756     { "lldtD",  { Sv }, 0 },
2757     { "ltrD",   { Sv }, 0 },
2758     { "verrD",  { Sv }, 0 },
2759     { "verwD",  { Sv }, 0 },
2760     { X86_64_TABLE (X86_64_0F00_REG_6) },
2761     { Bad_Opcode },
2762   },
2763   /* REG_0F01 */
2764   {
2765     { MOD_TABLE (MOD_0F01_REG_0) },
2766     { MOD_TABLE (MOD_0F01_REG_1) },
2767     { MOD_TABLE (MOD_0F01_REG_2) },
2768     { MOD_TABLE (MOD_0F01_REG_3) },
2769     { "smswD",  { Sv }, 0 },
2770     { MOD_TABLE (MOD_0F01_REG_5) },
2771     { "lmsw",   { Ew }, 0 },
2772     { MOD_TABLE (MOD_0F01_REG_7) },
2773   },
2774   /* REG_0F0D */
2775   {
2776     { "prefetch",       { Mb }, 0 },
2777     { "prefetchw",      { Mb }, 0 },
2778     { "prefetchwt1",    { Mb }, 0 },
2779     { "prefetch",       { Mb }, 0 },
2780     { "prefetch",       { Mb }, 0 },
2781     { "prefetch",       { Mb }, 0 },
2782     { "prefetch",       { Mb }, 0 },
2783     { "prefetch",       { Mb }, 0 },
2784   },
2785   /* REG_0F18 */
2786   {
2787     { MOD_TABLE (MOD_0F18_REG_0) },
2788     { MOD_TABLE (MOD_0F18_REG_1) },
2789     { MOD_TABLE (MOD_0F18_REG_2) },
2790     { MOD_TABLE (MOD_0F18_REG_3) },
2791     { "nopQ",           { Ev }, 0 },
2792     { "nopQ",           { Ev }, 0 },
2793     { MOD_TABLE (MOD_0F18_REG_6) },
2794     { MOD_TABLE (MOD_0F18_REG_7) },
2795   },
2796   /* REG_0F1C_P_0_MOD_0 */
2797   {
2798     { "cldemote",       { Mb }, 0 },
2799     { "nopQ",           { Ev }, 0 },
2800     { "nopQ",           { Ev }, 0 },
2801     { "nopQ",           { Ev }, 0 },
2802     { "nopQ",           { Ev }, 0 },
2803     { "nopQ",           { Ev }, 0 },
2804     { "nopQ",           { Ev }, 0 },
2805     { "nopQ",           { Ev }, 0 },
2806   },
2807   /* REG_0F1E_P_1_MOD_3 */
2808   {
2809     { "nopQ",           { Ev }, PREFIX_IGNORED },
2810     { "rdsspK",         { Edq }, 0 },
2811     { "nopQ",           { Ev }, PREFIX_IGNORED },
2812     { "nopQ",           { Ev }, PREFIX_IGNORED },
2813     { "nopQ",           { Ev }, PREFIX_IGNORED },
2814     { "nopQ",           { Ev }, PREFIX_IGNORED },
2815     { "nopQ",           { Ev }, PREFIX_IGNORED },
2816     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2817   },
2818   /* REG_0F38D8_PREFIX_1 */
2819   {
2820     { "aesencwide128kl",        { M }, 0 },
2821     { "aesdecwide128kl",        { M }, 0 },
2822     { "aesencwide256kl",        { M }, 0 },
2823     { "aesdecwide256kl",        { M }, 0 },
2824   },
2825   /* REG_0F3A0F_P_1 */
2826   {
2827     { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2828   },
2829   /* REG_0F71 */
2830   {
2831     { Bad_Opcode },
2832     { Bad_Opcode },
2833     { "psrlw",          { Nq, Ib }, PREFIX_OPCODE },
2834     { Bad_Opcode },
2835     { "psraw",          { Nq, Ib }, PREFIX_OPCODE },
2836     { Bad_Opcode },
2837     { "psllw",          { Nq, Ib }, PREFIX_OPCODE },
2838   },
2839   /* REG_0F72 */
2840   {
2841     { Bad_Opcode },
2842     { Bad_Opcode },
2843     { "psrld",          { Nq, Ib }, PREFIX_OPCODE },
2844     { Bad_Opcode },
2845     { "psrad",          { Nq, Ib }, PREFIX_OPCODE },
2846     { Bad_Opcode },
2847     { "pslld",          { Nq, Ib }, PREFIX_OPCODE },
2848   },
2849   /* REG_0F73 */
2850   {
2851     { Bad_Opcode },
2852     { Bad_Opcode },
2853     { "psrlq",          { Nq, Ib }, PREFIX_OPCODE },
2854     { "psrldq",         { Ux, Ib }, PREFIX_DATA },
2855     { Bad_Opcode },
2856     { Bad_Opcode },
2857     { "psllq",          { Nq, Ib }, PREFIX_OPCODE },
2858     { "pslldq",         { Ux, Ib }, PREFIX_DATA },
2859   },
2860   /* REG_0FA6 */
2861   {
2862     { PREFIX_TABLE (PREFIX_0FA6_REG_0) },
2863     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2864     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2865     { Bad_Opcode },
2866     { Bad_Opcode },
2867     { PREFIX_TABLE (PREFIX_0FA6_REG_5) },
2868   },
2869   /* REG_0FA7 */
2870   {
2871     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2872     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2873     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2874     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2875     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2876     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2877     { PREFIX_TABLE (PREFIX_0FA7_REG_6) },
2878   },
2879   /* REG_0FAE */
2880   {
2881     { MOD_TABLE (MOD_0FAE_REG_0) },
2882     { MOD_TABLE (MOD_0FAE_REG_1) },
2883     { MOD_TABLE (MOD_0FAE_REG_2) },
2884     { MOD_TABLE (MOD_0FAE_REG_3) },
2885     { MOD_TABLE (MOD_0FAE_REG_4) },
2886     { MOD_TABLE (MOD_0FAE_REG_5) },
2887     { MOD_TABLE (MOD_0FAE_REG_6) },
2888     { MOD_TABLE (MOD_0FAE_REG_7) },
2889   },
2890   /* REG_0FBA */
2891   {
2892     { Bad_Opcode },
2893     { Bad_Opcode },
2894     { Bad_Opcode },
2895     { Bad_Opcode },
2896     { "btQ",    { Ev, Ib }, 0 },
2897     { "btsQ",   { Evh1, Ib }, 0 },
2898     { "btrQ",   { Evh1, Ib }, 0 },
2899     { "btcQ",   { Evh1, Ib }, 0 },
2900   },
2901   /* REG_0FC7 */
2902   {
2903     { Bad_Opcode },
2904     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2905     { Bad_Opcode },
2906     { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2907     { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2908     { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2909     { MOD_TABLE (MOD_0FC7_REG_6) },
2910     { MOD_TABLE (MOD_0FC7_REG_7) },
2911   },
2912   /* REG_VEX_0F71 */
2913   {
2914     { Bad_Opcode },
2915     { Bad_Opcode },
2916     { "vpsrlw",         { Vex, Ux, Ib }, PREFIX_DATA },
2917     { Bad_Opcode },
2918     { "vpsraw",         { Vex, Ux, Ib }, PREFIX_DATA },
2919     { Bad_Opcode },
2920     { "vpsllw",         { Vex, Ux, Ib }, PREFIX_DATA },
2921   },
2922   /* REG_VEX_0F72 */
2923   {
2924     { Bad_Opcode },
2925     { Bad_Opcode },
2926     { "vpsrld",         { Vex, Ux, Ib }, PREFIX_DATA },
2927     { Bad_Opcode },
2928     { "vpsrad",         { Vex, Ux, Ib }, PREFIX_DATA },
2929     { Bad_Opcode },
2930     { "vpslld",         { Vex, Ux, Ib }, PREFIX_DATA },
2931   },
2932   /* REG_VEX_0F73 */
2933   {
2934     { Bad_Opcode },
2935     { Bad_Opcode },
2936     { "vpsrlq",         { Vex, Ux, Ib }, PREFIX_DATA },
2937     { "vpsrldq",        { Vex, Ux, Ib }, PREFIX_DATA },
2938     { Bad_Opcode },
2939     { Bad_Opcode },
2940     { "vpsllq",         { Vex, Ux, Ib }, PREFIX_DATA },
2941     { "vpslldq",        { Vex, Ux, Ib }, PREFIX_DATA },
2942   },
2943   /* REG_VEX_0FAE */
2944   {
2945     { Bad_Opcode },
2946     { Bad_Opcode },
2947     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2948     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2949   },
2950   /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2951   {
2952     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2953   },
2954   /* REG_VEX_0F38F3_L_0_P_0 */
2955   {
2956     { Bad_Opcode },
2957     { "%NFblsrS",               { VexGdq, Edq }, 0 },
2958     { "%NFblsmskS",             { VexGdq, Edq }, 0 },
2959     { "%NFblsiS",               { VexGdq, Edq }, 0 },
2960   },
2961   /* REG_VEX_MAP7_F8_L_0_W_0 */
2962   {
2963     { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2964   },
2965   /* REG_XOP_09_01_L_0 */
2966   {
2967     { Bad_Opcode },
2968     { "blcfill",        { VexGdq, Edq }, 0 },
2969     { "blsfill",        { VexGdq, Edq }, 0 },
2970     { "blcs",   { VexGdq, Edq }, 0 },
2971     { "tzmsk",  { VexGdq, Edq }, 0 },
2972     { "blcic",  { VexGdq, Edq }, 0 },
2973     { "blsic",  { VexGdq, Edq }, 0 },
2974     { "t1mskc", { VexGdq, Edq }, 0 },
2975   },
2976   /* REG_XOP_09_02_L_0 */
2977   {
2978     { Bad_Opcode },
2979     { "blcmsk", { VexGdq, Edq }, 0 },
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { Bad_Opcode },
2983     { Bad_Opcode },
2984     { "blci",   { VexGdq, Edq }, 0 },
2985   },
2986   /* REG_XOP_09_12_L_0 */
2987   {
2988     { "llwpcb", { Rdq }, 0 },
2989     { "slwpcb", { Rdq }, 0 },
2990   },
2991   /* REG_XOP_0A_12_L_0 */
2992   {
2993     { "lwpins", { VexGdq, Ed, Id }, 0 },
2994     { "lwpval", { VexGdq, Ed, Id }, 0 },
2995   },
2996
2997 #include "i386-dis-evex-reg.h"
2998 };
2999
3000 static const struct dis386 prefix_table[][4] = {
3001   /* PREFIX_90 */
3002   {
3003     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3004     { "pause", { XX }, 0 },
3005     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3006     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3007   },
3008
3009   /* PREFIX_0F00_REG_6_X86_64 */
3010   {
3011     { Bad_Opcode },
3012     { Bad_Opcode },
3013     { Bad_Opcode },
3014     { "lkgsD", { Sv }, 0 },
3015   },
3016
3017   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3018   {
3019     { "wrmsrns",        { Skip_MODRM }, 0 },
3020     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3021     { Bad_Opcode },
3022     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3023   },
3024
3025   /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3026   {
3027     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3028   },
3029
3030   /* PREFIX_0F01_REG_1_RM_2 */
3031   {
3032     { "clac",           { Skip_MODRM }, 0 },
3033     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3034     { Bad_Opcode },
3035     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3036   },
3037
3038   /* PREFIX_0F01_REG_1_RM_4 */
3039   {
3040     { Bad_Opcode },
3041     { Bad_Opcode },
3042     { "tdcall",         { Skip_MODRM }, 0 },
3043     { Bad_Opcode },
3044   },
3045
3046   /* PREFIX_0F01_REG_1_RM_5 */
3047   {
3048     { Bad_Opcode },
3049     { Bad_Opcode },
3050     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3051     { Bad_Opcode },
3052   },
3053
3054   /* PREFIX_0F01_REG_1_RM_6 */
3055   {
3056     { Bad_Opcode },
3057     { Bad_Opcode },
3058     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3059     { Bad_Opcode },
3060   },
3061
3062   /* PREFIX_0F01_REG_1_RM_7 */
3063   {
3064     { "encls",          { Skip_MODRM }, 0 },
3065     { Bad_Opcode },
3066     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3067     { Bad_Opcode },
3068   },
3069
3070   /* PREFIX_0F01_REG_3_RM_1 */
3071   {
3072     { "vmmcall",        { Skip_MODRM }, 0 },
3073     { "vmgexit",        { Skip_MODRM }, 0 },
3074     { Bad_Opcode },
3075     { "vmgexit",        { Skip_MODRM }, 0 },
3076   },
3077
3078   /* PREFIX_0F01_REG_5_MOD_0 */
3079   {
3080     { Bad_Opcode },
3081     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3082   },
3083
3084   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3085   {
3086     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3087     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3088     { Bad_Opcode },
3089     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3090   },
3091
3092   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3093   {
3094     { Bad_Opcode },
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3098   },
3099
3100   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3101   {
3102     { Bad_Opcode },
3103     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3104   },
3105
3106   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3107   {
3108     { Bad_Opcode },
3109     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3110   },
3111
3112   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3113   {
3114     { Bad_Opcode },
3115     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3116   },
3117
3118   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3119   {
3120     { "rdpkru", { Skip_MODRM }, 0 },
3121     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3122   },
3123
3124   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3125   {
3126     { "wrpkru", { Skip_MODRM }, 0 },
3127     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3128   },
3129
3130   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3131   {
3132     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3133     { "mcommit",        { Skip_MODRM }, 0 },
3134   },
3135
3136   /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3137   {
3138     { "rdpru", { Skip_MODRM }, 0 },
3139     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3140   },
3141
3142   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3143   {
3144     { "invlpgb",        { Skip_MODRM }, 0 },
3145     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3146     { Bad_Opcode },
3147     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3148   },
3149
3150   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3151   {
3152     { "tlbsync",        { Skip_MODRM }, 0 },
3153     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3154     { Bad_Opcode },
3155     { "pvalidate",      { Skip_MODRM }, 0 },
3156   },
3157
3158   /* PREFIX_0F09 */
3159   {
3160     { "wbinvd",   { XX }, 0 },
3161     { "wbnoinvd", { XX }, 0 },
3162   },
3163
3164   /* PREFIX_0F10 */
3165   {
3166     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3167     { "%XEVmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3168     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3169     { "%XEVmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3170   },
3171
3172   /* PREFIX_0F11 */
3173   {
3174     { "%XEVmovupX",     { EXxS, XM }, 0 },
3175     { "%XEVmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3176     { "%XEVmovupX",     { EXxS, XM }, 0 },
3177     { "%XEVmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3178   },
3179
3180   /* PREFIX_0F12 */
3181   {
3182     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3183     { "movsldup",       { XM, EXx }, 0 },
3184     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
3185     { "movddup",        { XM, EXq }, 0 },
3186   },
3187
3188   /* PREFIX_0F16 */
3189   {
3190     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3191     { "movshdup",       { XM, EXx }, 0 },
3192     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
3193   },
3194
3195   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3196   {
3197     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3198     { "nopQ",           { Ev }, 0 },
3199     { "nopQ",           { Ev }, 0 },
3200     { "nopQ",           { Ev }, 0 },
3201   },
3202
3203   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3204   {
3205     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3206     { "nopQ",           { Ev }, 0 },
3207     { "nopQ",           { Ev }, 0 },
3208     { "nopQ",           { Ev }, 0 },
3209   },
3210
3211   /* PREFIX_0F1A */
3212   {
3213     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3214     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3215     { "bndmov", { Gbnd, Ebnd }, 0 },
3216     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3217   },
3218
3219   /* PREFIX_0F1B */
3220   {
3221     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3222     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3223     { "bndmov", { EbndS, Gbnd }, 0 },
3224     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3225   },
3226
3227   /* PREFIX_0F1C */
3228   {
3229     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3230     { "nopQ",   { Ev }, PREFIX_IGNORED },
3231     { "nopQ",   { Ev }, 0 },
3232     { "nopQ",   { Ev }, PREFIX_IGNORED },
3233   },
3234
3235   /* PREFIX_0F1E */
3236   {
3237     { "nopQ",   { Ev }, 0 },
3238     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3239     { "nopQ",   { Ev }, 0 },
3240     { NULL,     { XX }, PREFIX_IGNORED },
3241   },
3242
3243   /* PREFIX_0F2A */
3244   {
3245     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3246     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3247     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3248     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3249   },
3250
3251   /* PREFIX_0F2B */
3252   {
3253     { "movntps", { Mx, XM }, 0 },
3254     { "movntss", { Md, XM }, 0 },
3255     { "movntpd", { Mx, XM }, 0 },
3256     { "movntsd", { Mq, XM }, 0 },
3257   },
3258
3259   /* PREFIX_0F2C */
3260   {
3261     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3262     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3263     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3264     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3265   },
3266
3267   /* PREFIX_0F2D */
3268   {
3269     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3270     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3271     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3272     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3273   },
3274
3275   /* PREFIX_0F2E */
3276   {
3277     { "%XEVucomisYX",   { XMScalar, EXd, EXxEVexS }, 0 },
3278     { Bad_Opcode },
3279     { "%XEVucomisYX",   { XMScalar, EXq, EXxEVexS }, 0 },
3280   },
3281
3282   /* PREFIX_0F2F */
3283   {
3284     { "%XEVcomisYX",    { XMScalar, EXd, EXxEVexS }, 0 },
3285     { Bad_Opcode },
3286     { "%XEVcomisYX",    { XMScalar, EXq, EXxEVexS }, 0 },
3287   },
3288
3289   /* PREFIX_0F51 */
3290   {
3291     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3292     { "%XEVsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3293     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3294     { "%XEVsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3295   },
3296
3297   /* PREFIX_0F52 */
3298   {
3299     { "Vrsqrtps",       { XM, EXx }, 0 },
3300     { "Vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3301   },
3302
3303   /* PREFIX_0F53 */
3304   {
3305     { "Vrcpps",         { XM, EXx }, 0 },
3306     { "Vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3307   },
3308
3309   /* PREFIX_0F58 */
3310   {
3311     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3312     { "%XEVadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3313     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3314     { "%XEVadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3315   },
3316
3317   /* PREFIX_0F59 */
3318   {
3319     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3320     { "%XEVmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3321     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3322     { "%XEVmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3323   },
3324
3325   /* PREFIX_0F5A */
3326   {
3327     { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3328     { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3329     { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3330     { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3331   },
3332
3333   /* PREFIX_0F5B */
3334   {
3335     { "Vcvtdq2ps",      { XM, EXx }, 0 },
3336     { "Vcvttps2dq",     { XM, EXx }, 0 },
3337     { "Vcvtps2dq",      { XM, EXx }, 0 },
3338   },
3339
3340   /* PREFIX_0F5C */
3341   {
3342     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3343     { "%XEVsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3344     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3345     { "%XEVsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3346   },
3347
3348   /* PREFIX_0F5D */
3349   {
3350     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3351     { "%XEVmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3352     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3353     { "%XEVmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3354   },
3355
3356   /* PREFIX_0F5E */
3357   {
3358     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3359     { "%XEVdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3360     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3361     { "%XEVdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3362   },
3363
3364   /* PREFIX_0F5F */
3365   {
3366     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3367     { "%XEVmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3368     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3369     { "%XEVmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3370   },
3371
3372   /* PREFIX_0F60 */
3373   {
3374     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3375     { Bad_Opcode },
3376     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3377   },
3378
3379   /* PREFIX_0F61 */
3380   {
3381     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3382     { Bad_Opcode },
3383     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3384   },
3385
3386   /* PREFIX_0F62 */
3387   {
3388     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3389     { Bad_Opcode },
3390     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3391   },
3392
3393   /* PREFIX_0F6F */
3394   {
3395     { "movq",   { MX, EM }, PREFIX_OPCODE },
3396     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3397     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3398   },
3399
3400   /* PREFIX_0F70 */
3401   {
3402     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3403     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3404     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3405     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3406   },
3407
3408   /* PREFIX_0F78 */
3409   {
3410     {"vmread",  { Em, Gm }, 0 },
3411     { Bad_Opcode },
3412     {"extrq",   { Uxmm, Ib, Ib }, 0 },
3413     {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3414   },
3415
3416   /* PREFIX_0F79 */
3417   {
3418     {"vmwrite", { Gm, Em }, 0 },
3419     { Bad_Opcode },
3420     {"extrq",   { XM, Uxmm }, 0 },
3421     {"insertq", { XM, Uxmm }, 0 },
3422   },
3423
3424   /* PREFIX_0F7C */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "Vhaddpd",        { XM, Vex, EXx }, 0 },
3429     { "Vhaddps",        { XM, Vex, EXx }, 0 },
3430   },
3431
3432   /* PREFIX_0F7D */
3433   {
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { "Vhsubpd",        { XM, Vex, EXx }, 0 },
3437     { "Vhsubps",        { XM, Vex, EXx }, 0 },
3438   },
3439
3440   /* PREFIX_0F7E */
3441   {
3442     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3443     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3444     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3445   },
3446
3447   /* PREFIX_0F7F */
3448   {
3449     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3450     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3451     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3452   },
3453
3454   /* PREFIX_0FA6_REG_0 */
3455   {
3456     { Bad_Opcode },
3457     { "montmul",        { { MONTMUL_Fixup, 0 } }, 0},
3458     { Bad_Opcode },
3459     { "sm2",    { Skip_MODRM }, 0 },
3460   },
3461
3462   /* PREFIX_0FA6_REG_5 */
3463   {
3464     { Bad_Opcode },
3465     { "sm3",    { Skip_MODRM }, 0 },
3466   },
3467
3468   /* PREFIX_0FA7_REG_6 */
3469   {
3470     { Bad_Opcode },
3471     { "sm4",    { Skip_MODRM }, 0 },
3472   },
3473
3474   /* PREFIX_0FAE_REG_0_MOD_3 */
3475   {
3476     { Bad_Opcode },
3477     { "rdfsbase", { Ev }, 0 },
3478   },
3479
3480   /* PREFIX_0FAE_REG_1_MOD_3 */
3481   {
3482     { Bad_Opcode },
3483     { "rdgsbase", { Ev }, 0 },
3484   },
3485
3486   /* PREFIX_0FAE_REG_2_MOD_3 */
3487   {
3488     { Bad_Opcode },
3489     { "wrfsbase", { Ev }, 0 },
3490   },
3491
3492   /* PREFIX_0FAE_REG_3_MOD_3 */
3493   {
3494     { Bad_Opcode },
3495     { "wrgsbase", { Ev }, 0 },
3496   },
3497
3498   /* PREFIX_0FAE_REG_4_MOD_0 */
3499   {
3500     { "xsave",  { FXSAVE }, PREFIX_REX2_ILLEGAL },
3501     { "ptwrite{%LQ|}", { Edq }, 0 },
3502   },
3503
3504   /* PREFIX_0FAE_REG_4_MOD_3 */
3505   {
3506     { Bad_Opcode },
3507     { "ptwrite{%LQ|}", { Edq }, 0 },
3508   },
3509
3510   /* PREFIX_0FAE_REG_5_MOD_3 */
3511   {
3512     { "lfence",         { Skip_MODRM }, 0 },
3513     { "incsspK",        { Edq }, PREFIX_OPCODE },
3514   },
3515
3516   /* PREFIX_0FAE_REG_6_MOD_0 */
3517   {
3518     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3519     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3520     { "clwb",   { Mb }, PREFIX_OPCODE },
3521   },
3522
3523   /* PREFIX_0FAE_REG_6_MOD_3 */
3524   {
3525     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3526     { "umonitor",       { Eva }, PREFIX_OPCODE },
3527     { "tpause", { Edq }, PREFIX_OPCODE },
3528     { "umwait", { Edq }, PREFIX_OPCODE },
3529   },
3530
3531   /* PREFIX_0FAE_REG_7_MOD_0 */
3532   {
3533     { "clflush",        { Mb }, 0 },
3534     { Bad_Opcode },
3535     { "clflushopt",     { Mb }, 0 },
3536   },
3537
3538   /* PREFIX_0FB8 */
3539   {
3540     { Bad_Opcode },
3541     { "popcntS", { Gv, Ev }, 0 },
3542   },
3543
3544   /* PREFIX_0FBC */
3545   {
3546     { "bsfS",   { Gv, Ev }, 0 },
3547     { "tzcntS", { Gv, Ev }, 0 },
3548     { "bsfS",   { Gv, Ev }, 0 },
3549   },
3550
3551   /* PREFIX_0FBD */
3552   {
3553     { "bsrS",   { Gv, Ev }, 0 },
3554     { "lzcntS", { Gv, Ev }, 0 },
3555     { "bsrS",   { Gv, Ev }, 0 },
3556   },
3557
3558   /* PREFIX_0FC2 */
3559   {
3560     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3561     { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3562     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3563     { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3564   },
3565
3566   /* PREFIX_0FC7_REG_6_MOD_0 */
3567   {
3568     { "vmptrld",{ Mq }, 0 },
3569     { "vmxon",  { Mq }, 0 },
3570     { "vmclear",{ Mq }, 0 },
3571   },
3572
3573   /* PREFIX_0FC7_REG_6_MOD_3 */
3574   {
3575     { "rdrand", { Ev }, 0 },
3576     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3577     { "rdrand", { Ev }, 0 }
3578   },
3579
3580   /* PREFIX_0FC7_REG_7_MOD_3 */
3581   {
3582     { "rdseed", { Ev }, 0 },
3583     { "rdpid",  { Em }, 0 },
3584     { "rdseed", { Ev }, 0 },
3585   },
3586
3587   /* PREFIX_0FD0 */
3588   {
3589     { Bad_Opcode },
3590     { Bad_Opcode },
3591     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3592     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3593   },
3594
3595   /* PREFIX_0FD6 */
3596   {
3597     { Bad_Opcode },
3598     { "movq2dq",{ XM, Nq }, 0 },
3599     { "movq",   { EXqS, XM }, 0 },
3600     { "movdq2q",{ MX, Ux }, 0 },
3601   },
3602
3603   /* PREFIX_0FE6 */
3604   {
3605     { Bad_Opcode },
3606     { "Vcvtdq2pd",      { XM, EXxmmq }, 0 },
3607     { "Vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3608     { "Vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3609   },
3610
3611   /* PREFIX_0FE7 */
3612   {
3613     { "movntq",         { Mq, MX }, 0 },
3614     { Bad_Opcode },
3615     { "movntdq",        { Mx, XM }, 0 },
3616   },
3617
3618   /* PREFIX_0FF0 */
3619   {
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { Bad_Opcode },
3623     { "Vlddqu",         { XM, M }, 0 },
3624   },
3625
3626   /* PREFIX_0FF7 */
3627   {
3628     { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3629     { Bad_Opcode },
3630     { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3631   },
3632
3633   /* PREFIX_0F38D8 */
3634   {
3635     { Bad_Opcode },
3636     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3637   },
3638
3639   /* PREFIX_0F38DC */
3640   {
3641     { Bad_Opcode },
3642     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3643     { "aesenc", { XM, EXx }, 0 },
3644   },
3645
3646   /* PREFIX_0F38DD */
3647   {
3648     { Bad_Opcode },
3649     { "aesdec128kl", { XM, M }, 0 },
3650     { "aesenclast", { XM, EXx }, 0 },
3651   },
3652
3653   /* PREFIX_0F38DE */
3654   {
3655     { Bad_Opcode },
3656     { "aesenc256kl", { XM, M }, 0 },
3657     { "aesdec", { XM, EXx }, 0 },
3658   },
3659
3660   /* PREFIX_0F38DF */
3661   {
3662     { Bad_Opcode },
3663     { "aesdec256kl", { XM, M }, 0 },
3664     { "aesdeclast", { XM, EXx }, 0 },
3665   },
3666
3667   /* PREFIX_0F38F0 */
3668   {
3669     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3670     { Bad_Opcode },
3671     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3672     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3673   },
3674
3675   /* PREFIX_0F38F1 */
3676   {
3677     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3678     { Bad_Opcode },
3679     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3680     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3681   },
3682
3683   /* PREFIX_0F38F6 */
3684   {
3685     { "wrssK",  { M, Gdq }, 0 },
3686     { "adoxL",  { VexGdq, Gdq, Edq }, 0 },
3687     { "adcxL",  { VexGdq, Gdq, Edq }, 0 },
3688     { Bad_Opcode },
3689   },
3690
3691   /* PREFIX_0F38F8_M_0 */
3692   {
3693     { Bad_Opcode },
3694     { "enqcmds", { Gva, M }, 0 },
3695     { "movdir64b", { Gva, M }, 0 },
3696     { "enqcmd", { Gva, M }, 0 },
3697   },
3698
3699   /* PREFIX_0F38F8_M_1_X86_64 */
3700   {
3701     { Bad_Opcode },
3702     { "uwrmsr",         { Gq, Rq }, 0 },
3703     { Bad_Opcode },
3704     { "urdmsr",         { Rq, Gq }, 0 },
3705   },
3706
3707   /* PREFIX_0F38FA */
3708   {
3709     { Bad_Opcode },
3710     { "encodekey128", { Gd, Rd }, 0 },
3711   },
3712
3713   /* PREFIX_0F38FB */
3714   {
3715     { Bad_Opcode },
3716     { "encodekey256", { Gd, Rd }, 0 },
3717   },
3718
3719   /* PREFIX_0F38FC */
3720   {
3721     { "aadd",   { Mdq, Gdq }, 0 },
3722     { "axor",   { Mdq, Gdq }, 0 },
3723     { "aand",   { Mdq, Gdq }, 0 },
3724     { "aor",    { Mdq, Gdq }, 0 },
3725   },
3726
3727   /* PREFIX_0F3A0F */
3728   {
3729     { Bad_Opcode },
3730     { REG_TABLE (REG_0F3A0F_P_1) },
3731   },
3732
3733   /* PREFIX_VEX_0F12 */
3734   {
3735     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3736     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3737     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3738     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3739   },
3740
3741   /* PREFIX_VEX_0F16 */
3742   {
3743     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3744     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3745     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3746   },
3747
3748   /* PREFIX_VEX_0F2A */
3749   {
3750     { Bad_Opcode },
3751     { "%XEvcvtsi2ssY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3752     { Bad_Opcode },
3753     { "%XEvcvtsi2sdY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3754   },
3755
3756   /* PREFIX_VEX_0F2C */
3757   {
3758     { Bad_Opcode },
3759     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3760     { Bad_Opcode },
3761     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3762   },
3763
3764   /* PREFIX_VEX_0F2D */
3765   {
3766     { Bad_Opcode },
3767     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3768     { Bad_Opcode },
3769     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3770   },
3771
3772   /* PREFIX_VEX_0F41_L_1_W_0 */
3773   {
3774     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
3775     { Bad_Opcode },
3776     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
3777   },
3778
3779   /* PREFIX_VEX_0F41_L_1_W_1 */
3780   {
3781     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
3782     { Bad_Opcode },
3783     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
3784   },
3785
3786   /* PREFIX_VEX_0F42_L_1_W_0 */
3787   {
3788     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
3789     { Bad_Opcode },
3790     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
3791   },
3792
3793   /* PREFIX_VEX_0F42_L_1_W_1 */
3794   {
3795     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
3796     { Bad_Opcode },
3797     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
3798   },
3799
3800   /* PREFIX_VEX_0F44_L_0_W_0 */
3801   {
3802     { "knotw",          { MaskG, MaskR }, 0 },
3803     { Bad_Opcode },
3804     { "knotb",          { MaskG, MaskR }, 0 },
3805   },
3806
3807   /* PREFIX_VEX_0F44_L_0_W_1 */
3808   {
3809     { "knotq",          { MaskG, MaskR }, 0 },
3810     { Bad_Opcode },
3811     { "knotd",          { MaskG, MaskR }, 0 },
3812   },
3813
3814   /* PREFIX_VEX_0F45_L_1_W_0 */
3815   {
3816     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
3817     { Bad_Opcode },
3818     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
3819   },
3820
3821   /* PREFIX_VEX_0F45_L_1_W_1 */
3822   {
3823     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
3824     { Bad_Opcode },
3825     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
3826   },
3827
3828   /* PREFIX_VEX_0F46_L_1_W_0 */
3829   {
3830     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
3831     { Bad_Opcode },
3832     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
3833   },
3834
3835   /* PREFIX_VEX_0F46_L_1_W_1 */
3836   {
3837     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
3838     { Bad_Opcode },
3839     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
3840   },
3841
3842   /* PREFIX_VEX_0F47_L_1_W_0 */
3843   {
3844     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
3845     { Bad_Opcode },
3846     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
3847   },
3848
3849   /* PREFIX_VEX_0F47_L_1_W_1 */
3850   {
3851     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
3852     { Bad_Opcode },
3853     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
3854   },
3855
3856   /* PREFIX_VEX_0F4A_L_1_W_0 */
3857   {
3858     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
3859     { Bad_Opcode },
3860     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
3861   },
3862
3863   /* PREFIX_VEX_0F4A_L_1_W_1 */
3864   {
3865     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
3866     { Bad_Opcode },
3867     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
3868   },
3869
3870   /* PREFIX_VEX_0F4B_L_1_W_0 */
3871   {
3872     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
3873     { Bad_Opcode },
3874     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
3875   },
3876
3877   /* PREFIX_VEX_0F4B_L_1_W_1 */
3878   {
3879     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
3880   },
3881
3882   /* PREFIX_VEX_0F6F */
3883   {
3884     { Bad_Opcode },
3885     { "vmovdqu",        { XM, EXx }, 0 },
3886     { "vmovdqa",        { XM, EXx }, 0 },
3887   },
3888
3889   /* PREFIX_VEX_0F70 */
3890   {
3891     { Bad_Opcode },
3892     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3893     { "vpshufd",        { XM, EXx, Ib }, 0 },
3894     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3895   },
3896
3897   /* PREFIX_VEX_0F7E */
3898   {
3899     { Bad_Opcode },
3900     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3901     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3902   },
3903
3904   /* PREFIX_VEX_0F7F */
3905   {
3906     { Bad_Opcode },
3907     { "vmovdqu",        { EXxS, XM }, 0 },
3908     { "vmovdqa",        { EXxS, XM }, 0 },
3909   },
3910
3911   /* PREFIX_VEX_0F90_L_0_W_0 */
3912   {
3913     { "%XEkmovw",               { MaskG, MaskE }, 0 },
3914     { Bad_Opcode },
3915     { "%XEkmovb",               { MaskG, MaskBDE }, 0 },
3916   },
3917
3918   /* PREFIX_VEX_0F90_L_0_W_1 */
3919   {
3920     { "%XEkmovq",               { MaskG, MaskE }, 0 },
3921     { Bad_Opcode },
3922     { "%XEkmovd",               { MaskG, MaskBDE }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F91_L_0_W_0 */
3926   {
3927     { "%XEkmovw",               { Mw, MaskG }, 0 },
3928     { Bad_Opcode },
3929     { "%XEkmovb",               { Mb, MaskG }, 0 },
3930   },
3931
3932   /* PREFIX_VEX_0F91_L_0_W_1 */
3933   {
3934     { "%XEkmovq",               { Mq, MaskG }, 0 },
3935     { Bad_Opcode },
3936     { "%XEkmovd",               { Md, MaskG }, 0 },
3937   },
3938
3939   /* PREFIX_VEX_0F92_L_0_W_0 */
3940   {
3941     { "%XEkmovw",               { MaskG, Rdq }, 0 },
3942     { Bad_Opcode },
3943     { "%XEkmovb",               { MaskG, Rdq }, 0 },
3944     { "%XEkmovd",               { MaskG, Rdq }, 0 },
3945   },
3946
3947   /* PREFIX_VEX_0F92_L_0_W_1 */
3948   {
3949     { Bad_Opcode },
3950     { Bad_Opcode },
3951     { Bad_Opcode },
3952     { "%XEkmovK",               { MaskG, Rdq }, 0 },
3953   },
3954
3955   /* PREFIX_VEX_0F93_L_0_W_0 */
3956   {
3957     { "%XEkmovw",               { Gdq, MaskR }, 0 },
3958     { Bad_Opcode },
3959     { "%XEkmovb",               { Gdq, MaskR }, 0 },
3960     { "%XEkmovd",               { Gdq, MaskR }, 0 },
3961   },
3962
3963   /* PREFIX_VEX_0F93_L_0_W_1 */
3964   {
3965     { Bad_Opcode },
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { "%XEkmovK",               { Gdq, MaskR }, 0 },
3969   },
3970
3971   /* PREFIX_VEX_0F98_L_0_W_0 */
3972   {
3973     { "kortestw", { MaskG, MaskR }, 0 },
3974     { Bad_Opcode },
3975     { "kortestb", { MaskG, MaskR }, 0 },
3976   },
3977
3978   /* PREFIX_VEX_0F98_L_0_W_1 */
3979   {
3980     { "kortestq", { MaskG, MaskR }, 0 },
3981     { Bad_Opcode },
3982     { "kortestd", { MaskG, MaskR }, 0 },
3983   },
3984
3985   /* PREFIX_VEX_0F99_L_0_W_0 */
3986   {
3987     { "ktestw", { MaskG, MaskR }, 0 },
3988     { Bad_Opcode },
3989     { "ktestb", { MaskG, MaskR }, 0 },
3990   },
3991
3992   /* PREFIX_VEX_0F99_L_0_W_1 */
3993   {
3994     { "ktestq", { MaskG, MaskR }, 0 },
3995     { Bad_Opcode },
3996     { "ktestd", { MaskG, MaskR }, 0 },
3997   },
3998
3999   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
4000   {
4001     { "ldtilecfg", { M }, 0 },
4002     { Bad_Opcode },
4003     { "sttilecfg", { M }, 0 },
4004   },
4005
4006   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
4007   {
4008     { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
4009     { Bad_Opcode },
4010     { Bad_Opcode },
4011     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
4012   },
4013
4014   /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
4015   {
4016     { Bad_Opcode },
4017     { "tilestored",     { MVexSIBMEM, TMM }, 0 },
4018     { "tileloaddt1",    { TMM, MVexSIBMEM }, 0 },
4019     { "tileloadd",      { TMM, MVexSIBMEM }, 0 },
4020   },
4021
4022   /* PREFIX_VEX_0F3850_W_0 */
4023   {
4024     { "%XEvpdpbuud",    { XM, Vex, EXx }, 0 },
4025     { "%XEvpdpbsud",    { XM, Vex, EXx }, 0 },
4026     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
4027     { "%XEvpdpbssd",    { XM, Vex, EXx }, 0 },
4028   },
4029
4030   /* PREFIX_VEX_0F3851_W_0 */
4031   {
4032     { "%XEvpdpbuuds",   { XM, Vex, EXx }, 0 },
4033     { "%XEvpdpbsuds",   { XM, Vex, EXx }, 0 },
4034     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4035     { "%XEvpdpbssds",   { XM, Vex, EXx }, 0 },
4036   },
4037   /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4038   {
4039     { Bad_Opcode },
4040     { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4041     { Bad_Opcode },
4042     { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4043   },
4044
4045   /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4046   {
4047     { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4048     { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4049     { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4050     { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4051   },
4052
4053   /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4054   {
4055     { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4056     { Bad_Opcode },
4057     { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4058   },
4059
4060   /* PREFIX_VEX_0F3872 */
4061   {
4062     { Bad_Opcode },
4063     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4064   },
4065
4066   /* PREFIX_VEX_0F38B0_W_0 */
4067   {
4068     { "vcvtneoph2ps", { XM, Mx }, 0 },
4069     { "vcvtneebf162ps", { XM, Mx }, 0 },
4070     { "vcvtneeph2ps", { XM, Mx }, 0 },
4071     { "vcvtneobf162ps", { XM, Mx }, 0 },
4072   },
4073
4074   /* PREFIX_VEX_0F38B1_W_0 */
4075   {
4076     { Bad_Opcode },
4077     { "vbcstnebf162ps", { XM, Mw }, 0 },
4078     { "vbcstnesh2ps", { XM, Mw }, 0 },
4079   },
4080
4081   /* PREFIX_VEX_0F38D2_W_0 */
4082   {
4083     { "%XEvpdpwuud",    { XM, Vex, EXx }, 0 },
4084     { "%XEvpdpwsud",    { XM, Vex, EXx }, 0 },
4085     { "%XEvpdpwusd",    { XM, Vex, EXx }, 0 },
4086   },
4087
4088   /* PREFIX_VEX_0F38D3_W_0 */
4089   {
4090     { "%XEvpdpwuuds",   { XM, Vex, EXx }, 0 },
4091     { "%XEvpdpwsuds",   { XM, Vex, EXx }, 0 },
4092     { "%XEvpdpwusds",   { XM, Vex, EXx }, 0 },
4093   },
4094
4095   /* PREFIX_VEX_0F38CB */
4096   {
4097     { Bad_Opcode },
4098     { Bad_Opcode },
4099     { Bad_Opcode },
4100     { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4101   },
4102
4103   /* PREFIX_VEX_0F38CC */
4104   {
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { Bad_Opcode },
4108     { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4109   },
4110
4111   /* PREFIX_VEX_0F38CD */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4117   },
4118
4119   /* PREFIX_VEX_0F38DA_W_0 */
4120   {
4121     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4122     { "vsm4key4", { XM, Vex, EXx }, 0 },
4123     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4124     { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4125   },
4126
4127   /* PREFIX_VEX_0F38F2_L_0 */
4128   {
4129     { "%NFandnS",          { Gdq, VexGdq, Edq }, 0 },
4130   },
4131
4132   /* PREFIX_VEX_0F38F3_L_0 */
4133   {
4134     { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4135   },
4136
4137   /* PREFIX_VEX_0F38F5_L_0 */
4138   {
4139     { "%NFbzhiS",       { Gdq, Edq, VexGdq }, 0 },
4140     { "%XEpextS",               { Gdq, VexGdq, Edq }, 0 },
4141     { Bad_Opcode },
4142     { "%XEpdepS",               { Gdq, VexGdq, Edq }, 0 },
4143   },
4144
4145   /* PREFIX_VEX_0F38F6_L_0 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "%XEmulxS",               { Gdq, VexGdq, Edq }, 0 },
4151   },
4152
4153   /* PREFIX_VEX_0F38F7_L_0 */
4154   {
4155     { "%NFbextrS",      { Gdq, Edq, VexGdq }, 0 },
4156     { "%XEsarxS",               { Gdq, Edq, VexGdq }, 0 },
4157     { "%XEshlxS",               { Gdq, Edq, VexGdq }, 0 },
4158     { "%XEshrxS",               { Gdq, Edq, VexGdq }, 0 },
4159   },
4160
4161   /* PREFIX_VEX_0F3AF0_L_0 */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "%XErorxS",               { Gdq, Edq, Ib }, 0 },
4167   },
4168
4169   /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4170   {
4171     { Bad_Opcode },
4172     { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4173     { Bad_Opcode },
4174     { "urdmsr", { Rq, Id }, 0 },
4175   },
4176
4177 #include "i386-dis-evex-prefix.h"
4178 };
4179
4180 static const struct dis386 x86_64_table[][2] = {
4181   /* X86_64_06 */
4182   {
4183     { "pushP", { es }, 0 },
4184   },
4185
4186   /* X86_64_07 */
4187   {
4188     { "popP", { es }, 0 },
4189   },
4190
4191   /* X86_64_0E */
4192   {
4193     { "pushP", { cs }, 0 },
4194   },
4195
4196   /* X86_64_16 */
4197   {
4198     { "pushP", { ss }, 0 },
4199   },
4200
4201   /* X86_64_17 */
4202   {
4203     { "popP", { ss }, 0 },
4204   },
4205
4206   /* X86_64_1E */
4207   {
4208     { "pushP", { ds }, 0 },
4209   },
4210
4211   /* X86_64_1F */
4212   {
4213     { "popP", { ds }, 0 },
4214   },
4215
4216   /* X86_64_27 */
4217   {
4218     { "daa", { XX }, 0 },
4219   },
4220
4221   /* X86_64_2F */
4222   {
4223     { "das", { XX }, 0 },
4224   },
4225
4226   /* X86_64_37 */
4227   {
4228     { "aaa", { XX }, 0 },
4229   },
4230
4231   /* X86_64_3F */
4232   {
4233     { "aas", { XX }, 0 },
4234   },
4235
4236   /* X86_64_60 */
4237   {
4238     { "pushaP", { XX }, 0 },
4239   },
4240
4241   /* X86_64_61 */
4242   {
4243     { "popaP", { XX }, 0 },
4244   },
4245
4246   /* X86_64_62 */
4247   {
4248     { MOD_TABLE (MOD_62_32BIT) },
4249     { EVEX_TABLE () },
4250   },
4251
4252   /* X86_64_63 */
4253   {
4254     { "arplS", { Sv, Gv }, 0 },
4255     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4256   },
4257
4258   /* X86_64_6D */
4259   {
4260     { "ins{R|}", { Yzr, indirDX }, 0 },
4261     { "ins{G|}", { Yzr, indirDX }, 0 },
4262   },
4263
4264   /* X86_64_6F */
4265   {
4266     { "outs{R|}", { indirDXr, Xz }, 0 },
4267     { "outs{G|}", { indirDXr, Xz }, 0 },
4268   },
4269
4270   /* X86_64_82 */
4271   {
4272     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4273     { REG_TABLE (REG_80) },
4274   },
4275
4276   /* X86_64_9A */
4277   {
4278     { "{l|}call{P|}", { Ap }, 0 },
4279   },
4280
4281   /* X86_64_C2 */
4282   {
4283     { "retP",           { Iw, BND }, 0 },
4284     { "ret@",           { Iw, BND }, 0 },
4285   },
4286
4287   /* X86_64_C3 */
4288   {
4289     { "retP",           { BND }, 0 },
4290     { "ret@",           { BND }, 0 },
4291   },
4292
4293   /* X86_64_C4 */
4294   {
4295     { MOD_TABLE (MOD_C4_32BIT) },
4296     { VEX_C4_TABLE () },
4297   },
4298
4299   /* X86_64_C5 */
4300   {
4301     { MOD_TABLE (MOD_C5_32BIT) },
4302     { VEX_C5_TABLE () },
4303   },
4304
4305   /* X86_64_CE */
4306   {
4307     { "into", { XX }, 0 },
4308   },
4309
4310   /* X86_64_D4 */
4311   {
4312     { "aam", { Ib }, 0 },
4313   },
4314
4315   /* X86_64_D5 */
4316   {
4317     { "aad", { Ib }, 0 },
4318   },
4319
4320   /* X86_64_E8 */
4321   {
4322     { "callP",          { Jv, BND }, 0 },
4323     { "call@",          { Jv, BND }, PREFIX_REX2_ILLEGAL }
4324   },
4325
4326   /* X86_64_E9 */
4327   {
4328     { "jmpP",           { Jv, BND }, 0 },
4329     { "jmp@",           { Jv, BND }, PREFIX_REX2_ILLEGAL }
4330   },
4331
4332   /* X86_64_EA */
4333   {
4334     { "{l|}jmp{P|}", { Ap }, 0 },
4335   },
4336
4337   /* X86_64_0F00_REG_6 */
4338   {
4339     { Bad_Opcode },
4340     { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4341   },
4342
4343   /* X86_64_0F01_REG_0 */
4344   {
4345     { "sgdt{Q|Q}", { M }, 0 },
4346     { "sgdt", { M }, 0 },
4347   },
4348
4349   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4350   {
4351     { Bad_Opcode },
4352     { "wrmsrlist",      { Skip_MODRM }, 0 },
4353   },
4354
4355   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4356   {
4357     { Bad_Opcode },
4358     { "rdmsrlist",      { Skip_MODRM }, 0 },
4359   },
4360
4361   /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4362   {
4363     { Bad_Opcode },
4364     { "pbndkb",         { Skip_MODRM }, 0 },
4365   },
4366
4367   /* X86_64_0F01_REG_1 */
4368   {
4369     { "sidt{Q|Q}", { M }, 0 },
4370     { "sidt", { M }, 0 },
4371   },
4372
4373   /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4374   {
4375     { Bad_Opcode },
4376     { "eretu",          { Skip_MODRM }, 0 },
4377   },
4378
4379   /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4380   {
4381     { Bad_Opcode },
4382     { "erets",          { Skip_MODRM }, 0 },
4383   },
4384
4385   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4386   {
4387     { Bad_Opcode },
4388     { "seamret",        { Skip_MODRM }, 0 },
4389   },
4390
4391   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4392   {
4393     { Bad_Opcode },
4394     { "seamops",        { Skip_MODRM }, 0 },
4395   },
4396
4397   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4398   {
4399     { Bad_Opcode },
4400     { "seamcall",       { Skip_MODRM }, 0 },
4401   },
4402
4403   /* X86_64_0F01_REG_2 */
4404   {
4405     { "lgdt{Q|Q}", { M }, 0 },
4406     { "lgdt", { M }, 0 },
4407   },
4408
4409   /* X86_64_0F01_REG_3 */
4410   {
4411     { "lidt{Q|Q}", { M }, 0 },
4412     { "lidt", { M }, 0 },
4413   },
4414
4415   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4416   {
4417     { Bad_Opcode },
4418     { "uiret",  { Skip_MODRM }, 0 },
4419   },
4420
4421   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4422   {
4423     { Bad_Opcode },
4424     { "testui", { Skip_MODRM }, 0 },
4425   },
4426
4427   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4428   {
4429     { Bad_Opcode },
4430     { "clui",   { Skip_MODRM }, 0 },
4431   },
4432
4433   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4434   {
4435     { Bad_Opcode },
4436     { "stui",   { Skip_MODRM }, 0 },
4437   },
4438
4439   /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4440   {
4441     { Bad_Opcode },
4442     { "rmpquery", { Skip_MODRM }, 0 },
4443   },
4444
4445   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4446   {
4447     { Bad_Opcode },
4448     { "rmpadjust",      { Skip_MODRM }, 0 },
4449   },
4450
4451   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4452   {
4453     { Bad_Opcode },
4454     { "rmpupdate",      { Skip_MODRM }, 0 },
4455   },
4456
4457   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4458   {
4459     { Bad_Opcode },
4460     { "psmash", { Skip_MODRM }, 0 },
4461   },
4462
4463   /* X86_64_0F18_REG_6_MOD_0 */
4464   {
4465     { "nopQ",           { Ev }, 0 },
4466     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4467   },
4468
4469   /* X86_64_0F18_REG_7_MOD_0 */
4470   {
4471     { "nopQ",           { Ev }, 0 },
4472     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4473   },
4474
4475   {
4476     /* X86_64_0F24 */
4477     { "movZ",           { Em, Td }, 0 },
4478   },
4479
4480   {
4481     /* X86_64_0F26 */
4482     { "movZ",           { Td, Em }, 0 },
4483   },
4484
4485   {
4486     /* X86_64_0F38F8_M_1 */
4487     { Bad_Opcode },
4488     { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4489   },
4490
4491   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4492   {
4493     { Bad_Opcode },
4494     { "senduipi",       { Eq }, 0 },
4495   },
4496
4497   /* X86_64_VEX_0F3849 */
4498   {
4499     { Bad_Opcode },
4500     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4501   },
4502
4503   /* X86_64_VEX_0F384B */
4504   {
4505     { Bad_Opcode },
4506     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4507   },
4508
4509   /* X86_64_VEX_0F385C */
4510   {
4511     { Bad_Opcode },
4512     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4513   },
4514
4515   /* X86_64_VEX_0F385E */
4516   {
4517     { Bad_Opcode },
4518     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4519   },
4520
4521   /* X86_64_VEX_0F386C */
4522   {
4523     { Bad_Opcode },
4524     { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4525   },
4526
4527   /* X86_64_VEX_0F38Ex */
4528   {
4529     { Bad_Opcode },
4530     { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4531   },
4532
4533   /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4534   {
4535     { Bad_Opcode },
4536     { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4537   },
4538 };
4539
4540 static const struct dis386 three_byte_table[][256] = {
4541
4542   /* THREE_BYTE_0F38 */
4543   {
4544     /* 00 */
4545     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4546     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4547     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4548     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4549     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4550     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4551     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4552     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4553     /* 08 */
4554     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4555     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4556     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4557     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     /* 10 */
4563     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4568     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4569     { Bad_Opcode },
4570     { "ptest",  { XM, EXx }, PREFIX_DATA },
4571     /* 18 */
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4577     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4578     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4579     { Bad_Opcode },
4580     /* 20 */
4581     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4582     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4583     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4584     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4585     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4586     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     /* 28 */
4590     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4591     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4592     { "movntdqa", { XM, Mx }, PREFIX_DATA },
4593     { "packusdw", { XM, EXx }, PREFIX_DATA },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     /* 30 */
4599     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4600     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4601     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4602     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4603     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4604     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4605     { Bad_Opcode },
4606     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4607     /* 38 */
4608     { "pminsb", { XM, EXx }, PREFIX_DATA },
4609     { "pminsd", { XM, EXx }, PREFIX_DATA },
4610     { "pminuw", { XM, EXx }, PREFIX_DATA },
4611     { "pminud", { XM, EXx }, PREFIX_DATA },
4612     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4613     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4614     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4615     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4616     /* 40 */
4617     { "pmulld", { XM, EXx }, PREFIX_DATA },
4618     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     /* 48 */
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     /* 50 */
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     /* 58 */
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     /* 60 */
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     /* 68 */
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     /* 70 */
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     /* 78 */
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     /* 80 */
4689     { "invept", { Gm, Mo }, PREFIX_DATA },
4690     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4691     { "invpcid", { Gm, M }, PREFIX_DATA },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     /* 88 */
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     /* 90 */
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     /* 98 */
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     /* a0 */
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     /* a8 */
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     /* b0 */
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     /* b8 */
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     /* c0 */
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     /* c8 */
4770     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4771     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4772     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4773     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4774     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4775     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4776     { Bad_Opcode },
4777     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4778     /* d0 */
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     /* d8 */
4788     { PREFIX_TABLE (PREFIX_0F38D8) },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "aesimc", { XM, EXx }, PREFIX_DATA },
4792     { PREFIX_TABLE (PREFIX_0F38DC) },
4793     { PREFIX_TABLE (PREFIX_0F38DD) },
4794     { PREFIX_TABLE (PREFIX_0F38DE) },
4795     { PREFIX_TABLE (PREFIX_0F38DF) },
4796     /* e0 */
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     /* e8 */
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     /* f0 */
4815     { PREFIX_TABLE (PREFIX_0F38F0) },
4816     { PREFIX_TABLE (PREFIX_0F38F1) },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { "wrussK",         { M, Gdq }, PREFIX_DATA },
4821     { PREFIX_TABLE (PREFIX_0F38F6) },
4822     { Bad_Opcode },
4823     /* f8 */
4824     { MOD_TABLE (MOD_0F38F8) },
4825     { "movdiri",        { Mdq, Gdq }, PREFIX_OPCODE },
4826     { PREFIX_TABLE (PREFIX_0F38FA) },
4827     { PREFIX_TABLE (PREFIX_0F38FB) },
4828     { PREFIX_TABLE (PREFIX_0F38FC) },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832   },
4833   /* THREE_BYTE_0F3A */
4834   {
4835     /* 00 */
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     /* 08 */
4845     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4846     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4847     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4848     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4849     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4850     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4851     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4852     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4853     /* 10 */
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4859     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4860     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4861     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4862     /* 18 */
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     /* 20 */
4872     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4873     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4874     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     /* 28 */
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     /* 30 */
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     /* 38 */
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     /* 40 */
4908     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4909     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4910     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4911     { Bad_Opcode },
4912     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     /* 48 */
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     /* 50 */
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     /* 58 */
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     /* 60 */
4944     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4945     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4946     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4947     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     /* 68 */
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     /* 70 */
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     /* 78 */
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     /* 80 */
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     /* 88 */
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     /* 90 */
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     /* 98 */
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     /* a0 */
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     /* a8 */
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     /* b0 */
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     /* b8 */
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     /* c0 */
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     /* c8 */
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5066     { Bad_Opcode },
5067     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5068     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5069     /* d0 */
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     /* d8 */
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5087     /* e0 */
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     /* e8 */
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     /* f0 */
5106     { PREFIX_TABLE (PREFIX_0F3A0F) },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     /* f8 */
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123   },
5124 };
5125
5126 static const struct dis386 xop_table[][256] = {
5127   /* XOP_08 */
5128   {
5129     /* 00 */
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     /* 08 */
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     /* 10 */
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     /* 18 */
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     /* 20 */
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     /* 28 */
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     /* 30 */
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     /* 38 */
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     /* 40 */
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     /* 48 */
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     /* 50 */
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     /* 58 */
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     /* 60 */
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     /* 68 */
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     /* 70 */
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     /* 78 */
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     /* 80 */
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5280     { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5281     { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5282     /* 88 */
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5290     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5291     /* 90 */
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5298     { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5299     { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5300     /* 98 */
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5308     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5309     /* a0 */
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5313     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5317     { Bad_Opcode },
5318     /* a8 */
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     /* b0 */
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5335     { Bad_Opcode },
5336     /* b8 */
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     /* c0 */
5346     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5347     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5348     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5349     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     /* c8 */
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5360     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5361     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5362     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5363     /* d0 */
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     /* d8 */
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     /* e0 */
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     /* e8 */
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5396     { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5397     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5398     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5399     /* f0 */
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     /* f8 */
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417   },
5418   /* XOP_09 */
5419   {
5420     /* 00 */
5421     { Bad_Opcode },
5422     { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5423     { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     /* 08 */
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     /* 10 */
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     /* 18 */
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     /* 20 */
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     /* 28 */
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     /* 30 */
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     /* 38 */
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     /* 40 */
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     /* 48 */
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     /* 50 */
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     /* 58 */
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     /* 60 */
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     /* 68 */
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     /* 70 */
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     /* 78 */
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     /* 80 */
5565     { VEX_W_TABLE (VEX_W_XOP_09_80) },
5566     { VEX_W_TABLE (VEX_W_XOP_09_81) },
5567     { VEX_W_TABLE (VEX_W_XOP_09_82) },
5568     { VEX_W_TABLE (VEX_W_XOP_09_83) },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     /* 88 */
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     /* 90 */
5583     { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5584     { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5585     { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5586     { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5587     { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5588     { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5589     { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5590     { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5591     /* 98 */
5592     { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5593     { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5594     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5595     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     /* a0 */
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     /* a8 */
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     /* b0 */
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     /* b8 */
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     /* c0 */
5637     { Bad_Opcode },
5638     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5639     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5640     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5644     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5645     /* c8 */
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     /* d0 */
5655     { Bad_Opcode },
5656     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5657     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5658     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5662     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5663     /* d8 */
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     /* e0 */
5673     { Bad_Opcode },
5674     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5675     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5676     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     /* e8 */
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     /* f0 */
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     /* f8 */
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708   },
5709   /* XOP_0A */
5710   {
5711     /* 00 */
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     /* 08 */
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     /* 10 */
5730     { "bextrS", { Gdq, Edq, Id }, 0 },
5731     { Bad_Opcode },
5732     { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     /* 18 */
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     /* 20 */
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     /* 28 */
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     /* 30 */
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     /* 38 */
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     /* 40 */
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     /* 48 */
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     /* 50 */
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     /* 58 */
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     /* 60 */
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     /* 68 */
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     /* 70 */
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     /* 78 */
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     /* 80 */
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     /* 88 */
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     /* 90 */
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     /* 98 */
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     /* a0 */
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     /* a8 */
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     /* b0 */
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     /* b8 */
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     /* c0 */
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     /* c8 */
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     /* d0 */
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     /* d8 */
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     /* e0 */
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     /* e8 */
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     /* f0 */
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     /* f8 */
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999   },
6000 };
6001
6002 static const struct dis386 vex_table[][256] = {
6003   /* VEX_0F */
6004   {
6005     /* 00 */
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     /* 08 */
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     /* 10 */
6024     { PREFIX_TABLE (PREFIX_0F10) },
6025     { PREFIX_TABLE (PREFIX_0F11) },
6026     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6027     { VEX_LEN_TABLE (VEX_LEN_0F13) },
6028     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6029     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6030     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6031     { VEX_LEN_TABLE (VEX_LEN_0F17) },
6032     /* 18 */
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     /* 20 */
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     /* 28 */
6051     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6052     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6053     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6054     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
6055     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6056     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6057     { PREFIX_TABLE (PREFIX_0F2E) },
6058     { PREFIX_TABLE (PREFIX_0F2F) },
6059     /* 30 */
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     /* 38 */
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     /* 40 */
6078     { Bad_Opcode },
6079     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6080     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6081     { Bad_Opcode },
6082     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6083     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6084     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6085     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6086     /* 48 */
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6090     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     /* 50 */
6096     { "vmovmskpX",      { Gdq, Ux }, PREFIX_OPCODE },
6097     { PREFIX_TABLE (PREFIX_0F51) },
6098     { PREFIX_TABLE (PREFIX_0F52) },
6099     { PREFIX_TABLE (PREFIX_0F53) },
6100     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6101     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6102     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6103     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6104     /* 58 */
6105     { PREFIX_TABLE (PREFIX_0F58) },
6106     { PREFIX_TABLE (PREFIX_0F59) },
6107     { PREFIX_TABLE (PREFIX_0F5A) },
6108     { PREFIX_TABLE (PREFIX_0F5B) },
6109     { PREFIX_TABLE (PREFIX_0F5C) },
6110     { PREFIX_TABLE (PREFIX_0F5D) },
6111     { PREFIX_TABLE (PREFIX_0F5E) },
6112     { PREFIX_TABLE (PREFIX_0F5F) },
6113     /* 60 */
6114     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6115     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6116     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6117     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6118     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6119     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6120     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6121     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6122     /* 68 */
6123     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6124     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6125     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6126     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6127     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6128     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6129     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6130     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6131     /* 70 */
6132     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6133     { REG_TABLE (REG_VEX_0F71) },
6134     { REG_TABLE (REG_VEX_0F72) },
6135     { REG_TABLE (REG_VEX_0F73) },
6136     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6139     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6140     /* 78 */
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { PREFIX_TABLE (PREFIX_0F7C) },
6146     { PREFIX_TABLE (PREFIX_0F7D) },
6147     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6148     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6149     /* 80 */
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     /* 88 */
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     /* 90 */
6168     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6169     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6170     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6171     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     /* 98 */
6177     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6178     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     /* a0 */
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     /* a8 */
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { REG_TABLE (REG_VEX_0FAE) },
6202     { Bad_Opcode },
6203     /* b0 */
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     /* b8 */
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     /* c0 */
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { PREFIX_TABLE (PREFIX_0FC2) },
6225     { Bad_Opcode },
6226     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6227     { "vpextrw",        { Gd, Uxmm, Ib }, PREFIX_DATA },
6228     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6229     { Bad_Opcode },
6230     /* c8 */
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     /* d0 */
6240     { PREFIX_TABLE (PREFIX_0FD0) },
6241     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6242     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6243     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6244     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6245     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6246     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6247     { "vpmovmskb",      { Gdq, Ux }, PREFIX_DATA },
6248     /* d8 */
6249     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6250     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6251     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6252     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6253     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6254     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6255     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6256     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6257     /* e0 */
6258     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6259     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6260     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6261     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6262     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6263     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6264     { PREFIX_TABLE (PREFIX_0FE6) },
6265     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
6266     /* e8 */
6267     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6268     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6269     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6270     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6271     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6272     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6273     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6274     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6275     /* f0 */
6276     { PREFIX_TABLE (PREFIX_0FF0) },
6277     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6278     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6279     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6280     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6281     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6282     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6283     { "vmaskmovdqu",    { XM, Uxmm }, PREFIX_DATA },
6284     /* f8 */
6285     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6286     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6287     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6288     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6289     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6290     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6291     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6292     { Bad_Opcode },
6293   },
6294   /* VEX_0F38 */
6295   {
6296     /* 00 */
6297     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6298     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6299     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6300     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6301     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6302     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6303     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6304     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6305     /* 08 */
6306     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6307     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6309     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6310     { VEX_W_TABLE (VEX_W_0F380C) },
6311     { VEX_W_TABLE (VEX_W_0F380D) },
6312     { VEX_W_TABLE (VEX_W_0F380E) },
6313     { VEX_W_TABLE (VEX_W_0F380F) },
6314     /* 10 */
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_W_TABLE (VEX_W_0F3813) },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6322     { "vptest",         { XM, EXx }, PREFIX_DATA },
6323     /* 18 */
6324     { VEX_W_TABLE (VEX_W_0F3818) },
6325     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6326     { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6327     { Bad_Opcode },
6328     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6329     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6330     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6331     { Bad_Opcode },
6332     /* 20 */
6333     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6334     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6335     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6336     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6337     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6338     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     /* 28 */
6342     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6343     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
6345     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6346     { VEX_W_TABLE (VEX_W_0F382C) },
6347     { VEX_W_TABLE (VEX_W_0F382D) },
6348     { VEX_W_TABLE (VEX_W_0F382E) },
6349     { VEX_W_TABLE (VEX_W_0F382F) },
6350     /* 30 */
6351     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6352     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6353     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6354     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6355     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6356     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6357     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6358     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6359     /* 38 */
6360     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6361     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6363     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6365     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6366     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6367     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6368     /* 40 */
6369     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6370     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6375     { VEX_W_TABLE (VEX_W_0F3846) },
6376     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6377     /* 48 */
6378     { Bad_Opcode },
6379     { X86_64_TABLE (X86_64_VEX_0F3849) },
6380     { Bad_Opcode },
6381     { X86_64_TABLE (X86_64_VEX_0F384B) },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     /* 50 */
6387     { VEX_W_TABLE (VEX_W_0F3850) },
6388     { VEX_W_TABLE (VEX_W_0F3851) },
6389     { VEX_W_TABLE (VEX_W_0F3852) },
6390     { VEX_W_TABLE (VEX_W_0F3853) },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     /* 58 */
6396     { VEX_W_TABLE (VEX_W_0F3858) },
6397     { VEX_W_TABLE (VEX_W_0F3859) },
6398     { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6399     { Bad_Opcode },
6400     { X86_64_TABLE (X86_64_VEX_0F385C) },
6401     { Bad_Opcode },
6402     { X86_64_TABLE (X86_64_VEX_0F385E) },
6403     { Bad_Opcode },
6404     /* 60 */
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     /* 68 */
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { X86_64_TABLE (X86_64_VEX_0F386C) },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     /* 70 */
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     /* 78 */
6432     { VEX_W_TABLE (VEX_W_0F3878) },
6433     { VEX_W_TABLE (VEX_W_0F3879) },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     /* 80 */
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     /* 88 */
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
6455     { Bad_Opcode },
6456     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
6457     { Bad_Opcode },
6458     /* 90 */
6459     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6460     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6461     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6462     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6466     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6467     /* 98 */
6468     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6469     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6470     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6471     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6472     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6473     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6474     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6475     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6476     /* a0 */
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6484     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6485     /* a8 */
6486     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6487     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6488     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6489     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6490     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6491     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6492     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6493     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6494     /* b0 */
6495     { VEX_W_TABLE (VEX_W_0F38B0) },
6496     { VEX_W_TABLE (VEX_W_0F38B1) },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_W_TABLE (VEX_W_0F38B4) },
6500     { VEX_W_TABLE (VEX_W_0F38B5) },
6501     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6502     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6503     /* b8 */
6504     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6505     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6506     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6507     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6508     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6509     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6510     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6511     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6512     /* c0 */
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     /* c8 */
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6526     { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6527     { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6528     { Bad_Opcode },
6529     { VEX_W_TABLE (VEX_W_0F38CF) },
6530     /* d0 */
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { VEX_W_TABLE (VEX_W_0F38D2) },
6534     { VEX_W_TABLE (VEX_W_0F38D3) },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     /* d8 */
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { VEX_W_TABLE (VEX_W_0F38DA) },
6543     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6544     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6545     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6546     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6547     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6548     /* e0 */
6549     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6550     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6551     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6552     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6553     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6554     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6555     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6556     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6557     /* e8 */
6558     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6559     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6560     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6561     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6562     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6563     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6564     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6565     { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6566     /* f0 */
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6570     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6573     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6574     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6575     /* f8 */
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584   },
6585   /* VEX_0F3A */
6586   {
6587     /* 00 */
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6589     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6590     { VEX_W_TABLE (VEX_W_0F3A02) },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A04) },
6593     { VEX_W_TABLE (VEX_W_0F3A05) },
6594     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6595     { Bad_Opcode },
6596     /* 08 */
6597     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6598     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6599     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6600     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6601     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6602     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6603     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6604     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6605     /* 10 */
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6612     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6613     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6614     /* 18 */
6615     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { VEX_W_TABLE (VEX_W_0F3A1D) },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     /* 20 */
6624     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6626     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     /* 28 */
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     /* 30 */
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     /* 38 */
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6652     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     /* 40 */
6660     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6661     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6662     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6663     { Bad_Opcode },
6664     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6665     { Bad_Opcode },
6666     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6667     { Bad_Opcode },
6668     /* 48 */
6669     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6670     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6671     { VEX_W_TABLE (VEX_W_0F3A4A) },
6672     { VEX_W_TABLE (VEX_W_0F3A4B) },
6673     { VEX_W_TABLE (VEX_W_0F3A4C) },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     /* 50 */
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     /* 58 */
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6692     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6693     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6694     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6695     /* 60 */
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6697     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     /* 68 */
6705     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6706     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6707     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6708     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6709     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6710     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6711     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6712     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6713     /* 70 */
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     /* 78 */
6723     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6724     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6725     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6726     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6727     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6728     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6729     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6730     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6731     /* 80 */
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     /* 88 */
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     /* 90 */
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     /* 98 */
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     /* a0 */
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     /* a8 */
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     /* b0 */
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     /* b8 */
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     /* c0 */
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     /* c8 */
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { VEX_W_TABLE (VEX_W_0F3ACE) },
6820     { VEX_W_TABLE (VEX_W_0F3ACF) },
6821     /* d0 */
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     /* d8 */
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { VEX_W_TABLE (VEX_W_0F3ADE) },
6838     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6839     /* e0 */
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     /* e8 */
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     /* f0 */
6858     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     /* f8 */
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875   },
6876 };
6877
6878 #include "i386-dis-evex.h"
6879
6880 static const struct dis386 vex_len_table[][2] = {
6881   /* VEX_LEN_0F12_P_0 */
6882   {
6883     { MOD_TABLE (MOD_0F12_PREFIX_0) },
6884   },
6885
6886   /* VEX_LEN_0F12_P_2 */
6887   {
6888     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
6889   },
6890
6891   /* VEX_LEN_0F13 */
6892   {
6893     { "%XEVmovlpYX",    { Mq, XM }, PREFIX_OPCODE },
6894   },
6895
6896   /* VEX_LEN_0F16_P_0 */
6897   {
6898     { MOD_TABLE (MOD_0F16_PREFIX_0) },
6899   },
6900
6901   /* VEX_LEN_0F16_P_2 */
6902   {
6903     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
6904   },
6905
6906   /* VEX_LEN_0F17 */
6907   {
6908     { "%XEVmovhpYX",    { Mq, XM }, PREFIX_OPCODE },
6909   },
6910
6911   /* VEX_LEN_0F41 */
6912   {
6913     { Bad_Opcode },
6914     { VEX_W_TABLE (VEX_W_0F41_L_1) },
6915   },
6916
6917   /* VEX_LEN_0F42 */
6918   {
6919     { Bad_Opcode },
6920     { VEX_W_TABLE (VEX_W_0F42_L_1) },
6921   },
6922
6923   /* VEX_LEN_0F44 */
6924   {
6925     { VEX_W_TABLE (VEX_W_0F44_L_0) },
6926   },
6927
6928   /* VEX_LEN_0F45 */
6929   {
6930     { Bad_Opcode },
6931     { VEX_W_TABLE (VEX_W_0F45_L_1) },
6932   },
6933
6934   /* VEX_LEN_0F46 */
6935   {
6936     { Bad_Opcode },
6937     { VEX_W_TABLE (VEX_W_0F46_L_1) },
6938   },
6939
6940   /* VEX_LEN_0F47 */
6941   {
6942     { Bad_Opcode },
6943     { VEX_W_TABLE (VEX_W_0F47_L_1) },
6944   },
6945
6946   /* VEX_LEN_0F4A */
6947   {
6948     { Bad_Opcode },
6949     { VEX_W_TABLE (VEX_W_0F4A_L_1) },
6950   },
6951
6952   /* VEX_LEN_0F4B */
6953   {
6954     { Bad_Opcode },
6955     { VEX_W_TABLE (VEX_W_0F4B_L_1) },
6956   },
6957
6958   /* VEX_LEN_0F6E */
6959   {
6960     { "%XEvmovYK",      { XMScalar, Edq }, PREFIX_DATA },
6961   },
6962
6963   /* VEX_LEN_0F77 */
6964   {
6965     { "vzeroupper",     { XX }, 0 },
6966     { "vzeroall",       { XX }, 0 },
6967   },
6968
6969   /* VEX_LEN_0F7E_P_1 */
6970   {
6971     { "%XEvmovqY",      { XMScalar, EXq }, 0 },
6972   },
6973
6974   /* VEX_LEN_0F7E_P_2 */
6975   {
6976     { "%XEvmovK",       { Edq, XMScalar }, 0 },
6977   },
6978
6979   /* VEX_LEN_0F90 */
6980   {
6981     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6982   },
6983
6984   /* VEX_LEN_0F91 */
6985   {
6986     { VEX_W_TABLE (VEX_W_0F91_L_0) },
6987   },
6988
6989   /* VEX_LEN_0F92 */
6990   {
6991     { VEX_W_TABLE (VEX_W_0F92_L_0) },
6992   },
6993
6994   /* VEX_LEN_0F93 */
6995   {
6996     { VEX_W_TABLE (VEX_W_0F93_L_0) },
6997   },
6998
6999   /* VEX_LEN_0F98 */
7000   {
7001     { VEX_W_TABLE (VEX_W_0F98_L_0) },
7002   },
7003
7004   /* VEX_LEN_0F99 */
7005   {
7006     { VEX_W_TABLE (VEX_W_0F99_L_0) },
7007   },
7008
7009   /* VEX_LEN_0FAE_R_2 */
7010   {
7011     { "vldmxcsr",       { Md }, 0 },
7012   },
7013
7014   /* VEX_LEN_0FAE_R_3 */
7015   {
7016     { "vstmxcsr",       { Md }, 0 },
7017   },
7018
7019   /* VEX_LEN_0FC4 */
7020   {
7021     { "%XEvpinsrwY",    { XM, Vex, Edw, Ib }, PREFIX_DATA },
7022   },
7023
7024   /* VEX_LEN_0FD6 */
7025   {
7026     { "%XEvmovqY",      { EXqS, XMScalar }, PREFIX_DATA },
7027   },
7028
7029   /* VEX_LEN_0F3816 */
7030   {
7031     { Bad_Opcode },
7032     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7033   },
7034
7035   /* VEX_LEN_0F3819 */
7036   {
7037     { Bad_Opcode },
7038     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7039   },
7040
7041   /* VEX_LEN_0F381A */
7042   {
7043     { Bad_Opcode },
7044     { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7045   },
7046
7047   /* VEX_LEN_0F3836 */
7048   {
7049     { Bad_Opcode },
7050     { VEX_W_TABLE (VEX_W_0F3836) },
7051   },
7052
7053   /* VEX_LEN_0F3841 */
7054   {
7055     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7056   },
7057
7058   /* VEX_LEN_0F3849_X86_64 */
7059   {
7060     { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7061   },
7062
7063   /* VEX_LEN_0F384B_X86_64 */
7064   {
7065     { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7066   },
7067
7068   /* VEX_LEN_0F385A */
7069   {
7070     { Bad_Opcode },
7071     { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7072   },
7073
7074   /* VEX_LEN_0F385C_X86_64 */
7075   {
7076     { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7077   },
7078
7079   /* VEX_LEN_0F385E_X86_64 */
7080   {
7081     { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7082   },
7083
7084   /* VEX_LEN_0F386C_X86_64 */
7085   {
7086     { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7087   },
7088
7089   /* VEX_LEN_0F38CB_P_3_W_0 */
7090   {
7091     { Bad_Opcode },
7092     { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7093   },
7094
7095   /* VEX_LEN_0F38CC_P_3_W_0 */
7096   {
7097     { Bad_Opcode },
7098     { "vsha512msg1", { XM, Rxmmq }, 0 },
7099   },
7100
7101   /* VEX_LEN_0F38CD_P_3_W_0 */
7102   {
7103     { Bad_Opcode },
7104     { "vsha512msg2", { XM, Rymm }, 0 },
7105   },
7106
7107   /* VEX_LEN_0F38DA_W_0_P_0 */
7108   {
7109     { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7110   },
7111
7112   /* VEX_LEN_0F38DA_W_0_P_2 */
7113   {
7114     { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7115   },
7116
7117   /* VEX_LEN_0F38DB */
7118   {
7119     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7120   },
7121
7122   /* VEX_LEN_0F38F2 */
7123   {
7124     { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7125   },
7126
7127   /* VEX_LEN_0F38F3 */
7128   {
7129     { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7130   },
7131
7132   /* VEX_LEN_0F38F5 */
7133   {
7134     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7135   },
7136
7137   /* VEX_LEN_0F38F6 */
7138   {
7139     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7140   },
7141
7142   /* VEX_LEN_0F38F7 */
7143   {
7144     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7145   },
7146
7147   /* VEX_LEN_0F3A00 */
7148   {
7149     { Bad_Opcode },
7150     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7151   },
7152
7153   /* VEX_LEN_0F3A01 */
7154   {
7155     { Bad_Opcode },
7156     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7157   },
7158
7159   /* VEX_LEN_0F3A06 */
7160   {
7161     { Bad_Opcode },
7162     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7163   },
7164
7165   /* VEX_LEN_0F3A14 */
7166   {
7167     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7168   },
7169
7170   /* VEX_LEN_0F3A15 */
7171   {
7172     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7173   },
7174
7175   /* VEX_LEN_0F3A16  */
7176   {
7177     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7178   },
7179
7180   /* VEX_LEN_0F3A17 */
7181   {
7182     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7183   },
7184
7185   /* VEX_LEN_0F3A18 */
7186   {
7187     { Bad_Opcode },
7188     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7189   },
7190
7191   /* VEX_LEN_0F3A19 */
7192   {
7193     { Bad_Opcode },
7194     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7195   },
7196
7197   /* VEX_LEN_0F3A20 */
7198   {
7199     { "%XEvpinsrbY",    { XM, Vex, Edb, Ib }, PREFIX_DATA },
7200   },
7201
7202   /* VEX_LEN_0F3A21 */
7203   {
7204     { "%XEvinsertpsY",  { XM, Vex, EXd, Ib }, PREFIX_DATA },
7205   },
7206
7207   /* VEX_LEN_0F3A22 */
7208   {
7209     { "%XEvpinsrYK",    { XM, Vex, Edq, Ib }, PREFIX_DATA },
7210   },
7211
7212   /* VEX_LEN_0F3A30 */
7213   {
7214     { "kshiftr%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7215   },
7216
7217   /* VEX_LEN_0F3A31 */
7218   {
7219     { "kshiftr%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7220   },
7221
7222   /* VEX_LEN_0F3A32 */
7223   {
7224     { "kshiftl%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7225   },
7226
7227   /* VEX_LEN_0F3A33 */
7228   {
7229     { "kshiftl%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7230   },
7231
7232   /* VEX_LEN_0F3A38 */
7233   {
7234     { Bad_Opcode },
7235     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7236   },
7237
7238   /* VEX_LEN_0F3A39 */
7239   {
7240     { Bad_Opcode },
7241     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7242   },
7243
7244   /* VEX_LEN_0F3A41 */
7245   {
7246     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7247   },
7248
7249   /* VEX_LEN_0F3A46 */
7250   {
7251     { Bad_Opcode },
7252     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7253   },
7254
7255   /* VEX_LEN_0F3A60 */
7256   {
7257     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7258   },
7259
7260   /* VEX_LEN_0F3A61 */
7261   {
7262     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7263   },
7264
7265   /* VEX_LEN_0F3A62 */
7266   {
7267     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7268   },
7269
7270   /* VEX_LEN_0F3A63 */
7271   {
7272     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7273   },
7274
7275   /* VEX_LEN_0F3ADE_W_0 */
7276   {
7277     { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7278   },
7279
7280   /* VEX_LEN_0F3ADF */
7281   {
7282     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7283   },
7284
7285   /* VEX_LEN_0F3AF0 */
7286   {
7287     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7288   },
7289
7290   /* VEX_LEN_MAP7_F8 */
7291   {
7292     { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7293   },
7294
7295   /* VEX_LEN_XOP_08_85 */
7296   {
7297     { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7298   },
7299
7300   /* VEX_LEN_XOP_08_86 */
7301   {
7302     { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7303   },
7304
7305   /* VEX_LEN_XOP_08_87 */
7306   {
7307     { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7308   },
7309
7310   /* VEX_LEN_XOP_08_8E */
7311   {
7312     { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7313   },
7314
7315   /* VEX_LEN_XOP_08_8F */
7316   {
7317     { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7318   },
7319
7320   /* VEX_LEN_XOP_08_95 */
7321   {
7322     { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7323   },
7324
7325   /* VEX_LEN_XOP_08_96 */
7326   {
7327     { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7328   },
7329
7330   /* VEX_LEN_XOP_08_97 */
7331   {
7332     { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7333   },
7334
7335   /* VEX_LEN_XOP_08_9E */
7336   {
7337     { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7338   },
7339
7340   /* VEX_LEN_XOP_08_9F */
7341   {
7342     { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7343   },
7344
7345   /* VEX_LEN_XOP_08_A3 */
7346   {
7347     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7348   },
7349
7350   /* VEX_LEN_XOP_08_A6 */
7351   {
7352     { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7353   },
7354
7355   /* VEX_LEN_XOP_08_B6 */
7356   {
7357     { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7358   },
7359
7360   /* VEX_LEN_XOP_08_C0 */
7361   {
7362     { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7363   },
7364
7365   /* VEX_LEN_XOP_08_C1 */
7366   {
7367     { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7368   },
7369
7370   /* VEX_LEN_XOP_08_C2 */
7371   {
7372     { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7373   },
7374
7375   /* VEX_LEN_XOP_08_C3 */
7376   {
7377     { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7378   },
7379
7380   /* VEX_LEN_XOP_08_CC */
7381   {
7382     { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7383   },
7384
7385   /* VEX_LEN_XOP_08_CD */
7386   {
7387     { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7388   },
7389
7390   /* VEX_LEN_XOP_08_CE */
7391   {
7392     { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7393   },
7394
7395   /* VEX_LEN_XOP_08_CF */
7396   {
7397     { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7398   },
7399
7400   /* VEX_LEN_XOP_08_EC */
7401   {
7402     { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7403   },
7404
7405   /* VEX_LEN_XOP_08_ED */
7406   {
7407     { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7408   },
7409
7410   /* VEX_LEN_XOP_08_EE */
7411   {
7412     { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7413   },
7414
7415   /* VEX_LEN_XOP_08_EF */
7416   {
7417     { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7418   },
7419
7420   /* VEX_LEN_XOP_09_01 */
7421   {
7422     { REG_TABLE (REG_XOP_09_01_L_0) },
7423   },
7424
7425   /* VEX_LEN_XOP_09_02 */
7426   {
7427     { REG_TABLE (REG_XOP_09_02_L_0) },
7428   },
7429
7430   /* VEX_LEN_XOP_09_12 */
7431   {
7432     { REG_TABLE (REG_XOP_09_12_L_0) },
7433   },
7434
7435   /* VEX_LEN_XOP_09_82_W_0 */
7436   {
7437     { "vfrczss",        { XM, EXd }, 0 },
7438   },
7439
7440   /* VEX_LEN_XOP_09_83_W_0 */
7441   {
7442     { "vfrczsd",        { XM, EXq }, 0 },
7443   },
7444
7445   /* VEX_LEN_XOP_09_90 */
7446   {
7447     { "vprotb",         { XM, EXx, VexW }, 0 },
7448   },
7449
7450   /* VEX_LEN_XOP_09_91 */
7451   {
7452     { "vprotw",         { XM, EXx, VexW }, 0 },
7453   },
7454
7455   /* VEX_LEN_XOP_09_92 */
7456   {
7457     { "vprotd",         { XM, EXx, VexW }, 0 },
7458   },
7459
7460   /* VEX_LEN_XOP_09_93 */
7461   {
7462     { "vprotq",         { XM, EXx, VexW }, 0 },
7463   },
7464
7465   /* VEX_LEN_XOP_09_94 */
7466   {
7467     { "vpshlb",         { XM, EXx, VexW }, 0 },
7468   },
7469
7470   /* VEX_LEN_XOP_09_95 */
7471   {
7472     { "vpshlw",         { XM, EXx, VexW }, 0 },
7473   },
7474
7475   /* VEX_LEN_XOP_09_96 */
7476   {
7477     { "vpshld",         { XM, EXx, VexW }, 0 },
7478   },
7479
7480   /* VEX_LEN_XOP_09_97 */
7481   {
7482     { "vpshlq",         { XM, EXx, VexW }, 0 },
7483   },
7484
7485   /* VEX_LEN_XOP_09_98 */
7486   {
7487     { "vpshab",         { XM, EXx, VexW }, 0 },
7488   },
7489
7490   /* VEX_LEN_XOP_09_99 */
7491   {
7492     { "vpshaw",         { XM, EXx, VexW }, 0 },
7493   },
7494
7495   /* VEX_LEN_XOP_09_9A */
7496   {
7497     { "vpshad",         { XM, EXx, VexW }, 0 },
7498   },
7499
7500   /* VEX_LEN_XOP_09_9B */
7501   {
7502     { "vpshaq",         { XM, EXx, VexW }, 0 },
7503   },
7504
7505   /* VEX_LEN_XOP_09_C1 */
7506   {
7507     { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7508   },
7509
7510   /* VEX_LEN_XOP_09_C2 */
7511   {
7512     { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7513   },
7514
7515   /* VEX_LEN_XOP_09_C3 */
7516   {
7517     { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7518   },
7519
7520   /* VEX_LEN_XOP_09_C6 */
7521   {
7522     { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7523   },
7524
7525   /* VEX_LEN_XOP_09_C7 */
7526   {
7527     { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7528   },
7529
7530   /* VEX_LEN_XOP_09_CB */
7531   {
7532     { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7533   },
7534
7535   /* VEX_LEN_XOP_09_D1 */
7536   {
7537     { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7538   },
7539
7540   /* VEX_LEN_XOP_09_D2 */
7541   {
7542     { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7543   },
7544
7545   /* VEX_LEN_XOP_09_D3 */
7546   {
7547     { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7548   },
7549
7550   /* VEX_LEN_XOP_09_D6 */
7551   {
7552     { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7553   },
7554
7555   /* VEX_LEN_XOP_09_D7 */
7556   {
7557     { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7558   },
7559
7560   /* VEX_LEN_XOP_09_DB */
7561   {
7562     { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7563   },
7564
7565   /* VEX_LEN_XOP_09_E1 */
7566   {
7567     { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7568   },
7569
7570   /* VEX_LEN_XOP_09_E2 */
7571   {
7572     { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7573   },
7574
7575   /* VEX_LEN_XOP_09_E3 */
7576   {
7577     { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7578   },
7579
7580   /* VEX_LEN_XOP_0A_12 */
7581   {
7582     { REG_TABLE (REG_XOP_0A_12_L_0) },
7583   },
7584 };
7585
7586 #include "i386-dis-evex-len.h"
7587
7588 static const struct dis386 vex_w_table[][2] = {
7589   {
7590     /* VEX_W_0F41_L_1_M_1 */
7591     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7592     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7593   },
7594   {
7595     /* VEX_W_0F42_L_1_M_1 */
7596     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7597     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7598   },
7599   {
7600     /* VEX_W_0F44_L_0_M_1 */
7601     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7602     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7603   },
7604   {
7605     /* VEX_W_0F45_L_1_M_1 */
7606     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7607     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7608   },
7609   {
7610     /* VEX_W_0F46_L_1_M_1 */
7611     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7612     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7613   },
7614   {
7615     /* VEX_W_0F47_L_1_M_1 */
7616     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7617     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7618   },
7619   {
7620     /* VEX_W_0F4A_L_1_M_1 */
7621     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7622     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7623   },
7624   {
7625     /* VEX_W_0F4B_L_1_M_1 */
7626     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7627     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7628   },
7629   {
7630     /* VEX_W_0F90_L_0 */
7631     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7632     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7633   },
7634   {
7635     /* VEX_W_0F91_L_0_M_0 */
7636     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7637     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7638   },
7639   {
7640     /* VEX_W_0F92_L_0_M_1 */
7641     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7642     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7643   },
7644   {
7645     /* VEX_W_0F93_L_0_M_1 */
7646     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7647     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7648   },
7649   {
7650     /* VEX_W_0F98_L_0_M_1 */
7651     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7652     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7653   },
7654   {
7655     /* VEX_W_0F99_L_0_M_1 */
7656     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7658   },
7659   {
7660     /* VEX_W_0F380C  */
7661     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7662   },
7663   {
7664     /* VEX_W_0F380D  */
7665     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7666   },
7667   {
7668     /* VEX_W_0F380E  */
7669     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7670   },
7671   {
7672     /* VEX_W_0F380F  */
7673     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7674   },
7675   {
7676     /* VEX_W_0F3813 */
7677     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7678   },
7679   {
7680     /* VEX_W_0F3816_L_1  */
7681     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7682   },
7683   {
7684     /* VEX_W_0F3818 */
7685     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7686   },
7687   {
7688     /* VEX_W_0F3819_L_1 */
7689     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7690   },
7691   {
7692     /* VEX_W_0F381A_L_1 */
7693     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7694   },
7695   {
7696     /* VEX_W_0F382C */
7697     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7698   },
7699   {
7700     /* VEX_W_0F382D */
7701     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7702   },
7703   {
7704     /* VEX_W_0F382E */
7705     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7706   },
7707   {
7708     /* VEX_W_0F382F */
7709     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7710   },
7711   {
7712     /* VEX_W_0F3836  */
7713     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7714   },
7715   {
7716     /* VEX_W_0F3846 */
7717     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7718   },
7719   {
7720     /* VEX_W_0F3849_X86_64_L_0 */
7721     { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7722   },
7723   {
7724     /* VEX_W_0F384B_X86_64_L_0 */
7725     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7726   },
7727   {
7728     /* VEX_W_0F3850 */
7729     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7730   },
7731   {
7732     /* VEX_W_0F3851 */
7733     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7734   },
7735   {
7736     /* VEX_W_0F3852 */
7737     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7738   },
7739   {
7740     /* VEX_W_0F3853 */
7741     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7742   },
7743   {
7744     /* VEX_W_0F3858 */
7745     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7746   },
7747   {
7748     /* VEX_W_0F3859 */
7749     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7750   },
7751   {
7752     /* VEX_W_0F385A_L_0 */
7753     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7754   },
7755   {
7756     /* VEX_W_0F385C_X86_64_L_0 */
7757     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7758   },
7759   {
7760     /* VEX_W_0F385E_X86_64_L_0 */
7761     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7762   },
7763   {
7764     /* VEX_W_0F386C_X86_64_L_0 */
7765     { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7766   },
7767   {
7768     /* VEX_W_0F3872_P_1 */
7769     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7770   },
7771   {
7772     /* VEX_W_0F3878 */
7773     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7774   },
7775   {
7776     /* VEX_W_0F3879 */
7777     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7778   },
7779   {
7780     /* VEX_W_0F38B0 */
7781     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7782   },
7783   {
7784     /* VEX_W_0F38B1 */
7785     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7786   },
7787   {
7788     /* VEX_W_0F38B4 */
7789     { Bad_Opcode },
7790     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7791   },
7792   {
7793     /* VEX_W_0F38B5 */
7794     { Bad_Opcode },
7795     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7796   },
7797   {
7798     /* VEX_W_0F38CB_P_3 */
7799     { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7800   },
7801   {
7802     /* VEX_W_0F38CC_P_3 */
7803     { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7804   },
7805   {
7806     /* VEX_W_0F38CD_P_3 */
7807     { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7808   },
7809   {
7810     /* VEX_W_0F38CF */
7811     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7812   },
7813   {
7814     /* VEX_W_0F38D2 */
7815     { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7816   },
7817   {
7818     /* VEX_W_0F38D3 */
7819     { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7820   },
7821   {
7822     /* VEX_W_0F38DA */
7823     { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7824   },
7825   {
7826     /* VEX_W_0F3A00_L_1 */
7827     { Bad_Opcode },
7828     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7829   },
7830   {
7831     /* VEX_W_0F3A01_L_1 */
7832     { Bad_Opcode },
7833     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7834   },
7835   {
7836     /* VEX_W_0F3A02 */
7837     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7838   },
7839   {
7840     /* VEX_W_0F3A04 */
7841     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7842   },
7843   {
7844     /* VEX_W_0F3A05 */
7845     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7846   },
7847   {
7848     /* VEX_W_0F3A06_L_1 */
7849     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7850   },
7851   {
7852     /* VEX_W_0F3A18_L_1 */
7853     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7854   },
7855   {
7856     /* VEX_W_0F3A19_L_1 */
7857     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7858   },
7859   {
7860     /* VEX_W_0F3A1D */
7861     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7862   },
7863   {
7864     /* VEX_W_0F3A38_L_1 */
7865     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7866   },
7867   {
7868     /* VEX_W_0F3A39_L_1 */
7869     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7870   },
7871   {
7872     /* VEX_W_0F3A46_L_1 */
7873     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7874   },
7875   {
7876     /* VEX_W_0F3A4A */
7877     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7878   },
7879   {
7880     /* VEX_W_0F3A4B */
7881     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7882   },
7883   {
7884     /* VEX_W_0F3A4C */
7885     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7886   },
7887   {
7888     /* VEX_W_0F3ACE */
7889     { Bad_Opcode },
7890     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7891   },
7892   {
7893     /* VEX_W_0F3ACF */
7894     { Bad_Opcode },
7895     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7896   },
7897   {
7898     /* VEX_W_0F3ADE */
7899     { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7900   },
7901   {
7902     /* VEX_W_MAP7_F8_L_0 */
7903     { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7904   },
7905   /* VEX_W_XOP_08_85_L_0 */
7906   {
7907     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7908   },
7909   /* VEX_W_XOP_08_86_L_0 */
7910   {
7911     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7912   },
7913   /* VEX_W_XOP_08_87_L_0 */
7914   {
7915     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7916   },
7917   /* VEX_W_XOP_08_8E_L_0 */
7918   {
7919     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7920   },
7921   /* VEX_W_XOP_08_8F_L_0 */
7922   {
7923     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7924   },
7925   /* VEX_W_XOP_08_95_L_0 */
7926   {
7927     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7928   },
7929   /* VEX_W_XOP_08_96_L_0 */
7930   {
7931     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7932   },
7933   /* VEX_W_XOP_08_97_L_0 */
7934   {
7935     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7936   },
7937   /* VEX_W_XOP_08_9E_L_0 */
7938   {
7939     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7940   },
7941   /* VEX_W_XOP_08_9F_L_0 */
7942   {
7943     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7944   },
7945   /* VEX_W_XOP_08_A6_L_0 */
7946   {
7947     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7948   },
7949   /* VEX_W_XOP_08_B6_L_0 */
7950   {
7951     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7952   },
7953   /* VEX_W_XOP_08_C0_L_0 */
7954   {
7955     { "vprotb",         { XM, EXx, Ib }, 0 },
7956   },
7957   /* VEX_W_XOP_08_C1_L_0 */
7958   {
7959     { "vprotw",         { XM, EXx, Ib }, 0 },
7960   },
7961   /* VEX_W_XOP_08_C2_L_0 */
7962   {
7963     { "vprotd",         { XM, EXx, Ib }, 0 },
7964   },
7965   /* VEX_W_XOP_08_C3_L_0 */
7966   {
7967     { "vprotq",         { XM, EXx, Ib }, 0 },
7968   },
7969   /* VEX_W_XOP_08_CC_L_0 */
7970   {
7971      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7972   },
7973   /* VEX_W_XOP_08_CD_L_0 */
7974   {
7975      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7976   },
7977   /* VEX_W_XOP_08_CE_L_0 */
7978   {
7979      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7980   },
7981   /* VEX_W_XOP_08_CF_L_0 */
7982   {
7983      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7984   },
7985   /* VEX_W_XOP_08_EC_L_0 */
7986   {
7987      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7988   },
7989   /* VEX_W_XOP_08_ED_L_0 */
7990   {
7991      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7992   },
7993   /* VEX_W_XOP_08_EE_L_0 */
7994   {
7995      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7996   },
7997   /* VEX_W_XOP_08_EF_L_0 */
7998   {
7999      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8000   },
8001   /* VEX_W_XOP_09_80 */
8002   {
8003     { "vfrczps",        { XM, EXx }, 0 },
8004   },
8005   /* VEX_W_XOP_09_81 */
8006   {
8007     { "vfrczpd",        { XM, EXx }, 0 },
8008   },
8009   /* VEX_W_XOP_09_82 */
8010   {
8011     { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8012   },
8013   /* VEX_W_XOP_09_83 */
8014   {
8015     { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8016   },
8017   /* VEX_W_XOP_09_C1_L_0 */
8018   {
8019     { "vphaddbw",       { XM, EXxmm }, 0 },
8020   },
8021   /* VEX_W_XOP_09_C2_L_0 */
8022   {
8023     { "vphaddbd",       { XM, EXxmm }, 0 },
8024   },
8025   /* VEX_W_XOP_09_C3_L_0 */
8026   {
8027     { "vphaddbq",       { XM, EXxmm }, 0 },
8028   },
8029   /* VEX_W_XOP_09_C6_L_0 */
8030   {
8031     { "vphaddwd",       { XM, EXxmm }, 0 },
8032   },
8033   /* VEX_W_XOP_09_C7_L_0 */
8034   {
8035     { "vphaddwq",       { XM, EXxmm }, 0 },
8036   },
8037   /* VEX_W_XOP_09_CB_L_0 */
8038   {
8039     { "vphadddq",       { XM, EXxmm }, 0 },
8040   },
8041   /* VEX_W_XOP_09_D1_L_0 */
8042   {
8043     { "vphaddubw",      { XM, EXxmm }, 0 },
8044   },
8045   /* VEX_W_XOP_09_D2_L_0 */
8046   {
8047     { "vphaddubd",      { XM, EXxmm }, 0 },
8048   },
8049   /* VEX_W_XOP_09_D3_L_0 */
8050   {
8051     { "vphaddubq",      { XM, EXxmm }, 0 },
8052   },
8053   /* VEX_W_XOP_09_D6_L_0 */
8054   {
8055     { "vphadduwd",      { XM, EXxmm }, 0 },
8056   },
8057   /* VEX_W_XOP_09_D7_L_0 */
8058   {
8059     { "vphadduwq",      { XM, EXxmm }, 0 },
8060   },
8061   /* VEX_W_XOP_09_DB_L_0 */
8062   {
8063     { "vphaddudq",      { XM, EXxmm }, 0 },
8064   },
8065   /* VEX_W_XOP_09_E1_L_0 */
8066   {
8067     { "vphsubbw",       { XM, EXxmm }, 0 },
8068   },
8069   /* VEX_W_XOP_09_E2_L_0 */
8070   {
8071     { "vphsubwd",       { XM, EXxmm }, 0 },
8072   },
8073   /* VEX_W_XOP_09_E3_L_0 */
8074   {
8075     { "vphsubdq",       { XM, EXxmm }, 0 },
8076   },
8077
8078 #include "i386-dis-evex-w.h"
8079 };
8080
8081 static const struct dis386 mod_table[][2] = {
8082   {
8083     /* MOD_62_32BIT */
8084     { "bound{S|}",      { Gv, Ma }, 0 },
8085     { EVEX_TABLE () },
8086   },
8087   {
8088     /* MOD_C4_32BIT */
8089     { "lesS",           { Gv, Mp }, 0 },
8090     { VEX_C4_TABLE () },
8091   },
8092   {
8093     /* MOD_C5_32BIT */
8094     { "ldsS",           { Gv, Mp }, 0 },
8095     { VEX_C5_TABLE () },
8096   },
8097   {
8098     /* MOD_0F01_REG_0 */
8099     { X86_64_TABLE (X86_64_0F01_REG_0) },
8100     { RM_TABLE (RM_0F01_REG_0) },
8101   },
8102   {
8103     /* MOD_0F01_REG_1 */
8104     { X86_64_TABLE (X86_64_0F01_REG_1) },
8105     { RM_TABLE (RM_0F01_REG_1) },
8106   },
8107   {
8108     /* MOD_0F01_REG_2 */
8109     { X86_64_TABLE (X86_64_0F01_REG_2) },
8110     { RM_TABLE (RM_0F01_REG_2) },
8111   },
8112   {
8113     /* MOD_0F01_REG_3 */
8114     { X86_64_TABLE (X86_64_0F01_REG_3) },
8115     { RM_TABLE (RM_0F01_REG_3) },
8116   },
8117   {
8118     /* MOD_0F01_REG_5 */
8119     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8120     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8121   },
8122   {
8123     /* MOD_0F01_REG_7 */
8124     { "invlpg",         { Mb }, 0 },
8125     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8126   },
8127   {
8128     /* MOD_0F12_PREFIX_0 */
8129     { "%XEVmovlpYX",    { XM, Vex, EXq }, 0 },
8130     { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8131   },
8132   {
8133     /* MOD_0F16_PREFIX_0 */
8134     { "%XEVmovhpYX",    { XM, Vex, EXq }, 0 },
8135     { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8136   },
8137   {
8138     /* MOD_0F18_REG_0 */
8139     { "prefetchnta",    { Mb }, 0 },
8140     { "nopQ",           { Ev }, 0 },
8141   },
8142   {
8143     /* MOD_0F18_REG_1 */
8144     { "prefetcht0",     { Mb }, 0 },
8145     { "nopQ",           { Ev }, 0 },
8146   },
8147   {
8148     /* MOD_0F18_REG_2 */
8149     { "prefetcht1",     { Mb }, 0 },
8150     { "nopQ",           { Ev }, 0 },
8151   },
8152   {
8153     /* MOD_0F18_REG_3 */
8154     { "prefetcht2",     { Mb }, 0 },
8155     { "nopQ",           { Ev }, 0 },
8156   },
8157   {
8158     /* MOD_0F18_REG_6 */
8159     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8160     { "nopQ",           { Ev }, 0 },
8161   },
8162   {
8163     /* MOD_0F18_REG_7 */
8164     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8165     { "nopQ",           { Ev }, 0 },
8166   },
8167   {
8168     /* MOD_0F1A_PREFIX_0 */
8169     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8170     { "nopQ",           { Ev }, 0 },
8171   },
8172   {
8173     /* MOD_0F1B_PREFIX_0 */
8174     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8175     { "nopQ",           { Ev }, 0 },
8176   },
8177   {
8178     /* MOD_0F1B_PREFIX_1 */
8179     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8180     { "nopQ",           { Ev }, PREFIX_IGNORED },
8181   },
8182   {
8183     /* MOD_0F1C_PREFIX_0 */
8184     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8185     { "nopQ",           { Ev }, 0 },
8186   },
8187   {
8188     /* MOD_0F1E_PREFIX_1 */
8189     { "nopQ",           { Ev }, PREFIX_IGNORED },
8190     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8191   },
8192   {
8193     /* MOD_0FAE_REG_0 */
8194     { "fxsave",         { FXSAVE }, 0 },
8195     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8196   },
8197   {
8198     /* MOD_0FAE_REG_1 */
8199     { "fxrstor",        { FXSAVE }, 0 },
8200     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8201   },
8202   {
8203     /* MOD_0FAE_REG_2 */
8204     { "ldmxcsr",        { Md }, 0 },
8205     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8206   },
8207   {
8208     /* MOD_0FAE_REG_3 */
8209     { "stmxcsr",        { Md }, 0 },
8210     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8211   },
8212   {
8213     /* MOD_0FAE_REG_4 */
8214     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8215     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8216   },
8217   {
8218     /* MOD_0FAE_REG_5 */
8219     { "xrstor",         { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8220     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8221   },
8222   {
8223     /* MOD_0FAE_REG_6 */
8224     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8225     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8226   },
8227   {
8228     /* MOD_0FAE_REG_7 */
8229     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8230     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8231   },
8232   {
8233     /* MOD_0FC7_REG_6 */
8234     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8235     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8236   },
8237   {
8238     /* MOD_0FC7_REG_7 */
8239     { "vmptrst",        { Mq }, 0 },
8240     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8241   },
8242   {
8243     /* MOD_0F38DC_PREFIX_1 */
8244     { "aesenc128kl",    { XM, M }, 0 },
8245     { "loadiwkey",      { XM, EXx }, 0 },
8246   },
8247   /* MOD_0F38F8 */
8248   {
8249     { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8250     { X86_64_TABLE (X86_64_0F38F8_M_1) },
8251   },
8252   {
8253     /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8254     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8255     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8256   },
8257
8258 #include "i386-dis-evex-mod.h"
8259 };
8260
8261 static const struct dis386 rm_table[][8] = {
8262   {
8263     /* RM_C6_REG_7 */
8264     { "xabort",         { Skip_MODRM, Ib }, 0 },
8265   },
8266   {
8267     /* RM_C7_REG_7 */
8268     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8269   },
8270   {
8271     /* RM_0F01_REG_0 */
8272     { "enclv",          { Skip_MODRM }, 0 },
8273     { "vmcall",         { Skip_MODRM }, 0 },
8274     { "vmlaunch",       { Skip_MODRM }, 0 },
8275     { "vmresume",       { Skip_MODRM }, 0 },
8276     { "vmxoff",         { Skip_MODRM }, 0 },
8277     { "pconfig",        { Skip_MODRM }, 0 },
8278     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8279     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8280   },
8281   {
8282     /* RM_0F01_REG_1 */
8283     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8284     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8285     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8286     { "stac",           { Skip_MODRM }, 0 },
8287     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8288     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8289     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8290     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8291   },
8292   {
8293     /* RM_0F01_REG_2 */
8294     { "xgetbv",         { Skip_MODRM }, 0 },
8295     { "xsetbv",         { Skip_MODRM }, 0 },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { "vmfunc",         { Skip_MODRM }, 0 },
8299     { "xend",           { Skip_MODRM }, 0 },
8300     { "xtest",          { Skip_MODRM }, 0 },
8301     { "enclu",          { Skip_MODRM }, 0 },
8302   },
8303   {
8304     /* RM_0F01_REG_3 */
8305     { "vmrun",          { Skip_MODRM }, 0 },
8306     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8307     { "vmload",         { Skip_MODRM }, 0 },
8308     { "vmsave",         { Skip_MODRM }, 0 },
8309     { "stgi",           { Skip_MODRM }, 0 },
8310     { "clgi",           { Skip_MODRM }, 0 },
8311     { "skinit",         { Skip_MODRM }, 0 },
8312     { "invlpga",        { Skip_MODRM }, 0 },
8313   },
8314   {
8315     /* RM_0F01_REG_5_MOD_3 */
8316     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8317     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8318     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8319     { Bad_Opcode },
8320     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8321     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8322     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8323     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8324   },
8325   {
8326     /* RM_0F01_REG_7_MOD_3 */
8327     { "swapgs",         { Skip_MODRM }, 0  },
8328     { "rdtscp",         { Skip_MODRM }, 0  },
8329     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8330     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8331     { "clzero",         { Skip_MODRM }, 0  },
8332     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8333     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8334     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8335   },
8336   {
8337     /* RM_0F1E_P_1_MOD_3_REG_7 */
8338     { "nopQ",           { Ev }, PREFIX_IGNORED },
8339     { "nopQ",           { Ev }, PREFIX_IGNORED },
8340     { "endbr64",        { Skip_MODRM }, 0 },
8341     { "endbr32",        { Skip_MODRM }, 0 },
8342     { "nopQ",           { Ev }, PREFIX_IGNORED },
8343     { "nopQ",           { Ev }, PREFIX_IGNORED },
8344     { "nopQ",           { Ev }, PREFIX_IGNORED },
8345     { "nopQ",           { Ev }, PREFIX_IGNORED },
8346   },
8347   {
8348     /* RM_0FAE_REG_6_MOD_3 */
8349     { "mfence",         { Skip_MODRM }, 0 },
8350   },
8351   {
8352     /* RM_0FAE_REG_7_MOD_3 */
8353     { "sfence",         { Skip_MODRM }, 0 },
8354   },
8355   {
8356     /* RM_0F3A0F_P_1_R_0 */
8357     { "hreset",         { Skip_MODRM, Ib }, 0 },
8358   },
8359   {
8360     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8361     { "tilerelease",    { Skip_MODRM }, 0 },
8362   },
8363   {
8364     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8365     { "tilezero",       { TMM, Skip_MODRM }, 0 },
8366   },
8367 };
8368
8369 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8370
8371 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8372    in conflict with actual prefix opcodes.  */
8373 #define REP_PREFIX      0x01
8374 #define XACQUIRE_PREFIX 0x02
8375 #define XRELEASE_PREFIX 0x03
8376 #define BND_PREFIX      0x04
8377 #define NOTRACK_PREFIX  0x05
8378
8379 static enum {
8380   ckp_okay,
8381   ckp_bogus,
8382   ckp_fetch_error,
8383 }
8384 ckprefix (instr_info *ins)
8385 {
8386   int i, length;
8387   uint8_t newrex;
8388
8389   i = 0;
8390   length = 0;
8391   /* The maximum instruction length is 15bytes.  */
8392   while (length < MAX_CODE_LENGTH - 1)
8393     {
8394       if (!fetch_code (ins->info, ins->codep + 1))
8395         return ckp_fetch_error;
8396       newrex = 0;
8397       switch (*ins->codep)
8398         {
8399         /* REX prefixes family.  */
8400         case 0x40:
8401         case 0x41:
8402         case 0x42:
8403         case 0x43:
8404         case 0x44:
8405         case 0x45:
8406         case 0x46:
8407         case 0x47:
8408         case 0x48:
8409         case 0x49:
8410         case 0x4a:
8411         case 0x4b:
8412         case 0x4c:
8413         case 0x4d:
8414         case 0x4e:
8415         case 0x4f:
8416           if (ins->address_mode == mode_64bit)
8417             newrex = *ins->codep;
8418           else
8419             return ckp_okay;
8420           ins->last_rex_prefix = i;
8421           break;
8422         /* REX2 must be the last prefix. */
8423         case REX2_OPCODE:
8424           if (ins->address_mode == mode_64bit)
8425             {
8426               if (ins->last_rex_prefix >= 0)
8427                 return ckp_bogus;
8428
8429               ins->codep++;
8430               if (!fetch_code (ins->info, ins->codep + 1))
8431                 return ckp_fetch_error;
8432               ins->rex2_payload = *ins->codep;
8433               ins->rex2 = ins->rex2_payload >> 4;
8434               ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8435               ins->codep++;
8436               ins->last_rex2_prefix = i;
8437               ins->all_prefixes[i] = REX2_OPCODE;
8438             }
8439           return ckp_okay;
8440         case 0xf3:
8441           ins->prefixes |= PREFIX_REPZ;
8442           ins->last_repz_prefix = i;
8443           break;
8444         case 0xf2:
8445           ins->prefixes |= PREFIX_REPNZ;
8446           ins->last_repnz_prefix = i;
8447           break;
8448         case 0xf0:
8449           ins->prefixes |= PREFIX_LOCK;
8450           ins->last_lock_prefix = i;
8451           break;
8452         case 0x2e:
8453           ins->prefixes |= PREFIX_CS;
8454           ins->last_seg_prefix = i;
8455           if (ins->address_mode != mode_64bit)
8456             ins->active_seg_prefix = PREFIX_CS;
8457           break;
8458         case 0x36:
8459           ins->prefixes |= PREFIX_SS;
8460           ins->last_seg_prefix = i;
8461           if (ins->address_mode != mode_64bit)
8462             ins->active_seg_prefix = PREFIX_SS;
8463           break;
8464         case 0x3e:
8465           ins->prefixes |= PREFIX_DS;
8466           ins->last_seg_prefix = i;
8467           if (ins->address_mode != mode_64bit)
8468             ins->active_seg_prefix = PREFIX_DS;
8469           break;
8470         case 0x26:
8471           ins->prefixes |= PREFIX_ES;
8472           ins->last_seg_prefix = i;
8473           if (ins->address_mode != mode_64bit)
8474             ins->active_seg_prefix = PREFIX_ES;
8475           break;
8476         case 0x64:
8477           ins->prefixes |= PREFIX_FS;
8478           ins->last_seg_prefix = i;
8479           ins->active_seg_prefix = PREFIX_FS;
8480           break;
8481         case 0x65:
8482           ins->prefixes |= PREFIX_GS;
8483           ins->last_seg_prefix = i;
8484           ins->active_seg_prefix = PREFIX_GS;
8485           break;
8486         case 0x66:
8487           ins->prefixes |= PREFIX_DATA;
8488           ins->last_data_prefix = i;
8489           break;
8490         case 0x67:
8491           ins->prefixes |= PREFIX_ADDR;
8492           ins->last_addr_prefix = i;
8493           break;
8494         case FWAIT_OPCODE:
8495           /* fwait is really an instruction.  If there are prefixes
8496              before the fwait, they belong to the fwait, *not* to the
8497              following instruction.  */
8498           ins->fwait_prefix = i;
8499           if (ins->prefixes || ins->rex)
8500             {
8501               ins->prefixes |= PREFIX_FWAIT;
8502               ins->codep++;
8503               /* This ensures that the previous REX prefixes are noticed
8504                  as unused prefixes, as in the return case below.  */
8505               return ins->rex ? ckp_bogus : ckp_okay;
8506             }
8507           ins->prefixes = PREFIX_FWAIT;
8508           break;
8509         default:
8510           return ckp_okay;
8511         }
8512       /* Rex is ignored when followed by another prefix.  */
8513       if (ins->rex)
8514         return ckp_bogus;
8515       if (*ins->codep != FWAIT_OPCODE)
8516         ins->all_prefixes[i++] = *ins->codep;
8517       ins->rex = newrex;
8518       ins->codep++;
8519       length++;
8520     }
8521   return ckp_bogus;
8522 }
8523
8524 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8525    prefix byte.  */
8526
8527 static const char *
8528 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8529 {
8530   static const char *rexes [16] =
8531     {
8532       "rex",            /* 0x40 */
8533       "rex.B",          /* 0x41 */
8534       "rex.X",          /* 0x42 */
8535       "rex.XB",         /* 0x43 */
8536       "rex.R",          /* 0x44 */
8537       "rex.RB",         /* 0x45 */
8538       "rex.RX",         /* 0x46 */
8539       "rex.RXB",        /* 0x47 */
8540       "rex.W",          /* 0x48 */
8541       "rex.WB",         /* 0x49 */
8542       "rex.WX",         /* 0x4a */
8543       "rex.WXB",        /* 0x4b */
8544       "rex.WR",         /* 0x4c */
8545       "rex.WRB",        /* 0x4d */
8546       "rex.WRX",        /* 0x4e */
8547       "rex.WRXB",       /* 0x4f */
8548     };
8549
8550   switch (pref)
8551     {
8552     /* REX prefixes family.  */
8553     case 0x40:
8554     case 0x41:
8555     case 0x42:
8556     case 0x43:
8557     case 0x44:
8558     case 0x45:
8559     case 0x46:
8560     case 0x47:
8561     case 0x48:
8562     case 0x49:
8563     case 0x4a:
8564     case 0x4b:
8565     case 0x4c:
8566     case 0x4d:
8567     case 0x4e:
8568     case 0x4f:
8569       return rexes [pref - 0x40];
8570     case 0xf3:
8571       return "repz";
8572     case 0xf2:
8573       return "repnz";
8574     case 0xf0:
8575       return "lock";
8576     case 0x2e:
8577       return "cs";
8578     case 0x36:
8579       return "ss";
8580     case 0x3e:
8581       return "ds";
8582     case 0x26:
8583       return "es";
8584     case 0x64:
8585       return "fs";
8586     case 0x65:
8587       return "gs";
8588     case 0x66:
8589       return (sizeflag & DFLAG) ? "data16" : "data32";
8590     case 0x67:
8591       if (mode == mode_64bit)
8592         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8593       else
8594         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8595     case FWAIT_OPCODE:
8596       return "fwait";
8597     case REP_PREFIX:
8598       return "rep";
8599     case XACQUIRE_PREFIX:
8600       return "xacquire";
8601     case XRELEASE_PREFIX:
8602       return "xrelease";
8603     case BND_PREFIX:
8604       return "bnd";
8605     case NOTRACK_PREFIX:
8606       return "notrack";
8607     case REX2_OPCODE:
8608       return "rex2";
8609     default:
8610       return NULL;
8611     }
8612 }
8613
8614 void
8615 print_i386_disassembler_options (FILE *stream)
8616 {
8617   fprintf (stream, _("\n\
8618 The following i386/x86-64 specific disassembler options are supported for use\n\
8619 with the -M switch (multiple options should be separated by commas):\n"));
8620
8621   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8622   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8623   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8624   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8625   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8626   fprintf (stream, _("  att-mnemonic  (AT&T syntax only)\n"
8627                      "              Display instruction with AT&T mnemonic\n"));
8628   fprintf (stream, _("  intel-mnemonic  (AT&T syntax only)\n"
8629                      "              Display instruction with Intel mnemonic\n"));
8630   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8631   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8632   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8633   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8634   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8635   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8636   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8637   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8638 }
8639
8640 /* Bad opcode.  */
8641 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8642
8643 /* Fetch error indicator.  */
8644 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8645
8646 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8647
8648 /* Get a pointer to struct dis386 with a valid name.  */
8649
8650 static const struct dis386 *
8651 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8652 {
8653   int vindex, vex_table_index;
8654
8655   if (dp->name != NULL)
8656     return dp;
8657
8658   switch (dp->op[0].bytemode)
8659     {
8660     case USE_REG_TABLE:
8661       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8662       break;
8663
8664     case USE_MOD_TABLE:
8665       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8666       dp = &mod_table[dp->op[1].bytemode][vindex];
8667       break;
8668
8669     case USE_RM_TABLE:
8670       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8671       break;
8672
8673     case USE_PREFIX_TABLE:
8674     use_prefix_table:
8675       if (ins->need_vex)
8676         {
8677           /* The prefix in VEX is implicit.  */
8678           switch (ins->vex.prefix)
8679             {
8680             case 0:
8681               vindex = 0;
8682               break;
8683             case REPE_PREFIX_OPCODE:
8684               vindex = 1;
8685               break;
8686             case DATA_PREFIX_OPCODE:
8687               vindex = 2;
8688               break;
8689             case REPNE_PREFIX_OPCODE:
8690               vindex = 3;
8691               break;
8692             default:
8693               abort ();
8694               break;
8695             }
8696         }
8697       else
8698         {
8699           int last_prefix = -1;
8700           int prefix = 0;
8701           vindex = 0;
8702           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8703              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8704              last one wins.  */
8705           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8706             {
8707               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8708                 {
8709                   vindex = 1;
8710                   prefix = PREFIX_REPZ;
8711                   last_prefix = ins->last_repz_prefix;
8712                 }
8713               else
8714                 {
8715                   vindex = 3;
8716                   prefix = PREFIX_REPNZ;
8717                   last_prefix = ins->last_repnz_prefix;
8718                 }
8719
8720               /* Check if prefix should be ignored.  */
8721               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8722                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8723                    & prefix) != 0
8724                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8725                 vindex = 0;
8726             }
8727
8728           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8729             {
8730               vindex = 2;
8731               prefix = PREFIX_DATA;
8732               last_prefix = ins->last_data_prefix;
8733             }
8734
8735           if (vindex != 0)
8736             {
8737               ins->used_prefixes |= prefix;
8738               ins->all_prefixes[last_prefix] = 0;
8739             }
8740         }
8741       dp = &prefix_table[dp->op[1].bytemode][vindex];
8742       break;
8743
8744     case USE_X86_64_EVEX_FROM_VEX_TABLE:
8745     case USE_X86_64_EVEX_PFX_TABLE:
8746     case USE_X86_64_EVEX_W_TABLE:
8747     case USE_X86_64_EVEX_MEM_W_TABLE:
8748       ins->evex_type = evex_from_vex;
8749       /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8750          EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0.  */
8751       if (ins->address_mode != mode_64bit
8752           || (ins->vex.mask_register_specifier & 0x3) != 0
8753           || ins->vex.ll != 0
8754           || ins->vex.zeroing != 0
8755           || ins->vex.b)
8756         return &bad_opcode;
8757
8758       if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
8759         goto use_prefix_table;
8760       if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
8761         goto use_vex_w_table;
8762       if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
8763         {
8764           if (ins->modrm.mod == 3)
8765             return &bad_opcode;
8766           goto use_vex_w_table;
8767         }
8768
8769       /* Fall through.  */
8770     case USE_X86_64_TABLE:
8771       vindex = ins->address_mode == mode_64bit ? 1 : 0;
8772       dp = &x86_64_table[dp->op[1].bytemode][vindex];
8773       break;
8774
8775     case USE_3BYTE_TABLE:
8776       if (ins->last_rex2_prefix >= 0)
8777         return &err_opcode;
8778       if (!fetch_code (ins->info, ins->codep + 2))
8779         return &err_opcode;
8780       vindex = *ins->codep++;
8781       dp = &three_byte_table[dp->op[1].bytemode][vindex];
8782       ins->end_codep = ins->codep;
8783       if (!fetch_modrm (ins))
8784         return &err_opcode;
8785       break;
8786
8787     case USE_VEX_LEN_TABLE:
8788       if (!ins->need_vex)
8789         abort ();
8790
8791       switch (ins->vex.length)
8792         {
8793         case 128:
8794           vindex = 0;
8795           break;
8796         case 512:
8797           /* This allows re-using in particular table entries where only
8798              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8799           if (ins->vex.evex)
8800             {
8801         case 256:
8802               vindex = 1;
8803               break;
8804             }
8805         /* Fall through.  */
8806         default:
8807           abort ();
8808           break;
8809         }
8810
8811       dp = &vex_len_table[dp->op[1].bytemode][vindex];
8812       break;
8813
8814     case USE_EVEX_LEN_TABLE:
8815       if (!ins->vex.evex)
8816         abort ();
8817
8818       switch (ins->vex.length)
8819         {
8820         case 128:
8821           vindex = 0;
8822           break;
8823         case 256:
8824           vindex = 1;
8825           break;
8826         case 512:
8827           vindex = 2;
8828           break;
8829         default:
8830           abort ();
8831           break;
8832         }
8833
8834       dp = &evex_len_table[dp->op[1].bytemode][vindex];
8835       break;
8836
8837     case USE_XOP_8F_TABLE:
8838       if (!fetch_code (ins->info, ins->codep + 3))
8839         return &err_opcode;
8840       ins->rex = ~(*ins->codep >> 5) & 0x7;
8841
8842       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8843       switch ((*ins->codep & 0x1f))
8844         {
8845         default:
8846           dp = &bad_opcode;
8847           return dp;
8848         case 0x8:
8849           vex_table_index = XOP_08;
8850           break;
8851         case 0x9:
8852           vex_table_index = XOP_09;
8853           break;
8854         case 0xa:
8855           vex_table_index = XOP_0A;
8856           break;
8857         }
8858       ins->codep++;
8859       ins->vex.w = *ins->codep & 0x80;
8860       if (ins->vex.w && ins->address_mode == mode_64bit)
8861         ins->rex |= REX_W;
8862
8863       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8864       if (ins->address_mode != mode_64bit)
8865         {
8866           /* In 16/32-bit mode REX_B is silently ignored.  */
8867           ins->rex &= ~REX_B;
8868         }
8869
8870       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8871       switch ((*ins->codep & 0x3))
8872         {
8873         case 0:
8874           break;
8875         case 1:
8876           ins->vex.prefix = DATA_PREFIX_OPCODE;
8877           break;
8878         case 2:
8879           ins->vex.prefix = REPE_PREFIX_OPCODE;
8880           break;
8881         case 3:
8882           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8883           break;
8884         }
8885       ins->need_vex = 3;
8886       ins->codep++;
8887       vindex = *ins->codep++;
8888       dp = &xop_table[vex_table_index][vindex];
8889
8890       ins->end_codep = ins->codep;
8891       if (!fetch_modrm (ins))
8892         return &err_opcode;
8893
8894       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8895          having to decode the bits for every otherwise valid encoding.  */
8896       if (ins->vex.prefix)
8897         return &bad_opcode;
8898       break;
8899
8900     case USE_VEX_C4_TABLE:
8901       /* VEX prefix.  */
8902       if (!fetch_code (ins->info, ins->codep + 3))
8903         return &err_opcode;
8904       ins->rex = ~(*ins->codep >> 5) & 0x7;
8905       switch ((*ins->codep & 0x1f))
8906         {
8907         default:
8908           dp = &bad_opcode;
8909           return dp;
8910         case 0x1:
8911           vex_table_index = VEX_0F;
8912           break;
8913         case 0x2:
8914           vex_table_index = VEX_0F38;
8915           break;
8916         case 0x3:
8917           vex_table_index = VEX_0F3A;
8918           break;
8919         case 0x7:
8920           vex_table_index = VEX_MAP7;
8921           break;
8922         }
8923       ins->codep++;
8924       ins->vex.w = *ins->codep & 0x80;
8925       if (ins->address_mode == mode_64bit)
8926         {
8927           if (ins->vex.w)
8928             ins->rex |= REX_W;
8929         }
8930       else
8931         {
8932           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8933              is ignored, other REX bits are 0 and the highest bit in
8934              VEX.vvvv is also ignored (but we mustn't clear it here).  */
8935           ins->rex = 0;
8936         }
8937       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8938       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8939       switch ((*ins->codep & 0x3))
8940         {
8941         case 0:
8942           break;
8943         case 1:
8944           ins->vex.prefix = DATA_PREFIX_OPCODE;
8945           break;
8946         case 2:
8947           ins->vex.prefix = REPE_PREFIX_OPCODE;
8948           break;
8949         case 3:
8950           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8951           break;
8952         }
8953       ins->need_vex = 3;
8954       ins->codep++;
8955       vindex = *ins->codep++;
8956       ins->condition_code = vindex & 0xf;
8957       if (vex_table_index != VEX_MAP7)
8958         dp = &vex_table[vex_table_index][vindex];
8959       else if (vindex == 0xf8)
8960         dp = &map7_f8_opcode;
8961       else
8962         dp = &bad_opcode;
8963       ins->end_codep = ins->codep;
8964       /* There is no MODRM byte for VEX0F 77.  */
8965       if ((vex_table_index != VEX_0F || vindex != 0x77)
8966           && !fetch_modrm (ins))
8967         return &err_opcode;
8968       break;
8969
8970     case USE_VEX_C5_TABLE:
8971       /* VEX prefix.  */
8972       if (!fetch_code (ins->info, ins->codep + 2))
8973         return &err_opcode;
8974       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
8975
8976       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
8977          VEX.vvvv is 1.  */
8978       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8979       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8980       switch ((*ins->codep & 0x3))
8981         {
8982         case 0:
8983           break;
8984         case 1:
8985           ins->vex.prefix = DATA_PREFIX_OPCODE;
8986           break;
8987         case 2:
8988           ins->vex.prefix = REPE_PREFIX_OPCODE;
8989           break;
8990         case 3:
8991           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8992           break;
8993         }
8994       ins->need_vex = 2;
8995       ins->codep++;
8996       vindex = *ins->codep++;
8997       dp = &vex_table[VEX_0F][vindex];
8998       ins->end_codep = ins->codep;
8999       /* There is no MODRM byte for VEX 77.  */
9000       if (vindex != 0x77 && !fetch_modrm (ins))
9001         return &err_opcode;
9002       break;
9003
9004     case USE_VEX_W_TABLE:
9005     use_vex_w_table:
9006       if (!ins->need_vex)
9007         abort ();
9008
9009       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9010       break;
9011
9012     case USE_EVEX_TABLE:
9013       ins->two_source_ops = false;
9014       /* EVEX prefix.  */
9015       ins->vex.evex = true;
9016       if (!fetch_code (ins->info, ins->codep + 4))
9017         return &err_opcode;
9018       /* The first byte after 0x62.  */
9019       if (*ins->codep & 0x8)
9020         ins->rex2 |= REX_B;
9021       if (!(*ins->codep & 0x10))
9022         ins->rex2 |= REX_R;
9023
9024       ins->rex = ~(*ins->codep >> 5) & 0x7;
9025       switch (*ins->codep & 0x7)
9026         {
9027         default:
9028           return &bad_opcode;
9029         case 0x1:
9030           vex_table_index = EVEX_0F;
9031           break;
9032         case 0x2:
9033           vex_table_index = EVEX_0F38;
9034           break;
9035         case 0x3:
9036           vex_table_index = EVEX_0F3A;
9037           break;
9038         case 0x4:
9039           vex_table_index = EVEX_MAP4;
9040           ins->evex_type = evex_from_legacy;
9041           if (ins->address_mode != mode_64bit)
9042             return &bad_opcode;
9043           ins->rex |= REX_OPCODE;
9044           break;
9045         case 0x5:
9046           vex_table_index = EVEX_MAP5;
9047           break;
9048         case 0x6:
9049           vex_table_index = EVEX_MAP6;
9050           break;
9051         case 0x7:
9052           vex_table_index = EVEX_MAP7;
9053           break;
9054         }
9055
9056       /* The second byte after 0x62.  */
9057       ins->codep++;
9058       ins->vex.w = *ins->codep & 0x80;
9059       if (ins->vex.w && ins->address_mode == mode_64bit)
9060         ins->rex |= REX_W;
9061
9062       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9063
9064       if (!(*ins->codep & 0x4))
9065         ins->rex2 |= REX_X;
9066
9067       ins->vex.u = *ins->codep & 0x4;
9068
9069       switch ((*ins->codep & 0x3))
9070         {
9071         case 0:
9072           break;
9073         case 1:
9074           ins->vex.prefix = DATA_PREFIX_OPCODE;
9075           break;
9076         case 2:
9077           ins->vex.prefix = REPE_PREFIX_OPCODE;
9078           break;
9079         case 3:
9080           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9081           break;
9082         }
9083
9084       /* The third byte after 0x62.  */
9085       ins->codep++;
9086
9087       /* Remember the static rounding bits.  */
9088       ins->vex.ll = (*ins->codep >> 5) & 3;
9089       ins->vex.b = *ins->codep & 0x10;
9090
9091       ins->vex.v = *ins->codep & 0x8;
9092       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9093       ins->vex.scc = *ins->codep & 0xf;
9094       ins->vex.zeroing = *ins->codep & 0x80;
9095       /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9096          when it's an evex_default one.  */
9097       ins->vex.nf = *ins->codep & 0x4;
9098
9099       if (ins->address_mode != mode_64bit)
9100         {
9101           /* Report bad for !evex_default and when two fixed values of evex
9102              change.  */
9103           if (ins->evex_type != evex_default || (ins->rex2 & REX_B)
9104               || ((ins->rex2 & REX_X) && (ins->modrm.mod != 3)))
9105             return &bad_opcode;
9106           /* In 16/32-bit mode silently ignore following bits.  */
9107           ins->rex &= ~REX_B;
9108           ins->rex2 &= ~REX_R;
9109         }
9110
9111       ins->need_vex = 4;
9112
9113       ins->codep++;
9114       vindex = *ins->codep++;
9115       ins->condition_code = vindex & 0xf;
9116       if (vex_table_index != EVEX_MAP7)
9117         dp = &evex_table[vex_table_index][vindex];
9118       else if (vindex == 0xf8)
9119         dp = &map7_f8_opcode;
9120       else
9121         dp = &bad_opcode;
9122       ins->end_codep = ins->codep;
9123       if (!fetch_modrm (ins))
9124         return &err_opcode;
9125
9126       /* When modrm.mod != 3, the U bit is used by APX for bit X4.
9127          When modrm.mod == 3, the U bit is used by AVX10.  The U bit and
9128          the b bit should not be zero at the same time.  */
9129       if (ins->modrm.mod == 3 && !ins->vex.u && !ins->vex.b)
9130         return &bad_opcode;
9131
9132       /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9133          which has the same encoding as vex.length == 128 and they can share
9134          the same processing with vex.length in OP_VEX.  */
9135       if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9136         {
9137           if (ins->vex.u)
9138             ins->vex.length = 512;
9139           else
9140             ins->vex.length = 256;
9141         }
9142       else
9143         {
9144           switch (ins->vex.ll)
9145             {
9146             case 0x0:
9147               ins->vex.length = 128;
9148               break;
9149             case 0x1:
9150               ins->vex.length = 256;
9151               break;
9152             case 0x2:
9153               ins->vex.length = 512;
9154               break;
9155             default:
9156               return &bad_opcode;
9157             }
9158         }
9159       break;
9160
9161     case 0:
9162       dp = &bad_opcode;
9163       break;
9164
9165     default:
9166       abort ();
9167     }
9168
9169   if (dp->name != NULL)
9170     return dp;
9171   else
9172     return get_valid_dis386 (dp, ins);
9173 }
9174
9175 static bool
9176 get_sib (instr_info *ins, int sizeflag)
9177 {
9178   /* If modrm.mod == 3, operand must be register.  */
9179   if (ins->need_modrm
9180       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9181       && ins->modrm.mod != 3
9182       && ins->modrm.rm == 4)
9183     {
9184       if (!fetch_code (ins->info, ins->codep + 2))
9185         return false;
9186       ins->sib.index = (ins->codep[1] >> 3) & 7;
9187       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9188       ins->sib.base = ins->codep[1] & 7;
9189       ins->has_sib = true;
9190     }
9191   else
9192     ins->has_sib = false;
9193
9194   return true;
9195 }
9196
9197 /* Like oappend_with_style (below) but always with text style.  */
9198
9199 static void
9200 oappend (instr_info *ins, const char *s)
9201 {
9202   oappend_with_style (ins, s, dis_style_text);
9203 }
9204
9205 /* Like oappend (above), but S is a string starting with '%'.  In
9206    Intel syntax, the '%' is elided.  */
9207
9208 static void
9209 oappend_register (instr_info *ins, const char *s)
9210 {
9211   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9212 }
9213
9214 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9215    STYLE is the default style to use in the fprintf_styled_func calls,
9216    however, FMT might include embedded style markers (see oappend_style),
9217    these embedded markers are not printed, but instead change the style
9218    used in the next fprintf_styled_func call.  */
9219
9220 static void ATTRIBUTE_PRINTF_3
9221 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9222                  const char *fmt, ...)
9223 {
9224   va_list ap;
9225   enum disassembler_style curr_style = style;
9226   const char *start, *curr;
9227   char staging_area[50];
9228
9229   va_start (ap, fmt);
9230   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9231      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9232      with the staging area.  */
9233   if (strcmp (fmt, "%s"))
9234     {
9235       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9236
9237       va_end (ap);
9238
9239       if (res < 0)
9240         return;
9241
9242       if ((size_t) res >= sizeof (staging_area))
9243         abort ();
9244
9245       start = curr = staging_area;
9246     }
9247   else
9248     {
9249       start = curr = va_arg (ap, const char *);
9250       va_end (ap);
9251     }
9252
9253   do
9254     {
9255       if (*curr == '\0'
9256           || (*curr == STYLE_MARKER_CHAR
9257               && ISXDIGIT (*(curr + 1))
9258               && *(curr + 2) == STYLE_MARKER_CHAR))
9259         {
9260           /* Output content between our START position and CURR.  */
9261           int len = curr - start;
9262           int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9263                                                 "%.*s", len, start);
9264           if (n < 0)
9265             break;
9266
9267           if (*curr == '\0')
9268             break;
9269
9270           /* Skip over the initial STYLE_MARKER_CHAR.  */
9271           ++curr;
9272
9273           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9274              is possible, that if the input is corrupted in some way, that
9275              we might set CURR_STYLE to an invalid value.  Don't worry
9276              though, we check for this situation.  */
9277           if (*curr >= '0' && *curr <= '9')
9278             curr_style = (enum disassembler_style) (*curr - '0');
9279           else if (*curr >= 'a' && *curr <= 'f')
9280             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9281           else
9282             curr_style = dis_style_text;
9283
9284           /* Check for an invalid style having been selected.  This should
9285              never happen, but it doesn't hurt to be a little paranoid.  */
9286           if (curr_style > dis_style_comment_start)
9287             curr_style = dis_style_text;
9288
9289           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9290           curr += 2;
9291
9292           /* Reset the START to after the style marker.  */
9293           start = curr;
9294         }
9295       else
9296         ++curr;
9297     }
9298   while (true);
9299 }
9300
9301 static int
9302 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9303 {
9304   const struct dis386 *dp;
9305   int i;
9306   int ret;
9307   char *op_txt[MAX_OPERANDS];
9308   int needcomma;
9309   bool intel_swap_2_3;
9310   int sizeflag, orig_sizeflag;
9311   const char *p;
9312   struct dis_private priv;
9313   int prefix_length;
9314   int op_count;
9315   instr_info ins = {
9316     .info = info,
9317     .intel_syntax = intel_syntax >= 0
9318                     ? intel_syntax
9319                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9320     .intel_mnemonic = !SYSV386_COMPAT,
9321     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9322     .start_pc = pc,
9323     .start_codep = priv.the_buffer,
9324     .codep = priv.the_buffer,
9325     .obufp = ins.obuf,
9326     .last_lock_prefix = -1,
9327     .last_repz_prefix = -1,
9328     .last_repnz_prefix = -1,
9329     .last_data_prefix = -1,
9330     .last_addr_prefix = -1,
9331     .last_rex_prefix = -1,
9332     .last_rex2_prefix = -1,
9333     .last_seg_prefix = -1,
9334     .fwait_prefix = -1,
9335   };
9336   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9337
9338   priv.orig_sizeflag = AFLAG | DFLAG;
9339   if ((info->mach & bfd_mach_i386_i386) != 0)
9340     ins.address_mode = mode_32bit;
9341   else if (info->mach == bfd_mach_i386_i8086)
9342     {
9343       ins.address_mode = mode_16bit;
9344       priv.orig_sizeflag = 0;
9345     }
9346   else
9347     ins.address_mode = mode_64bit;
9348
9349   for (p = info->disassembler_options; p != NULL;)
9350     {
9351       if (startswith (p, "amd64"))
9352         ins.isa64 = amd64;
9353       else if (startswith (p, "intel64"))
9354         ins.isa64 = intel64;
9355       else if (startswith (p, "x86-64"))
9356         {
9357           ins.address_mode = mode_64bit;
9358           priv.orig_sizeflag |= AFLAG | DFLAG;
9359         }
9360       else if (startswith (p, "i386"))
9361         {
9362           ins.address_mode = mode_32bit;
9363           priv.orig_sizeflag |= AFLAG | DFLAG;
9364         }
9365       else if (startswith (p, "i8086"))
9366         {
9367           ins.address_mode = mode_16bit;
9368           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9369         }
9370       else if (startswith (p, "intel"))
9371         {
9372           if (startswith (p + 5, "-mnemonic"))
9373             ins.intel_mnemonic = true;
9374           else
9375             ins.intel_syntax = 1;
9376         }
9377       else if (startswith (p, "att"))
9378         {
9379           ins.intel_syntax = 0;
9380           if (startswith (p + 3, "-mnemonic"))
9381             ins.intel_mnemonic = false;
9382         }
9383       else if (startswith (p, "addr"))
9384         {
9385           if (ins.address_mode == mode_64bit)
9386             {
9387               if (p[4] == '3' && p[5] == '2')
9388                 priv.orig_sizeflag &= ~AFLAG;
9389               else if (p[4] == '6' && p[5] == '4')
9390                 priv.orig_sizeflag |= AFLAG;
9391             }
9392           else
9393             {
9394               if (p[4] == '1' && p[5] == '6')
9395                 priv.orig_sizeflag &= ~AFLAG;
9396               else if (p[4] == '3' && p[5] == '2')
9397                 priv.orig_sizeflag |= AFLAG;
9398             }
9399         }
9400       else if (startswith (p, "data"))
9401         {
9402           if (p[4] == '1' && p[5] == '6')
9403             priv.orig_sizeflag &= ~DFLAG;
9404           else if (p[4] == '3' && p[5] == '2')
9405             priv.orig_sizeflag |= DFLAG;
9406         }
9407       else if (startswith (p, "suffix"))
9408         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9409
9410       p = strchr (p, ',');
9411       if (p != NULL)
9412         p++;
9413     }
9414
9415   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9416     {
9417       i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9418       return -1;
9419     }
9420
9421   if (ins.intel_syntax)
9422     {
9423       ins.open_char = '[';
9424       ins.close_char = ']';
9425       ins.separator_char = '+';
9426       ins.scale_char = '*';
9427     }
9428   else
9429     {
9430       ins.open_char = '(';
9431       ins.close_char =  ')';
9432       ins.separator_char = ',';
9433       ins.scale_char = ',';
9434     }
9435
9436   /* The output looks better if we put 7 bytes on a line, since that
9437      puts most long word instructions on a single line.  */
9438   info->bytes_per_line = 7;
9439
9440   info->private_data = &priv;
9441   priv.fetched = 0;
9442   priv.insn_start = pc;
9443
9444   for (i = 0; i < MAX_OPERANDS; ++i)
9445     {
9446       op_out[i][0] = 0;
9447       ins.op_out[i] = op_out[i];
9448     }
9449
9450   sizeflag = priv.orig_sizeflag;
9451
9452   switch (ckprefix (&ins))
9453     {
9454     case ckp_okay:
9455       break;
9456
9457     case ckp_bogus:
9458       /* Too many prefixes or unused REX prefixes.  */
9459       for (i = 0;
9460            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9461            i++)
9462         i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9463                          (i == 0 ? "" : " "),
9464                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9465                                       sizeflag));
9466       ret = i;
9467       goto out;
9468
9469     case ckp_fetch_error:
9470       goto fetch_error_out;
9471     }
9472
9473   ins.nr_prefixes = ins.codep - ins.start_codep;
9474
9475   if (!fetch_code (info, ins.codep + 1))
9476     {
9477     fetch_error_out:
9478       ret = fetch_error (&ins);
9479       goto out;
9480     }
9481
9482   ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9483
9484   if ((ins.prefixes & PREFIX_FWAIT)
9485       && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9486     {
9487       /* Handle ins.prefixes before fwait.  */
9488       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9489            i++)
9490         i386_dis_printf (info, dis_style_mnemonic, "%s ",
9491                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9492                                       sizeflag));
9493       i386_dis_printf (info, dis_style_mnemonic, "fwait");
9494       ret = i + 1;
9495       goto out;
9496     }
9497
9498   /* REX2.M in rex2 prefix represents map0 or map1.  */
9499   if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9500     {
9501       if (!ins.rex2)
9502         {
9503           ins.codep++;
9504           if (!fetch_code (info, ins.codep + 1))
9505             goto fetch_error_out;
9506         }
9507
9508       dp = &dis386_twobyte[*ins.codep];
9509       ins.need_modrm = twobyte_has_modrm[*ins.codep];
9510     }
9511   else
9512     {
9513       dp = &dis386[*ins.codep];
9514       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9515     }
9516   ins.condition_code = *ins.codep & 0xf;
9517   ins.codep++;
9518
9519   /* Save sizeflag for printing the extra ins.prefixes later before updating
9520      it for mnemonic and operand processing.  The prefix names depend
9521      only on the address mode.  */
9522   orig_sizeflag = sizeflag;
9523   if (ins.prefixes & PREFIX_ADDR)
9524     sizeflag ^= AFLAG;
9525   if ((ins.prefixes & PREFIX_DATA))
9526     sizeflag ^= DFLAG;
9527
9528   ins.end_codep = ins.codep;
9529   if (ins.need_modrm && !fetch_modrm (&ins))
9530     goto fetch_error_out;
9531
9532   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9533     {
9534       if (!get_sib (&ins, sizeflag)
9535           || !dofloat (&ins, sizeflag))
9536         goto fetch_error_out;
9537     }
9538   else
9539     {
9540       dp = get_valid_dis386 (dp, &ins);
9541       if (dp == &err_opcode)
9542         goto fetch_error_out;
9543
9544       /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9545          is interpreted as the operand size override.  */
9546       if (ins.evex_type == evex_from_legacy
9547           && ins.vex.prefix == DATA_PREFIX_OPCODE)
9548         sizeflag ^= DFLAG;
9549
9550       if(ins.evex_type == evex_default)
9551         ins.vex.nf = false;
9552       else
9553         /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9554            are cleared separately.) in mask_register_specifier and keep the low
9555            2 bits of mask_register_specifier to report errors for invalid cases
9556            .  */
9557         ins.vex.mask_register_specifier &= 0x3;
9558
9559       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9560         {
9561           if (!get_sib (&ins, sizeflag))
9562             goto fetch_error_out;
9563           for (i = 0; i < MAX_OPERANDS; ++i)
9564             {
9565               ins.obufp = ins.op_out[i];
9566               ins.op_ad = MAX_OPERANDS - 1 - i;
9567               if (dp->op[i].rtn
9568                   && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9569                 goto fetch_error_out;
9570               /* For EVEX instruction after the last operand masking
9571                  should be printed.  */
9572               if (i == 0 && ins.vex.evex)
9573                 {
9574                   /* Don't print {%k0}.  */
9575                   if (ins.vex.mask_register_specifier)
9576                     {
9577                       const char *reg_name
9578                         = att_names_mask[ins.vex.mask_register_specifier];
9579
9580                       oappend (&ins, "{");
9581                       oappend_register (&ins, reg_name);
9582                       oappend (&ins, "}");
9583
9584                       if (ins.vex.zeroing)
9585                         oappend (&ins, "{z}");
9586                     }
9587                   else if (ins.vex.zeroing)
9588                     {
9589                       oappend (&ins, "{bad}");
9590                       continue;
9591                     }
9592
9593                   /* Instructions with a mask register destination allow for
9594                      zeroing-masking only (if any masking at all), which is
9595                      _not_ expressed by EVEX.z.  */
9596                   if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9597                     ins.illegal_masking = true;
9598
9599                   /* S/G insns require a mask and don't allow
9600                      zeroing-masking.  */
9601                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9602                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9603                       && (ins.vex.mask_register_specifier == 0
9604                           || ins.vex.zeroing))
9605                     ins.illegal_masking = true;
9606
9607                   if (ins.illegal_masking)
9608                     oappend (&ins, "/(bad)");
9609                 }
9610             }
9611           /* vex.nf is cleared after being consumed.  */
9612           if (ins.vex.nf)
9613             oappend (&ins, "{bad-nf}");
9614
9615           /* Check whether rounding control was enabled for an insn not
9616              supporting it, when evex.b is not treated as evex.nd.  */
9617           if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9618               && !(ins.evex_used & EVEX_b_used))
9619             {
9620               for (i = 0; i < MAX_OPERANDS; ++i)
9621                 {
9622                   ins.obufp = ins.op_out[i];
9623                   if (*ins.obufp)
9624                     continue;
9625                   oappend (&ins, names_rounding[ins.vex.ll]);
9626                   oappend (&ins, "bad}");
9627                   break;
9628                 }
9629             }
9630         }
9631     }
9632
9633   /* Clear instruction information.  */
9634   info->insn_info_valid = 0;
9635   info->branch_delay_insns = 0;
9636   info->data_size = 0;
9637   info->insn_type = dis_noninsn;
9638   info->target = 0;
9639   info->target2 = 0;
9640
9641   /* Reset jump operation indicator.  */
9642   ins.op_is_jump = false;
9643   {
9644     int jump_detection = 0;
9645
9646     /* Extract flags.  */
9647     for (i = 0; i < MAX_OPERANDS; ++i)
9648       {
9649         if ((dp->op[i].rtn == OP_J)
9650             || (dp->op[i].rtn == OP_indirE))
9651           jump_detection |= 1;
9652         else if ((dp->op[i].rtn == BND_Fixup)
9653                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9654           jump_detection |= 2;
9655         else if ((dp->op[i].bytemode == cond_jump_mode)
9656                  || (dp->op[i].bytemode == loop_jcxz_mode))
9657           jump_detection |= 4;
9658       }
9659
9660     /* Determine if this is a jump or branch.  */
9661     if ((jump_detection & 0x3) == 0x3)
9662       {
9663         ins.op_is_jump = true;
9664         if (jump_detection & 0x4)
9665           info->insn_type = dis_condbranch;
9666         else
9667           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9668             ? dis_jsr : dis_branch;
9669       }
9670   }
9671   /* The purpose of placing the check here is to wait for the EVEX prefix for
9672      conditional CMP and TEST to be consumed and cleared, and then make a
9673      unified judgment. Because they are both in map4, we can not distinguish
9674      EVEX prefix for conditional CMP and TEST from others during the
9675      EVEX prefix stage of parsing.  */
9676   if (ins.evex_type == evex_from_legacy)
9677     {
9678       /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9679          all bits of EVEX.vvvv and EVEX.V' must be 1.  */
9680       if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
9681         {
9682           i386_dis_printf (info, dis_style_text, "(bad)");
9683           ret = ins.end_codep - priv.the_buffer;
9684           goto out;
9685         }
9686
9687       /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9688          lower 2 bits of EVEX.aaa must be 0.  */
9689       if ((ins.vex.mask_register_specifier & 0x3) != 0
9690           || ins.vex.ll != 0 || ins.vex.zeroing != 0)
9691         {
9692           i386_dis_printf (info, dis_style_text, "(bad)");
9693           ret = ins.end_codep - priv.the_buffer;
9694           goto out;
9695         }
9696     }
9697   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9698      are all 0s in inverted form.  */
9699   if (ins.need_vex && ins.vex.register_specifier != 0)
9700     {
9701       i386_dis_printf (info, dis_style_text, "(bad)");
9702       ret = ins.end_codep - priv.the_buffer;
9703       goto out;
9704     }
9705
9706   if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9707       && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9708     {
9709       i386_dis_printf (info, dis_style_text, "(bad)");
9710       ret = ins.end_codep - priv.the_buffer;
9711       goto out;
9712     }
9713
9714   switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9715     {
9716     case PREFIX_DATA:
9717       /* If only the data prefix is marked as mandatory, its absence renders
9718          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9719       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9720         {
9721           i386_dis_printf (info, dis_style_text, "(bad)");
9722           ret = ins.end_codep - priv.the_buffer;
9723           goto out;
9724         }
9725       ins.used_prefixes |= PREFIX_DATA;
9726       /* Fall through.  */
9727     case PREFIX_OPCODE:
9728       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9729          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9730          used by putop and MMX/SSE operand and may be overridden by the
9731          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9732          separately.  */
9733       if (((ins.need_vex
9734             ? ins.vex.prefix == REPE_PREFIX_OPCODE
9735               || ins.vex.prefix == REPNE_PREFIX_OPCODE
9736             : (ins.prefixes
9737                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9738            && (ins.used_prefixes
9739                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9740           || (((ins.need_vex
9741                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9742                 : ((ins.prefixes
9743                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9744                    == PREFIX_DATA))
9745                && (ins.used_prefixes & PREFIX_DATA) == 0))
9746           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9747               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9748         {
9749           i386_dis_printf (info, dis_style_text, "(bad)");
9750           ret = ins.end_codep - priv.the_buffer;
9751           goto out;
9752         }
9753       break;
9754
9755     case PREFIX_IGNORED:
9756       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9757          origins in all_prefixes.  */
9758       ins.used_prefixes &= ~PREFIX_OPCODE;
9759       if (ins.last_data_prefix >= 0)
9760         ins.all_prefixes[ins.last_data_prefix] = 0x66;
9761       if (ins.last_repz_prefix >= 0)
9762         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9763       if (ins.last_repnz_prefix >= 0)
9764         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9765       break;
9766
9767     case PREFIX_NP_OR_DATA:
9768       if (ins.vex.prefix == REPE_PREFIX_OPCODE
9769           || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9770         {
9771           i386_dis_printf (info, dis_style_text, "(bad)");
9772           ret = ins.end_codep - priv.the_buffer;
9773           goto out;
9774         }
9775       break;
9776
9777     case NO_PREFIX:
9778       if (ins.vex.prefix)
9779         {
9780           i386_dis_printf (info, dis_style_text, "(bad)");
9781           ret = ins.end_codep - priv.the_buffer;
9782           goto out;
9783         }
9784       break;
9785     }
9786
9787   /* Check if the REX prefix is used.  */
9788   if ((ins.rex ^ ins.rex_used) == 0
9789       && !ins.need_vex && ins.last_rex_prefix >= 0)
9790     ins.all_prefixes[ins.last_rex_prefix] = 0;
9791
9792   /* Check if the REX2 prefix is used.  */
9793   if (ins.last_rex2_prefix >= 0
9794       && ((ins.rex2 & REX2_SPECIAL)
9795           || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9796               && (ins.rex ^ ins.rex_used) == 0
9797               && (ins.rex2 & 7))))
9798     ins.all_prefixes[ins.last_rex2_prefix] = 0;
9799
9800   /* Check if the SEG prefix is used.  */
9801   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9802                        | PREFIX_FS | PREFIX_GS)) != 0
9803       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9804     ins.all_prefixes[ins.last_seg_prefix] = 0;
9805
9806   /* Check if the ADDR prefix is used.  */
9807   if ((ins.prefixes & PREFIX_ADDR) != 0
9808       && (ins.used_prefixes & PREFIX_ADDR) != 0)
9809     ins.all_prefixes[ins.last_addr_prefix] = 0;
9810
9811   /* Check if the DATA prefix is used.  */
9812   if ((ins.prefixes & PREFIX_DATA) != 0
9813       && (ins.used_prefixes & PREFIX_DATA) != 0
9814       && !ins.need_vex)
9815     ins.all_prefixes[ins.last_data_prefix] = 0;
9816
9817   /* Print the extra ins.prefixes.  */
9818   prefix_length = 0;
9819   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9820     if (ins.all_prefixes[i])
9821       {
9822         const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9823                                         orig_sizeflag);
9824
9825         if (name == NULL)
9826           abort ();
9827         prefix_length += strlen (name) + 1;
9828         if (ins.all_prefixes[i] == REX2_OPCODE)
9829           i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9830                            (unsigned int) ins.rex2_payload);
9831         else
9832           i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9833       }
9834
9835   /* Check maximum code length.  */
9836   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9837     {
9838       i386_dis_printf (info, dis_style_text, "(bad)");
9839       ret = MAX_CODE_LENGTH;
9840       goto out;
9841     }
9842
9843   /* Calculate the number of operands this instruction has.  */
9844   op_count = 0;
9845   for (i = 0; i < MAX_OPERANDS; ++i)
9846     if (*ins.op_out[i] != '\0')
9847       ++op_count;
9848
9849   /* Calculate the number of spaces to print after the mnemonic.  */
9850   ins.obufp = ins.mnemonicendp;
9851   if (op_count > 0)
9852     {
9853       i = strlen (ins.obuf) + prefix_length;
9854       if (i < 7)
9855         i = 7 - i;
9856       else
9857         i = 1;
9858     }
9859   else
9860     i = 0;
9861
9862   /* Print the instruction mnemonic along with any trailing whitespace.  */
9863   i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9864
9865   /* The enter and bound instructions are printed with operands in the same
9866      order as the intel book; everything else is printed in reverse order.  */
9867   intel_swap_2_3 = false;
9868   if (ins.intel_syntax || ins.two_source_ops)
9869     {
9870       for (i = 0; i < MAX_OPERANDS; ++i)
9871         op_txt[i] = ins.op_out[i];
9872
9873       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9874           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9875         {
9876           op_txt[2] = ins.op_out[3];
9877           op_txt[3] = ins.op_out[2];
9878           intel_swap_2_3 = true;
9879         }
9880
9881       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9882         {
9883           bool riprel;
9884
9885           ins.op_ad = ins.op_index[i];
9886           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9887           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9888           riprel = ins.op_riprel[i];
9889           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9890           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9891         }
9892     }
9893   else
9894     {
9895       for (i = 0; i < MAX_OPERANDS; ++i)
9896         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9897     }
9898
9899   needcomma = 0;
9900   for (i = 0; i < MAX_OPERANDS; ++i)
9901     if (*op_txt[i])
9902       {
9903         /* In Intel syntax embedded rounding / SAE are not separate operands.
9904            Instead they're attached to the prior register operand.  Simply
9905            suppress emission of the comma to achieve that effect.  */
9906         switch (i & -(ins.intel_syntax && dp))
9907           {
9908           case 2:
9909             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9910               needcomma = 0;
9911             break;
9912           case 3:
9913             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9914               needcomma = 0;
9915             break;
9916           }
9917         if (needcomma)
9918           i386_dis_printf (info, dis_style_text, ",");
9919         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9920           {
9921             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9922
9923             if (ins.op_is_jump)
9924               {
9925                 info->insn_info_valid = 1;
9926                 info->branch_delay_insns = 0;
9927                 info->data_size = 0;
9928                 info->target = target;
9929                 info->target2 = 0;
9930               }
9931             (*info->print_address_func) (target, info);
9932           }
9933         else
9934           i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9935         needcomma = 1;
9936       }
9937
9938   for (i = 0; i < MAX_OPERANDS; i++)
9939     if (ins.op_index[i] != -1 && ins.op_riprel[i])
9940       {
9941         i386_dis_printf (info, dis_style_comment_start, "        # ");
9942         (*info->print_address_func)
9943           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9944                      + ins.op_address[ins.op_index[i]]),
9945           info);
9946         break;
9947       }
9948   ret = ins.codep - priv.the_buffer;
9949  out:
9950   info->private_data = NULL;
9951   return ret;
9952 }
9953
9954 /* Here for backwards compatibility.  When gdb stops using
9955    print_insn_i386_att and print_insn_i386_intel these functions can
9956    disappear, and print_insn_i386 be merged into print_insn.  */
9957 int
9958 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9959 {
9960   return print_insn (pc, info, 0);
9961 }
9962
9963 int
9964 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9965 {
9966   return print_insn (pc, info, 1);
9967 }
9968
9969 int
9970 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9971 {
9972   return print_insn (pc, info, -1);
9973 }
9974
9975 static const char *float_mem[] = {
9976   /* d8 */
9977   "fadd{s|}",
9978   "fmul{s|}",
9979   "fcom{s|}",
9980   "fcomp{s|}",
9981   "fsub{s|}",
9982   "fsubr{s|}",
9983   "fdiv{s|}",
9984   "fdivr{s|}",
9985   /* d9 */
9986   "fld{s|}",
9987   "(bad)",
9988   "fst{s|}",
9989   "fstp{s|}",
9990   "fldenv{C|C}",
9991   "fldcw",
9992   "fNstenv{C|C}",
9993   "fNstcw",
9994   /* da */
9995   "fiadd{l|}",
9996   "fimul{l|}",
9997   "ficom{l|}",
9998   "ficomp{l|}",
9999   "fisub{l|}",
10000   "fisubr{l|}",
10001   "fidiv{l|}",
10002   "fidivr{l|}",
10003   /* db */
10004   "fild{l|}",
10005   "fisttp{l|}",
10006   "fist{l|}",
10007   "fistp{l|}",
10008   "(bad)",
10009   "fld{t|}",
10010   "(bad)",
10011   "fstp{t|}",
10012   /* dc */
10013   "fadd{l|}",
10014   "fmul{l|}",
10015   "fcom{l|}",
10016   "fcomp{l|}",
10017   "fsub{l|}",
10018   "fsubr{l|}",
10019   "fdiv{l|}",
10020   "fdivr{l|}",
10021   /* dd */
10022   "fld{l|}",
10023   "fisttp{ll|}",
10024   "fst{l||}",
10025   "fstp{l|}",
10026   "frstor{C|C}",
10027   "(bad)",
10028   "fNsave{C|C}",
10029   "fNstsw",
10030   /* de */
10031   "fiadd{s|}",
10032   "fimul{s|}",
10033   "ficom{s|}",
10034   "ficomp{s|}",
10035   "fisub{s|}",
10036   "fisubr{s|}",
10037   "fidiv{s|}",
10038   "fidivr{s|}",
10039   /* df */
10040   "fild{s|}",
10041   "fisttp{s|}",
10042   "fist{s|}",
10043   "fistp{s|}",
10044   "fbld",
10045   "fild{ll|}",
10046   "fbstp",
10047   "fistp{ll|}",
10048 };
10049
10050 static const unsigned char float_mem_mode[] = {
10051   /* d8 */
10052   d_mode,
10053   d_mode,
10054   d_mode,
10055   d_mode,
10056   d_mode,
10057   d_mode,
10058   d_mode,
10059   d_mode,
10060   /* d9 */
10061   d_mode,
10062   0,
10063   d_mode,
10064   d_mode,
10065   0,
10066   w_mode,
10067   0,
10068   w_mode,
10069   /* da */
10070   d_mode,
10071   d_mode,
10072   d_mode,
10073   d_mode,
10074   d_mode,
10075   d_mode,
10076   d_mode,
10077   d_mode,
10078   /* db */
10079   d_mode,
10080   d_mode,
10081   d_mode,
10082   d_mode,
10083   0,
10084   t_mode,
10085   0,
10086   t_mode,
10087   /* dc */
10088   q_mode,
10089   q_mode,
10090   q_mode,
10091   q_mode,
10092   q_mode,
10093   q_mode,
10094   q_mode,
10095   q_mode,
10096   /* dd */
10097   q_mode,
10098   q_mode,
10099   q_mode,
10100   q_mode,
10101   0,
10102   0,
10103   0,
10104   w_mode,
10105   /* de */
10106   w_mode,
10107   w_mode,
10108   w_mode,
10109   w_mode,
10110   w_mode,
10111   w_mode,
10112   w_mode,
10113   w_mode,
10114   /* df */
10115   w_mode,
10116   w_mode,
10117   w_mode,
10118   w_mode,
10119   t_mode,
10120   q_mode,
10121   t_mode,
10122   q_mode
10123 };
10124
10125 #define ST { OP_ST, 0 }
10126 #define STi { OP_STi, 0 }
10127
10128 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10129 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10130 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10131 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10132 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10133 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10134 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10135 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10136 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10137
10138 static const struct dis386 float_reg[][8] = {
10139   /* d8 */
10140   {
10141     { "fadd",   { ST, STi }, 0 },
10142     { "fmul",   { ST, STi }, 0 },
10143     { "fcom",   { STi }, 0 },
10144     { "fcomp",  { STi }, 0 },
10145     { "fsub",   { ST, STi }, 0 },
10146     { "fsubr",  { ST, STi }, 0 },
10147     { "fdiv",   { ST, STi }, 0 },
10148     { "fdivr",  { ST, STi }, 0 },
10149   },
10150   /* d9 */
10151   {
10152     { "fld",    { STi }, 0 },
10153     { "fxch",   { STi }, 0 },
10154     { FGRPd9_2 },
10155     { Bad_Opcode },
10156     { FGRPd9_4 },
10157     { FGRPd9_5 },
10158     { FGRPd9_6 },
10159     { FGRPd9_7 },
10160   },
10161   /* da */
10162   {
10163     { "fcmovb", { ST, STi }, 0 },
10164     { "fcmove", { ST, STi }, 0 },
10165     { "fcmovbe",{ ST, STi }, 0 },
10166     { "fcmovu", { ST, STi }, 0 },
10167     { Bad_Opcode },
10168     { FGRPda_5 },
10169     { Bad_Opcode },
10170     { Bad_Opcode },
10171   },
10172   /* db */
10173   {
10174     { "fcmovnb",{ ST, STi }, 0 },
10175     { "fcmovne",{ ST, STi }, 0 },
10176     { "fcmovnbe",{ ST, STi }, 0 },
10177     { "fcmovnu",{ ST, STi }, 0 },
10178     { FGRPdb_4 },
10179     { "fucomi", { ST, STi }, 0 },
10180     { "fcomi",  { ST, STi }, 0 },
10181     { Bad_Opcode },
10182   },
10183   /* dc */
10184   {
10185     { "fadd",   { STi, ST }, 0 },
10186     { "fmul",   { STi, ST }, 0 },
10187     { Bad_Opcode },
10188     { Bad_Opcode },
10189     { "fsub{!M|r}",     { STi, ST }, 0 },
10190     { "fsub{M|}",       { STi, ST }, 0 },
10191     { "fdiv{!M|r}",     { STi, ST }, 0 },
10192     { "fdiv{M|}",       { STi, ST }, 0 },
10193   },
10194   /* dd */
10195   {
10196     { "ffree",  { STi }, 0 },
10197     { Bad_Opcode },
10198     { "fst",    { STi }, 0 },
10199     { "fstp",   { STi }, 0 },
10200     { "fucom",  { STi }, 0 },
10201     { "fucomp", { STi }, 0 },
10202     { Bad_Opcode },
10203     { Bad_Opcode },
10204   },
10205   /* de */
10206   {
10207     { "faddp",  { STi, ST }, 0 },
10208     { "fmulp",  { STi, ST }, 0 },
10209     { Bad_Opcode },
10210     { FGRPde_3 },
10211     { "fsub{!M|r}p",    { STi, ST }, 0 },
10212     { "fsub{M|}p",      { STi, ST }, 0 },
10213     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10214     { "fdiv{M|}p",      { STi, ST }, 0 },
10215   },
10216   /* df */
10217   {
10218     { "ffreep", { STi }, 0 },
10219     { Bad_Opcode },
10220     { Bad_Opcode },
10221     { Bad_Opcode },
10222     { FGRPdf_4 },
10223     { "fucomip", { ST, STi }, 0 },
10224     { "fcomip", { ST, STi }, 0 },
10225     { Bad_Opcode },
10226   },
10227 };
10228
10229 static const char *const fgrps[][8] = {
10230   /* Bad opcode 0 */
10231   {
10232     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10233   },
10234
10235   /* d9_2  1 */
10236   {
10237     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10238   },
10239
10240   /* d9_4  2 */
10241   {
10242     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10243   },
10244
10245   /* d9_5  3 */
10246   {
10247     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10248   },
10249
10250   /* d9_6  4 */
10251   {
10252     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10253   },
10254
10255   /* d9_7  5 */
10256   {
10257     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10258   },
10259
10260   /* da_5  6 */
10261   {
10262     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10263   },
10264
10265   /* db_4  7 */
10266   {
10267     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10268     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10269   },
10270
10271   /* de_3  8 */
10272   {
10273     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10274   },
10275
10276   /* df_4  9 */
10277   {
10278     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10279   },
10280 };
10281
10282 static const char *const oszc_flags[16] = {
10283   " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}",
10284   " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}",
10285   " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}",
10286   " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}"
10287 };
10288
10289 static const char *const scc_suffix[16] = {
10290   "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f",
10291   "l", "ge", "le", "g"
10292 };
10293
10294 static void
10295 swap_operand (instr_info *ins)
10296 {
10297   char *p = ins->mnemonicendp;
10298
10299   if (p[-1] == '}')
10300     {
10301       while (*--p != '{')
10302         {
10303           if (p <= ins->obuf + 2)
10304             abort ();
10305         }
10306       if (p[-1] == ' ')
10307         --p;
10308     }
10309   memmove (p + 2, p, ins->mnemonicendp - p + 1);
10310   p[0] = '.';
10311   p[1] = 's';
10312   ins->mnemonicendp += 2;
10313 }
10314
10315 static bool
10316 dofloat (instr_info *ins, int sizeflag)
10317 {
10318   const struct dis386 *dp;
10319   unsigned char floatop = ins->codep[-1];
10320
10321   if (ins->modrm.mod != 3)
10322     {
10323       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10324
10325       putop (ins, float_mem[fp_indx], sizeflag);
10326       ins->obufp = ins->op_out[0];
10327       ins->op_ad = 2;
10328       return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10329     }
10330   /* Skip mod/rm byte.  */
10331   MODRM_CHECK;
10332   ins->codep++;
10333
10334   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10335   if (dp->name == NULL)
10336     {
10337       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10338
10339       /* Instruction fnstsw is only one with strange arg.  */
10340       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10341         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10342     }
10343   else
10344     {
10345       putop (ins, dp->name, sizeflag);
10346
10347       ins->obufp = ins->op_out[0];
10348       ins->op_ad = 2;
10349       if (dp->op[0].rtn
10350           && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10351         return false;
10352
10353       ins->obufp = ins->op_out[1];
10354       ins->op_ad = 1;
10355       if (dp->op[1].rtn
10356           && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10357         return false;
10358     }
10359   return true;
10360 }
10361
10362 static bool
10363 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10364        int sizeflag ATTRIBUTE_UNUSED)
10365 {
10366   oappend_register (ins, "%st");
10367   return true;
10368 }
10369
10370 static bool
10371 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10372         int sizeflag ATTRIBUTE_UNUSED)
10373 {
10374   char scratch[8];
10375   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10376
10377   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10378     abort ();
10379   oappend_register (ins, scratch);
10380   return true;
10381 }
10382
10383 /* Capital letters in template are macros.  */
10384 static int
10385 putop (instr_info *ins, const char *in_template, int sizeflag)
10386 {
10387   const char *p;
10388   int alt = 0;
10389   int cond = 1;
10390   unsigned int l = 0, len = 0;
10391   char last[4];
10392   bool evex_printed = false;
10393
10394   /* We don't want to add any prefix or suffix to (bad), so return early.  */
10395   if (!strncmp (in_template, "(bad)", 5))
10396     {
10397       oappend (ins, "(bad)");
10398       *ins->obufp = 0;
10399       ins->mnemonicendp = ins->obufp;
10400       return 0;
10401     }
10402
10403   for (p = in_template; *p; p++)
10404     {
10405       if (len > l)
10406         {
10407           if (l >= sizeof (last) || !ISUPPER (*p))
10408             abort ();
10409           last[l++] = *p;
10410           continue;
10411         }
10412       switch (*p)
10413         {
10414         default:
10415           if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10416               && !(ins->rex2 & 7) && !evex_printed)
10417             {
10418               oappend (ins, "{evex} ");
10419               evex_printed = true;
10420             }
10421           *ins->obufp++ = *p;
10422           break;
10423         case '%':
10424           len++;
10425           break;
10426         case '!':
10427           cond = 0;
10428           break;
10429         case '{':
10430           if (ins->intel_syntax)
10431             {
10432               while (*++p != '|')
10433                 if (*p == '}' || *p == '\0')
10434                   abort ();
10435               alt = 1;
10436             }
10437           break;
10438         case '|':
10439           while (*++p != '}')
10440             {
10441               if (*p == '\0')
10442                 abort ();
10443             }
10444           break;
10445         case '}':
10446           alt = 0;
10447           break;
10448         case 'A':
10449           if (ins->intel_syntax)
10450             break;
10451           if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10452               || (sizeflag & SUFFIX_ALWAYS))
10453             *ins->obufp++ = 'b';
10454           break;
10455         case 'B':
10456           if (l == 0)
10457             {
10458             case_B:
10459               if (ins->intel_syntax)
10460                 break;
10461               if (sizeflag & SUFFIX_ALWAYS)
10462                 *ins->obufp++ = 'b';
10463             }
10464           else if (l == 1 && last[0] == 'L')
10465             {
10466               if (ins->address_mode == mode_64bit
10467                   && !(ins->prefixes & PREFIX_ADDR))
10468                 {
10469                   *ins->obufp++ = 'a';
10470                   *ins->obufp++ = 'b';
10471                   *ins->obufp++ = 's';
10472                 }
10473
10474               goto case_B;
10475             }
10476           else
10477             abort ();
10478           break;
10479         case 'C':
10480           if (l == 1 && last[0] == 'C')
10481             {
10482               /* Condition code (taken from the map-0 Jcc entries).  */
10483               for (const char *q = dis386[0x70 | ins->condition_code].name + 1;
10484                    ISLOWER(*q); ++q)
10485                 *ins->obufp++ = *q;
10486               break;
10487             }
10488           else if (l == 1 && last[0] == 'S')
10489             {
10490               /* Add scc suffix.  */
10491               oappend (ins, scc_suffix[ins->vex.scc]);
10492
10493               /* For SCC insns, the ND bit is required to be set to 0.  */
10494               if (ins->vex.nd)
10495                 oappend (ins, "(bad)");
10496
10497               /* These bits have been consumed and should be cleared or restored
10498                  to default values.  */
10499               ins->vex.v = 1;
10500               ins->vex.nf = false;
10501               ins->vex.mask_register_specifier = 0;
10502               break;
10503             }
10504
10505           if (l)
10506             abort ();
10507           if (ins->intel_syntax && !alt)
10508             break;
10509           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10510             {
10511               if (sizeflag & DFLAG)
10512                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10513               else
10514                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10515               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10516             }
10517           break;
10518         case 'D':
10519           if (l == 1)
10520             {
10521               switch (last[0])
10522               {
10523               case 'X':
10524                 if (!ins->vex.evex || ins->vex.w)
10525                   *ins->obufp++ = 'd';
10526                 else
10527                   oappend (ins, "{bad}");
10528                 break;
10529               default:
10530                 abort ();
10531               }
10532               break;
10533             }
10534           if (l)
10535             abort ();
10536           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10537             break;
10538           USED_REX (REX_W);
10539           if (ins->modrm.mod == 3)
10540             {
10541               if (ins->rex & REX_W)
10542                 *ins->obufp++ = 'q';
10543               else
10544                 {
10545                   if (sizeflag & DFLAG)
10546                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10547                   else
10548                     *ins->obufp++ = 'w';
10549                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10550                 }
10551             }
10552           else
10553             *ins->obufp++ = 'w';
10554           break;
10555         case 'E':
10556           if (l == 1)
10557             {
10558               switch (last[0])
10559                 {
10560                 case 'X':
10561                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10562                       || (ins->rex2 & 7)
10563                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10564                       || !ins->vex.v || ins->vex.mask_register_specifier)
10565                     break;
10566                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10567                      merely distinguished by EVEX.W.  Look for a use of the
10568                      respective macro.  */
10569                   if (ins->vex.w)
10570                     {
10571                       const char *pct = strchr (p + 1, '%');
10572
10573                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10574                         break;
10575                     }
10576                   *ins->obufp++ = '{';
10577                   *ins->obufp++ = 'e';
10578                   *ins->obufp++ = 'v';
10579                   *ins->obufp++ = 'e';
10580                   *ins->obufp++ = 'x';
10581                   *ins->obufp++ = '}';
10582                   *ins->obufp++ = ' ';
10583                   break;
10584                 case 'N':
10585                   /* Skip printing {evex} for some special instructions in MAP4.  */
10586                   evex_printed = true;
10587                   break;
10588                 default:
10589                   abort ();
10590                 }
10591                 break;
10592             }
10593           /* For jcxz/jecxz */
10594           if (ins->address_mode == mode_64bit)
10595             {
10596               if (sizeflag & AFLAG)
10597                 *ins->obufp++ = 'r';
10598               else
10599                 *ins->obufp++ = 'e';
10600             }
10601           else
10602             if (sizeflag & AFLAG)
10603               *ins->obufp++ = 'e';
10604           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10605           break;
10606         case 'F':
10607           if (l == 0)
10608             {
10609               if (ins->intel_syntax)
10610                 break;
10611               if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10612                 {
10613                   if (sizeflag & AFLAG)
10614                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10615                   else
10616                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10617                   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10618                 }
10619             }
10620           else if (l == 1 && last[0] == 'C')
10621             {
10622               if (ins->vex.nd && !ins->vex.nf)
10623                 break;
10624               *ins->obufp++ = 'c';
10625               *ins->obufp++ = 'f';
10626               /* Skip printing {evex} */
10627               evex_printed = true;
10628             }
10629           else if (l == 1 && last[0] == 'N')
10630             {
10631               if (ins->vex.nf)
10632                 {
10633                   oappend (ins, "{nf} ");
10634                   /* This bit needs to be cleared after it is consumed.  */
10635                   ins->vex.nf = false;
10636                   evex_printed = true;
10637                 }
10638               else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
10639                        && ins->vex.v)
10640                 {
10641                   oappend (ins, "{evex} ");
10642                   evex_printed = true;
10643                 }
10644             }
10645           else if (l == 1 && last[0] == 'D')
10646             {
10647               /* Get oszc flags value from register_specifier.  */
10648               int oszc_value = ~ins->vex.register_specifier & 0xf;
10649
10650               /* Add {dfv=of, sf, zf, cf} flags.  */
10651               oappend (ins, oszc_flags[oszc_value]);
10652
10653               /* These bits have been consumed and should be cleared.  */
10654               ins->vex.register_specifier = 0;
10655             }
10656           else
10657             abort ();
10658           break;
10659         case 'G':
10660           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10661                                     && !(sizeflag & SUFFIX_ALWAYS)))
10662             break;
10663           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10664             *ins->obufp++ = 'l';
10665           else
10666             *ins->obufp++ = 'w';
10667           if (!(ins->rex & REX_W))
10668             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10669           break;
10670         case 'H':
10671           if (l == 0)
10672             {
10673               if (ins->intel_syntax)
10674                 break;
10675               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10676                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10677                 {
10678                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10679                   *ins->obufp++ = ',';
10680                   *ins->obufp++ = 'p';
10681
10682                   /* Set active_seg_prefix even if not set in 64-bit mode
10683                      because here it is a valid branch hint. */
10684                   if (ins->prefixes & PREFIX_DS)
10685                     {
10686                       ins->active_seg_prefix = PREFIX_DS;
10687                       *ins->obufp++ = 't';
10688                     }
10689                   else
10690                     {
10691                       ins->active_seg_prefix = PREFIX_CS;
10692                       *ins->obufp++ = 'n';
10693                     }
10694                 }
10695             }
10696           else if (l == 1 && last[0] == 'X')
10697             {
10698               if (!ins->vex.w)
10699                 *ins->obufp++ = 'h';
10700               else
10701                 oappend (ins, "{bad}");
10702             }
10703           else
10704             abort ();
10705           break;
10706         case 'K':
10707           USED_REX (REX_W);
10708           if (ins->rex & REX_W)
10709             *ins->obufp++ = 'q';
10710           else
10711             *ins->obufp++ = 'd';
10712           break;
10713         case 'L':
10714           if (ins->intel_syntax)
10715             break;
10716           if (sizeflag & SUFFIX_ALWAYS)
10717             {
10718               if (ins->rex & REX_W)
10719                 *ins->obufp++ = 'q';
10720               else
10721                 *ins->obufp++ = 'l';
10722             }
10723           break;
10724         case 'M':
10725           if (ins->intel_mnemonic != cond)
10726             *ins->obufp++ = 'r';
10727           break;
10728         case 'N':
10729           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10730             *ins->obufp++ = 'n';
10731           else
10732             ins->used_prefixes |= PREFIX_FWAIT;
10733           break;
10734         case 'O':
10735           USED_REX (REX_W);
10736           if (ins->rex & REX_W)
10737             *ins->obufp++ = 'o';
10738           else if (ins->intel_syntax && (sizeflag & DFLAG))
10739             *ins->obufp++ = 'q';
10740           else
10741             *ins->obufp++ = 'd';
10742           if (!(ins->rex & REX_W))
10743             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10744           break;
10745         case '@':
10746           if (ins->address_mode == mode_64bit
10747               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10748                   || !(ins->prefixes & PREFIX_DATA)))
10749             {
10750               if (sizeflag & SUFFIX_ALWAYS)
10751                 *ins->obufp++ = 'q';
10752               break;
10753             }
10754           /* Fall through.  */
10755         case 'P':
10756           if (l == 0)
10757             {
10758               if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10759                 {
10760                   /* For pushp and popp, p is printed and do not print {rex2}
10761                      for them.  */
10762                   *ins->obufp++ = 'p';
10763                   ins->rex2 |= REX2_SPECIAL;
10764                   break;
10765                 }
10766
10767               /* For "!P" print nothing else in Intel syntax.  */
10768               if (!cond && ins->intel_syntax)
10769                 break;
10770
10771               if ((ins->modrm.mod == 3 || !cond)
10772                   && !(sizeflag & SUFFIX_ALWAYS))
10773                 break;
10774           /* Fall through.  */
10775         case 'T':
10776               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10777                   || ((sizeflag & SUFFIX_ALWAYS)
10778                       && ins->address_mode != mode_64bit))
10779                 {
10780                   *ins->obufp++ = (sizeflag & DFLAG)
10781                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10782                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10783                 }
10784               else if (sizeflag & SUFFIX_ALWAYS)
10785                 *ins->obufp++ = 'q';
10786             }
10787           else if (l == 1 && last[0] == 'L')
10788             {
10789               if ((ins->prefixes & PREFIX_DATA)
10790                   || (ins->rex & REX_W)
10791                   || (sizeflag & SUFFIX_ALWAYS))
10792                 {
10793                   USED_REX (REX_W);
10794                   if (ins->rex & REX_W)
10795                     *ins->obufp++ = 'q';
10796                   else
10797                     {
10798                       if (sizeflag & DFLAG)
10799                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10800                       else
10801                         *ins->obufp++ = 'w';
10802                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10803                     }
10804                 }
10805             }
10806           else
10807             abort ();
10808           break;
10809         case 'Q':
10810           if (l == 0)
10811             {
10812               if (ins->intel_syntax && !alt)
10813                 break;
10814               USED_REX (REX_W);
10815               if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10816                   || (sizeflag & SUFFIX_ALWAYS))
10817                 {
10818                   if (ins->rex & REX_W)
10819                     *ins->obufp++ = 'q';
10820                   else
10821                     {
10822                       if (sizeflag & DFLAG)
10823                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10824                       else
10825                         *ins->obufp++ = 'w';
10826                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10827                     }
10828                 }
10829             }
10830           else if (l == 1 && last[0] == 'D')
10831             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10832           else if (l == 1 && last[0] == 'L')
10833             {
10834               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10835                        : ins->address_mode != mode_64bit)
10836                 break;
10837               if ((ins->rex & REX_W))
10838                 {
10839                   USED_REX (REX_W);
10840                   *ins->obufp++ = 'q';
10841                 }
10842               else if ((ins->address_mode == mode_64bit && cond)
10843                       || (sizeflag & SUFFIX_ALWAYS))
10844                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10845             }
10846           else
10847             abort ();
10848           break;
10849         case 'R':
10850           USED_REX (REX_W);
10851           if (ins->rex & REX_W)
10852             *ins->obufp++ = 'q';
10853           else if (sizeflag & DFLAG)
10854             {
10855               if (ins->intel_syntax)
10856                   *ins->obufp++ = 'd';
10857               else
10858                   *ins->obufp++ = 'l';
10859             }
10860           else
10861             *ins->obufp++ = 'w';
10862           if (ins->intel_syntax && !p[1]
10863               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10864             *ins->obufp++ = 'e';
10865           if (!(ins->rex & REX_W))
10866             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10867           break;
10868         case 'S':
10869           if (l == 0)
10870             {
10871             case_S:
10872               if (ins->intel_syntax)
10873                 break;
10874               if (sizeflag & SUFFIX_ALWAYS)
10875                 {
10876                   if (ins->rex & REX_W)
10877                     *ins->obufp++ = 'q';
10878                   else
10879                     {
10880                       if (sizeflag & DFLAG)
10881                         *ins->obufp++ = 'l';
10882                       else
10883                         *ins->obufp++ = 'w';
10884                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10885                     }
10886                 }
10887               break;
10888             }
10889           if (l != 1)
10890             abort ();
10891           switch (last[0])
10892             {
10893             case 'L':
10894               if (ins->address_mode == mode_64bit
10895                   && !(ins->prefixes & PREFIX_ADDR))
10896                 {
10897                   *ins->obufp++ = 'a';
10898                   *ins->obufp++ = 'b';
10899                   *ins->obufp++ = 's';
10900                 }
10901
10902               goto case_S;
10903             case 'X':
10904               if (!ins->vex.evex || !ins->vex.w)
10905                 *ins->obufp++ = 's';
10906               else
10907                 oappend (ins, "{bad}");
10908               break;
10909             default:
10910               abort ();
10911             }
10912           break;
10913         case 'U':
10914           if (l == 1 && (last[0] == 'Z'))
10915             {
10916               /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is
10917                  used to control whether its destination register has its upper
10918                  bits zeroed.  */
10919               if (ins->vex.nd)
10920                 oappend (ins, "zu");
10921             }
10922           else
10923             abort ();
10924           break;
10925         case 'V':
10926           if (l == 0)
10927             {
10928               if (ins->need_vex)
10929                 *ins->obufp++ = 'v';
10930             }
10931           else if (l == 1)
10932             {
10933               switch (last[0])
10934                 {
10935                 case 'X':
10936                   if (ins->vex.evex)
10937                     break;
10938                   *ins->obufp++ = '{';
10939                   *ins->obufp++ = 'v';
10940                   *ins->obufp++ = 'e';
10941                   *ins->obufp++ = 'x';
10942                   *ins->obufp++ = '}';
10943                   *ins->obufp++ = ' ';
10944                   break;
10945                 case 'L':
10946                   if (ins->rex & REX_W)
10947                     {
10948                       *ins->obufp++ = 'a';
10949                       *ins->obufp++ = 'b';
10950                       *ins->obufp++ = 's';
10951                     }
10952                   goto case_S;
10953                 default:
10954                   abort ();
10955                 }
10956             }
10957           else
10958             abort ();
10959           break;
10960         case 'W':
10961           if (l == 0)
10962             {
10963               /* operand size flag for cwtl, cbtw */
10964               USED_REX (REX_W);
10965               if (ins->rex & REX_W)
10966                 {
10967                   if (ins->intel_syntax)
10968                     *ins->obufp++ = 'd';
10969                   else
10970                     *ins->obufp++ = 'l';
10971                 }
10972               else if (sizeflag & DFLAG)
10973                 *ins->obufp++ = 'w';
10974               else
10975                 *ins->obufp++ = 'b';
10976               if (!(ins->rex & REX_W))
10977                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10978             }
10979           else if (l == 1)
10980             {
10981               if (!ins->need_vex)
10982                 abort ();
10983               if (last[0] == 'X')
10984                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10985               else if (last[0] == 'B')
10986                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10987               else
10988                 abort ();
10989             }
10990           else
10991             abort ();
10992           break;
10993         case 'X':
10994           if (l != 0)
10995             abort ();
10996           if (ins->need_vex
10997               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10998               : ins->prefixes & PREFIX_DATA)
10999             {
11000               *ins->obufp++ = 'd';
11001               ins->used_prefixes |= PREFIX_DATA;
11002             }
11003           else
11004             *ins->obufp++ = 's';
11005           break;
11006         case 'Y':
11007           if (l == 0)
11008             {
11009               if (ins->vex.mask_register_specifier)
11010                 ins->illegal_masking = true;
11011             }
11012           else if (l == 1 && last[0] == 'X')
11013             {
11014               if (!ins->need_vex)
11015                 break;
11016               if (ins->intel_syntax
11017                   || ((ins->modrm.mod == 3 || ins->vex.b)
11018                       && !(sizeflag & SUFFIX_ALWAYS)))
11019                 break;
11020               switch (ins->vex.length)
11021                 {
11022                 case 128:
11023                   *ins->obufp++ = 'x';
11024                   break;
11025                 case 256:
11026                   *ins->obufp++ = 'y';
11027                   break;
11028                 case 512:
11029                   if (!ins->vex.evex)
11030                 default:
11031                     abort ();
11032                 }
11033             }
11034           else
11035             abort ();
11036           break;
11037         case 'Z':
11038           if (l == 0)
11039             {
11040               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11041               ins->modrm.mod = 3;
11042               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11043                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11044             }
11045           else if (l == 1 && last[0] == 'X')
11046             {
11047               if (!ins->vex.evex)
11048                 abort ();
11049               if (ins->intel_syntax
11050                   || ((ins->modrm.mod == 3 || ins->vex.b)
11051                       && !(sizeflag & SUFFIX_ALWAYS)))
11052                 break;
11053               switch (ins->vex.length)
11054                 {
11055                 case 128:
11056                   *ins->obufp++ = 'x';
11057                   break;
11058                 case 256:
11059                   *ins->obufp++ = 'y';
11060                   break;
11061                 case 512:
11062                   *ins->obufp++ = 'z';
11063                   break;
11064                 default:
11065                   abort ();
11066                 }
11067             }
11068           else
11069             abort ();
11070           break;
11071         case '^':
11072           if (ins->intel_syntax)
11073             break;
11074           if (ins->isa64 == intel64 && (ins->rex & REX_W))
11075             {
11076               USED_REX (REX_W);
11077               *ins->obufp++ = 'q';
11078               break;
11079             }
11080           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11081             {
11082               if (sizeflag & DFLAG)
11083                 *ins->obufp++ = 'l';
11084               else
11085                 *ins->obufp++ = 'w';
11086               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11087             }
11088           break;
11089         }
11090
11091       if (len == l)
11092         len = l = 0;
11093     }
11094   *ins->obufp = 0;
11095   ins->mnemonicendp = ins->obufp;
11096   return 0;
11097 }
11098
11099 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11100    the buffer pointed to by INS->obufp has space.  A style marker is made
11101    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11102    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11103    that the number of styles is not greater than 16.  */
11104
11105 static void
11106 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11107 {
11108   unsigned num = (unsigned) style;
11109
11110   /* We currently assume that STYLE can be encoded as a single hex
11111      character.  If more styles are added then this might start to fail,
11112      and we'll need to expand this code.  */
11113   if (num > 0xf)
11114     abort ();
11115
11116   *ins->obufp++ = STYLE_MARKER_CHAR;
11117   *ins->obufp++ = (num < 10 ? ('0' + num)
11118                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
11119   *ins->obufp++ = STYLE_MARKER_CHAR;
11120
11121   /* This final null character is not strictly necessary, after inserting a
11122      style marker we should always be inserting some additional content.
11123      However, having the buffer null terminated doesn't cost much, and make
11124      it easier to debug what's going on.  Also, if we do ever forget to add
11125      any additional content after this style marker, then the buffer will
11126      still be well formed.  */
11127   *ins->obufp = '\0';
11128 }
11129
11130 static void
11131 oappend_with_style (instr_info *ins, const char *s,
11132                     enum disassembler_style style)
11133 {
11134   oappend_insert_style (ins, style);
11135   ins->obufp = stpcpy (ins->obufp, s);
11136 }
11137
11138 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11139    the style for the character as STYLE.  */
11140
11141 static void
11142 oappend_char_with_style (instr_info *ins, const char c,
11143                          enum disassembler_style style)
11144 {
11145   oappend_insert_style (ins, style);
11146   *ins->obufp++ = c;
11147   *ins->obufp = '\0';
11148 }
11149
11150 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11151
11152 static void
11153 oappend_char (instr_info *ins, const char c)
11154 {
11155   oappend_char_with_style (ins, c, dis_style_text);
11156 }
11157
11158 static void
11159 append_seg (instr_info *ins)
11160 {
11161   /* Only print the active segment register.  */
11162   if (!ins->active_seg_prefix)
11163     return;
11164
11165   ins->used_prefixes |= ins->active_seg_prefix;
11166   switch (ins->active_seg_prefix)
11167     {
11168     case PREFIX_CS:
11169       oappend_register (ins, att_names_seg[1]);
11170       break;
11171     case PREFIX_DS:
11172       oappend_register (ins, att_names_seg[3]);
11173       break;
11174     case PREFIX_SS:
11175       oappend_register (ins, att_names_seg[2]);
11176       break;
11177     case PREFIX_ES:
11178       oappend_register (ins, att_names_seg[0]);
11179       break;
11180     case PREFIX_FS:
11181       oappend_register (ins, att_names_seg[4]);
11182       break;
11183     case PREFIX_GS:
11184       oappend_register (ins, att_names_seg[5]);
11185       break;
11186     default:
11187       break;
11188     }
11189   oappend_char (ins, ':');
11190 }
11191
11192 static void
11193 print_operand_value (instr_info *ins, bfd_vma disp,
11194                      enum disassembler_style style)
11195 {
11196   char tmp[30];
11197
11198   if (ins->address_mode != mode_64bit)
11199     disp &= 0xffffffff;
11200   sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11201   oappend_with_style (ins, tmp, style);
11202 }
11203
11204 /* Like oappend, but called for immediate operands.  */
11205
11206 static void
11207 oappend_immediate (instr_info *ins, bfd_vma imm)
11208 {
11209   if (!ins->intel_syntax)
11210     oappend_char_with_style (ins, '$', dis_style_immediate);
11211   print_operand_value (ins, imm, dis_style_immediate);
11212 }
11213
11214 /* Put DISP in BUF as signed hex number.  */
11215
11216 static void
11217 print_displacement (instr_info *ins, bfd_signed_vma val)
11218 {
11219   char tmp[30];
11220
11221   if (val < 0)
11222     {
11223       oappend_char_with_style (ins, '-', dis_style_address_offset);
11224       val = (bfd_vma) 0 - val;
11225
11226       /* Check for possible overflow.  */
11227       if (val < 0)
11228         {
11229           switch (ins->address_mode)
11230             {
11231             case mode_64bit:
11232               oappend_with_style (ins, "0x8000000000000000",
11233                                   dis_style_address_offset);
11234               break;
11235             case mode_32bit:
11236               oappend_with_style (ins, "0x80000000",
11237                                   dis_style_address_offset);
11238               break;
11239             case mode_16bit:
11240               oappend_with_style (ins, "0x8000",
11241                                   dis_style_address_offset);
11242               break;
11243             }
11244           return;
11245         }
11246     }
11247
11248   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11249   oappend_with_style (ins, tmp, dis_style_address_offset);
11250 }
11251
11252 static void
11253 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11254 {
11255   /* Check if there is a broadcast, when evex.b is not treated as evex.nd.  */
11256   if (ins->vex.b && ins->evex_type == evex_default)
11257     {
11258       if (!ins->vex.no_broadcast)
11259         switch (bytemode)
11260           {
11261           case x_mode:
11262           case evex_half_bcst_xmmq_mode:
11263             if (ins->vex.w)
11264               oappend (ins, "QWORD BCST ");
11265             else
11266               oappend (ins, "DWORD BCST ");
11267             break;
11268           case xh_mode:
11269           case evex_half_bcst_xmmqh_mode:
11270           case evex_half_bcst_xmmqdh_mode:
11271             oappend (ins, "WORD BCST ");
11272             break;
11273           default:
11274             ins->vex.no_broadcast = true;
11275             break;
11276           }
11277       return;
11278     }
11279   switch (bytemode)
11280     {
11281     case b_mode:
11282     case b_swap_mode:
11283     case db_mode:
11284       oappend (ins, "BYTE PTR ");
11285       break;
11286     case w_mode:
11287     case w_swap_mode:
11288     case dw_mode:
11289       oappend (ins, "WORD PTR ");
11290       break;
11291     case indir_v_mode:
11292       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11293         {
11294           oappend (ins, "QWORD PTR ");
11295           break;
11296         }
11297       /* Fall through.  */
11298     case stack_v_mode:
11299       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11300                                               || (ins->rex & REX_W)))
11301         {
11302           oappend (ins, "QWORD PTR ");
11303           break;
11304         }
11305       /* Fall through.  */
11306     case v_mode:
11307     case v_swap_mode:
11308     case dq_mode:
11309       USED_REX (REX_W);
11310       if (ins->rex & REX_W)
11311         oappend (ins, "QWORD PTR ");
11312       else if (bytemode == dq_mode)
11313         oappend (ins, "DWORD PTR ");
11314       else
11315         {
11316           if (sizeflag & DFLAG)
11317             oappend (ins, "DWORD PTR ");
11318           else
11319             oappend (ins, "WORD PTR ");
11320           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11321         }
11322       break;
11323     case z_mode:
11324       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11325         *ins->obufp++ = 'D';
11326       oappend (ins, "WORD PTR ");
11327       if (!(ins->rex & REX_W))
11328         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11329       break;
11330     case a_mode:
11331       if (sizeflag & DFLAG)
11332         oappend (ins, "QWORD PTR ");
11333       else
11334         oappend (ins, "DWORD PTR ");
11335       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11336       break;
11337     case movsxd_mode:
11338       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11339         oappend (ins, "WORD PTR ");
11340       else
11341         oappend (ins, "DWORD PTR ");
11342       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11343       break;
11344     case d_mode:
11345     case d_swap_mode:
11346       oappend (ins, "DWORD PTR ");
11347       break;
11348     case q_mode:
11349     case q_swap_mode:
11350       oappend (ins, "QWORD PTR ");
11351       break;
11352     case m_mode:
11353       if (ins->address_mode == mode_64bit)
11354         oappend (ins, "QWORD PTR ");
11355       else
11356         oappend (ins, "DWORD PTR ");
11357       break;
11358     case f_mode:
11359       if (sizeflag & DFLAG)
11360         oappend (ins, "FWORD PTR ");
11361       else
11362         oappend (ins, "DWORD PTR ");
11363       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11364       break;
11365     case t_mode:
11366       oappend (ins, "TBYTE PTR ");
11367       break;
11368     case x_mode:
11369     case xh_mode:
11370     case x_swap_mode:
11371     case evex_x_gscat_mode:
11372     case evex_x_nobcst_mode:
11373     case bw_unit_mode:
11374       if (ins->need_vex)
11375         {
11376           switch (ins->vex.length)
11377             {
11378             case 128:
11379               oappend (ins, "XMMWORD PTR ");
11380               break;
11381             case 256:
11382               oappend (ins, "YMMWORD PTR ");
11383               break;
11384             case 512:
11385               oappend (ins, "ZMMWORD PTR ");
11386               break;
11387             default:
11388               abort ();
11389             }
11390         }
11391       else
11392         oappend (ins, "XMMWORD PTR ");
11393       break;
11394     case xmm_mode:
11395       oappend (ins, "XMMWORD PTR ");
11396       break;
11397     case ymm_mode:
11398       oappend (ins, "YMMWORD PTR ");
11399       break;
11400     case xmmq_mode:
11401     case evex_half_bcst_xmmqh_mode:
11402     case evex_half_bcst_xmmq_mode:
11403       switch (ins->vex.length)
11404         {
11405         case 0:
11406         case 128:
11407           oappend (ins, "QWORD PTR ");
11408           break;
11409         case 256:
11410           oappend (ins, "XMMWORD PTR ");
11411           break;
11412         case 512:
11413           oappend (ins, "YMMWORD PTR ");
11414           break;
11415         default:
11416           abort ();
11417         }
11418       break;
11419     case xmmdw_mode:
11420       if (!ins->need_vex)
11421         abort ();
11422
11423       switch (ins->vex.length)
11424         {
11425         case 128:
11426           oappend (ins, "WORD PTR ");
11427           break;
11428         case 256:
11429           oappend (ins, "DWORD PTR ");
11430           break;
11431         case 512:
11432           oappend (ins, "QWORD PTR ");
11433           break;
11434         default:
11435           abort ();
11436         }
11437       break;
11438     case xmmqd_mode:
11439     case evex_half_bcst_xmmqdh_mode:
11440       if (!ins->need_vex)
11441         abort ();
11442
11443       switch (ins->vex.length)
11444         {
11445         case 128:
11446           oappend (ins, "DWORD PTR ");
11447           break;
11448         case 256:
11449           oappend (ins, "QWORD PTR ");
11450           break;
11451         case 512:
11452           oappend (ins, "XMMWORD PTR ");
11453           break;
11454         default:
11455           abort ();
11456         }
11457       break;
11458     case ymmq_mode:
11459       if (!ins->need_vex)
11460         abort ();
11461
11462       switch (ins->vex.length)
11463         {
11464         case 128:
11465           oappend (ins, "QWORD PTR ");
11466           break;
11467         case 256:
11468           oappend (ins, "YMMWORD PTR ");
11469           break;
11470         case 512:
11471           oappend (ins, "ZMMWORD PTR ");
11472           break;
11473         default:
11474           abort ();
11475         }
11476       break;
11477     case o_mode:
11478       oappend (ins, "OWORD PTR ");
11479       break;
11480     case vex_vsib_d_w_dq_mode:
11481     case vex_vsib_q_w_dq_mode:
11482       if (!ins->need_vex)
11483         abort ();
11484       if (ins->vex.w)
11485         oappend (ins, "QWORD PTR ");
11486       else
11487         oappend (ins, "DWORD PTR ");
11488       break;
11489     case mask_bd_mode:
11490       if (!ins->need_vex || ins->vex.length != 128)
11491         abort ();
11492       if (ins->vex.w)
11493         oappend (ins, "DWORD PTR ");
11494       else
11495         oappend (ins, "BYTE PTR ");
11496       break;
11497     case mask_mode:
11498       if (!ins->need_vex)
11499         abort ();
11500       if (ins->vex.w)
11501         oappend (ins, "QWORD PTR ");
11502       else
11503         oappend (ins, "WORD PTR ");
11504       break;
11505     case v_bnd_mode:
11506     case v_bndmk_mode:
11507     default:
11508       break;
11509     }
11510 }
11511
11512 static void
11513 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11514                 int bytemode, int sizeflag)
11515 {
11516   const char (*names)[8];
11517
11518   /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11519      as the consumer will inspect it only for the destination operand.  */
11520   if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11521     ins->illegal_masking = true;
11522
11523   USED_REX (rexmask);
11524   if (ins->rex & rexmask)
11525     reg += 8;
11526   if (ins->rex2 & rexmask)
11527     reg += 16;
11528
11529   switch (bytemode)
11530     {
11531     case b_mode:
11532     case b_swap_mode:
11533       if (reg & 4)
11534         USED_REX (0);
11535       if (ins->rex || ins->rex2)
11536         names = att_names8rex;
11537       else
11538         names = att_names8;
11539       break;
11540     case w_mode:
11541       names = att_names16;
11542       break;
11543     case d_mode:
11544     case dw_mode:
11545     case db_mode:
11546       names = att_names32;
11547       break;
11548     case q_mode:
11549       names = att_names64;
11550       break;
11551     case m_mode:
11552     case v_bnd_mode:
11553       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11554       break;
11555     case bnd_mode:
11556     case bnd_swap_mode:
11557       if (reg > 0x3)
11558         {
11559           oappend (ins, "(bad)");
11560           return;
11561         }
11562       names = att_names_bnd;
11563       break;
11564     case indir_v_mode:
11565       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11566         {
11567           names = att_names64;
11568           break;
11569         }
11570       /* Fall through.  */
11571     case stack_v_mode:
11572       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11573                                               || (ins->rex & REX_W)))
11574         {
11575           names = att_names64;
11576           break;
11577         }
11578       bytemode = v_mode;
11579       /* Fall through.  */
11580     case v_mode:
11581     case v_swap_mode:
11582     case dq_mode:
11583       USED_REX (REX_W);
11584       if (ins->rex & REX_W)
11585         names = att_names64;
11586       else if (bytemode != v_mode && bytemode != v_swap_mode)
11587         names = att_names32;
11588       else
11589         {
11590           if (sizeflag & DFLAG)
11591             names = att_names32;
11592           else
11593             names = att_names16;
11594           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11595         }
11596       break;
11597     case movsxd_mode:
11598       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11599         names = att_names16;
11600       else
11601         names = att_names32;
11602       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11603       break;
11604     case va_mode:
11605       names = (ins->address_mode == mode_64bit
11606                ? att_names64 : att_names32);
11607       if (!(ins->prefixes & PREFIX_ADDR))
11608         names = (ins->address_mode == mode_16bit
11609                      ? att_names16 : names);
11610       else
11611         {
11612           /* Remove "addr16/addr32".  */
11613           ins->all_prefixes[ins->last_addr_prefix] = 0;
11614           names = (ins->address_mode != mode_32bit
11615                        ? att_names32 : att_names16);
11616           ins->used_prefixes |= PREFIX_ADDR;
11617         }
11618       break;
11619     case mask_bd_mode:
11620     case mask_mode:
11621       if (reg > 0x7)
11622         {
11623           oappend (ins, "(bad)");
11624           return;
11625         }
11626       names = att_names_mask;
11627       break;
11628     case 0:
11629       return;
11630     default:
11631       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11632       return;
11633     }
11634   oappend_register (ins, names[reg]);
11635 }
11636
11637 static bool
11638 get8s (instr_info *ins, bfd_vma *res)
11639 {
11640   if (!fetch_code (ins->info, ins->codep + 1))
11641     return false;
11642   *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11643   return true;
11644 }
11645
11646 static bool
11647 get16 (instr_info *ins, bfd_vma *res)
11648 {
11649   if (!fetch_code (ins->info, ins->codep + 2))
11650     return false;
11651   *res = *ins->codep++;
11652   *res |= (bfd_vma) *ins->codep++ << 8;
11653   return true;
11654 }
11655
11656 static bool
11657 get16s (instr_info *ins, bfd_vma *res)
11658 {
11659   if (!get16 (ins, res))
11660     return false;
11661   *res = (*res ^ 0x8000) - 0x8000;
11662   return true;
11663 }
11664
11665 static bool
11666 get32 (instr_info *ins, bfd_vma *res)
11667 {
11668   if (!fetch_code (ins->info, ins->codep + 4))
11669     return false;
11670   *res = *ins->codep++;
11671   *res |= (bfd_vma) *ins->codep++ << 8;
11672   *res |= (bfd_vma) *ins->codep++ << 16;
11673   *res |= (bfd_vma) *ins->codep++ << 24;
11674   return true;
11675 }
11676
11677 static bool
11678 get32s (instr_info *ins, bfd_vma *res)
11679 {
11680   if (!get32 (ins, res))
11681     return false;
11682
11683   *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11684
11685   return true;
11686 }
11687
11688 static bool
11689 get64 (instr_info *ins, uint64_t *res)
11690 {
11691   unsigned int a;
11692   unsigned int b;
11693
11694   if (!fetch_code (ins->info, ins->codep + 8))
11695     return false;
11696   a = *ins->codep++;
11697   a |= (unsigned int) *ins->codep++ << 8;
11698   a |= (unsigned int) *ins->codep++ << 16;
11699   a |= (unsigned int) *ins->codep++ << 24;
11700   b = *ins->codep++;
11701   b |= (unsigned int) *ins->codep++ << 8;
11702   b |= (unsigned int) *ins->codep++ << 16;
11703   b |= (unsigned int) *ins->codep++ << 24;
11704   *res = a + ((uint64_t) b << 32);
11705   return true;
11706 }
11707
11708 static void
11709 set_op (instr_info *ins, bfd_vma op, bool riprel)
11710 {
11711   ins->op_index[ins->op_ad] = ins->op_ad;
11712   if (ins->address_mode == mode_64bit)
11713     ins->op_address[ins->op_ad] = op;
11714   else /* Mask to get a 32-bit address.  */
11715     ins->op_address[ins->op_ad] = op & 0xffffffff;
11716   ins->op_riprel[ins->op_ad] = riprel;
11717 }
11718
11719 static bool
11720 BadOp (instr_info *ins)
11721 {
11722   /* Throw away prefixes and 1st. opcode byte.  */
11723   struct dis_private *priv = ins->info->private_data;
11724
11725   ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11726   ins->obufp = stpcpy (ins->obufp, "(bad)");
11727   return true;
11728 }
11729
11730 static bool
11731 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11732                int sizeflag ATTRIBUTE_UNUSED)
11733 {
11734   if (ins->modrm.mod != 3)
11735     return BadOp (ins);
11736
11737   /* Skip mod/rm byte.  */
11738   MODRM_CHECK;
11739   ins->codep++;
11740   ins->has_skipped_modrm = true;
11741   return true;
11742 }
11743
11744 static bool
11745 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11746 {
11747   int add = (ins->rex & REX_B) ? 8 : 0;
11748   int riprel = 0;
11749   int shift;
11750
11751   add += (ins->rex2 & REX_B) ? 16 : 0;
11752
11753   /* Handles EVEX other than APX EVEX-promoted instructions.  */
11754   if (ins->vex.evex && ins->evex_type == evex_default)
11755     {
11756
11757       /* Zeroing-masking is invalid for memory destinations. Set the flag
11758          uniformly, as the consumer will inspect it only for the destination
11759          operand.  */
11760       if (ins->vex.zeroing)
11761         ins->illegal_masking = true;
11762
11763       switch (bytemode)
11764         {
11765         case dw_mode:
11766         case w_mode:
11767         case w_swap_mode:
11768           shift = 1;
11769           break;
11770         case db_mode:
11771         case b_mode:
11772           shift = 0;
11773           break;
11774         case dq_mode:
11775           if (ins->address_mode != mode_64bit)
11776             {
11777         case d_mode:
11778         case d_swap_mode:
11779               shift = 2;
11780               break;
11781             }
11782             /* fall through */
11783         case vex_vsib_d_w_dq_mode:
11784         case vex_vsib_q_w_dq_mode:
11785         case evex_x_gscat_mode:
11786           shift = ins->vex.w ? 3 : 2;
11787           break;
11788         case xh_mode:
11789         case evex_half_bcst_xmmqh_mode:
11790         case evex_half_bcst_xmmqdh_mode:
11791           if (ins->vex.b)
11792             {
11793               shift = ins->vex.w ? 2 : 1;
11794               break;
11795             }
11796           /* Fall through.  */
11797         case x_mode:
11798         case evex_half_bcst_xmmq_mode:
11799           if (ins->vex.b)
11800             {
11801               shift = ins->vex.w ? 3 : 2;
11802               break;
11803             }
11804           /* Fall through.  */
11805         case xmmqd_mode:
11806         case xmmdw_mode:
11807         case xmmq_mode:
11808         case ymmq_mode:
11809         case evex_x_nobcst_mode:
11810         case x_swap_mode:
11811           switch (ins->vex.length)
11812             {
11813             case 128:
11814               shift = 4;
11815               break;
11816             case 256:
11817               shift = 5;
11818               break;
11819             case 512:
11820               shift = 6;
11821               break;
11822             default:
11823               abort ();
11824             }
11825           /* Make necessary corrections to shift for modes that need it.  */
11826           if (bytemode == xmmq_mode
11827               || bytemode == evex_half_bcst_xmmqh_mode
11828               || bytemode == evex_half_bcst_xmmq_mode
11829               || (bytemode == ymmq_mode && ins->vex.length == 128))
11830             shift -= 1;
11831           else if (bytemode == xmmqd_mode
11832                    || bytemode == evex_half_bcst_xmmqdh_mode)
11833             shift -= 2;
11834           else if (bytemode == xmmdw_mode)
11835             shift -= 3;
11836           break;
11837         case ymm_mode:
11838           shift = 5;
11839           break;
11840         case xmm_mode:
11841           shift = 4;
11842           break;
11843         case q_mode:
11844         case q_swap_mode:
11845           shift = 3;
11846           break;
11847         case bw_unit_mode:
11848           shift = ins->vex.w ? 1 : 0;
11849           break;
11850         default:
11851           abort ();
11852         }
11853     }
11854   else
11855     shift = 0;
11856
11857   USED_REX (REX_B);
11858   if (ins->intel_syntax)
11859     intel_operand_size (ins, bytemode, sizeflag);
11860   append_seg (ins);
11861
11862   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11863     {
11864       /* 32/64 bit address mode */
11865       bfd_vma disp = 0;
11866       int havedisp;
11867       int havebase;
11868       int needindex;
11869       int needaddr32;
11870       int base, rbase;
11871       int vindex = 0;
11872       int scale = 0;
11873       int addr32flag = !((sizeflag & AFLAG)
11874                          || bytemode == v_bnd_mode
11875                          || bytemode == v_bndmk_mode
11876                          || bytemode == bnd_mode
11877                          || bytemode == bnd_swap_mode);
11878       bool check_gather = false;
11879       const char (*indexes)[8] = NULL;
11880
11881       havebase = 1;
11882       base = ins->modrm.rm;
11883
11884       if (base == 4)
11885         {
11886           vindex = ins->sib.index;
11887           USED_REX (REX_X);
11888           if (ins->rex & REX_X)
11889             vindex += 8;
11890           switch (bytemode)
11891             {
11892             case vex_vsib_d_w_dq_mode:
11893             case vex_vsib_q_w_dq_mode:
11894               if (!ins->need_vex)
11895                 abort ();
11896               if (ins->vex.evex)
11897                 {
11898                   /* S/G EVEX insns require EVEX.X4 not to be set.  */
11899                   if (ins->rex2 & REX_X)
11900                     {
11901                       oappend (ins, "(bad)");
11902                       return true;
11903                     }
11904
11905                   if (!ins->vex.v)
11906                     vindex += 16;
11907                   check_gather = ins->obufp == ins->op_out[1];
11908                 }
11909
11910               switch (ins->vex.length)
11911                 {
11912                 case 128:
11913                   indexes = att_names_xmm;
11914                   break;
11915                 case 256:
11916                   if (!ins->vex.w
11917                       || bytemode == vex_vsib_q_w_dq_mode)
11918                     indexes = att_names_ymm;
11919                   else
11920                     indexes = att_names_xmm;
11921                   break;
11922                 case 512:
11923                   if (!ins->vex.w
11924                       || bytemode == vex_vsib_q_w_dq_mode)
11925                     indexes = att_names_zmm;
11926                   else
11927                     indexes = att_names_ymm;
11928                   break;
11929                 default:
11930                   abort ();
11931                 }
11932               break;
11933             default:
11934               if (ins->rex2 & REX_X)
11935                 vindex += 16;
11936
11937               if (vindex != 4)
11938                 indexes = ins->address_mode == mode_64bit && !addr32flag
11939                           ? att_names64 : att_names32;
11940               break;
11941             }
11942           scale = ins->sib.scale;
11943           base = ins->sib.base;
11944           ins->codep++;
11945         }
11946       else
11947         {
11948           /* Check for mandatory SIB.  */
11949           if (bytemode == vex_vsib_d_w_dq_mode
11950               || bytemode == vex_vsib_q_w_dq_mode
11951               || bytemode == vex_sibmem_mode)
11952             {
11953               oappend (ins, "(bad)");
11954               return true;
11955             }
11956         }
11957       rbase = base + add;
11958
11959       switch (ins->modrm.mod)
11960         {
11961         case 0:
11962           if (base == 5)
11963             {
11964               havebase = 0;
11965               if (ins->address_mode == mode_64bit && !ins->has_sib)
11966                 riprel = 1;
11967               if (!get32s (ins, &disp))
11968                 return false;
11969               if (riprel && bytemode == v_bndmk_mode)
11970                 {
11971                   oappend (ins, "(bad)");
11972                   return true;
11973                 }
11974             }
11975           break;
11976         case 1:
11977           if (!get8s (ins, &disp))
11978             return false;
11979           if (ins->vex.evex && shift > 0)
11980             disp <<= shift;
11981           break;
11982         case 2:
11983           if (!get32s (ins, &disp))
11984             return false;
11985           break;
11986         }
11987
11988       needindex = 0;
11989       needaddr32 = 0;
11990       if (ins->has_sib
11991           && !havebase
11992           && !indexes
11993           && ins->address_mode != mode_16bit)
11994         {
11995           if (ins->address_mode == mode_64bit)
11996             {
11997               if (addr32flag)
11998                 {
11999                   /* Without base nor index registers, zero-extend the
12000                      lower 32-bit displacement to 64 bits.  */
12001                   disp &= 0xffffffff;
12002                   needindex = 1;
12003                 }
12004               needaddr32 = 1;
12005             }
12006           else
12007             {
12008               /* In 32-bit mode, we need index register to tell [offset]
12009                  from [eiz*1 + offset].  */
12010               needindex = 1;
12011             }
12012         }
12013
12014       havedisp = (havebase
12015                   || needindex
12016                   || (ins->has_sib && (indexes || scale != 0)));
12017
12018       if (!ins->intel_syntax)
12019         if (ins->modrm.mod != 0 || base == 5)
12020           {
12021             if (havedisp || riprel)
12022               print_displacement (ins, disp);
12023             else
12024               print_operand_value (ins, disp, dis_style_address_offset);
12025             if (riprel)
12026               {
12027                 set_op (ins, disp, true);
12028                 oappend_char (ins, '(');
12029                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12030                                     dis_style_register);
12031                 oappend_char (ins, ')');
12032               }
12033           }
12034
12035       if ((havebase || indexes || needindex || needaddr32 || riprel)
12036           && (ins->address_mode != mode_64bit
12037               || ((bytemode != v_bnd_mode)
12038                   && (bytemode != v_bndmk_mode)
12039                   && (bytemode != bnd_mode)
12040                   && (bytemode != bnd_swap_mode))))
12041         ins->used_prefixes |= PREFIX_ADDR;
12042
12043       if (havedisp || (ins->intel_syntax && riprel))
12044         {
12045           oappend_char (ins, ins->open_char);
12046           if (ins->intel_syntax && riprel)
12047             {
12048               set_op (ins, disp, true);
12049               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12050                                   dis_style_register);
12051             }
12052           if (havebase)
12053             oappend_register
12054               (ins,
12055                (ins->address_mode == mode_64bit && !addr32flag
12056                 ? att_names64 : att_names32)[rbase]);
12057           if (ins->has_sib)
12058             {
12059               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12060                  print index to tell base + index from base.  */
12061               if (scale != 0
12062                   || needindex
12063                   || indexes
12064                   || (havebase && base != ESP_REG_NUM))
12065                 {
12066                   if (!ins->intel_syntax || havebase)
12067                     oappend_char (ins, ins->separator_char);
12068                   if (indexes)
12069                     {
12070                       if (ins->address_mode == mode_64bit || vindex < 16)
12071                         oappend_register (ins, indexes[vindex]);
12072                       else
12073                         oappend (ins, "(bad)");
12074                     }
12075                   else
12076                     oappend_register (ins,
12077                                       ins->address_mode == mode_64bit
12078                                       && !addr32flag
12079                                       ? att_index64
12080                                       : att_index32);
12081
12082                   oappend_char (ins, ins->scale_char);
12083                   oappend_char_with_style (ins, '0' + (1 << scale),
12084                                            dis_style_immediate);
12085                 }
12086             }
12087           if (ins->intel_syntax
12088               && (disp || ins->modrm.mod != 0 || base == 5))
12089             {
12090               if (!havedisp || (bfd_signed_vma) disp >= 0)
12091                   oappend_char (ins, '+');
12092               if (havedisp)
12093                 print_displacement (ins, disp);
12094               else
12095                 print_operand_value (ins, disp, dis_style_address_offset);
12096             }
12097
12098           oappend_char (ins, ins->close_char);
12099
12100           if (check_gather)
12101             {
12102               /* Both XMM/YMM/ZMM registers must be distinct.  */
12103               int modrm_reg = ins->modrm.reg;
12104
12105               if (ins->rex & REX_R)
12106                 modrm_reg += 8;
12107               if (ins->rex2 & REX_R)
12108                 modrm_reg += 16;
12109               if (vindex == modrm_reg)
12110                 oappend (ins, "/(bad)");
12111             }
12112         }
12113       else if (ins->intel_syntax)
12114         {
12115           if (ins->modrm.mod != 0 || base == 5)
12116             {
12117               if (!ins->active_seg_prefix)
12118                 {
12119                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12120                   oappend (ins, ":");
12121                 }
12122               print_operand_value (ins, disp, dis_style_text);
12123             }
12124         }
12125     }
12126   else if (bytemode == v_bnd_mode
12127            || bytemode == v_bndmk_mode
12128            || bytemode == bnd_mode
12129            || bytemode == bnd_swap_mode
12130            || bytemode == vex_vsib_d_w_dq_mode
12131            || bytemode == vex_vsib_q_w_dq_mode)
12132     {
12133       oappend (ins, "(bad)");
12134       return true;
12135     }
12136   else
12137     {
12138       /* 16 bit address mode */
12139       bfd_vma disp = 0;
12140
12141       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12142       switch (ins->modrm.mod)
12143         {
12144         case 0:
12145           if (ins->modrm.rm == 6)
12146             {
12147         case 2:
12148               if (!get16s (ins, &disp))
12149                 return false;
12150             }
12151           break;
12152         case 1:
12153           if (!get8s (ins, &disp))
12154             return false;
12155           if (ins->vex.evex && shift > 0)
12156             disp <<= shift;
12157           break;
12158         }
12159
12160       if (!ins->intel_syntax)
12161         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12162           print_displacement (ins, disp);
12163
12164       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12165         {
12166           oappend_char (ins, ins->open_char);
12167           oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12168                                           : att_index16[ins->modrm.rm]);
12169           if (ins->intel_syntax
12170               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12171             {
12172               if ((bfd_signed_vma) disp >= 0)
12173                 oappend_char (ins, '+');
12174               print_displacement (ins, disp);
12175             }
12176
12177           oappend_char (ins, ins->close_char);
12178         }
12179       else if (ins->intel_syntax)
12180         {
12181           if (!ins->active_seg_prefix)
12182             {
12183               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12184               oappend (ins, ":");
12185             }
12186           print_operand_value (ins, disp & 0xffff, dis_style_text);
12187         }
12188     }
12189   if (ins->vex.b && ins->evex_type == evex_default)
12190     {
12191       ins->evex_used |= EVEX_b_used;
12192
12193       /* Broadcast can only ever be valid for memory sources.  */
12194       if (ins->obufp == ins->op_out[0])
12195         ins->vex.no_broadcast = true;
12196
12197       if (!ins->vex.no_broadcast
12198           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12199         {
12200           if (bytemode == xh_mode)
12201             {
12202               switch (ins->vex.length)
12203                 {
12204                 case 128:
12205                   oappend (ins, "{1to8}");
12206                   break;
12207                 case 256:
12208                   oappend (ins, "{1to16}");
12209                   break;
12210                 case 512:
12211                   oappend (ins, "{1to32}");
12212                   break;
12213                 default:
12214                   abort ();
12215                 }
12216             }
12217           else if (bytemode == q_mode
12218                    || bytemode == ymmq_mode)
12219             ins->vex.no_broadcast = true;
12220           else if (ins->vex.w
12221                    || bytemode == evex_half_bcst_xmmqdh_mode
12222                    || bytemode == evex_half_bcst_xmmq_mode)
12223             {
12224               switch (ins->vex.length)
12225                 {
12226                 case 128:
12227                   oappend (ins, "{1to2}");
12228                   break;
12229                 case 256:
12230                   oappend (ins, "{1to4}");
12231                   break;
12232                 case 512:
12233                   oappend (ins, "{1to8}");
12234                   break;
12235                 default:
12236                   abort ();
12237                 }
12238             }
12239           else if (bytemode == x_mode
12240                    || bytemode == evex_half_bcst_xmmqh_mode)
12241             {
12242               switch (ins->vex.length)
12243                 {
12244                 case 128:
12245                   oappend (ins, "{1to4}");
12246                   break;
12247                 case 256:
12248                   oappend (ins, "{1to8}");
12249                   break;
12250                 case 512:
12251                   oappend (ins, "{1to16}");
12252                   break;
12253                 default:
12254                   abort ();
12255                 }
12256             }
12257           else
12258             ins->vex.no_broadcast = true;
12259         }
12260       if (ins->vex.no_broadcast)
12261         oappend (ins, "{bad}");
12262     }
12263
12264   return true;
12265 }
12266
12267 static bool
12268 OP_E (instr_info *ins, int bytemode, int sizeflag)
12269 {
12270   /* Skip mod/rm byte.  */
12271   MODRM_CHECK;
12272   if (!ins->has_skipped_modrm)
12273     {
12274       ins->codep++;
12275       ins->has_skipped_modrm = true;
12276     }
12277
12278   if (ins->modrm.mod == 3)
12279     {
12280       if ((sizeflag & SUFFIX_ALWAYS)
12281           && (bytemode == b_swap_mode
12282               || bytemode == bnd_swap_mode
12283               || bytemode == v_swap_mode))
12284         swap_operand (ins);
12285
12286       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12287       return true;
12288     }
12289
12290   /* Masking is invalid for insns with GPR-like memory destination. Set the
12291      flag uniformly, as the consumer will inspect it only for the destination
12292      operand.  */
12293   if (ins->vex.mask_register_specifier)
12294     ins->illegal_masking = true;
12295
12296   return OP_E_memory (ins, bytemode, sizeflag);
12297 }
12298
12299 static bool
12300 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12301 {
12302   if (ins->modrm.mod == 3 && bytemode == f_mode)
12303     /* bad lcall/ljmp */
12304     return BadOp (ins);
12305   if (!ins->intel_syntax)
12306     oappend (ins, "*");
12307   return OP_E (ins, bytemode, sizeflag);
12308 }
12309
12310 static bool
12311 OP_G (instr_info *ins, int bytemode, int sizeflag)
12312 {
12313   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12314   return true;
12315 }
12316
12317 static bool
12318 OP_REG (instr_info *ins, int code, int sizeflag)
12319 {
12320   const char *s;
12321   int add = 0;
12322
12323   switch (code)
12324     {
12325     case es_reg: case ss_reg: case cs_reg:
12326     case ds_reg: case fs_reg: case gs_reg:
12327       oappend_register (ins, att_names_seg[code - es_reg]);
12328       return true;
12329     }
12330
12331   USED_REX (REX_B);
12332   if (ins->rex & REX_B)
12333     add = 8;
12334   if (ins->rex2 & REX_B)
12335     add += 16;
12336
12337   switch (code)
12338     {
12339     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12340     case sp_reg: case bp_reg: case si_reg: case di_reg:
12341       s = att_names16[code - ax_reg + add];
12342       break;
12343     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12344       USED_REX (0);
12345       /* Fall through.  */
12346     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12347       if (ins->rex)
12348         s = att_names8rex[code - al_reg + add];
12349       else
12350         s = att_names8[code - al_reg];
12351       break;
12352     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12353     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12354       if (ins->address_mode == mode_64bit
12355           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12356         {
12357           s = att_names64[code - rAX_reg + add];
12358           break;
12359         }
12360       code += eAX_reg - rAX_reg;
12361       /* Fall through.  */
12362     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12363     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12364       USED_REX (REX_W);
12365       if (ins->rex & REX_W)
12366         s = att_names64[code - eAX_reg + add];
12367       else
12368         {
12369           if (sizeflag & DFLAG)
12370             s = att_names32[code - eAX_reg + add];
12371           else
12372             s = att_names16[code - eAX_reg + add];
12373           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12374         }
12375       break;
12376     default:
12377       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12378       return true;
12379     }
12380   oappend_register (ins, s);
12381   return true;
12382 }
12383
12384 static bool
12385 OP_IMREG (instr_info *ins, int code, int sizeflag)
12386 {
12387   const char *s;
12388
12389   switch (code)
12390     {
12391     case indir_dx_reg:
12392       if (!ins->intel_syntax)
12393         {
12394           oappend (ins, "(%dx)");
12395           return true;
12396         }
12397       s = att_names16[dx_reg - ax_reg];
12398       break;
12399     case al_reg: case cl_reg:
12400       s = att_names8[code - al_reg];
12401       break;
12402     case eAX_reg:
12403       USED_REX (REX_W);
12404       if (ins->rex & REX_W)
12405         {
12406           s = *att_names64;
12407           break;
12408         }
12409       /* Fall through.  */
12410     case z_mode_ax_reg:
12411       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12412         s = *att_names32;
12413       else
12414         s = *att_names16;
12415       if (!(ins->rex & REX_W))
12416         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12417       break;
12418     default:
12419       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12420       return true;
12421     }
12422   oappend_register (ins, s);
12423   return true;
12424 }
12425
12426 static bool
12427 OP_I (instr_info *ins, int bytemode, int sizeflag)
12428 {
12429   bfd_vma op;
12430
12431   switch (bytemode)
12432     {
12433     case b_mode:
12434       if (!fetch_code (ins->info, ins->codep + 1))
12435         return false;
12436       op = *ins->codep++;
12437       break;
12438     case v_mode:
12439       USED_REX (REX_W);
12440       if (ins->rex & REX_W)
12441         {
12442           if (!get32s (ins, &op))
12443             return false;
12444         }
12445       else
12446         {
12447           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12448           if (sizeflag & DFLAG)
12449             {
12450     case d_mode:
12451               if (!get32 (ins, &op))
12452                 return false;
12453             }
12454           else
12455             {
12456               /* Fall through.  */
12457     case w_mode:
12458               if (!get16 (ins, &op))
12459                 return false;
12460             }
12461         }
12462       break;
12463     case const_1_mode:
12464       if (ins->intel_syntax)
12465         oappend_with_style (ins, "1", dis_style_immediate);
12466       else
12467         oappend_with_style (ins, "$1", dis_style_immediate);
12468       return true;
12469     default:
12470       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12471       return true;
12472     }
12473
12474   oappend_immediate (ins, op);
12475   return true;
12476 }
12477
12478 static bool
12479 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12480 {
12481   uint64_t op;
12482
12483   if (bytemode != v_mode || ins->address_mode != mode_64bit
12484       || !(ins->rex & REX_W))
12485     return OP_I (ins, bytemode, sizeflag);
12486
12487   USED_REX (REX_W);
12488
12489   if (!get64 (ins, &op))
12490     return false;
12491
12492   oappend_immediate (ins, op);
12493   return true;
12494 }
12495
12496 static bool
12497 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12498 {
12499   bfd_vma op;
12500
12501   switch (bytemode)
12502     {
12503     case b_mode:
12504     case b_T_mode:
12505       if (!get8s (ins, &op))
12506         return false;
12507       if (bytemode == b_T_mode)
12508         {
12509           if (ins->address_mode != mode_64bit
12510               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12511             {
12512               /* The operand-size prefix is overridden by a REX prefix.  */
12513               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12514                 op &= 0xffffffff;
12515               else
12516                 op &= 0xffff;
12517           }
12518         }
12519       else
12520         {
12521           if (!(ins->rex & REX_W))
12522             {
12523               if (sizeflag & DFLAG)
12524                 op &= 0xffffffff;
12525               else
12526                 op &= 0xffff;
12527             }
12528         }
12529       break;
12530     case v_mode:
12531       /* The operand-size prefix is overridden by a REX prefix.  */
12532       if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12533         {
12534           if (!get16 (ins, &op))
12535             return false;
12536         }
12537       else if (!get32s (ins, &op))
12538         return false;
12539       break;
12540     default:
12541       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12542       return true;
12543     }
12544
12545   oappend_immediate (ins, op);
12546   return true;
12547 }
12548
12549 static bool
12550 OP_J (instr_info *ins, int bytemode, int sizeflag)
12551 {
12552   bfd_vma disp;
12553   bfd_vma mask = -1;
12554   bfd_vma segment = 0;
12555
12556   switch (bytemode)
12557     {
12558     case b_mode:
12559       if (!get8s (ins, &disp))
12560         return false;
12561       break;
12562     case v_mode:
12563     case dqw_mode:
12564       if ((sizeflag & DFLAG)
12565           || (ins->address_mode == mode_64bit
12566               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12567                   || (ins->rex & REX_W))))
12568         {
12569           if (!get32s (ins, &disp))
12570             return false;
12571         }
12572       else
12573         {
12574           if (!get16s (ins, &disp))
12575             return false;
12576           /* In 16bit mode, address is wrapped around at 64k within
12577              the same segment.  Otherwise, a data16 prefix on a jump
12578              instruction means that the pc is masked to 16 bits after
12579              the displacement is added!  */
12580           mask = 0xffff;
12581           if ((ins->prefixes & PREFIX_DATA) == 0)
12582             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12583                        & ~((bfd_vma) 0xffff));
12584         }
12585       if (ins->address_mode != mode_64bit
12586           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12587         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12588       break;
12589     default:
12590       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12591       return true;
12592     }
12593   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12594          | segment;
12595   set_op (ins, disp, false);
12596   print_operand_value (ins, disp, dis_style_text);
12597   return true;
12598 }
12599
12600 static bool
12601 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12602 {
12603   if (bytemode == w_mode)
12604     {
12605       oappend_register (ins, att_names_seg[ins->modrm.reg]);
12606       return true;
12607     }
12608   return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12609 }
12610
12611 static bool
12612 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12613 {
12614   bfd_vma seg, offset;
12615   int res;
12616   char scratch[24];
12617
12618   if (sizeflag & DFLAG)
12619     {
12620       if (!get32 (ins, &offset))
12621         return false;;
12622     }
12623   else if (!get16 (ins, &offset))
12624     return false;
12625   if (!get16 (ins, &seg))
12626     return false;;
12627   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12628
12629   res = snprintf (scratch, ARRAY_SIZE (scratch),
12630                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12631                   (unsigned) seg, (unsigned) offset);
12632   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12633     abort ();
12634   oappend (ins, scratch);
12635   return true;
12636 }
12637
12638 static bool
12639 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12640 {
12641   bfd_vma off;
12642
12643   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12644     intel_operand_size (ins, bytemode, sizeflag);
12645   append_seg (ins);
12646
12647   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12648     {
12649       if (!get32 (ins, &off))
12650         return false;
12651     }
12652   else
12653     {
12654       if (!get16 (ins, &off))
12655         return false;
12656     }
12657
12658   if (ins->intel_syntax)
12659     {
12660       if (!ins->active_seg_prefix)
12661         {
12662           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12663           oappend (ins, ":");
12664         }
12665     }
12666   print_operand_value (ins, off, dis_style_address_offset);
12667   return true;
12668 }
12669
12670 static bool
12671 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12672 {
12673   uint64_t off;
12674
12675   if (ins->address_mode != mode_64bit
12676       || (ins->prefixes & PREFIX_ADDR))
12677     return OP_OFF (ins, bytemode, sizeflag);
12678
12679   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12680     intel_operand_size (ins, bytemode, sizeflag);
12681   append_seg (ins);
12682
12683   if (!get64 (ins, &off))
12684     return false;
12685
12686   if (ins->intel_syntax)
12687     {
12688       if (!ins->active_seg_prefix)
12689         {
12690           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12691           oappend (ins, ":");
12692         }
12693     }
12694   print_operand_value (ins, off, dis_style_address_offset);
12695   return true;
12696 }
12697
12698 static void
12699 ptr_reg (instr_info *ins, int code, int sizeflag)
12700 {
12701   const char *s;
12702
12703   *ins->obufp++ = ins->open_char;
12704   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12705   if (ins->address_mode == mode_64bit)
12706     {
12707       if (!(sizeflag & AFLAG))
12708         s = att_names32[code - eAX_reg];
12709       else
12710         s = att_names64[code - eAX_reg];
12711     }
12712   else if (sizeflag & AFLAG)
12713     s = att_names32[code - eAX_reg];
12714   else
12715     s = att_names16[code - eAX_reg];
12716   oappend_register (ins, s);
12717   oappend_char (ins, ins->close_char);
12718 }
12719
12720 static bool
12721 OP_ESreg (instr_info *ins, int code, int sizeflag)
12722 {
12723   if (ins->intel_syntax)
12724     {
12725       switch (ins->codep[-1])
12726         {
12727         case 0x6d:      /* insw/insl */
12728           intel_operand_size (ins, z_mode, sizeflag);
12729           break;
12730         case 0xa5:      /* movsw/movsl/movsq */
12731         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12732         case 0xab:      /* stosw/stosl */
12733         case 0xaf:      /* scasw/scasl */
12734           intel_operand_size (ins, v_mode, sizeflag);
12735           break;
12736         default:
12737           intel_operand_size (ins, b_mode, sizeflag);
12738         }
12739     }
12740   oappend_register (ins, att_names_seg[0]);
12741   oappend_char (ins, ':');
12742   ptr_reg (ins, code, sizeflag);
12743   return true;
12744 }
12745
12746 static bool
12747 OP_DSreg (instr_info *ins, int code, int sizeflag)
12748 {
12749   if (ins->intel_syntax)
12750     {
12751       switch (ins->codep[-1])
12752         {
12753         case 0x6f:      /* outsw/outsl */
12754           intel_operand_size (ins, z_mode, sizeflag);
12755           break;
12756         case 0xa5:      /* movsw/movsl/movsq */
12757         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12758         case 0xad:      /* lodsw/lodsl/lodsq */
12759           intel_operand_size (ins, v_mode, sizeflag);
12760           break;
12761         default:
12762           intel_operand_size (ins, b_mode, sizeflag);
12763         }
12764     }
12765   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12766      default segment register DS is printed.  */
12767   if (!ins->active_seg_prefix)
12768     ins->active_seg_prefix = PREFIX_DS;
12769   append_seg (ins);
12770   ptr_reg (ins, code, sizeflag);
12771   return true;
12772 }
12773
12774 static bool
12775 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12776       int sizeflag ATTRIBUTE_UNUSED)
12777 {
12778   int add, res;
12779   char scratch[8];
12780
12781   if (ins->rex & REX_R)
12782     {
12783       USED_REX (REX_R);
12784       add = 8;
12785     }
12786   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12787     {
12788       ins->all_prefixes[ins->last_lock_prefix] = 0;
12789       ins->used_prefixes |= PREFIX_LOCK;
12790       add = 8;
12791     }
12792   else
12793     add = 0;
12794   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12795                   ins->modrm.reg + add);
12796   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12797     abort ();
12798   oappend_register (ins, scratch);
12799   return true;
12800 }
12801
12802 static bool
12803 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12804       int sizeflag ATTRIBUTE_UNUSED)
12805 {
12806   int add, res;
12807   char scratch[8];
12808
12809   USED_REX (REX_R);
12810   if (ins->rex & REX_R)
12811     add = 8;
12812   else
12813     add = 0;
12814   res = snprintf (scratch, ARRAY_SIZE (scratch),
12815                   ins->intel_syntax ? "dr%d" : "%%db%d",
12816                   ins->modrm.reg + add);
12817   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12818     abort ();
12819   oappend (ins, scratch);
12820   return true;
12821 }
12822
12823 static bool
12824 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12825       int sizeflag ATTRIBUTE_UNUSED)
12826 {
12827   int res;
12828   char scratch[8];
12829
12830   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12831   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12832     abort ();
12833   oappend_register (ins, scratch);
12834   return true;
12835 }
12836
12837 static bool
12838 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12839         int sizeflag ATTRIBUTE_UNUSED)
12840 {
12841   int reg = ins->modrm.reg;
12842   const char (*names)[8];
12843
12844   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12845   if (ins->prefixes & PREFIX_DATA)
12846     {
12847       names = att_names_xmm;
12848       USED_REX (REX_R);
12849       if (ins->rex & REX_R)
12850         reg += 8;
12851     }
12852   else
12853     names = att_names_mm;
12854   oappend_register (ins, names[reg]);
12855   return true;
12856 }
12857
12858 static void
12859 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12860 {
12861   const char (*names)[8];
12862
12863   if (bytemode == xmmq_mode
12864       || bytemode == evex_half_bcst_xmmqh_mode
12865       || bytemode == evex_half_bcst_xmmq_mode)
12866     {
12867       switch (ins->vex.length)
12868         {
12869         case 0:
12870         case 128:
12871         case 256:
12872           names = att_names_xmm;
12873           break;
12874         case 512:
12875           names = att_names_ymm;
12876           ins->evex_used |= EVEX_len_used;
12877           break;
12878         default:
12879           abort ();
12880         }
12881     }
12882   else if (bytemode == ymm_mode)
12883     names = att_names_ymm;
12884   else if (bytemode == tmm_mode)
12885     {
12886       if (reg >= 8)
12887         {
12888           oappend (ins, "(bad)");
12889           return;
12890         }
12891       names = att_names_tmm;
12892     }
12893   else if (ins->need_vex
12894            && bytemode != xmm_mode
12895            && bytemode != scalar_mode
12896            && bytemode != xmmdw_mode
12897            && bytemode != xmmqd_mode
12898            && bytemode != evex_half_bcst_xmmqdh_mode
12899            && bytemode != w_swap_mode
12900            && bytemode != b_mode
12901            && bytemode != w_mode
12902            && bytemode != d_mode
12903            && bytemode != q_mode)
12904     {
12905       ins->evex_used |= EVEX_len_used;
12906       switch (ins->vex.length)
12907         {
12908         case 128:
12909           names = att_names_xmm;
12910           break;
12911         case 256:
12912           if (ins->vex.w
12913               || bytemode != vex_vsib_q_w_dq_mode)
12914             names = att_names_ymm;
12915           else
12916             names = att_names_xmm;
12917           break;
12918         case 512:
12919           if (ins->vex.w
12920               || bytemode != vex_vsib_q_w_dq_mode)
12921             names = att_names_zmm;
12922           else
12923             names = att_names_ymm;
12924           break;
12925         default:
12926           abort ();
12927         }
12928     }
12929   else
12930     names = att_names_xmm;
12931   oappend_register (ins, names[reg]);
12932 }
12933
12934 static bool
12935 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12936 {
12937   unsigned int reg = ins->modrm.reg;
12938
12939   USED_REX (REX_R);
12940   if (ins->rex & REX_R)
12941     reg += 8;
12942   if (ins->vex.evex)
12943     {
12944       if (ins->rex2 & REX_R)
12945         reg += 16;
12946     }
12947
12948   if (bytemode == tmm_mode)
12949     ins->modrm.reg = reg;
12950   else if (bytemode == scalar_mode)
12951     ins->vex.no_broadcast = true;
12952
12953   print_vector_reg (ins, reg, bytemode);
12954   return true;
12955 }
12956
12957 static bool
12958 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12959 {
12960   int reg;
12961   const char (*names)[8];
12962
12963   if (ins->modrm.mod != 3)
12964     {
12965       if (ins->intel_syntax
12966           && (bytemode == v_mode || bytemode == v_swap_mode))
12967         {
12968           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12969           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12970         }
12971       return OP_E (ins, bytemode, sizeflag);
12972     }
12973
12974   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12975     swap_operand (ins);
12976
12977   /* Skip mod/rm byte.  */
12978   MODRM_CHECK;
12979   ins->codep++;
12980   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12981   reg = ins->modrm.rm;
12982   if (ins->prefixes & PREFIX_DATA)
12983     {
12984       names = att_names_xmm;
12985       USED_REX (REX_B);
12986       if (ins->rex & REX_B)
12987         reg += 8;
12988     }
12989   else
12990     names = att_names_mm;
12991   oappend_register (ins, names[reg]);
12992   return true;
12993 }
12994
12995 /* cvt* are the only instructions in sse2 which have
12996    both SSE and MMX operands and also have 0x66 prefix
12997    in their opcode. 0x66 was originally used to differentiate
12998    between SSE and MMX instruction(operands). So we have to handle the
12999    cvt* separately using OP_EMC and OP_MXC */
13000 static bool
13001 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13002 {
13003   if (ins->modrm.mod != 3)
13004     {
13005       if (ins->intel_syntax && bytemode == v_mode)
13006         {
13007           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13008           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13009         }
13010       return OP_E (ins, bytemode, sizeflag);
13011     }
13012
13013   /* Skip mod/rm byte.  */
13014   MODRM_CHECK;
13015   ins->codep++;
13016   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13017   oappend_register (ins, att_names_mm[ins->modrm.rm]);
13018   return true;
13019 }
13020
13021 static bool
13022 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13023         int sizeflag ATTRIBUTE_UNUSED)
13024 {
13025   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13026   oappend_register (ins, att_names_mm[ins->modrm.reg]);
13027   return true;
13028 }
13029
13030 static bool
13031 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13032 {
13033   int reg;
13034
13035   /* Skip mod/rm byte.  */
13036   MODRM_CHECK;
13037   ins->codep++;
13038
13039   if (bytemode == dq_mode)
13040     bytemode = ins->vex.w ? q_mode : d_mode;
13041
13042   if (ins->modrm.mod != 3)
13043     return OP_E_memory (ins, bytemode, sizeflag);
13044
13045   reg = ins->modrm.rm;
13046   USED_REX (REX_B);
13047   if (ins->rex & REX_B)
13048     reg += 8;
13049   if (ins->vex.evex)
13050     {
13051       USED_REX (REX_X);
13052       if ((ins->rex & REX_X))
13053         reg += 16;
13054       ins->rex2_used &= ~REX_B;
13055     }
13056   else if (ins->rex2 & REX_B)
13057     reg += 16;
13058
13059   if ((sizeflag & SUFFIX_ALWAYS)
13060       && (bytemode == x_swap_mode
13061           || bytemode == w_swap_mode
13062           || bytemode == d_swap_mode
13063           || bytemode == q_swap_mode))
13064     swap_operand (ins);
13065
13066   if (bytemode == tmm_mode)
13067     ins->modrm.rm = reg;
13068
13069   print_vector_reg (ins, reg, bytemode);
13070   return true;
13071 }
13072
13073 static bool
13074 OP_R (instr_info *ins, int bytemode, int sizeflag)
13075 {
13076   if (ins->modrm.mod != 3)
13077     return BadOp (ins);
13078
13079   switch (bytemode)
13080     {
13081     case d_mode:
13082     case dq_mode:
13083     case q_mode:
13084     case mask_mode:
13085       return OP_E (ins, bytemode, sizeflag);
13086     case q_mm_mode:
13087       return OP_EM (ins, x_mode, sizeflag);
13088     case xmm_mode:
13089       if (ins->vex.length <= 128)
13090         break;
13091       return BadOp (ins);
13092     }
13093
13094   return OP_EX (ins, bytemode, sizeflag);
13095 }
13096
13097 static bool
13098 OP_M (instr_info *ins, int bytemode, int sizeflag)
13099 {
13100   /* Skip mod/rm byte.  */
13101   MODRM_CHECK;
13102   ins->codep++;
13103
13104   if (ins->modrm.mod == 3)
13105     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13106     return BadOp (ins);
13107
13108   if (bytemode == x_mode)
13109     ins->vex.no_broadcast = true;
13110
13111   return OP_E_memory (ins, bytemode, sizeflag);
13112 }
13113
13114 static bool
13115 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13116 {
13117   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13118     return BadOp (ins);
13119   return OP_E (ins, bytemode, sizeflag);
13120 }
13121
13122 /* montmul instruction need display repz and skip modrm */
13123
13124 static bool
13125 MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13126 {
13127   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13128     return BadOp (ins);
13129
13130   /* The 0xf3 prefix should be displayed as "repz" for montmul. */
13131   if (ins->prefixes & PREFIX_REPZ)
13132     ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
13133
13134   /* Skip mod/rm byte.  */
13135   MODRM_CHECK;
13136   ins->codep++;
13137   return true;
13138 }
13139
13140 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13141    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13142
13143 static bool
13144 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13145 {
13146   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13147     {
13148       ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13149       return true;
13150     }
13151   if (opnd == 0)
13152     return OP_REG (ins, eAX_reg, sizeflag);
13153   return OP_IMREG (ins, eAX_reg, sizeflag);
13154 }
13155
13156 static const char *const Suffix3DNow[] = {
13157 /* 00 */        NULL,           NULL,           NULL,           NULL,
13158 /* 04 */        NULL,           NULL,           NULL,           NULL,
13159 /* 08 */        NULL,           NULL,           NULL,           NULL,
13160 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13161 /* 10 */        NULL,           NULL,           NULL,           NULL,
13162 /* 14 */        NULL,           NULL,           NULL,           NULL,
13163 /* 18 */        NULL,           NULL,           NULL,           NULL,
13164 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13165 /* 20 */        NULL,           NULL,           NULL,           NULL,
13166 /* 24 */        NULL,           NULL,           NULL,           NULL,
13167 /* 28 */        NULL,           NULL,           NULL,           NULL,
13168 /* 2C */        NULL,           NULL,           NULL,           NULL,
13169 /* 30 */        NULL,           NULL,           NULL,           NULL,
13170 /* 34 */        NULL,           NULL,           NULL,           NULL,
13171 /* 38 */        NULL,           NULL,           NULL,           NULL,
13172 /* 3C */        NULL,           NULL,           NULL,           NULL,
13173 /* 40 */        NULL,           NULL,           NULL,           NULL,
13174 /* 44 */        NULL,           NULL,           NULL,           NULL,
13175 /* 48 */        NULL,           NULL,           NULL,           NULL,
13176 /* 4C */        NULL,           NULL,           NULL,           NULL,
13177 /* 50 */        NULL,           NULL,           NULL,           NULL,
13178 /* 54 */        NULL,           NULL,           NULL,           NULL,
13179 /* 58 */        NULL,           NULL,           NULL,           NULL,
13180 /* 5C */        NULL,           NULL,           NULL,           NULL,
13181 /* 60 */        NULL,           NULL,           NULL,           NULL,
13182 /* 64 */        NULL,           NULL,           NULL,           NULL,
13183 /* 68 */        NULL,           NULL,           NULL,           NULL,
13184 /* 6C */        NULL,           NULL,           NULL,           NULL,
13185 /* 70 */        NULL,           NULL,           NULL,           NULL,
13186 /* 74 */        NULL,           NULL,           NULL,           NULL,
13187 /* 78 */        NULL,           NULL,           NULL,           NULL,
13188 /* 7C */        NULL,           NULL,           NULL,           NULL,
13189 /* 80 */        NULL,           NULL,           NULL,           NULL,
13190 /* 84 */        NULL,           NULL,           NULL,           NULL,
13191 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13192 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13193 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13194 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13195 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13196 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13197 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13198 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13199 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13200 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13201 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13202 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13203 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13204 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13205 /* C0 */        NULL,           NULL,           NULL,           NULL,
13206 /* C4 */        NULL,           NULL,           NULL,           NULL,
13207 /* C8 */        NULL,           NULL,           NULL,           NULL,
13208 /* CC */        NULL,           NULL,           NULL,           NULL,
13209 /* D0 */        NULL,           NULL,           NULL,           NULL,
13210 /* D4 */        NULL,           NULL,           NULL,           NULL,
13211 /* D8 */        NULL,           NULL,           NULL,           NULL,
13212 /* DC */        NULL,           NULL,           NULL,           NULL,
13213 /* E0 */        NULL,           NULL,           NULL,           NULL,
13214 /* E4 */        NULL,           NULL,           NULL,           NULL,
13215 /* E8 */        NULL,           NULL,           NULL,           NULL,
13216 /* EC */        NULL,           NULL,           NULL,           NULL,
13217 /* F0 */        NULL,           NULL,           NULL,           NULL,
13218 /* F4 */        NULL,           NULL,           NULL,           NULL,
13219 /* F8 */        NULL,           NULL,           NULL,           NULL,
13220 /* FC */        NULL,           NULL,           NULL,           NULL,
13221 };
13222
13223 static bool
13224 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13225                 int sizeflag ATTRIBUTE_UNUSED)
13226 {
13227   const char *mnemonic;
13228
13229   if (!fetch_code (ins->info, ins->codep + 1))
13230     return false;
13231   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13232      place where an 8-bit immediate would normally go.  ie. the last
13233      byte of the instruction.  */
13234   ins->obufp = ins->mnemonicendp;
13235   mnemonic = Suffix3DNow[*ins->codep++];
13236   if (mnemonic)
13237     ins->obufp = stpcpy (ins->obufp, mnemonic);
13238   else
13239     {
13240       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13241          of the opcode (0x0f0f) and the opcode suffix, we need to do
13242          all the ins->modrm processing first, and don't know until now that
13243          we have a bad opcode.  This necessitates some cleaning up.  */
13244       ins->op_out[0][0] = '\0';
13245       ins->op_out[1][0] = '\0';
13246       BadOp (ins);
13247     }
13248   ins->mnemonicendp = ins->obufp;
13249   return true;
13250 }
13251
13252 static const struct op simd_cmp_op[] =
13253 {
13254   { STRING_COMMA_LEN ("eq") },
13255   { STRING_COMMA_LEN ("lt") },
13256   { STRING_COMMA_LEN ("le") },
13257   { STRING_COMMA_LEN ("unord") },
13258   { STRING_COMMA_LEN ("neq") },
13259   { STRING_COMMA_LEN ("nlt") },
13260   { STRING_COMMA_LEN ("nle") },
13261   { STRING_COMMA_LEN ("ord") }
13262 };
13263
13264 static const struct op vex_cmp_op[] =
13265 {
13266   { STRING_COMMA_LEN ("eq_uq") },
13267   { STRING_COMMA_LEN ("nge") },
13268   { STRING_COMMA_LEN ("ngt") },
13269   { STRING_COMMA_LEN ("false") },
13270   { STRING_COMMA_LEN ("neq_oq") },
13271   { STRING_COMMA_LEN ("ge") },
13272   { STRING_COMMA_LEN ("gt") },
13273   { STRING_COMMA_LEN ("true") },
13274   { STRING_COMMA_LEN ("eq_os") },
13275   { STRING_COMMA_LEN ("lt_oq") },
13276   { STRING_COMMA_LEN ("le_oq") },
13277   { STRING_COMMA_LEN ("unord_s") },
13278   { STRING_COMMA_LEN ("neq_us") },
13279   { STRING_COMMA_LEN ("nlt_uq") },
13280   { STRING_COMMA_LEN ("nle_uq") },
13281   { STRING_COMMA_LEN ("ord_s") },
13282   { STRING_COMMA_LEN ("eq_us") },
13283   { STRING_COMMA_LEN ("nge_uq") },
13284   { STRING_COMMA_LEN ("ngt_uq") },
13285   { STRING_COMMA_LEN ("false_os") },
13286   { STRING_COMMA_LEN ("neq_os") },
13287   { STRING_COMMA_LEN ("ge_oq") },
13288   { STRING_COMMA_LEN ("gt_oq") },
13289   { STRING_COMMA_LEN ("true_us") },
13290 };
13291
13292 static bool
13293 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13294            int sizeflag ATTRIBUTE_UNUSED)
13295 {
13296   unsigned int cmp_type;
13297
13298   if (!fetch_code (ins->info, ins->codep + 1))
13299     return false;
13300   cmp_type = *ins->codep++;
13301   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13302     {
13303       char suffix[3];
13304       char *p = ins->mnemonicendp - 2;
13305       suffix[0] = p[0];
13306       suffix[1] = p[1];
13307       suffix[2] = '\0';
13308       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13309       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13310     }
13311   else if (ins->need_vex
13312            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13313     {
13314       char suffix[3];
13315       char *p = ins->mnemonicendp - 2;
13316       suffix[0] = p[0];
13317       suffix[1] = p[1];
13318       suffix[2] = '\0';
13319       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13320       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13321       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13322     }
13323   else
13324     {
13325       /* We have a reserved extension byte.  Output it directly.  */
13326       oappend_immediate (ins, cmp_type);
13327     }
13328   return true;
13329 }
13330
13331 static bool
13332 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13333 {
13334   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13335   if (!ins->intel_syntax)
13336     {
13337       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13338       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13339       if (bytemode == eBX_reg)
13340         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13341       ins->two_source_ops = true;
13342     }
13343   /* Skip mod/rm byte.  */
13344   MODRM_CHECK;
13345   ins->codep++;
13346   return true;
13347 }
13348
13349 static bool
13350 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13351             int sizeflag ATTRIBUTE_UNUSED)
13352 {
13353   /* monitor %{e,r,}ax,%ecx,%edx"  */
13354   if (!ins->intel_syntax)
13355     {
13356       const char (*names)[8] = (ins->address_mode == mode_64bit
13357                                 ? att_names64 : att_names32);
13358
13359       if (ins->prefixes & PREFIX_ADDR)
13360         {
13361           /* Remove "addr16/addr32".  */
13362           ins->all_prefixes[ins->last_addr_prefix] = 0;
13363           names = (ins->address_mode != mode_32bit
13364                    ? att_names32 : att_names16);
13365           ins->used_prefixes |= PREFIX_ADDR;
13366         }
13367       else if (ins->address_mode == mode_16bit)
13368         names = att_names16;
13369       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13370       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13371       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13372       ins->two_source_ops = true;
13373     }
13374   /* Skip mod/rm byte.  */
13375   MODRM_CHECK;
13376   ins->codep++;
13377   return true;
13378 }
13379
13380 static bool
13381 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13382 {
13383   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13384      lods and stos.  */
13385   if (ins->prefixes & PREFIX_REPZ)
13386     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13387
13388   switch (bytemode)
13389     {
13390     case al_reg:
13391     case eAX_reg:
13392     case indir_dx_reg:
13393       return OP_IMREG (ins, bytemode, sizeflag);
13394     case eDI_reg:
13395       return OP_ESreg (ins, bytemode, sizeflag);
13396     case eSI_reg:
13397       return OP_DSreg (ins, bytemode, sizeflag);
13398     default:
13399       abort ();
13400       break;
13401     }
13402   return true;
13403 }
13404
13405 static bool
13406 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13407            int sizeflag ATTRIBUTE_UNUSED)
13408 {
13409   if (ins->isa64 != amd64)
13410     return true;
13411
13412   ins->obufp = ins->obuf;
13413   BadOp (ins);
13414   ins->mnemonicendp = ins->obufp;
13415   ++ins->codep;
13416   return true;
13417 }
13418
13419 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13420    "bnd".  */
13421
13422 static bool
13423 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13424            int sizeflag ATTRIBUTE_UNUSED)
13425 {
13426   if (ins->prefixes & PREFIX_REPNZ)
13427     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13428   return true;
13429 }
13430
13431 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13432    "notrack".  */
13433
13434 static bool
13435 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13436                int sizeflag ATTRIBUTE_UNUSED)
13437 {
13438   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13439      we've seen a PREFIX_DS.  */
13440   if ((ins->prefixes & PREFIX_DS) != 0
13441       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13442     {
13443       /* NOTRACK prefix is only valid on indirect branch instructions.
13444          NB: DATA prefix is unsupported for Intel64.  */
13445       ins->active_seg_prefix = 0;
13446       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13447     }
13448   return true;
13449 }
13450
13451 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13452    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13453  */
13454
13455 static bool
13456 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13457 {
13458   if (ins->modrm.mod != 3
13459       && (ins->prefixes & PREFIX_LOCK) != 0)
13460     {
13461       if (ins->prefixes & PREFIX_REPZ)
13462         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13463       if (ins->prefixes & PREFIX_REPNZ)
13464         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13465     }
13466
13467   return OP_E (ins, bytemode, sizeflag);
13468 }
13469
13470 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13471    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13472  */
13473
13474 static bool
13475 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13476 {
13477   if (ins->modrm.mod != 3)
13478     {
13479       if (ins->prefixes & PREFIX_REPZ)
13480         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13481       if (ins->prefixes & PREFIX_REPNZ)
13482         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13483     }
13484
13485   return OP_E (ins, bytemode, sizeflag);
13486 }
13487
13488 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13489    "xrelease" for memory operand.  No check for LOCK prefix.   */
13490
13491 static bool
13492 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13493 {
13494   if (ins->modrm.mod != 3
13495       && ins->last_repz_prefix > ins->last_repnz_prefix
13496       && (ins->prefixes & PREFIX_REPZ) != 0)
13497     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13498
13499   return OP_E (ins, bytemode, sizeflag);
13500 }
13501
13502 static bool
13503 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13504 {
13505   USED_REX (REX_W);
13506   if (ins->rex & REX_W)
13507     {
13508       /* Change cmpxchg8b to cmpxchg16b.  */
13509       char *p = ins->mnemonicendp - 2;
13510       ins->mnemonicendp = stpcpy (p, "16b");
13511       bytemode = o_mode;
13512     }
13513   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13514     {
13515       if (ins->prefixes & PREFIX_REPZ)
13516         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13517       if (ins->prefixes & PREFIX_REPNZ)
13518         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13519     }
13520
13521   return OP_M (ins, bytemode, sizeflag);
13522 }
13523
13524 static bool
13525 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13526 {
13527   const char (*names)[8] = att_names_xmm;
13528
13529   if (ins->need_vex)
13530     {
13531       switch (ins->vex.length)
13532         {
13533         case 128:
13534           break;
13535         case 256:
13536           names = att_names_ymm;
13537           break;
13538         default:
13539           abort ();
13540         }
13541     }
13542   oappend_register (ins, names[reg]);
13543   return true;
13544 }
13545
13546 static bool
13547 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13548 {
13549   /* Add proper suffix to "fxsave" and "fxrstor".  */
13550   USED_REX (REX_W);
13551   if (ins->rex & REX_W)
13552     {
13553       char *p = ins->mnemonicendp;
13554       *p++ = '6';
13555       *p++ = '4';
13556       *p = '\0';
13557       ins->mnemonicendp = p;
13558     }
13559   return OP_M (ins, bytemode, sizeflag);
13560 }
13561
13562 /* Display the destination register operand for instructions with
13563    VEX. */
13564
13565 static bool
13566 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13567 {
13568   int reg, modrm_reg, sib_index = -1;
13569   const char (*names)[8];
13570
13571   if (!ins->need_vex)
13572     return true;
13573
13574   if (ins->evex_type == evex_from_legacy)
13575     {
13576       ins->evex_used |= EVEX_b_used;
13577       if (!ins->vex.nd)
13578         return true;
13579     }
13580
13581   reg = ins->vex.register_specifier;
13582   ins->vex.register_specifier = 0;
13583   if (ins->address_mode != mode_64bit)
13584     {
13585       if (ins->vex.evex && !ins->vex.v)
13586         {
13587           oappend (ins, "(bad)");
13588           return true;
13589         }
13590
13591       reg &= 7;
13592     }
13593   else if (ins->vex.evex && !ins->vex.v)
13594     reg += 16;
13595
13596   switch (bytemode)
13597     {
13598     case scalar_mode:
13599       oappend_register (ins, att_names_xmm[reg]);
13600       return true;
13601
13602     case vex_vsib_d_w_dq_mode:
13603     case vex_vsib_q_w_dq_mode:
13604       /* This must be the 3rd operand.  */
13605       if (ins->obufp != ins->op_out[2])
13606         abort ();
13607       if (ins->vex.length == 128
13608           || (bytemode != vex_vsib_d_w_dq_mode
13609               && !ins->vex.w))
13610         oappend_register (ins, att_names_xmm[reg]);
13611       else
13612         oappend_register (ins, att_names_ymm[reg]);
13613
13614       /* All 3 XMM/YMM registers must be distinct.  */
13615       modrm_reg = ins->modrm.reg;
13616       if (ins->rex & REX_R)
13617         modrm_reg += 8;
13618
13619       if (ins->has_sib && ins->modrm.rm == 4)
13620         {
13621           sib_index = ins->sib.index;
13622           if (ins->rex & REX_X)
13623             sib_index += 8;
13624         }
13625
13626       if (reg == modrm_reg || reg == sib_index)
13627         strcpy (ins->obufp, "/(bad)");
13628       if (modrm_reg == sib_index || modrm_reg == reg)
13629         strcat (ins->op_out[0], "/(bad)");
13630       if (sib_index == modrm_reg || sib_index == reg)
13631         strcat (ins->op_out[1], "/(bad)");
13632
13633       return true;
13634
13635     case tmm_mode:
13636       /* All 3 TMM registers must be distinct.  */
13637       if (reg >= 8)
13638         oappend (ins, "(bad)");
13639       else
13640         {
13641           /* This must be the 3rd operand.  */
13642           if (ins->obufp != ins->op_out[2])
13643             abort ();
13644           oappend_register (ins, att_names_tmm[reg]);
13645           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13646             strcpy (ins->obufp, "/(bad)");
13647         }
13648
13649       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13650           || ins->modrm.rm == reg)
13651         {
13652           if (ins->modrm.reg <= 8
13653               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13654             strcat (ins->op_out[0], "/(bad)");
13655           if (ins->modrm.rm <= 8
13656               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13657             strcat (ins->op_out[1], "/(bad)");
13658         }
13659
13660       return true;
13661     }
13662
13663   switch (ins->vex.length)
13664     {
13665     case 128:
13666       switch (bytemode)
13667         {
13668         case x_mode:
13669           names = att_names_xmm;
13670           ins->evex_used |= EVEX_len_used;
13671           break;
13672         case v_mode:
13673         case dq_mode:
13674           if (ins->rex & REX_W)
13675             names = att_names64;
13676           else if (bytemode == v_mode
13677                    && !(sizeflag & DFLAG))
13678             names = att_names16;
13679           else
13680             names = att_names32;
13681           break;
13682         case b_mode:
13683           names = att_names8rex;
13684           break;
13685         case q_mode:
13686           names = att_names64;
13687           break;
13688         case mask_bd_mode:
13689         case mask_mode:
13690           if (reg > 0x7)
13691             {
13692               oappend (ins, "(bad)");
13693               return true;
13694             }
13695           names = att_names_mask;
13696           break;
13697         default:
13698           abort ();
13699           return true;
13700         }
13701       break;
13702     case 256:
13703       switch (bytemode)
13704         {
13705         case x_mode:
13706           names = att_names_ymm;
13707           ins->evex_used |= EVEX_len_used;
13708           break;
13709         case mask_bd_mode:
13710         case mask_mode:
13711           if (reg <= 0x7)
13712             {
13713               names = att_names_mask;
13714               break;
13715             }
13716           /* Fall through.  */
13717         default:
13718           /* See PR binutils/20893 for a reproducer.  */
13719           oappend (ins, "(bad)");
13720           return true;
13721         }
13722       break;
13723     case 512:
13724       names = att_names_zmm;
13725       ins->evex_used |= EVEX_len_used;
13726       break;
13727     default:
13728       abort ();
13729       break;
13730     }
13731   oappend_register (ins, names[reg]);
13732   return true;
13733 }
13734
13735 static bool
13736 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13737 {
13738   if (ins->modrm.mod == 3)
13739     return OP_VEX (ins, bytemode, sizeflag);
13740   return true;
13741 }
13742
13743 static bool
13744 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13745 {
13746   OP_VEX (ins, bytemode, sizeflag);
13747
13748   if (ins->vex.w)
13749     {
13750       /* Swap 2nd and 3rd operands.  */
13751       char *tmp = ins->op_out[2];
13752
13753       ins->op_out[2] = ins->op_out[1];
13754       ins->op_out[1] = tmp;
13755     }
13756   return true;
13757 }
13758
13759 static bool
13760 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13761 {
13762   int reg;
13763   const char (*names)[8] = att_names_xmm;
13764
13765   if (!fetch_code (ins->info, ins->codep + 1))
13766     return false;
13767   reg = *ins->codep++;
13768
13769   if (bytemode != x_mode && bytemode != scalar_mode)
13770     abort ();
13771
13772   reg >>= 4;
13773   if (ins->address_mode != mode_64bit)
13774     reg &= 7;
13775
13776   if (bytemode == x_mode && ins->vex.length == 256)
13777     names = att_names_ymm;
13778
13779   oappend_register (ins, names[reg]);
13780
13781   if (ins->vex.w)
13782     {
13783       /* Swap 3rd and 4th operands.  */
13784       char *tmp = ins->op_out[3];
13785
13786       ins->op_out[3] = ins->op_out[2];
13787       ins->op_out[2] = tmp;
13788     }
13789   return true;
13790 }
13791
13792 static bool
13793 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13794           int sizeflag ATTRIBUTE_UNUSED)
13795 {
13796   oappend_immediate (ins, ins->codep[-1] & 0xf);
13797   return true;
13798 }
13799
13800 static bool
13801 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13802              int sizeflag ATTRIBUTE_UNUSED)
13803 {
13804   unsigned int cmp_type;
13805
13806   if (!ins->vex.evex)
13807     abort ();
13808
13809   if (!fetch_code (ins->info, ins->codep + 1))
13810     return false;
13811   cmp_type = *ins->codep++;
13812   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13813      If it's the case, print suffix, otherwise - print the immediate.  */
13814   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13815       && cmp_type != 3
13816       && cmp_type != 7)
13817     {
13818       char suffix[3];
13819       char *p = ins->mnemonicendp - 2;
13820
13821       /* vpcmp* can have both one- and two-lettered suffix.  */
13822       if (p[0] == 'p')
13823         {
13824           p++;
13825           suffix[0] = p[0];
13826           suffix[1] = '\0';
13827         }
13828       else
13829         {
13830           suffix[0] = p[0];
13831           suffix[1] = p[1];
13832           suffix[2] = '\0';
13833         }
13834
13835       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13836       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13837     }
13838   else
13839     {
13840       /* We have a reserved extension byte.  Output it directly.  */
13841       oappend_immediate (ins, cmp_type);
13842     }
13843   return true;
13844 }
13845
13846 static const struct op xop_cmp_op[] =
13847 {
13848   { STRING_COMMA_LEN ("lt") },
13849   { STRING_COMMA_LEN ("le") },
13850   { STRING_COMMA_LEN ("gt") },
13851   { STRING_COMMA_LEN ("ge") },
13852   { STRING_COMMA_LEN ("eq") },
13853   { STRING_COMMA_LEN ("neq") },
13854   { STRING_COMMA_LEN ("false") },
13855   { STRING_COMMA_LEN ("true") }
13856 };
13857
13858 static bool
13859 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13860              int sizeflag ATTRIBUTE_UNUSED)
13861 {
13862   unsigned int cmp_type;
13863
13864   if (!fetch_code (ins->info, ins->codep + 1))
13865     return false;
13866   cmp_type = *ins->codep++;
13867   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13868     {
13869       char suffix[3];
13870       char *p = ins->mnemonicendp - 2;
13871
13872       /* vpcom* can have both one- and two-lettered suffix.  */
13873       if (p[0] == 'm')
13874         {
13875           p++;
13876           suffix[0] = p[0];
13877           suffix[1] = '\0';
13878         }
13879       else
13880         {
13881           suffix[0] = p[0];
13882           suffix[1] = p[1];
13883           suffix[2] = '\0';
13884         }
13885
13886       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13887       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13888     }
13889   else
13890     {
13891       /* We have a reserved extension byte.  Output it directly.  */
13892       oappend_immediate (ins, cmp_type);
13893     }
13894   return true;
13895 }
13896
13897 static const struct op pclmul_op[] =
13898 {
13899   { STRING_COMMA_LEN ("lql") },
13900   { STRING_COMMA_LEN ("hql") },
13901   { STRING_COMMA_LEN ("lqh") },
13902   { STRING_COMMA_LEN ("hqh") }
13903 };
13904
13905 static bool
13906 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13907               int sizeflag ATTRIBUTE_UNUSED)
13908 {
13909   unsigned int pclmul_type;
13910
13911   if (!fetch_code (ins->info, ins->codep + 1))
13912     return false;
13913   pclmul_type = *ins->codep++;
13914   switch (pclmul_type)
13915     {
13916     case 0x10:
13917       pclmul_type = 2;
13918       break;
13919     case 0x11:
13920       pclmul_type = 3;
13921       break;
13922     default:
13923       break;
13924     }
13925   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13926     {
13927       char suffix[4];
13928       char *p = ins->mnemonicendp - 3;
13929       suffix[0] = p[0];
13930       suffix[1] = p[1];
13931       suffix[2] = p[2];
13932       suffix[3] = '\0';
13933       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13934       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13935     }
13936   else
13937     {
13938       /* We have a reserved extension byte.  Output it directly.  */
13939       oappend_immediate (ins, pclmul_type);
13940     }
13941   return true;
13942 }
13943
13944 static bool
13945 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13946 {
13947   /* Add proper suffix to "movsxd".  */
13948   char *p = ins->mnemonicendp;
13949
13950   switch (bytemode)
13951     {
13952     case movsxd_mode:
13953       if (!ins->intel_syntax)
13954         {
13955           USED_REX (REX_W);
13956           if (ins->rex & REX_W)
13957             {
13958               *p++ = 'l';
13959               *p++ = 'q';
13960               break;
13961             }
13962         }
13963
13964       *p++ = 'x';
13965       *p++ = 'd';
13966       break;
13967     default:
13968       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13969       break;
13970     }
13971
13972   ins->mnemonicendp = p;
13973   *p = '\0';
13974   return OP_E (ins, bytemode, sizeflag);
13975 }
13976
13977 static bool
13978 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13979 {
13980   unsigned int reg = ins->vex.register_specifier;
13981   unsigned int modrm_reg = ins->modrm.reg;
13982   unsigned int modrm_rm = ins->modrm.rm;
13983
13984   /* Calc destination register number.  */
13985   if (ins->rex & REX_R)
13986     modrm_reg += 8;
13987   if (ins->rex2 & REX_R)
13988     modrm_reg += 16;
13989
13990   /* Calc src1 register number.  */
13991   if (ins->address_mode != mode_64bit)
13992     reg &= 7;
13993   else if (ins->vex.evex && !ins->vex.v)
13994     reg += 16;
13995
13996   /* Calc src2 register number.  */
13997   if (ins->modrm.mod == 3)
13998     {
13999       if (ins->rex & REX_B)
14000         modrm_rm += 8;
14001       if (ins->rex & REX_X)
14002         modrm_rm += 16;
14003     }
14004
14005   /* Destination and source registers must be distinct, output bad if
14006      dest == src1 or dest == src2.  */
14007   if (modrm_reg == reg
14008       || (ins->modrm.mod == 3
14009           && modrm_reg == modrm_rm))
14010     {
14011       oappend (ins, "(bad)");
14012       return true;
14013     }
14014   return OP_XMM (ins, bytemode, sizeflag);
14015 }
14016
14017 static bool
14018 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14019 {
14020   if (ins->modrm.mod != 3 || !ins->vex.b)
14021     return true;
14022
14023   switch (bytemode)
14024     {
14025     case evex_rounding_64_mode:
14026       if (ins->address_mode != mode_64bit || !ins->vex.w)
14027         return true;
14028       /* Fall through.  */
14029     case evex_rounding_mode:
14030       ins->evex_used |= EVEX_b_used;
14031       oappend (ins, names_rounding[ins->vex.ll]);
14032       break;
14033     case evex_sae_mode:
14034       ins->evex_used |= EVEX_b_used;
14035       oappend (ins, "{");
14036       break;
14037     default:
14038       abort ();
14039     }
14040   oappend (ins, "sae}");
14041   return true;
14042 }
14043
14044 static bool
14045 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14046 {
14047   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14048     {
14049       if (ins->intel_syntax)
14050         {
14051           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
14052         }
14053       else
14054         {
14055           USED_REX (REX_W);
14056           if (ins->rex & REX_W)
14057             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
14058           else
14059             {
14060               if (sizeflag & DFLAG)
14061                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
14062               else
14063                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14064               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14065             }
14066         }
14067       bytemode = v_mode;
14068     }
14069
14070   return OP_M (ins, bytemode, sizeflag);
14071 }
14072
14073 static bool
14074 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14075 {
14076   if (ins->modrm.mod != 3)
14077     return true;
14078
14079   unsigned int vvvv_reg = ins->vex.register_specifier
14080     | (!ins->vex.v << 4);
14081   unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14082     + (ins->rex2 & REX_B ? 16 : 0);
14083
14084   /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers.  */
14085   if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14086       || (!ins->modrm.reg
14087           && vvvv_reg == rm_reg))
14088     {
14089       oappend (ins, "(bad)");
14090       return true;
14091     }
14092
14093   return OP_VEX (ins, bytemode, sizeflag);
14094 }
14095
14096 static bool
14097 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14098 {
14099   if (ins->last_rex2_prefix >= 0)
14100     {
14101       uint64_t op;
14102
14103       if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14104           || (ins->rex & REX_W) != 0x0)
14105         {
14106           oappend (ins, "(bad)");
14107           return true;
14108         }
14109
14110       if (bytemode == eAX_reg)
14111         return true;
14112
14113       if (!get64 (ins, &op))
14114         return false;
14115
14116       ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14117       ins->rex2 |= REX2_SPECIAL;
14118       oappend_immediate (ins, op);
14119
14120       return true;
14121     }
14122
14123   if (bytemode == eAX_reg)
14124     return OP_IMREG (ins, bytemode, sizeflag);
14125   return OP_OFF64 (ins, bytemode, sizeflag);
14126 }
14127
14128 static bool
14129 CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag)
14130 {
14131   /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the
14132      source and destination operands.  */
14133   bool dstmem = !ins->vex.nd && ins->vex.nf;
14134
14135   if (opnd == 0)
14136     {
14137       if (dstmem)
14138         return OP_E (ins, v_swap_mode, sizeflag);
14139       return OP_G (ins, v_mode, sizeflag);
14140     }
14141
14142   /* These bits have been consumed and should be cleared.  */
14143   ins->vex.nf = false;
14144   ins->vex.mask_register_specifier = 0;
14145
14146   if (dstmem)
14147     return OP_G (ins, v_mode, sizeflag);
14148   return OP_E (ins, v_mode, sizeflag);
14149 }