| blob | 2cb8768868b30ce1a228f8bd73e4e416b9de4b9b |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2021 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bool
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bool
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bool
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2505 {
2506 /* First bundle: */
2511 /* Second bundle: */
2516 /* Third bundle: */
2520 /* .Lplt_tail: */
2522 /* Fourth bundle: */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2530 /* Subsequent entries in a procedure linkage table look like this. */
2532 {
2537 };
2539 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2540 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2541 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2542 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2543 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2544 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2545 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2546 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2548 enum stub_insn_type
2549 {
2551 THUMB32_TYPE,
2552 ARM_TYPE,
2553 DATA_TYPE
2554 };
2556 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2557 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2558 is inserted in arm_build_one_stub(). */
2559 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2560 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2561 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2562 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2563 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2564 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2565 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2566 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2569 {
2570 bfd_vma data;
2576 /* See note [Thumb nop sequence] when adding a veneer. */
2578 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2579 to reach the stub if necessary. */
2581 {
2584 };
2586 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2587 available. */
2589 {
2593 };
2595 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2597 {
2605 };
2607 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2609 {
2612 };
2614 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2615 M-profile architectures. */
2617 {
2621 };
2623 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2624 allowed. */
2626 {
2632 };
2634 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2635 available. */
2637 {
2642 };
2644 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2645 one, when the destination is close enough. */
2647 {
2651 };
2653 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2654 blx to reach the stub if necessary. */
2656 {
2660 };
2662 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2663 blx to reach the stub if necessary. We can not add into pc;
2664 it is not guaranteed to mode switch (different in ARMv6 and
2665 ARMv7). */
2667 {
2672 };
2674 /* V4T ARM -> ARM long branch stub, PIC. */
2676 {
2681 };
2683 /* V4T Thumb -> ARM long branch stub, PIC. */
2685 {
2691 };
2693 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2694 architectures. */
2696 {
2704 };
2706 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2707 allowed. */
2709 {
2716 };
2718 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2719 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2721 {
2725 };
2727 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2728 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2730 {
2736 };
2738 /* NaCl ARM -> ARM long branch stub. */
2740 {
2749 };
2751 /* NaCl ARM -> ARM long branch stub, PIC. */
2753 {
2762 };
2764 /* Stub used for transition to secure state (aka SG veneer). */
2766 {
2769 };
2772 /* Cortex-A8 erratum-workaround stubs. */
2774 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2775 can't use a conditional branch to reach this stub). */
2778 {
2782 };
2784 /* Stub used for b.w and bl.w instructions. */
2787 {
2789 };
2792 {
2794 };
2796 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2797 instruction (which switches to ARM mode) to point to this stub. Jump to the
2798 real destination using an ARM-mode branch. */
2801 {
2803 };
2805 /* For each section group there can be a specially created linker section
2806 to hold the stubs for that group. The name of the stub section is based
2807 upon the name of another section within that group with the suffix below
2808 applied.
2810 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2811 create what appeared to be a linker stub section when it actually
2812 contained user code/data. For example, consider this fragment:
2814 const char * stubborn_problems[] = { "np" };
2816 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2817 section called:
2819 .data.rel.local.stubborn_problems
2821 This then causes problems in arm32_arm_build_stubs() as it triggers:
2823 // Ignore non-stub sections.
2824 if (!strstr (stub_sec->name, STUB_SUFFIX))
2825 continue;
2827 And so the section would be ignored instead of being processed. Hence
2828 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2829 C identifier. */
2832 /* One entry per long/short branch stub defined above. */
2833 #define DEF_STUBS \
2834 DEF_STUB (long_branch_any_any) \
2835 DEF_STUB (long_branch_v4t_arm_thumb) \
2836 DEF_STUB (long_branch_thumb_only) \
2837 DEF_STUB (long_branch_v4t_thumb_thumb) \
2838 DEF_STUB (long_branch_v4t_thumb_arm) \
2839 DEF_STUB (short_branch_v4t_thumb_arm) \
2840 DEF_STUB (long_branch_any_arm_pic) \
2841 DEF_STUB (long_branch_any_thumb_pic) \
2842 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2843 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2844 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2845 DEF_STUB (long_branch_thumb_only_pic) \
2846 DEF_STUB (long_branch_any_tls_pic) \
2847 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2848 DEF_STUB (long_branch_arm_nacl) \
2849 DEF_STUB (long_branch_arm_nacl_pic) \
2850 DEF_STUB (cmse_branch_thumb_only) \
2851 DEF_STUB (a8_veneer_b_cond) \
2852 DEF_STUB (a8_veneer_b) \
2853 DEF_STUB (a8_veneer_bl) \
2854 DEF_STUB (a8_veneer_blx) \
2855 DEF_STUB (long_branch_thumb2_only) \
2856 DEF_STUB (long_branch_thumb2_only_pure)
2858 #define DEF_STUB(x) arm_stub_##x,
2859 enum elf32_arm_stub_type
2860 {
2861 arm_stub_none,
2862 DEF_STUBS
2863 max_stub_type
2864 };
2865 #undef DEF_STUB
2867 /* Note the first a8_veneer type. */
2871 {
2876 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2878 {
2880 DEF_STUBS
2881 };
2883 struct elf32_arm_stub_hash_entry
2884 {
2885 /* Base hash table entry structure. */
2888 /* The stub section. */
2891 /* Offset within stub_sec of the beginning of this stub. */
2892 bfd_vma stub_offset;
2894 /* Given the symbol's value and its section we can determine its final
2895 value when building the stubs (so the stub knows where to jump). */
2896 bfd_vma target_value;
2899 /* Same as above but for the source of the branch to the stub. Used for
2900 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2901 such, source section does not need to be recorded since Cortex-A8 erratum
2902 workaround stubs are only generated when both source and target are in the
2903 same section. */
2904 bfd_vma source_value;
2906 /* The instruction which caused this stub to be generated (only valid for
2907 Cortex-A8 erratum workaround stubs at present). */
2910 /* The stub type. */
2912 /* Its encoding size in bytes. */
2914 /* Its template. */
2916 /* The size of the template (number of entries). */
2919 /* The symbol table entry, if any, that this was derived from. */
2922 /* Type of branch. */
2925 /* Where this stub is being called from, or, in the case of combined
2926 stub sections, the first input section in the group. */
2929 /* The name for the local symbol at the start of this stub. The
2930 stub name in the hash table has to be unique; this does not, so
2931 it can be friendlier. */
2933 };
2935 /* Used to build a map of a section. This is required for mixed-endian
2936 code/data. */
2939 {
2940 bfd_vma vma;
2942 }
2943 elf32_arm_section_map;
2945 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2948 {
2949 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2950 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2951 VFP11_ERRATUM_ARM_VENEER,
2952 VFP11_ERRATUM_THUMB_VENEER
2953 }
2954 elf32_vfp11_erratum_type;
2957 {
2959 bfd_vma vma;
2960 union
2961 {
2962 struct
2963 {
2967 struct
2968 {
2973 elf32_vfp11_erratum_type type;
2974 }
2975 elf32_vfp11_erratum_list;
2977 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2978 veneer. */
2980 {
2981 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2982 STM32L4XX_ERRATUM_VENEER
2983 }
2984 elf32_stm32l4xx_erratum_type;
2987 {
2989 bfd_vma vma;
2990 union
2991 {
2992 struct
2993 {
2997 struct
2998 {
3003 elf32_stm32l4xx_erratum_type type;
3004 }
3005 elf32_stm32l4xx_erratum_list;
3008 {
3009 DELETE_EXIDX_ENTRY,
3010 INSERT_EXIDX_CANTUNWIND_AT_END
3011 }
3012 arm_unwind_edit_type;
3014 /* A (sorted) list of edits to apply to an unwind table. */
3016 {
3017 arm_unwind_edit_type type;
3018 /* Note: we sometimes want to insert an unwind entry corresponding to a
3019 section different from the one we're currently writing out, so record the
3020 (text) section this edit relates to here. */
3024 }
3025 arm_unwind_table_edit;
3028 {
3029 /* Information about mapping symbols. */
3034 /* Information about CPU errata. */
3040 /* Information about unwind tables. */
3041 union
3042 {
3043 /* Unwind info attached to a text section. */
3044 struct
3045 {
3049 /* Unwind info attached to an .ARM.exidx section. */
3050 struct
3051 {
3056 }
3057 _arm_elf_section_data;
3059 #define elf32_arm_section_data(sec) \
3060 ((_arm_elf_section_data *) elf_section_data (sec))
3062 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3063 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3064 so may be created multiple times: we use an array of these entries whilst
3065 relaxing which we can refresh easily, then create stubs for each potentially
3066 erratum-triggering instruction once we've settled on a solution. */
3068 struct a8_erratum_fix
3069 {
3072 bfd_vma offset;
3073 bfd_vma target_offset;
3078 };
3080 /* A table of relocs applied to branches which might trigger Cortex-A8
3081 erratum. */
3083 struct a8_erratum_reloc
3084 {
3085 bfd_vma from;
3086 bfd_vma destination;
3092 };
3094 /* The size of the thread control block. */
3095 #define TCB_SIZE 8
3097 /* ARM-specific information about a PLT entry, over and above the usual
3098 gotplt_union. */
3099 struct arm_plt_info
3100 {
3101 /* We reference count Thumb references to a PLT entry separately,
3102 so that we can emit the Thumb trampoline only if needed. */
3103 bfd_signed_vma thumb_refcount;
3105 /* Some references from Thumb code may be eliminated by BL->BLX
3106 conversion, so record them separately. */
3107 bfd_signed_vma maybe_thumb_refcount;
3109 /* How many of the recorded PLT accesses were from non-call relocations.
3110 This information is useful when deciding whether anything takes the
3111 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3112 non-call references to the function should resolve directly to the
3113 real runtime target. */
3116 /* Since PLT entries have variable size if the Thumb prologue is
3117 used, we need to record the index into .got.plt instead of
3118 recomputing it from the PLT offset. */
3119 bfd_signed_vma got_offset;
3120 };
3122 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3123 struct arm_local_iplt_info
3124 {
3125 /* The information that is usually found in the generic ELF part of
3126 the hash table entry. */
3129 /* The information that is usually found in the ARM-specific part of
3130 the hash table entry. */
3133 /* A list of all potential dynamic relocations against this symbol. */
3135 };
3137 /* Structure to handle FDPIC support for local functions. */
3138 struct fdpic_local
3139 {
3143 };
3145 struct elf_arm_obj_tdata
3146 {
3149 /* Zero to warn when linking objects with incompatible enum sizes. */
3152 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3155 /* The number of entries in each of the arrays in this strcuture.
3156 Used to avoid buffer overruns. */
3157 bfd_size_type num_entries;
3159 /* tls_type for each local got entry. */
3162 /* GOTPLT entries for TLS descriptors. */
3165 /* Information for local symbols that need entries in .iplt. */
3168 /* Maintains FDPIC counters and funcdesc info. */
3170 };
3172 #define elf_arm_tdata(bfd) \
3173 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3175 #define elf32_arm_num_entries(bfd) \
3176 (elf_arm_tdata (bfd)->num_entries)
3178 #define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3181 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3184 #define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3187 #define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3190 #define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
3193 && elf_object_id (bfd) == ARM_ELF_DATA)
3195 static bool
3197 {
3199 ARM_ELF_DATA);
3200 }
3202 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3204 /* Structure to handle FDPIC support for extern functions. */
3211 };
3213 /* Arm ELF linker hash entry. */
3214 struct elf32_arm_link_hash_entry
3215 {
3218 /* ARM-specific PLT information. */
3221 #define GOT_UNKNOWN 0
3222 #define GOT_NORMAL 1
3223 #define GOT_TLS_GD 2
3224 #define GOT_TLS_IE 4
3225 #define GOT_TLS_GDESC 8
3226 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3242 /* A pointer to the most recently used stub hash entry against this
3243 symbol. */
3246 /* Counter for FDPIC relocations against this symbol. */
3248 };
3250 /* Traverse an arm ELF linker hash table. */
3251 #define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
3254 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3255 (info)))
3257 /* Get the ARM elf linker hash table from a link_info structure. */
3258 #define elf32_arm_hash_table(p) \
3259 ((is_elf_hash_table ((p)->hash) \
3260 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3261 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3263 #define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3267 /* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269 struct map_stub
3270 {
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3274 /* The stub section. */
3276 };
3278 #define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3281 /* ARM ELF linker hash table. */
3282 struct elf32_arm_link_hash_table
3283 {
3284 /* The main hash table. */
3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 /* Nonzero to output a BE8 image. */
3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
3345 /* Global counter for the number of fixes we have emitted. */
3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3352 /* Global counter for the number of fixes we have emitted. */
3355 /* Nonzero to force PIC branch veneers. */
3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
3364 /* True if the target uses REL relocations. */
3367 /* Nonzero if import library must be a secure gateway import library
3368 as per ARMv8-M Security Extensions. */
3371 /* The import library whose symbols' address must remain stable in
3372 the import library generated. */
3375 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3376 bfd_vma next_tls_desc_index;
3378 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3379 bfd_vma num_tls_desc;
3381 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3384 /* Offset in .plt section of tls_arm_trampoline. */
3385 bfd_vma tls_trampoline;
3387 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3388 union
3389 {
3390 bfd_signed_vma refcount;
3391 bfd_vma offset;
3394 /* For convenience in allocate_dynrelocs. */
3397 /* The amount of space used by the reserved portion of the sgotplt
3398 section, plus whatever space is used by the jump slots. */
3399 bfd_vma sgotplt_jump_table_size;
3401 /* The stub hash table. */
3404 /* Linker stub bfd. */
3407 /* Linker call-backs. */
3412 /* Array to keep track of which stub sections have been created, and
3413 information on stub grouping. */
3416 /* Input stub section holding secure gateway veneers. */
3419 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3420 start to be allocated. */
3421 bfd_vma new_cmse_stub_offset;
3423 /* Number of elements in stub_group. */
3426 /* Assorted information used by elf32_arm_size_stubs. */
3431 /* True if the target system uses FDPIC. */
3434 /* Fixup section. Used for FDPIC. */
3436 };
3438 /* Add an FDPIC read-only fixup. */
3439 static void
3441 {
3442 bfd_vma fixup_offset;
3447 }
3451 {
3452 #if GCC_VERSION >= 3004
3454 #else
3458 {
3462 }
3464 #endif
3465 }
3469 {
3470 #if GCC_VERSION >= 3004
3472 #else
3477 {
3479 sum++;
3481 }
3483 #endif
3484 }
3489 static void
3495 bfd_vma addr,
3496 bfd_vma dynreloc_value,
3497 bfd_vma seg)
3498 {
3500 {
3505 {
3507 Elf_Internal_Rela outrel;
3516 }
3517 else
3518 {
3532 }
3534 }
3535 }
3537 /* Create an entry in an ARM ELF linker hash table. */
3543 {
3547 /* Allocate the structure if it has not already been allocated by a
3548 subclass. */
3555 /* Call the allocation method of the superclass. */
3560 {
3577 }
3580 }
3582 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3583 symbols. */
3585 static bool
3587 {
3589 {
3590 bfd_size_type num_syms;
3594 /* Whilst it might be tempting to allocate a single block of memory and
3595 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3596 structure, this interferes with the work of memory checkers looking
3597 for buffer overruns. So allocate each array individually. */
3633 #if GCC_VERSION >= 3000
3642 #endif
3643 }
3645 }
3647 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3648 to input bfd ABFD. Create the information if it doesn't already exist.
3649 Return null if an allocation fails. */
3653 {
3665 }
3667 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3668 in ABFD's symbol table. If the symbol is global, H points to its
3669 hash table entry, otherwise H is null.
3671 Return true if the symbol does have PLT information. When returning
3672 true, point *ROOT_PLT at the target-independent reference count/offset
3673 union and *ARM_PLT at the ARM-specific information. */
3675 static bool
3680 {
3687 {
3691 }
3706 }
3710 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3711 before it. */
3713 static bool
3716 {
3723 }
3725 /* Return a pointer to the head of the dynamic reloc list that should
3726 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3727 ABFD's symbol table. Return null if an error occurs. */
3732 {
3734 {
3741 }
3742 else
3743 {
3744 /* Track dynamic relocs needed for local syms too.
3745 We really need local syms available to do this
3746 easily. Oh well. */
3756 }
3757 }
3759 /* Initialize an entry in the stub hash table. */
3765 {
3766 /* Allocate the structure if it has not already been allocated by a
3767 subclass. */
3769 {
3774 }
3776 /* Call the allocation method of the superclass. */
3779 {
3782 /* Initialize the local fields. */
3797 }
3800 }
3802 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3803 shortcuts to them in our hash table. */
3805 static bool
3807 {
3817 /* Also create .rofixup. */
3819 {
3826 }
3829 }
3831 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3833 static bool
3835 {
3840 flagword flags;
3848 {
3855 }
3858 {
3866 }
3869 {
3875 }
3877 }
3879 /* Determine if we're dealing with a Thumb only architecture. */
3881 static bool
3883 {
3886 Tag_CPU_arch_profile);
3893 /* Force return logic to be reviewed for each new architecture. */
3905 }
3907 /* Determine if we're dealing with a Thumb-2 object. */
3909 static bool
3911 {
3914 Tag_THUMB_ISA_use);
3916 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3920 /* Variant of thumb is described by the architecture tag. */
3923 /* Force return logic to be reviewed for each new architecture. */
3933 }
3935 /* Determine whether Thumb-2 BL instruction is available. */
3937 static bool
3939 {
3943 /* Force return logic to be reviewed for each new architecture. */
3946 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3949 }
3951 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3952 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3953 hash table. */
3955 static bool
3957 {
3971 {
3976 {
3978 htab->plt_entry_size
3980 }
3981 else
3982 {
3983 htab->plt_header_size
3985 htab->plt_entry_size
3987 }
3991 }
3992 else
3993 {
3994 /* PR ld/16017
3995 Test for thumb only architectures. Note - we cannot just call
3996 using_thumb_only() as the attributes in the output bfd have not been
3997 initialised at this point, so instead we use the input bfd. */
4002 {
4005 }
4007 }
4013 else
4015 }
4024 }
4026 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4028 static void
4032 {
4039 {
4040 /* Copy over PLT info. */
4048 /* Copy FDPIC counters. */
4053 /* We should only allocate a function to .iplt once the final
4054 symbol information is known. */
4058 {
4061 }
4062 }
4065 }
4067 /* Destroy an ARM elf linker hash table. */
4069 static void
4071 {
4077 }
4079 /* Create an ARM elf linker hash table. */
4083 {
4092 elf32_arm_link_hash_newfunc,
4094 ARM_ELF_DATA))
4095 {
4098 }
4102 #ifdef FOUR_WORD_PLT
4105 #else
4108 #endif
4115 {
4118 }
4122 }
4124 /* Determine what kind of NOPs are available. */
4126 static bool
4128 {
4130 Tag_CPU_arch);
4132 /* Force return logic to be reviewed for each new architecture. */
4140 }
4142 static bool
4144 {
4146 {
4163 }
4164 }
4166 /* Determine the type of stub needed, if any, for a call. */
4168 static enum elf32_arm_stub_type
4175 bfd_vma destination,
4179 {
4180 bfd_vma location;
4181 bfd_signed_vma branch_offset;
4206 /* True for architectures that implement the thumb2 movw instruction. */
4209 /* Determine where the call point is. */
4216 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4217 are considering a function call relocation. */
4223 /* For TLS call relocs, it is the caller's responsibility to provide
4224 the address of the appropriate trampoline. */
4231 {
4236 else
4239 {
4242 /* Note when dealing with PLT entries: the main PLT stub is in
4243 ARM mode, so if the branch is in Thumb mode, another
4244 Thumb->ARM stub will be inserted later just before the ARM
4245 PLT stub. If a long branch stub is needed, we'll add a
4246 Thumb->Arm one and branch directly to the ARM PLT entry.
4247 Here, we have to check if a pre-PLT Thumb->ARM stub
4248 is needed and if it will be close enough. */
4255 /* Thumb branch/call to PLT: it can become a branch to ARM
4256 or to Thumb. We must perform the same checks and
4257 corrections as in elf32_arm_final_link_relocate. */
4260 {
4264 {
4265 /* If the Thumb BLX instruction is available, convert
4266 the BL to a BLX instruction to call the ARM-mode
4267 PLT entry. */
4269 }
4270 else
4271 {
4273 /* Target the Thumb stub before the ARM PLT entry. */
4276 }
4277 }
4278 else
4279 {
4281 }
4282 }
4283 }
4284 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4291 {
4292 /* Handle cases where:
4293 - this call goes too far (different Thumb/Thumb2 max
4294 distance)
4295 - it's a Thumb->Arm call and blx is not available, or it's a
4296 Thumb->Arm branch (not bl). A stub is needed in this case,
4297 but only if this call is not through a PLT entry. Indeed,
4298 PLT stubs handle mode switching already. */
4302 || (thumb2_bl
4305 || (thumb2
4315 {
4316 /* If we need to insert a Thumb-Thumb long branch stub to a
4317 PLT, use one that branches directly to the ARM PLT
4318 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4319 stub, undo this now. */
4321 {
4324 }
4327 {
4328 /* Thumb to thumb. */
4330 {
4332 _bfd_error_handler
4334 " section with SHF_ARM_PURECODE section"
4335 " attribute is only supported for M-profile"
4340 /* PIC stubs. */
4343 /* V5T and above. Stub starts with ARM code, so
4344 we must be able to switch mode before
4345 reaching it, which is only possible for 'bl'
4346 (ie R_ARM_THM_CALL relocation). */
4347 ? arm_stub_long_branch_any_thumb_pic
4348 /* On V4T, use Thumb code only. */
4351 /* non-PIC stubs. */
4354 /* V5T and above. */
4355 ? arm_stub_long_branch_any_any
4356 /* V4T. */
4358 }
4359 else
4360 {
4363 else
4364 {
4366 _bfd_error_handler
4368 " section with SHF_ARM_PURECODE section"
4369 " attribute is only supported for M-profile"
4374 /* PIC stub. */
4375 ? arm_stub_long_branch_thumb_only_pic
4376 /* non-PIC stub. */
4379 }
4380 }
4381 }
4382 else
4383 {
4385 _bfd_error_handler
4387 " section with SHF_ARM_PURECODE section"
4392 /* Thumb to arm. */
4396 {
4397 _bfd_error_handler
4401 }
4403 stub_type =
4405 /* PIC stubs. */
4407 /* TLS PIC stubs. */
4411 /* V5T PIC and above. */
4412 ? arm_stub_long_branch_any_arm_pic
4413 /* V4T PIC stub. */
4416 /* non-PIC stubs. */
4418 /* V5T and above. */
4419 ? arm_stub_long_branch_any_any
4420 /* V4T. */
4423 /* Handle v4t short branches. */
4428 }
4429 }
4430 }
4435 {
4437 _bfd_error_handler
4439 " section with SHF_ARM_PURECODE section"
4440 " attribute is only supported for M-profile"
4444 {
4445 /* Arm to thumb. */
4450 {
4451 _bfd_error_handler
4455 }
4457 /* We have an extra 2-bytes reach because of
4458 the mode change (bit 24 (H) of BLX encoding). */
4464 {
4466 /* PIC stubs. */
4468 /* V5T and above. */
4469 ? arm_stub_long_branch_any_thumb_pic
4470 /* V4T stub. */
4473 /* non-PIC stubs. */
4475 /* V5T and above. */
4476 ? arm_stub_long_branch_any_any
4477 /* V4T. */
4479 }
4480 }
4481 else
4482 {
4483 /* Arm to arm. */
4486 {
4487 stub_type =
4489 /* PIC stubs. */
4491 /* TLS PIC Stub. */
4492 ? arm_stub_long_branch_any_tls_pic
4494 ? arm_stub_long_branch_arm_nacl_pic
4496 /* non-PIC stubs. */
4498 ? arm_stub_long_branch_arm_nacl
4500 }
4501 }
4502 }
4504 /* If a stub is needed, record the actual destination type. */
4509 }
4511 /* Build a name for an entry in the stub hash table. */
4519 {
4521 bfd_size_type len;
4524 {
4533 }
4534 else
4535 {
4547 }
4550 }
4552 /* Look up an entry in the stub hash. Stub entries are cached because
4553 creating the stub name takes a bit of time. */
4562 {
4570 /* If the input section is the CMSE stubs one and it needs a long
4571 branch stub to reach it's final destination, give up with an
4572 error message: this is not supported. See PR ld/24709. */
4574 {
4580 CMSE_STUB_NAME,
4586 /* Exit, rather than leave incompletely processed
4587 relocations. */
4589 }
4591 /* If this input section is part of a group of sections sharing one
4592 stub section, then use the id of the first section in the group.
4593 Stub names need to include a section id, as there may well be
4594 more than one stub used to reach say, printf, and we need to
4595 distinguish between them. */
4603 {
4605 }
4606 else
4607 {
4620 }
4623 }
4625 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4626 section. */
4628 static bool
4630 {
4635 {
4641 }
4644 }
4646 /* Required alignment (as a power of 2) for the dedicated section holding
4647 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4648 with input sections. */
4650 static int
4651 arm_dedicated_stub_output_section_required_alignment
4653 {
4658 {
4659 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4660 boundary. */
4667 }
4670 }
4672 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4673 NULL if veneers of this type are interspersed with input sections. */
4677 {
4682 {
4689 }
4692 }
4694 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4695 returns the address of the hash table field in HTAB holding a pointer to the
4696 corresponding input section. Otherwise, returns NULL. */
4701 {
4706 {
4713 }
4716 }
4718 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4719 is the section that branch into veneer and can be NULL if stub should go in
4720 a dedicated output section. Returns a pointer to the stub section, and the
4721 section to which the stub section will be attached (in *LINK_SEC_P).
4722 LINK_SEC_P may be NULL. */
4728 {
4736 {
4746 {
4750 }
4751 }
4752 else
4753 {
4763 }
4766 {
4768 bfd_size_type len;
4780 align);
4787 }
4796 }
4798 /* Add a new stub entry to the stub hash. Not all fields of the new
4799 stub entry are initialised. */
4805 {
4811 stub_type);
4815 /* Enter this entry into the linker stub hash table. */
4819 {
4825 }
4832 }
4834 /* Store an Arm insn into an output section not processed by
4835 elf32_arm_write_section. */
4837 static void
4840 {
4843 else
4845 }
4847 /* Store a 16-bit Thumb insn into an output section not processed by
4848 elf32_arm_write_section. */
4850 static void
4853 {
4856 else
4858 }
4860 /* Store a Thumb2 insn into an output section not processed by
4861 elf32_arm_write_section. */
4863 static void
4866 {
4867 /* T2 instructions are 16-bit streamed. */
4869 {
4872 }
4873 else
4874 {
4877 }
4878 }
4880 /* If it's possible to change R_TYPE to a more efficient access
4881 model, return the new reloc type. */
4883 static unsigned
4886 {
4893 /* We do not support relaxations for Old TLS models. */
4895 {
4902 }
4905 }
4907 static bfd_reloc_status_type elf32_arm_final_link_relocate
4913 static unsigned int
4915 {
4917 {
4949 }
4950 }
4952 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4953 veneering (TRUE) or have their own symbol (FALSE). */
4955 static bool
4957 {
4962 {
4968 }
4971 }
4973 /* Returns the padding needed for the dedicated section used stubs of type
4974 STUB_TYPE. */
4976 static int
4978 {
4983 {
4989 }
4992 }
4994 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4995 returns the address of the hash table field in HTAB holding the offset at
4996 which new veneers should be layed out in the stub section. */
5001 {
5003 {
5010 }
5011 }
5013 static bool
5016 {
5017 #define MAXRELOCS 3
5025 bfd_vma sym_value;
5035 /* Massage our args to the form they really have. */
5039 /* Fail if the target section could not be assigned to an output
5040 section. The user should fix his linker script. */
5055 /* We have to do less-strictly-aligned fixes last. */
5058 /* Assign a slot at the end of section if none assigned yet. */
5060 {
5063 }
5068 /* This is the address of the stub destination. */
5078 {
5080 {
5082 {
5085 {
5086 /* We've borrowed the reloc_addend field to mean we should
5087 insert a condition code into this (Thumb-1 branch)
5088 instruction. See THUMB16_BCOND_INSN. */
5091 }
5094 }
5104 {
5107 }
5114 /* Handle cases where the target is encoded within the
5115 instruction. */
5117 {
5120 }
5134 }
5135 }
5140 /* Stub size has already been computed in arm_size_one_stub. Check
5141 consistency. */
5144 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5148 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5149 to relocate in each stub. */
5150 removed_sg_veneer =
5155 {
5156 Elf_Internal_Rela rel;
5159 bfd_vma points_to =
5168 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5169 template should refer back to the instruction after the original
5170 branch. We use target_section as Cortex-A8 erratum workaround stubs
5171 are only generated when both source and target are in the same
5172 section. */
5184 }
5187 #undef MAXRELOCS
5188 }
5190 /* Calculate the template, template size and instruction size for a stub.
5191 Return value is the instruction size. */
5193 static unsigned int
5197 {
5212 {
5214 {
5228 }
5229 }
5232 }
5234 /* As above, but don't actually build the stub. Just bump offset so
5235 we know stub section sizes. */
5237 static bool
5240 {
5245 /* Massage our args to the form they really have. */
5254 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5256 {
5260 }
5262 /* Already accounted for. */
5270 }
5272 /* External entry points for sizing and building linker stubs. */
5274 /* Set up various things so that we can make a list of input sections
5275 for each output section included in the link. Returns -1 on error,
5276 0 when no stubs will be needed, and 1 on success. */
5278 int
5281 {
5293 /* Count the number of input BFDs and find the top input section id. */
5297 {
5302 {
5305 }
5306 }
5315 /* We can't use output_bfd->section_count here to find the top output
5316 section index as some sections may have been removed, and
5317 _bfd_strip_section_from_output doesn't renumber the indices. */
5321 {
5324 }
5333 /* For sections we aren't interested in, mark their entries with a
5334 value we can check later. */
5336 do
5343 {
5346 }
5349 }
5351 /* The linker repeatedly calls this function for each input section,
5352 in the order that input sections are linked into output sections.
5353 Build lists of input sections to determine groupings between which
5354 we may insert linker stubs. */
5356 void
5359 {
5366 {
5370 {
5371 /* Steal the link_sec pointer for our list. */
5372 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5373 /* This happens to make the list in reverse order,
5374 which we reverse later. */
5377 }
5378 }
5379 }
5381 /* See whether we can group stub sections together. Grouping stub
5382 sections may result in fewer stubs. More importantly, we need to
5383 put all .init* and .fini* stubs at the end of the .init or
5384 .fini output sections respectively, because glibc splits the
5385 _init and _fini functions into multiple parts. Putting a stub in
5386 the middle of a function is not a good idea. */
5388 static void
5390 bfd_size_type stub_group_size,
5392 {
5395 do
5396 {
5403 /* Reverse the list: we must avoid placing stubs at the
5404 beginning of the section because the beginning of the text
5405 section may be required for an interrupt vector in bare metal
5406 code. */
5407 #define NEXT_SEC PREV_SEC
5410 {
5411 /* Pop from tail. */
5415 /* Push on head. */
5418 }
5421 {
5425 bfd_vma end_of_next;
5429 {
5433 /* End of NEXT is too far from start, so stop. */
5435 /* Add NEXT to the group. */
5437 }
5439 /* OK, the size from the start to the start of CURR is less
5440 than stub_group_size and thus can be handled by one stub
5441 section. (Or the head section is itself larger than
5442 stub_group_size, in which case we may be toast.)
5443 We should really be keeping track of the total size of
5444 stubs added here, as stubs contribute to the final output
5445 section size. */
5446 do
5447 {
5449 /* Set up this stub group. */
5451 }
5454 /* But wait, there's more! Input sections up to stub_group_size
5455 bytes after the stub section can be handled by it too. */
5457 {
5461 {
5464 /* End of NEXT is too far from stubs, so stop. */
5466 /* Add NEXT to the stub group. */
5470 }
5471 }
5473 }
5474 }
5478 #undef PREV_SEC
5479 #undef NEXT_SEC
5480 }
5482 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5483 erratum fix. */
5485 static int
5487 {
5495 else
5497 }
5502 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5503 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5504 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5505 otherwise. */
5507 static bool
5517 {
5530 {
5534 bfd_vma base_vma;
5553 {
5564 /* Span is entirely within a single 4KB region: skip scanning. */
5569 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5571 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5572 * The branch target is in the same 4KB region as the
5573 first half of the branch.
5574 * The instruction before the branch is a 32-bit
5575 length non-branch instruction. */
5577 {
5586 {
5587 /* Load the rest of the insn (in manual-friendly order). */
5590 /* Encoding T4: B<c>.W. */
5592 /* Encoding T1: BL<c>.W. */
5594 /* Encoding T2: BLX<c>.W. */
5596 /* Encoding T3: B<c>.W (not permitted in IT block). */
5599 }
5604 && insn_32bit
5605 && is_32bit_branch
5606 && last_was_32bit
5608 {
5612 bfd_vma target;
5624 {
5628 /* We don't care about the error returned from this
5629 function, only if there is glue or not. */
5636 /* Keep a simpler condition, for the sake of clarity. */
5642 {
5646 else
5648 }
5649 }
5651 /* Check if we have an offending branch instruction. */
5654 /* We've already made a stub for this instruction, e.g.
5655 it's a long branch or a Thumb->ARM stub. Assume that
5656 stub will suffice to work around the A8 erratum (see
5657 setting of always_after_branch above). */
5658 ;
5660 {
5669 }
5671 {
5691 }
5694 {
5697 /* The original instruction is a BL, but the target is
5698 an ARM instruction. If we were not making a stub,
5699 the BL would have been converted to a BLX. Use the
5700 BLX stub instead in that case. */
5703 {
5707 }
5708 /* Conversely, if the original instruction was
5709 BLX but the target is Thumb mode, use the BL
5710 stub. */
5713 {
5717 }
5722 /* If we found a relocation, use the proper destination,
5723 not the offset in the (unrelocated) instruction.
5724 Note this is always done if we switched the stub type
5725 above. */
5727 offset =
5730 /* If the stub will use a Thumb-mode branch to a
5731 PLT target, redirect it to the preceding Thumb
5732 entry point. */
5738 /* The BLX stub is ARM-mode code. Adjust the offset to
5739 take the different PC value (+8 instead of +4) into
5740 account. */
5745 {
5749 {
5755 }
5758 {
5759 /* If we're doing a subsequent scan,
5760 check if we've found the same fix as
5761 before, and try and reuse the stub
5762 name. */
5766 {
5770 }
5771 }
5774 {
5778 }
5791 num_a8_fixes++;
5792 }
5793 }
5794 }
5799 }
5800 }
5804 }
5811 }
5813 /* Create or update a stub entry depending on whether the stub can already be
5814 found in HTAB. The stub is identified by:
5815 - its type STUB_TYPE
5816 - its source branch (note that several can share the same stub) whose
5817 section and relocation (if any) are given by SECTION and IRELA
5818 respectively
5819 - its target symbol whose input section, hash, name, value and branch type
5820 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5821 respectively
5823 If found, the value of the stub's target symbol is updated from SYM_VALUE
5824 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5825 TRUE and the stub entry is initialized.
5827 Returns the stub that was created or updated, or NULL if an error
5828 occurred. */
5837 {
5849 else
5850 {
5855 /* Support for grouping stub sections. */
5858 /* Get the name of this stub. */
5860 stub_type);
5863 }
5867 /* The proper stub has already been created, just update its value. */
5869 {
5874 }
5878 {
5882 }
5892 else
5893 {
5900 {
5903 }
5905 /* For historical reasons, use the existing names for ARM-to-Thumb and
5906 Thumb-to-ARM stubs. */
5917 else
5919 }
5923 }
5925 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5926 gateway veneer to transition from non secure to secure state and create them
5927 accordingly.
5929 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5930 defines the conditions that govern Secure Gateway veneer creation for a
5931 given symbol <SYM> as follows:
5932 - it has function type
5933 - it has non local binding
5934 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5935 same type, binding and value as <SYM> (called normal symbol).
5936 An entry function can handle secure state transition itself in which case
5937 its special symbol would have a different value from the normal symbol.
5939 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5940 entry mapping while HTAB gives the name to hash entry mapping.
5941 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5942 created.
5944 The return value gives whether a stub failed to be allocated. */
5946 static bool
5950 {
5958 bfd_vma sym_value;
5974 NULL);
5978 /* Scan symbols. */
5980 {
5984 {
5992 /* Special symbol with local binding. */
5994 }
5995 else
5996 {
6002 /* Special symbol has incorrect binding or type. */
6007 }
6010 {
6016 }
6019 {
6026 }
6032 /* No associated normal symbol or it is neither global nor weak. */
6037 {
6038 /* Initialize here to avoid warning about use of possibly
6039 uninitialized variable. */
6043 {
6044 /* Searching for a normal symbol with local binding. */
6046 {
6047 lsym_name =
6053 }
6054 }
6057 {
6058 _bfd_error_handler
6062 }
6063 else
6064 _bfd_error_handler
6069 }
6075 {
6076 _bfd_error_handler
6080 }
6084 /* If this section is a link-once section that will be discarded, then
6085 don't create any stubs. */
6087 {
6088 _bfd_error_handler
6091 }
6094 {
6095 _bfd_error_handler
6098 }
6103 stub_entry
6110 else
6111 {
6114 }
6115 }
6120 }
6122 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6123 code entry function, ie can be called from non secure code without using a
6124 veneer. */
6126 static bool
6128 {
6132 file_ptr offset;
6135 /* Defined symbol of function type. */
6142 /* Read first instruction. */
6152 /* Starts by SG instruction. */
6154 }
6156 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6157 secure gateway veneers (ie. the veneers was not in the input import library)
6158 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6160 static bool
6162 {
6166 /* Massage our args to the form they really have. */
6180 }
6182 /* Set offset of each secure gateway veneers so that its address remain
6183 identical to the one in the input import library referred by
6184 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6185 (present in input import library but absent from the executable being
6186 linked) or if new veneers appeared and there is no output import library
6187 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6188 number of secure gateway veneers found in the input import library.
6190 The function returns whether an error occurred. If no error occurred,
6191 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6192 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6193 veneer observed set for new veneers to be layed out after. */
6195 static bool
6199 {
6202 flagword flags;
6209 bfd_size_type cmse_stub_size;
6218 /* No input secure gateway import library. */
6224 {
6228 }
6230 /* Get symbol table size. */
6235 /* Read in the input secure gateway import library's symbol table. */
6242 {
6245 }
6248 cmse_stub_size =
6252 out_sec_name =
6254 stub_out_sec =
6259 /* Set addresses of veneers mentionned in input secure gateway import
6260 library's symbol table. */
6262 {
6273 {
6275 "symbol should be absolute, global and "
6280 }
6289 /* Stub entry should have been created by cmse_scan or the symbol be of
6290 a secure function callable from non secure code. */
6292 {
6295 _bfd_error_handler
6299 stub_entry
6306 else
6307 {
6309 new_cmse_stubs_created++;
6311 }
6314 }
6315 /* Symbol found is not callable from non secure code. */
6317 {
6319 {
6321 sym_name);
6323 }
6325 }
6326 else
6327 {
6328 /* Only stubs for SG veneers should have been created. */
6331 /* Check visibility hasn't changed. */
6334 _bfd_error_handler
6336 sym_name);
6339 }
6341 /* Size should match that of a SG veneer. */
6343 {
6347 }
6349 /* Previous veneer address is before current SG veneer section. */
6351 {
6352 /* Avoid offset underflow. */
6357 }
6359 /* Complain if stub offset not a multiple of stub size. */
6361 {
6362 _bfd_error_handler
6366 }
6371 new_cmse_stubs_created--;
6377 }
6380 {
6382 _bfd_error_handler
6386 }
6389 {
6390 _bfd_error_handler
6392 out_sec_name);
6394 }
6396 free_sym_buf:
6399 }
6401 /* Determine and set the size of the stub section for a final link.
6403 The basic idea here is to examine all the relocations looking for
6404 PC-relative calls to a target that is unreachable with a "bl"
6405 instruction. */
6407 bool
6411 bfd_signed_vma group_size,
6413 asection *,
6416 {
6420 bfd_size_type stub_group_size;
6432 {
6437 }
6439 /* Propagate mach to stub bfd, because it may not have been
6440 finalized when we created stub_bfd. */
6444 /* Stash our params away. */
6453 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6454 as the first half of a 32-bit branch straddling two 4K pages. This is a
6455 crude way of enforcing that. */
6461 else
6465 {
6466 /* Default values. */
6467 /* Thumb branch range is +-4MB has to be used as the default
6468 maximum size (a given section can contain both ARM and Thumb
6469 code, so the worst case has to be taken into account).
6471 This value is 24K less than that, which allows for 2025
6472 12-byte stubs. If we exceed that, then we will fail to link.
6473 The user will have to relink with an explicit group size
6474 option. */
6476 }
6480 /* If we're applying the cortex A8 fix, we need to determine the
6481 program header size now, because we cannot change it later --
6482 that could alter section placements. Notice the A8 erratum fix
6483 ends up requiring the section addresses to remain unchanged
6484 modulo the page size. That's something we cannot represent
6485 inside BFD, and we don't want to force the section alignment to
6486 be the page size. */
6491 {
6503 {
6517 /* We'll need the symbol table in a second. */
6522 /* Limit scan of symbols to object file whose profile is
6523 Microcontroller to not hinder performance in the general case. */
6525 {
6535 }
6537 /* Walk over each section attached to the input bfd. */
6541 {
6544 /* If there aren't any relocs, then there's nothing more
6545 to do. */
6551 /* If this section is a link-once section that will be
6552 discarded, then don't create any stubs. */
6557 /* Get the relocs. */
6558 internal_relocs
6564 /* Now examine each relocation. */
6568 {
6571 bfd_vma sym_value;
6572 bfd_vma destination;
6583 {
6585 error_ret_free_internal:
6588 /* Fall through. */
6589 error_ret_free_local:
6593 }
6597 hash = elf32_arm_hash_entry
6601 /* Only look for stubs on branch instructions, or
6602 non-relaxed TLSCALL */
6616 : (elf32_arm_local_got_tls_type
6621 /* Now determine the call target, its name, value,
6622 section. */
6630 {
6631 /* A non-relaxed TLS call. The target is the
6632 plt-resident trampoline and nothing to do
6633 with the symbol. */
6640 }
6642 {
6643 /* It's a local symbol. */
6647 {
6648 local_syms
6651 local_syms
6657 }
6666 else
6667 sym_sec =
6671 /* This is an undefined symbol. It can never
6672 be resolved. */
6681 branch_type =
6683 sym_name
6687 }
6688 else
6689 {
6690 /* It's an external symbol. */
6698 {
6705 /* For a destination in a shared library,
6706 use the PLT stub as target address to
6707 decide whether a branch stub is
6708 needed. */
6713 {
6717 destination = (sym_value
6720 }
6725 }
6728 {
6729 /* For a shared library, use the PLT stub as
6730 target address to decide whether a long
6731 branch stub is needed.
6732 For absolute code, they cannot be handled. */
6740 {
6744 destination = (sym_value
6747 }
6748 else
6750 }
6751 else
6752 {
6755 }
6757 branch_type =
6760 }
6762 do
6763 {
6767 /* Determine what (if any) linker stub is needed. */
6775 /* We've either created a stub for this reloc already,
6776 or we are about to. */
6777 stub_entry =
6788 else
6790 }
6793 /* Look for relocations which might trigger Cortex-A8
6794 erratum. */
6800 {
6806 {
6807 /* Found a candidate. Note we haven't checked the
6808 destination is within 4K here: if we do so (and
6809 don't create an entry in a8_relocs) we can't tell
6810 that a branch should have been relocated when
6811 scanning later. */
6813 {
6819 }
6829 num_a8_relocs++;
6830 }
6831 }
6832 }
6834 /* We're done with the internal relocs, free them. */
6837 }
6840 {
6841 /* Sort relocs which might apply to Cortex-A8 erratum. */
6846 /* Scan for branches which might trigger Cortex-A8 erratum. */
6853 }
6857 {
6860 else
6862 }
6863 }
6876 /* OK, we've added some stubs. Find out the new size of the
6877 stub sections. */
6881 {
6882 /* Ignore non-stub sections. */
6887 }
6889 /* Add new SG veneers after those already in the input import
6890 library. */
6892 stub_type++)
6893 {
6905 }
6907 /* Compute stub section size, considering padding. */
6910 stub_type++)
6911 {
6917 /* Skip if no stub input section or no stub section padding
6918 required. */
6921 /* Stub section padding required but no dedicated section. */
6927 }
6929 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6932 {
6939 stub_sec->size
6941 NULL);
6942 }
6945 /* Ask the linker to do its stuff. */
6948 }
6950 /* Add stubs for Cortex-A8 erratum fixes now. */
6952 {
6954 {
6967 {
6971 }
6990 }
6992 /* Stash the Cortex-A8 erratum fix array for use later in
6993 elf32_arm_write_section(). */
6996 }
6997 else
6998 {
7001 }
7003 }
7005 /* Build all the stubs associated with the current output file. The
7006 stubs are kept in a hash table attached to the main linker hash
7007 table. We also set up the .plt entries for statically linked PIC
7008 functions here. This function is called via arm_elf_finish in the
7009 linker. */
7011 bool
7013 {
7026 {
7027 bfd_size_type size;
7029 /* Ignore non-stub sections. */
7033 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7034 must at least be done for stub section requiring padding and for SG
7035 veneers to ensure that a non secure code branching to a removed SG
7036 veneer causes an error. */
7043 }
7045 /* Add new SG veneers after those already in the input import library. */
7047 {
7059 }
7061 /* Build the stubs as directed by the stub hash table. */
7065 {
7066 /* Place the cortex a8 stubs last. */
7069 }
7072 }
7074 /* Locate the Thumb encoded calling stub for NAME. */
7080 {
7085 /* We need a pointer to the armelf specific hash table. */
7097 hash = elf_link_hash_lookup
7108 }
7110 /* Locate the ARM encoded calling stub for NAME. */
7116 {
7121 /* We need a pointer to the elfarm specific hash table. */
7132 myh = elf_link_hash_lookup
7143 }
7145 /* ARM->Thumb glue (static images):
7147 .arm
7148 __func_from_arm:
7149 ldr r12, __func_addr
7150 bx r12
7151 __func_addr:
7152 .word func @ behave as if you saw a ARM_32 reloc.
7154 (v5t static images)
7155 .arm
7156 __func_from_arm:
7157 ldr pc, __func_addr
7158 __func_addr:
7159 .word func @ behave as if you saw a ARM_32 reloc.
7161 (relocatable images)
7162 .arm
7163 __func_from_arm:
7164 ldr r12, __func_offset
7165 add r12, r12, pc
7166 bx r12
7167 __func_offset:
7168 .word func - . */
7170 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7175 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7179 #define ARM2THUMB_PIC_GLUE_SIZE 16
7184 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7186 .thumb .thumb
7187 .align 2 .align 2
7188 __func_from_thumb: __func_from_thumb:
7189 bx pc push {r6, lr}
7190 nop ldr r6, __func_addr
7191 .arm mov lr, pc
7192 b func bx r6
7193 .arm
7194 ;; back_to_thumb
7195 ldmia r13! {r6, lr}
7196 bx lr
7197 __func_addr:
7198 .word func */
7200 #define THUMB2ARM_GLUE_SIZE 8
7205 #define VFP11_ERRATUM_VENEER_SIZE 8
7206 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7207 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7209 #define ARM_BX_VENEER_SIZE 12
7214 #ifndef ELFARM_NABI_C_INCLUDED
7215 static void
7217 {
7222 {
7223 /* Do not include empty glue sections in the output. */
7225 {
7229 }
7231 }
7242 }
7244 bool
7246 {
7254 ARM2THUMB_GLUE_SECTION_NAME);
7258 THUMB2ARM_GLUE_SECTION_NAME);
7262 VFP11_ERRATUM_VENEER_SECTION_NAME);
7266 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7270 ARM_BX_GLUE_SECTION_NAME);
7273 }
7275 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7276 returns the symbol identifying the stub. */
7281 {
7288 bfd_vma val;
7289 bfd_size_type size;
7295 s = bfd_get_linker_section
7306 myh = elf_link_hash_lookup
7310 {
7311 /* We've already seen this guy. */
7314 }
7316 /* The only trick here is using hash_table->arm_glue_size as the value.
7317 Even though the section isn't allocated yet, this is where we will be
7318 putting it. The +1 on the value marks that the stub has not been
7319 output yet - not that it is a Thumb function. */
7338 else
7345 }
7347 /* Allocate space for ARMv4 BX veneers. */
7349 static void
7351 {
7357 bfd_vma val;
7359 /* BX PC does not need a veneer. */
7367 /* Check if this veneer has already been allocated. */
7371 s = bfd_get_linker_section
7376 /* Add symbol for veneer. */
7383 myh = elf_link_hash_lookup
7401 }
7404 /* Add an entry to the code/data map for section SEC. */
7406 static void
7408 {
7413 {
7418 }
7423 {
7428 }
7431 {
7434 }
7435 }
7438 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7439 veneers are handled for now. */
7441 static bfd_vma
7447 {
7453 bfd_vma val;
7461 s = bfd_get_linker_section
7475 myh = elf_link_hash_lookup
7490 /* Link veneer back to calling location. */
7504 /* A symbol for the return from the veneer. */
7508 myh = elf_link_hash_lookup
7525 /* Generate a mapping symbol for the veneer section, and explicitly add an
7526 entry for that symbol to the code/data map for the section. */
7528 {
7530 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7531 ever requires this erratum fix. */
7541 /* The elf32_arm_init_maps function only cares about symbols from input
7542 BFDs. We must make a note of this generated mapping symbol
7543 ourselves so that code byteswapping works properly in
7544 elf32_arm_write_section. */
7546 }
7552 /* The offset of the veneer. */
7554 }
7556 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7557 veneers need to be handled because used only in Cortex-M. */
7559 static bfd_vma
7565 bfd_size_type veneer_size)
7566 {
7572 bfd_vma val;
7580 s = bfd_get_linker_section
7594 myh = elf_link_hash_lookup
7609 /* Link veneer back to calling location. */
7623 /* A symbol for the return from the veneer. */
7627 myh = elf_link_hash_lookup
7644 /* Generate a mapping symbol for the veneer section, and explicitly add an
7645 entry for that symbol to the code/data map for the section. */
7647 {
7649 /* Creates a THUMB symbol since there is no other choice. */
7659 /* The elf32_arm_init_maps function only cares about symbols from input
7660 BFDs. We must make a note of this generated mapping symbol
7661 ourselves so that code byteswapping works properly in
7662 elf32_arm_write_section. */
7664 }
7670 /* The offset of the veneer. */
7672 }
7674 #define ARM_GLUE_SECTION_FLAGS \
7675 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7676 | SEC_READONLY | SEC_LINKER_CREATED)
7678 /* Create a fake section for use by the ARM backend of the linker. */
7680 static bool
7682 {
7687 /* Already made. */
7696 /* Set the gc mark to prevent the section from being removed by garbage
7697 collection, despite the fact that no relocs refer to this section. */
7701 }
7703 /* Set size of .plt entries. This function is called from the
7704 linker scripts in ld/emultempl/{armelf}.em. */
7706 void
7708 {
7710 }
7712 /* Add the glue sections to ABFD. This function is called from the
7713 linker scripts in ld/emultempl/{armelf}.em. */
7715 bool
7718 {
7724 /* If we are only performing a partial
7725 link do not bother adding the glue. */
7737 return addglue
7739 }
7741 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7742 ensures they are not marked for deletion by
7743 strip_excluded_output_sections () when veneers are going to be created
7744 later. Not doing so would trigger assert on empty section size in
7745 lang_size_sections_1 (). */
7747 void
7749 {
7752 /* If we are only performing a partial
7753 link do not bother adding the glue. */
7758 {
7769 }
7770 }
7772 /* Select a BFD to be used to hold the sections used by the glue code.
7773 This function is called from the linker scripts in ld/emultempl/
7774 {armelf/pe}.em. */
7776 bool
7778 {
7781 /* If we are only performing a partial link
7782 do not bother getting a bfd to hold the glue. */
7786 /* Make sure we don't attach the glue sections to a dynamic object. */
7795 /* Save the bfd for later use. */
7799 }
7801 static void
7803 {
7807 Tag_CPU_arch);
7810 {
7813 }
7814 else
7815 {
7818 }
7819 }
7821 bool
7824 {
7833 /* If we are only performing a partial link do not bother
7834 to construct any glue. */
7838 /* Here we have a bfd that is to be included on the link. We have a
7839 hook to do reloc rummaging, before section sizes are nailed down. */
7846 {
7848 abfd);
7850 }
7852 /* PR 5398: If we have not decided to include any loadable sections in
7853 the output then we will not have a glue owner bfd. This is OK, it
7854 just means that there is nothing else for us to do here. */
7858 /* Rummage around all the relocs and map the glue vectors. */
7865 {
7874 /* Load the relocs. */
7875 internal_relocs
7883 {
7892 /* These are the only relocation types we care about. */
7897 /* Get the section contents if we haven't done so already. */
7899 {
7900 /* Get cached copy if it exists. */
7903 else
7904 {
7905 /* Go get them off disk. */
7908 }
7909 }
7912 {
7918 }
7920 /* If the relocation is not against a symbol it cannot concern us. */
7923 /* We don't care about local symbols. */
7927 /* This is an external symbol. */
7932 /* If the relocation is against a static symbol it must be within
7933 the current section and so cannot be a cross ARM/Thumb relocation. */
7937 /* If the call will go through a PLT entry then we do not need
7938 glue. */
7943 {
7945 /* This one is a call from arm code. We need to look up
7946 the target of the call. If it is a thumb target, we
7947 insert glue. */
7955 }
7956 }
7965 }
7969 error_return:
7976 }
7977 #endif
7980 /* Initialise maps of ARM/Thumb/data for input BFDs. */
7982 void
7984 {
7989 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7999 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8000 should contain the number of local symbols, which should come before any
8001 global symbols. Mapping symbols are always local. */
8003 NULL);
8005 /* No internal symbols read? Skip this BFD. */
8010 {
8017 {
8022 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8024 }
8025 }
8026 }
8029 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8030 say what they wanted. */
8032 void
8034 {
8042 {
8043 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8048 else
8050 }
8051 }
8054 void
8056 {
8062 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8064 {
8066 {
8073 /* Give a warning, but do as the user requests anyway. */
8076 }
8077 }
8079 /* For earlier architectures, we might need the workaround, but do not
8080 enable it by default. If users is running with broken hardware, they
8081 must enable the erratum fix explicitly. */
8083 }
8085 void
8087 {
8094 /* We assume only Cortex-M4 may require the fix. */
8097 {
8099 /* Give a warning, but do as the user requests anyway. */
8100 _bfd_error_handler
8103 }
8104 }
8106 enum bfd_arm_vfp11_pipe
8107 {
8108 VFP11_FMAC,
8109 VFP11_LS,
8110 VFP11_DS,
8111 VFP11_BAD
8112 };
8114 /* Return a VFP register number. This is encoded as RX:X for single-precision
8115 registers, or X:RX for double-precision registers, where RX is the group of
8116 four bits in the instruction encoding and X is the single extension bit.
8117 RX and X fields are specified using their lowest (starting) bit. The return
8118 value is:
8120 0...31: single-precision registers s0...s31
8121 32...63: double-precision registers d0...d31.
8123 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8124 encounter VFP3 instructions, so we allow the full range for DP registers. */
8126 static unsigned int
8129 {
8132 else
8134 }
8136 /* Set bits in *WMASK according to a register number REG as encoded by
8137 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8139 static void
8141 {
8146 }
8148 /* Return TRUE if WMASK overwrites anything in REGS. */
8150 static bool
8152 {
8156 {
8169 }
8172 }
8174 /* In this function, we're interested in two things: finding input registers
8175 for VFP data-processing instructions, and finding the set of registers which
8176 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8177 hold the written set, so FLDM etc. are easy to deal with (we're only
8178 interested in 32 SP registers or 16 dp registers, due to the VFP version
8179 implemented by the chip in question). DP registers are marked by setting
8180 both SP registers in the write mask). */
8182 static enum bfd_arm_vfp11_pipe
8185 {
8190 {
8200 {
8222 vfp_binop:
8230 {
8235 {
8249 /* These instructions will not bounce due to underflow. */
8255 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8256 registers to cause the erratum in previous instructions. */
8262 {
8267 /* Only FCVTSD can underflow. */
8274 }
8279 }
8280 }
8285 }
8286 }
8287 /* Two-register transfer. */
8289 {
8293 {
8296 else
8297 {
8300 }
8301 }
8304 }
8306 {
8311 {
8318 {
8326 }
8336 }
8339 }
8340 /* Single-register transfer. Note L==0. */
8342 {
8347 {
8350 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8351 destination register. I don't know if this is exactly right,
8352 but it is the conservative choice. */
8358 }
8361 }
8364 }
8370 /* Look for potentially-troublesome code sequences which might trigger the
8371 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8372 (available from ARM) for details of the erratum. A short version is
8373 described in ld.texinfo. */
8375 bool
8377 {
8388 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8389 The states transition as follows:
8391 0 -> 1 (vector) or 0 -> 2 (scalar)
8392 A VFP FMAC-pipeline instruction has been seen. Fill
8393 regs[0]..regs[numregs-1] with its input operands. Remember this
8394 instruction in 'first_fmac'.
8396 1 -> 2
8397 Any instruction, except for a VFP instruction which overwrites
8398 regs[*].
8400 1 -> 3 [ -> 0 ] or
8401 2 -> 3 [ -> 0 ]
8402 A VFP instruction has been seen which overwrites any of regs[*].
8403 We must make a veneer! Reset state to 0 before examining next
8404 instruction.
8406 2 -> 0
8407 If we fail to match anything in state 2, reset to state 0 and reset
8408 the instruction pointer to the instruction after 'first_fmac'.
8410 If the VFP11 vector mode is in use, there must be at least two unrelated
8411 instructions between anti-dependent VFP11 instructions to properly avoid
8412 triggering the erratum, hence the use of the extra state 1. */
8414 /* If we are only performing a partial link do not bother
8415 to construct any glue. */
8419 /* Skip if this bfd does not correspond to an ELF image. */
8423 /* We should have chosen a fix type by the time we get here. */
8429 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8434 {
8438 /* If we don't have executable progbits, we're not interested in this
8439 section. Also skip if section is to be excluded. */
8459 elf32_arm_compare_mapping);
8462 {
8468 /* FIXME: Only ARM mode is supported at present. We may need to
8469 support Thumb-2 mode also at some point. */
8474 {
8489 {
8493 /* I'm assuming the VFP11 erratum can trigger with denorm
8494 operands on either the FMAC or the DS pipeline. This might
8495 lead to slightly overenthusiastic veneer insertion. */
8497 {
8501 }
8505 {
8508 other_regs,
8512 numregs))
8514 else
8516 }
8520 {
8523 other_regs,
8527 numregs))
8529 else
8530 {
8533 }
8534 }
8539 }
8542 {
8551 {
8558 }
8561 first_fmac);
8569 }
8572 }
8573 }
8578 }
8582 error_return:
8587 }
8589 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8590 after sections have been laid out, using specially-named symbols. */
8592 void
8595 {
8603 /* Skip if this bfd does not correspond to an ELF image. */
8616 {
8621 {
8623 bfd_vma vma;
8626 {
8629 /* Find veneer symbol. */
8633 myh = elf_link_hash_lookup
8649 /* Find return location. */
8653 myh = elf_link_hash_lookup
8669 }
8670 }
8671 }
8674 }
8676 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8677 return locations after sections have been laid out, using
8678 specially-named symbols. */
8680 void
8683 {
8691 /* Skip if this bfd does not correspond to an ELF image. */
8704 {
8709 {
8711 bfd_vma vma;
8714 {
8716 /* Find veneer symbol. */
8720 myh = elf_link_hash_lookup
8735 /* Find return location. */
8739 myh = elf_link_hash_lookup
8755 }
8756 }
8757 }
8760 }
8764 {
8765 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8766 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8768 }
8772 {
8773 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8774 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8776 }
8780 {
8781 /* A6.5 Extension register load or store instruction
8782 A7.7.229
8783 We look for SP 32-bit and DP 64-bit registers.
8784 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8785 <list> is consecutive 64-bit registers
8786 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8787 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8788 <list> is consecutive 32-bit registers
8789 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8790 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8791 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8792 return
8797 /* (IA with !), includes VPOP (when reg number is SP). */
8799 /* (DB with !). */
8801 }
8803 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8804 VLDM opcode and:
8805 - computes the number and the mode of memory accesses
8806 - decides if the replacement should be done:
8807 . replaces only if > 8-word accesses
8808 . or (testing purposes only) replaces all accesses. */
8810 static bool
8812 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8813 {
8816 /* The field encoding the register list is the same for both LDMIA
8817 and LDMDB encodings. */
8823 /* DEFAULT mode accounts for the real bug condition situation,
8824 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8828 }
8830 /* Look for potentially-troublesome code sequences which might trigger
8831 the STM STM32L4XX erratum. */
8833 bool
8836 {
8844 /* If we are only performing a partial link do not bother
8845 to construct any glue. */
8849 /* Skip if this bfd does not correspond to an ELF image. */
8856 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8861 {
8865 /* If we don't have executable progbits, we're not interested in this
8866 section. Also skip if section is to be excluded. */
8886 elf32_arm_compare_mapping);
8889 {
8896 /* Only Thumb2 mode need be supported with this CM4 specific
8897 code, we should not encounter any arm mode eg span_type
8898 != 'a'. */
8903 {
8910 /* The first 16-bits of all 32-bit thumb2 instructions start
8911 with opcode[15..13]=0b111 and the encoded op1 can be anything
8912 except opcode[12..11]!=0b00.
8913 See 32-bit Thumb instruction encoding. */
8917 /* Compute the predicate that tells if the instruction
8918 is concerned by the IT block
8919 - Creates an error if there is a ldm that is not
8920 last in the IT block thus cannot be replaced
8921 - Otherwise we can create a branch at the end of the
8922 IT block, it will be controlled naturally by IT
8923 with the proper pseudo-predicate
8924 - So the only interesting predicate is the one that
8925 tells that we are not on the last item of an IT
8926 block. */
8931 {
8932 /* Load the rest of the insn (in manual-friendly order). */
8937 /* Veneers are created for (v)ldm depending on
8938 option flags and memory accesses conditions; but
8939 if the instruction is not the last instruction of
8940 an IT block, we cannot create a jump there, so we
8941 bail out. */
8943 && stm32l4xx_need_create_replacing_stub
8945 {
8947 {
8948 _bfd_error_handler
8949 /* xgettext:c-format */
8951 " in non-last IT block instruction:"
8952 " STM32L4XX veneer cannot be generated; "
8953 "use gcc option -mrestrict-it to generate"
8956 }
8957 else
8958 {
8961 bfd_zmalloc
8967 /* We create only thumb branches. */
8969 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8970 record_stm32l4xx_erratum_veneer
8972 i,
8973 is_ldm ?
8974 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8975 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8979 }
8980 }
8981 }
8982 else
8983 {
8984 /* A7.7.37 IT p208
8985 IT blocks are only encoded in T1
8986 Encoding T1: IT{x{y{z}}} <firstcond>
8987 1 0 1 1 - 1 1 1 1 - firstcond - mask
8988 if mask = '0000' then see 'related encodings'
8989 We don't deal with UNPREDICTABLE, just ignore these.
8990 There can be no nested IT blocks so an IT block
8991 is naturally a new one for which it is worth
8992 computing its size. */
8995 /* If we have a new IT block we compute its size. */
8997 {
8998 /* Compute the number of instructions controlled
8999 by the IT block, it will be used to decide
9000 whether we are inside an IT block or not. */
9003 }
9004 }
9007 }
9008 }
9013 }
9017 error_return:
9022 }
9024 /* Set target relocation values needed during linking. */
9026 void
9030 {
9046 else
9047 {
9050 }
9057 else
9069 }
9071 /* Replace the target offset of a Thumb bl or b.w instruction. */
9073 static void
9075 {
9076 bfd_vma upper;
9077 bfd_vma lower;
9094 }
9096 /* Thumb code calling an ARM function. */
9098 static int
9106 bfd_vma offset,
9107 bfd_signed_vma addend,
9108 bfd_vma val,
9110 {
9112 bfd_vma my_offset;
9128 THUMB2ARM_GLUE_SECTION_NAME);
9135 {
9139 {
9140 _bfd_error_handler
9146 }
9157 ret_offset =
9158 /* Address of destination of the stub. */
9161 /* Offset from the start of the current section
9162 to the start of the stubs. */
9164 /* Offset of the start of this stub from the start of the stubs. */
9165 + my_offset
9166 /* Address of the start of the current section. */
9168 /* The branch instruction is 4 bytes into the stub. */
9170 /* ARM branches work from the pc of the instruction + 8. */
9176 }
9180 /* Now go back and fix up the original BL insn to point to here. */
9181 ret_offset =
9182 /* Address of where the stub is located. */
9184 /* Address of where the BL is located. */
9187 /* Addend in the relocation. */
9188 - addend
9189 /* Biassing for PC-relative addressing. */
9195 }
9197 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9205 bfd_vma val,
9208 {
9209 bfd_vma my_offset;
9225 {
9229 {
9230 _bfd_error_handler
9234 }
9242 {
9243 /* For relocatable objects we can't use absolute addresses,
9244 so construct the address from a relative offset. */
9245 /* TODO: If the offset is small it's probably worth
9246 constructing the address with adds. */
9253 /* Adjust the offset by 4 for the position of the add,
9254 and 8 for the pipeline offset. */
9261 }
9263 {
9267 /* It's a thumb address. Add the low order bit. */
9270 }
9271 else
9272 {
9279 /* It's a thumb address. Add the low order bit. */
9284 }
9285 }
9290 }
9292 /* Arm code calling a Thumb function. */
9294 static int
9302 bfd_vma offset,
9303 bfd_signed_vma addend,
9304 bfd_vma val,
9306 {
9308 bfd_vma my_offset;
9319 ARM2THUMB_GLUE_SECTION_NAME);
9333 /* Somehow these are both 4 too far, so subtract 8. */
9335 + my_offset
9347 }
9349 /* Populate Arm stub for an exported Thumb function. */
9351 static bool
9353 {
9360 bfd_vma val;
9364 /* Allocate stubs for exported Thumb functions on v4t. */
9373 ARM2THUMB_GLUE_SECTION_NAME);
9391 }
9393 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9395 static bfd_vma
9397 {
9399 bfd_vma glue_addr;
9408 ARM_BX_GLUE_SECTION_NAME);
9418 {
9424 }
9427 }
9429 /* Generate Arm stubs for exported Thumb symbols. */
9430 static void
9433 {
9437 /* Ignore this if we are not called by the ELF backend linker. */
9444 /* If blx is available then exported Thumb symbols are OK and there is
9445 nothing to do. */
9450 link_info);
9451 }
9453 /* Reserve space for COUNT dynamic relocations in relocation selection
9454 SRELOC. */
9456 static void
9458 bfd_size_type count)
9459 {
9467 }
9469 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9470 dynamic, the relocations should go in SRELOC, otherwise they should
9471 go in the special .rel.iplt section. */
9473 static void
9475 bfd_size_type count)
9476 {
9482 else
9483 {
9486 }
9487 }
9489 /* Add relocation REL to the end of relocation section SRELOC. */
9491 static void
9494 {
9509 }
9511 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9512 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9513 to .plt. */
9515 static void
9520 {
9528 {
9532 /* NaCl uses a special first entry in .iplt too. */
9536 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9538 }
9539 else
9540 {
9545 {
9546 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9547 /* For lazy binding, relocations will be put into .rel.plt, in
9548 .rel.got otherwise. */
9549 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9552 else
9554 }
9555 else
9556 {
9557 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9559 }
9561 /* If this is the first .plt entry, make room for the special
9562 first entry. */
9567 }
9569 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9575 /* We also need to make an entry in the .got.plt section, which
9576 will be placed in the .got section by the linker script. */
9579 else
9582 /* Function descriptor takes 64 bits in GOT. */
9584 else
9586 }
9588 static bfd_vma
9590 {
9592 }
9594 static bfd_vma
9596 {
9598 }
9600 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9601 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9602 Otherwise, DYNINDX is the index of the symbol in the dynamic
9603 symbol table and SYM_VALUE is undefined.
9605 ROOT_PLT points to the offset of the PLT entry from the start of its
9606 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9607 bookkeeping information.
9609 Returns FALSE if there was a problem. */
9611 static bool
9616 {
9622 bfd_vma plt_index;
9623 Elf_Internal_Rela rel;
9624 bfd_vma got_header_size;
9628 /* Pick the appropriate sections and sizes. */
9630 {
9635 /* There are no reserved entries in .igot.plt, and no special
9636 first entry in .iplt. */
9638 }
9639 else
9640 {
9646 }
9655 /* Get the offset into the .(i)got.plt table of the entry that
9656 corresponds to this function. */
9659 /* Get the index in the procedure linkage table which
9660 corresponds to this symbol. This is the index of this symbol
9661 in all the symbols for which we are making plt entries.
9662 After the reserved .got.plt entries, all symbols appear in
9663 the same order as in .plt. */
9665 /* Function descriptor takes 8 bytes. */
9667 else
9670 /* Calculate the address of the GOT entry. */
9675 /* ...and the address of the PLT entry. */
9682 {
9684 bfd_vma val;
9687 {
9695 else
9697 }
9698 }
9700 {
9702 bfd_vma val;
9705 {
9715 else
9717 }
9722 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9723 referencing the GOT for this PLT entry. */
9730 /* Create the R_ARM_ABS32 relocation referencing the
9731 beginning of the PLT for this GOT entry. */
9736 }
9738 {
9739 /* Calculate the displacement between the PLT slot and the
9740 common tail that's part of the special initial PLT slot. */
9741 int32_t tail_displacement
9751 /* Calculate the displacement between the PLT slot and the entry
9752 in the GOT. The offset accounts for the value produced by
9753 adding to pc in the penultimate instruction of the PLT stub. */
9754 got_displacement = (got_address
9757 /* NaCl does not support interworking at all. */
9775 }
9777 {
9779 ? elf32_arm_fdpic_thumb_plt_entry
9782 /* Fill-up Thumb stub if needed. */
9784 {
9789 }
9790 /* As we are using 32 bit instructions even for the Thumb
9791 version, we have to use 'put_arm_insn' instead of
9792 'put_thumb_insn'. */
9800 {
9801 /* funcdesc_value_reloc_offset. */
9809 }
9810 }
9812 {
9813 /* PR ld/16017: Generate thumb only PLT entries. */
9815 {
9816 /* FIXME: We ought to be able to generate thumb-1 PLT
9817 instructions... */
9819 output_bfd);
9821 }
9823 /* Calculate the displacement between the PLT slot and the entry in
9824 the GOT. The 12-byte offset accounts for the value produced by
9825 adding to pc in the 3rd instruction of the PLT stub. */
9828 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9829 instead of 'put_thumb_insn'. */
9850 }
9851 else
9852 {
9853 /* Calculate the displacement between the PLT slot and the
9854 entry in the GOT. The eight-byte offset accounts for the
9855 value produced by adding to pc in the first instruction
9856 of the PLT stub. */
9860 {
9865 }
9868 {
9883 #ifdef FOUR_WORD_PLT
9885 #endif
9886 }
9887 else
9888 {
9905 }
9906 }
9908 /* Fill in the entry in the .rel(a).(i)plt section. */
9912 {
9913 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9914 The dynamic linker or static executable then calls SYM_VALUE
9915 to determine the correct run-time value of the .igot.plt entry. */
9918 }
9919 else
9920 {
9921 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9922 used by PLT entry. */
9924 {
9927 }
9928 else
9929 {
9934 /* PR ld/16017
9935 When thumb only we need to set the LSB for any address that
9936 will be used with an interworking branch instruction. */
9939 }
9940 }
9942 /* Fill in the entry in the global offset table. */
9947 {
9948 /* Setup initial funcdesc value. */
9949 /* FIXME: we don't support lazy binding because there is a
9950 race condition between both words getting written and
9951 some other thread attempting to read them. The ARM
9952 architecture does not have an atomic 64 bit load/store
9953 instruction that could be used to prevent it; it is
9954 recommended that threaded FDPIC applications run with the
9955 LD_BIND_NOW environment variable set. */
9960 }
9964 else
9965 {
9967 {
9968 /* For FDPIC we put PLT relocationss into .rel.got when not
9969 lazy binding otherwise we put them in .rel.plt. For now,
9970 we don't support lazy binding so put it in .rel.got. */
9973 else
9975 }
9976 else
9977 {
9980 }
9981 }
9984 }
9986 /* Some relocations map to different relocations depending on the
9987 target. Return the real relocation. */
9989 static int
9992 {
9994 {
9998 else
10006 }
10007 }
10009 /* Return the base VMA address which should be subtracted from real addresses
10010 when resolving @dtpoff relocation.
10011 This is PT_TLS segment p_vaddr. */
10013 static bfd_vma
10015 {
10016 /* If tls_sec is NULL, we should have signalled an error already. */
10020 }
10022 /* Return the relocation value for @tpoff relocation
10023 if STT_TLS virtual address is ADDRESS. */
10025 static bfd_vma
10027 {
10029 bfd_vma base;
10031 /* If tls_sec is NULL, we should have signalled an error already. */
10036 }
10038 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10039 VALUE is the relocation value. */
10041 static bfd_reloc_status_type
10043 {
10050 }
10052 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10053 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10054 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10056 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10057 is to then call final_link_relocate. Return other values in the
10058 case of error.
10060 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10061 the pre-relaxed code. It would be nice if the relocs were updated
10062 to match the optimization. */
10064 static bfd_reloc_status_type
10068 {
10072 {
10079 else
10080 {
10084 else
10086 }
10091 /* Thumb insn. */
10094 {
10096 /* nop */
10098 }
10100 {
10102 /* nop */
10104 else
10105 /* ldr rx,[ry] */
10107 }
10109 {
10111 /* nop */
10113 else
10114 /* mov r0, rx */
10117 }
10118 else
10119 {
10121 /* It's a 32 bit instruction, fetch the rest of it for
10122 error generation. */
10125 _bfd_error_handler
10126 /* xgettext:c-format */
10132 }
10136 /* arm insn. */
10139 {
10141 /* mov rx, ry */
10144 }
10146 {
10148 /* nop */
10150 else
10151 /* ldr rx,[ry] */
10154 }
10156 {
10158 /* nop */
10160 else
10161 /* mov r0, rx */
10164 }
10165 else
10166 {
10167 _bfd_error_handler
10168 /* xgettext:c-format */
10174 }
10178 /* GD->IE relaxation, turn the instruction into 'nop' or
10179 'ldr r0, [pc,r0]' */
10185 /* GD->IE relaxation. */
10187 /* add r0,pc; ldr r0, [r0] */
10190 /* nop.w */
10192 else
10193 /* nop; nop */
10199 }
10201 }
10203 /* For a given value of n, calculate the value of G_n as required to
10204 deal with group relocations. We return it in the form of an
10205 encoded constant-and-rotation, together with the final residual. If n is
10206 specified as less than zero, then final_residual is filled with the
10207 input value and no further action is performed. */
10209 static bfd_vma
10211 {
10213 bfd_vma g_n;
10218 {
10221 /* Calculate which part of the value to mask. */
10224 else
10225 {
10228 /* Determine the most significant bit in the residual and
10229 align the resulting value to a 2-bit boundary. */
10234 /* The desired shift is now (msb - 6), or zero, whichever
10235 is the greater. */
10239 }
10241 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10246 /* Calculate the residual for the next time around. */
10248 }
10253 }
10255 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10256 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10258 static int
10260 {
10270 }
10272 /* Perform a relocation as part of a final link. */
10274 static bfd_reloc_status_type
10281 bfd_vma value,
10290 {
10300 bfd_vma addend;
10301 bfd_signed_vma signed_addend;
10303 bfd_vma dynreloc_value;
10308 bfd_vma plt_offset;
10309 bfd_vma gotplt_offset;
10320 /* Some relocation types map to different relocations depending on the
10321 target. We pick the right one here. */
10324 /* It is possible to have linker relaxations on some TLS access
10325 models. Update our information here. */
10338 else
10344 {
10345 bfd_vma sign;
10348 {
10353 }
10354 /* Note: the addend and signed_addend calculated here are
10355 incorrect for any split field. */
10361 }
10362 else
10365 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10366 are resolving a function call relocation. */
10373 /* Record the symbol information that should be used in dynamic
10374 relocations. */
10380 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10381 VALUE appropriately for relocations that we resolve at link time. */
10386 {
10391 {
10395 /* Populate .iplt entries here, because not all of them will
10396 be seen by finish_dynamic_symbol. The lower bit is set if
10397 we have already populated the entry. */
10399 plt_offset--;
10400 else
10401 {
10405 else
10407 }
10409 /* Static relocations always resolve to the .iplt entry. */
10416 /* If there are non-call relocations that resolve to the .iplt
10417 entry, then all dynamic ones must too. */
10419 {
10422 }
10423 }
10424 else
10425 /* We populate the .plt entry in finish_dynamic_symbol. */
10427 }
10428 else
10429 {
10433 }
10439 {
10441 /* We don't need to find a value for this symbol. It's just a
10442 marker. */
10449 /* Fall through. */
10461 /* Handle relocations which should use the PLT entry. ABS32/REL32
10462 will use the symbol's value, which may point to a PLT entry, but we
10463 don't need to handle that here. If we created a PLT entry, all
10464 branches in this object should go to it, except if the PLT is too
10465 far away, in which case a long branch stub should be inserted. */
10472 {
10473 /* If we've created a .plt section, and assigned a PLT entry
10474 to this function, it must either be a STT_GNU_IFUNC reference
10475 or not be known to bind locally. In other cases, we should
10476 have cleared the PLT entry by now. */
10486 }
10488 /* When generating a shared object or relocatable executable, these
10489 relocations are copied into the output file to be resolved at
10490 run time. */
10511 {
10512 Elf_Internal_Rela outrel;
10518 {
10524 _bfd_error_handler
10529 }
10534 {
10540 }
10565 else
10566 {
10569 /* This symbol is local, or marked to become local. */
10572 /* On SVR4-ish systems, the dynamic loader cannot
10573 relocate the text and data segments independently,
10574 so the symbol does not matter. */
10577 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10578 to the .iplt entry. Instead, every non-call reference
10579 must use an R_ARM_IRELATIVE relocation to obtain the
10580 correct run-time address. */
10584 else
10588 else
10590 }
10594 else
10597 /* If this reloc is against an external symbol, we do not want to
10598 fiddle with the addend. Otherwise, we need to include the symbol
10599 value so that it becomes an addend for the dynamic reloc. */
10606 }
10608 {
10617 {
10621 {
10622 /* Check for Arm calling Arm function. */
10623 /* FIXME: Should we translate the instruction into a BL
10624 instruction instead ? */
10626 _bfd_error_handler
10631 }
10633 {
10634 /* Check for Arm calling Thumb function. */
10636 {
10641 error_message))
10643 else
10645 }
10646 }
10648 /* Check if a stub has to be inserted because the
10649 destination is too far or we are changing mode. */
10653 {
10664 {
10665 /* The target is out of reach, so redirect the
10666 branch to the local stub for this function. */
10670 stub_type);
10671 {
10679 }
10680 }
10681 else
10682 {
10683 /* If the call goes through a PLT entry, make sure to
10684 check distance to the right destination address. */
10686 {
10691 /* The PLT entry is in ARM mode, regardless of the
10692 target function. */
10694 }
10695 }
10696 }
10698 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10699 where:
10700 S is the address of the symbol in the relocation.
10701 P is address of the instruction being relocated.
10702 A is the addend (extracted from the instruction) in bytes.
10704 S is held in 'value'.
10705 P is the base address of the section containing the
10706 instruction plus the offset of the reloc into that
10707 section, ie:
10708 (input_section->output_section->vma +
10709 input_section->output_offset +
10710 rel->r_offset).
10711 A is the addend, converted into bytes, ie:
10712 (signed_addend * 4)
10714 Note: None of these operations have knowledge of the pipeline
10715 size of the processor, thus it is up to the assembler to
10716 encode this information into the addend. */
10725 /* A branch to an undefined weak symbol is turned into a jump to
10726 the next instruction unless a PLT entry will be created.
10727 Do the same for local undefined symbols (but not for STN_UNDEF).
10728 The jump to the next instruction is optimized as a NOP depending
10729 on the architecture. */
10733 {
10738 else
10740 }
10741 else
10742 {
10743 /* Perform a signed range check. */
10754 {
10755 /* Set the H bit in the BLX instruction. */
10757 {
10760 else
10762 }
10764 /* Select the correct instruction (BL or BLX). */
10765 /* Only if we are not handling a BL to a stub. In this
10766 case, mode switching is performed by the stub. */
10770 {
10773 }
10774 }
10775 }
10776 }
10808 {
10809 /* Check for overflow. */
10812 }
10818 }
10826 /* There is no way to tell whether the user intended to use a signed or
10827 unsigned addend. When checking for overflow we accept either,
10828 as specified by the AAELF. */
10838 /* See comment for R_ARM_ABS8. */
10846 /* Support ldr and str instructions for the thumb. */
10848 {
10849 /* Need to refetch addend. */
10851 /* ??? Need to determine shift amount from operand size. */
10853 }
10856 /* ??? Isn't value unsigned? */
10860 /* ??? Value needs to be properly shifted into place first. */
10866 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10867 {
10868 bfd_vma insn;
10869 bfd_signed_vma relocation;
10875 {
10880 }
10887 /* PR 21523: Use an absolute value. The user of this reloc will
10888 have already selected an ADD or SUB insn appropriately. */
10894 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10908 }
10911 /* PR 10073: This reloc is not generated by the GNU toolchain,
10912 but it is supported for compatibility with third party libraries
10913 generated by other compilers, specifically the ARM/IAR. */
10914 {
10915 bfd_vma insn;
10916 bfd_signed_vma relocation;
10930 /* We do not check for overflow of this reloc. Although strictly
10931 speaking this is incorrect, it appears to be necessary in order
10932 to work with IAR generated relocs. Since GCC and GAS do not
10933 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10934 a problem for them. */
10942 }
10945 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10946 {
10947 bfd_vma insn;
10948 bfd_signed_vma relocation;
10954 {
10958 }
10978 }
10983 /* Thumb BL (branch long instruction). */
10984 {
10985 bfd_vma relocation;
10986 bfd_vma reloc_sign;
10990 bfd_signed_vma reloc_signed_max;
10991 bfd_signed_vma reloc_signed_min;
10992 bfd_vma check;
10993 bfd_signed_vma signed_check;
10998 /* A branch to an undefined weak symbol is turned into a jump to
10999 the next instruction unless a PLT entry will be created.
11000 The jump to the next instruction is optimized as a NOP.W for
11001 Thumb-2 enabled architectures. */
11004 {
11006 {
11009 }
11010 else
11011 {
11014 }
11016 }
11018 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11019 with Thumb-1) involving the J1 and J2 bits. */
11021 {
11031 /* Sign extend. */
11035 }
11038 {
11039 /* Check for Thumb to Thumb call. */
11040 /* FIXME: Should we translate the instruction into a BL
11041 instruction instead ? */
11043 _bfd_error_handler
11048 }
11049 else
11050 {
11051 /* If it is not a call to Thumb, assume call to Arm.
11052 If it is a call relative to a section name, then it is not a
11053 function call at all, but rather a long jump. Calls through
11054 the PLT do not require stubs. */
11056 {
11058 {
11059 /* Convert BL to BLX. */
11061 }
11064 {
11068 error_message))
11070 else
11072 }
11073 }
11077 {
11078 /* Make sure this is a BL. */
11080 }
11081 }
11085 {
11086 /* Check if a stub has to be inserted because the destination
11087 is too far. */
11099 {
11100 /* The target is out of reach or we are changing modes, so
11101 redirect the branch to the local stub for this
11102 function. */
11106 stub_type);
11108 {
11115 }
11117 /* If this call becomes a call to Arm, force BLX. */
11119 {
11124 }
11125 }
11126 }
11128 /* Handle calls via the PLT. */
11130 {
11138 {
11139 /* If the Thumb BLX instruction is available, convert
11140 the BL to a BLX instruction to call the ARM-mode
11141 PLT entry. */
11144 }
11145 else
11146 {
11148 /* Target the Thumb stub before the ARM PLT entry. */
11151 }
11153 }
11163 /* If this is a signed value, the rightshift just dropped
11164 leading 1 bits (assuming twos complement). */
11167 else
11170 /* Calculate the permissable maximum and minimum values for
11171 this relocation according to whether we're relocating for
11172 Thumb-2 or not. */
11179 /* Assumes two's complement. */
11184 /* For a BLX instruction, make sure that the relocation is rounded up
11185 to a word boundary. This follows the semantics of the instruction
11186 which specifies that bit 1 of the target address will come from bit
11187 1 of the base address. */
11190 /* Put RELOCATION back into the insn. Assumes two's complement.
11191 We use the Thumb-2 encoding, which is safe even if dealing with
11192 a Thumb-1 instruction by virtue of our overflow check above. */
11202 /* Put the relocated value back in the object file: */
11207 }
11211 /* Thumb32 conditional branch instruction. */
11212 {
11213 bfd_vma relocation;
11219 bfd_signed_vma signed_check;
11224 /* Need to refetch the addend, reconstruct the top three bits,
11225 and squish the two 11 bit pieces together. */
11227 {
11241 }
11243 /* Handle calls via the PLT. */
11245 {
11249 /* Target the Thumb stub before the ARM PLT entry. */
11252 }
11261 {
11265 stub_type);
11267 {
11271 }
11272 }
11283 /* Put RELOCATION back into the insn. */
11284 {
11293 }
11295 /* Put the relocated value back in the object file: */
11300 }
11305 /* Thumb B (branch) instruction). */
11306 {
11307 bfd_signed_vma relocation;
11310 bfd_signed_vma signed_check;
11312 /* CZB cannot jump backward. */
11314 {
11318 }
11331 else
11337 /* Assumes two's complement. */
11342 }
11347 {
11348 bfd_vma insn;
11349 bfd_vma relocation;
11353 {
11354 /* Extract the addend. */
11357 }
11367 }
11375 /* Relocation is relative to the start of the
11376 global offset table. */
11382 /* If we are addressing a Thumb function, we need to adjust the
11383 address by one, so that attempts to call the function pointer will
11384 correctly interpret it as Thumb code. */
11388 /* Note that sgot->output_offset is not involved in this
11389 calculation. We always want the start of .got. If we
11390 define _GLOBAL_OFFSET_TABLE in a different way, as is
11391 permitted by the ABI, we might have to change this
11392 calculation. */
11399 /* Use global offset table as symbol value. */
11413 /* Relocation is to the entry for this symbol in the
11414 global offset table. */
11421 {
11422 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11423 symbol, and the relocation resolves directly to the runtime
11424 target rather than to the .iplt entry. This means that any
11425 .got entry would be the same value as the .igot.plt entry,
11426 so there's no point creating both. */
11429 }
11431 {
11432 bfd_vma off;
11437 {
11438 /* We have already processsed one GOT relocation against
11439 this symbol. */
11444 }
11445 else
11446 {
11447 Elf_Internal_Rela outrel;
11452 {
11453 /* If the symbol doesn't resolve locally in a static
11454 object, we have an undefined reference. If the
11455 symbol doesn't resolve locally in a dynamic object,
11456 it should be resolved by the dynamic linker. */
11458 {
11461 }
11462 else
11465 }
11466 else
11467 {
11473 else
11474 {
11478 }
11480 }
11482 /* The GOT entry is initialized to zero by default.
11483 See if we should install a different value. */
11486 {
11490 }
11499 {
11504 }
11507 }
11509 }
11510 else
11511 {
11512 bfd_vma off;
11519 /* The offset must always be a multiple of 4. We use the
11520 least significant bit to record whether we have already
11521 generated the necessary reloc. */
11524 else
11525 {
11526 Elf_Internal_Rela outrel;
11533 else
11534 {
11538 }
11540 /* The GOT entry is initialized to zero by default.
11541 See if we should install a different value. */
11552 {
11558 }
11561 }
11564 }
11581 {
11582 bfd_vma off;
11591 else
11592 {
11593 /* If we don't know the module number, create a relocation
11594 for it. */
11596 {
11597 Elf_Internal_Rela outrel;
11612 }
11613 else
11617 }
11620 {
11626 }
11627 else
11628 {
11636 }
11637 }
11648 {
11656 {
11661 h)
11664 {
11667 }
11671 }
11672 else
11673 {
11677 {
11680 input_bfd,
11682 r_symndx);
11684 }
11688 }
11690 /* Linker relaxations happens from one of the
11691 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11699 else
11700 {
11702 Elf_Internal_Rela outrel;
11705 /* The GOT entries have not been initialized yet. Do it
11706 now, and emit any relocations. If both an IE GOT and a
11707 GD GOT are necessary, we emit the GD first. */
11714 {
11717 }
11720 {
11723 /* We should have relaxed, unless this is an undefined
11724 weak symbol. */
11733 + offplt
11745 /* For globals, the first word in the relocation gets
11746 the relocation index and the top bit set, or zero,
11747 if we're binding now. For locals, it gets the
11748 symbol's offset in the tls section. */
11756 /* Second word in the relocation is always zero. */
11760 }
11762 {
11764 {
11780 else
11781 {
11784 R_ARM_TLS_DTPOFF32);
11793 }
11794 }
11795 else
11796 {
11797 /* If we are not emitting relocations for a
11798 general dynamic reference, then we must be in a
11799 static link or an executable link with the
11800 symbol binding locally. Mark it as belonging
11801 to module 1, the executable. */
11806 }
11809 }
11812 {
11814 {
11817 else
11829 }
11830 else
11834 }
11838 else
11840 }
11849 {
11850 bfd_signed_vma offset;
11851 /* TLS stubs are arm mode. The original symbol is a
11852 data object, so branch_type is bogus. */
11854 enum elf32_arm_stub_type stub_type
11862 {
11864 = elf32_arm_get_stub_entry
11870 }
11871 else
11877 {
11887 }
11888 else
11889 {
11890 /* Thumb blx encodes the offset in a complicated
11891 fashion. */
11901 {
11903 }
11904 else
11905 {
11907 /* Round up the offset to a word boundary. */
11909 }
11921 }
11922 }
11923 /* These relocations needs special care, as besides the fact
11924 they point somewhere in .gotplt, the addend must be
11925 adjusted accordingly depending on the type of instruction
11926 we refer to. */
11928 {
11937 {
11944 /* bl/blx */
11947 /* add */
11949 else
11950 {
11951 _bfd_error_handler
11952 /* xgettext:c-format */
11954 "unexpected %s instruction '%#lx' "
11959 }
11960 }
11961 else
11962 {
11966 {
11977 _bfd_error_handler
11978 /* xgettext:c-format */
11980 "unexpected %s instruction '%#lx' "
11985 }
11986 }
11994 }
11995 else
12003 {
12004 /* For FDPIC relocations, resolve to the offset of the GOT
12005 entry from the start of GOT. */
12011 }
12012 else
12013 {
12017 }
12018 }
12022 {
12023 _bfd_error_handler
12024 /* xgettext:c-format */
12029 }
12030 else
12039 {
12042 /* Ensure that we have a BX instruction. */
12046 {
12047 /* Branch to veneer. */
12048 bfd_vma glue_addr;
12055 }
12056 else
12057 {
12058 /* Preserve Rm (lowest four bits) and the condition code
12059 (highest four bits). Other bits encode MOV PC,Rm. */
12061 }
12064 }
12071 /* Until we properly support segment-base-relative addressing then
12072 we assume the segment base to be zero, as for the group relocations.
12073 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12074 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12078 {
12082 {
12085 }
12107 }
12114 /* Until we properly support segment-base-relative addressing then
12115 we assume the segment base to be zero, as for the above relocations.
12116 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12117 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12118 as R_ARM_THM_MOVT_ABS. */
12122 {
12123 bfd_vma insn;
12129 {
12135 }
12161 }
12174 {
12178 /* sb is the origin of the *segment* containing the symbol. */
12180 bfd_vma residual;
12181 bfd_vma g_n;
12182 bfd_signed_vma signed_value;
12185 /* Determine which group of bits to select. */
12187 {
12209 }
12211 /* If REL, extract the addend from the insn. If RELA, it will
12212 have already been fetched for us. */
12214 {
12221 else
12222 {
12223 /* Compensate for the fact that in the instruction, the
12224 rotation is stored in multiples of 2 bits. */
12227 /* Rotate "constant" right by "rotation" bits. */
12230 }
12232 /* Determine if the instruction is an ADD or a SUB.
12233 (For REL, this determines the sign of the addend.) */
12236 {
12237 _bfd_error_handler
12238 /* xgettext:c-format */
12243 }
12246 }
12248 /* Compute the value (X) to go in the place. */
12254 /* PC relative. */
12256 else
12257 /* Section base relative. */
12260 /* If the target symbol is a Thumb function, then set the
12261 Thumb bit in the address. */
12265 /* Calculate the value of the relevant G_n, in encoded
12266 constant-with-rotation format. */
12270 /* Check for overflow if required. */
12277 {
12278 _bfd_error_handler
12279 /* xgettext:c-format */
12286 }
12288 /* Mask out the value and the ADD/SUB part of the opcode; take care
12289 not to destroy the S bit. */
12292 /* Set the opcode according to whether the value to go in the
12293 place is negative. */
12296 else
12299 /* Encode the offset. */
12303 }
12312 {
12316 /* sb is the origin of the *segment* containing the symbol. */
12318 bfd_vma residual;
12319 bfd_signed_vma signed_value;
12322 /* Determine which groups of bits to calculate. */
12324 {
12342 }
12344 /* If REL, extract the addend from the insn. If RELA, it will
12345 have already been fetched for us. */
12347 {
12350 }
12352 /* Compute the value (X) to go in the place. */
12356 /* PC relative. */
12358 else
12359 /* Section base relative. */
12362 /* Calculate the value of the relevant G_{n-1} to obtain
12363 the residual at that stage. */
12367 /* Check for overflow. */
12369 {
12370 _bfd_error_handler
12371 /* xgettext:c-format */
12378 }
12380 /* Mask out the value and U bit. */
12383 /* Set the U bit if the value to go in the place is non-negative. */
12387 /* Encode the offset. */
12391 }
12400 {
12404 /* sb is the origin of the *segment* containing the symbol. */
12406 bfd_vma residual;
12407 bfd_signed_vma signed_value;
12410 /* Determine which groups of bits to calculate. */
12412 {
12430 }
12432 /* If REL, extract the addend from the insn. If RELA, it will
12433 have already been fetched for us. */
12435 {
12438 }
12440 /* Compute the value (X) to go in the place. */
12444 /* PC relative. */
12446 else
12447 /* Section base relative. */
12450 /* Calculate the value of the relevant G_{n-1} to obtain
12451 the residual at that stage. */
12455 /* Check for overflow. */
12457 {
12458 _bfd_error_handler
12459 /* xgettext:c-format */
12466 }
12468 /* Mask out the value and U bit. */
12471 /* Set the U bit if the value to go in the place is non-negative. */
12475 /* Encode the offset. */
12479 }
12488 {
12492 /* sb is the origin of the *segment* containing the symbol. */
12494 bfd_vma residual;
12495 bfd_signed_vma signed_value;
12498 /* Determine which groups of bits to calculate. */
12500 {
12518 }
12520 /* If REL, extract the addend from the insn. If RELA, it will
12521 have already been fetched for us. */
12523 {
12526 }
12528 /* Compute the value (X) to go in the place. */
12532 /* PC relative. */
12534 else
12535 /* Section base relative. */
12538 /* Calculate the value of the relevant G_{n-1} to obtain
12539 the residual at that stage. */
12543 /* Check for overflow. (The absolute value to go in the place must be
12544 divisible by four and, after having been divided by four, must
12545 fit in eight bits.) */
12547 {
12548 _bfd_error_handler
12549 /* xgettext:c-format */
12556 }
12558 /* Mask out the value and U bit. */
12561 /* Set the U bit if the value to go in the place is non-negative. */
12565 /* Encode the offset. */
12569 }
12576 {
12582 /* Compute address. */
12588 /* Clean imm8 insn. */
12590 /* And update with correct part of address. */
12592 /* Update insn. */
12594 }
12600 {
12602 {
12607 {
12610 }
12617 {
12620 }
12622 /* Resolve relocation. */
12625 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12626 not done yet. */
12630 }
12631 else
12632 {
12635 bfd_vma addr;
12638 /* For static binaries, sym_sec can be null. */
12640 {
12643 }
12644 else
12645 {
12648 }
12651 {
12654 }
12656 /* This case cannot occur since funcdesc is allocated by
12657 the dynamic loader so we cannot resolve the relocation. */
12659 {
12662 }
12664 /* Resolve relocation. */
12667 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12671 }
12672 }
12677 {
12679 {
12680 Elf_Internal_Rela outrel;
12682 /* Resolve relocation. */
12686 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12688 {
12691 bfd_vma addr;
12694 /* For static binaries sym_sec can be null. */
12696 {
12699 }
12700 else
12701 {
12704 }
12706 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12710 }
12712 /* Add a dynamic relocation on GOT entry if not already done. */
12714 {
12716 {
12721 else
12725 sgot->contents
12727 }
12728 else
12729 {
12731 }
12739 else
12742 else
12745 }
12746 }
12747 else
12748 {
12749 /* Such relocation on static function should not have been
12750 emitted by the compiler. */
12752 }
12753 }
12758 {
12760 {
12762 Elf_Internal_Rela outrel;
12766 {
12769 }
12776 {
12779 }
12781 /* Replace static FUNCDESC relocation with a
12782 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12783 executable. */
12790 else
12796 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12800 }
12801 else
12802 {
12804 {
12807 bfd_vma addr;
12809 Elf_Internal_Rela outrel;
12811 /* For static binaries sym_sec can be null. */
12813 {
12816 }
12817 else
12818 {
12821 }
12826 /* Replace static FUNCDESC relocation with a
12827 R_ARM_RELATIVE dynamic relocation. */
12834 else
12840 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12844 }
12845 else
12846 {
12847 Elf_Internal_Rela outrel;
12849 /* Add a dynamic relocation. */
12855 }
12856 }
12857 }
12862 {
12863 bfd_vma relocation;
12868 {
12876 /* Sign extend. */
12878 }
12885 /* Put RELOCATION back into the insn. */
12886 {
12893 }
12895 /* Put the relocated value back in the object file: */
12900 }
12903 {
12904 bfd_vma relocation;
12909 {
12917 /* Sign extend. */
12920 }
12927 /* Put RELOCATION back into the insn. */
12928 {
12935 }
12937 /* Put the relocated value back in the object file: */
12942 }
12945 {
12946 bfd_vma relocation;
12951 {
12959 /* Sign extend. */
12962 }
12969 /* Put RELOCATION back into the insn. */
12970 {
12977 }
12979 /* Put the relocated value back in the object file: */
12984 }
12988 }
12989 }
12991 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12992 static void
12996 bfd_signed_vma increment)
12997 {
12998 bfd_signed_vma addend;
13002 {
13020 }
13021 else
13022 {
13023 bfd_vma contents;
13027 /* Get the (signed) value from the instruction. */
13030 {
13031 bfd_signed_vma mask;
13036 }
13038 /* Add in the increment, (which is a byte value). */
13040 {
13052 /* Should we check for overflow here ? */
13054 /* Drop any undesired bits. */
13057 }
13062 }
13063 }
13065 #define IS_ARM_TLS_RELOC(R_TYPE) \
13066 ((R_TYPE) == R_ARM_TLS_GD32 \
13067 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13068 || (R_TYPE) == R_ARM_TLS_LDO32 \
13069 || (R_TYPE) == R_ARM_TLS_LDM32 \
13070 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13071 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13072 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13073 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13074 || (R_TYPE) == R_ARM_TLS_LE32 \
13075 || (R_TYPE) == R_ARM_TLS_IE32 \
13076 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13077 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13079 /* Specific set of relocations for the gnu tls dialect. */
13080 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13081 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13082 || (R_TYPE) == R_ARM_TLS_CALL \
13083 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13084 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13085 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13087 /* Relocate an ARM ELF section. */
13089 static int
13098 {
13116 {
13123 bfd_vma relocation;
13124 bfd_reloc_status_type r;
13125 arelent bfd_reloc;
13148 {
13153 /* An object file might have a reference to a local
13154 undefined symbol. This is a daft object file, but we
13155 should at least do something about it. V4BX & NONE
13156 relocations do not use the symbol and are explicitly
13157 allowed to use the undefined symbol, so allow those.
13158 Likewise for relocations against STN_UNDEF. */
13171 {
13178 {
13183 {
13205 {
13206 _bfd_error_handler
13207 /* xgettext:c-format */
13213 }
13217 /* Get the (signed) value from the instruction. */
13220 {
13221 bfd_signed_vma mask;
13226 }
13228 }
13231 addend =
13236 /* Cases here must match those in the preceding
13237 switch statement. */
13239 {
13262 }
13263 }
13264 }
13265 else
13267 }
13268 else
13269 {
13278 }
13285 {
13286 /* This is a relocatable link. We don't have to change
13287 anything, unless the reloc is against a section symbol,
13288 in which case we have to adjust according to where the
13289 section symbol winds up in the output section. */
13291 {
13295 else
13297 }
13299 }
13303 else
13304 {
13305 name = (bfd_elf_string_from_elf_section
13309 }
13317 {
13318 _bfd_error_handler
13320 /* xgettext:c-format */
13322 /* xgettext:c-format */
13324 input_bfd,
13325 input_section,
13328 name);
13329 }
13331 /* We call elf32_arm_final_link_relocate unless we're completely
13332 done, i.e., the relaxation produced the final output we want,
13333 and we won't let anybody mess with it. Also, we have to do
13334 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13335 both in relaxed and non-relaxed cases. */
13341 {
13344 /* This may have been marked unresolved because it came from
13345 a shared library. But we've just dealt with that. */
13347 }
13348 else
13352 {
13363 }
13365 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13366 because such sections are not SEC_ALLOC and thus ld.so will
13367 not process them. */
13373 {
13374 _bfd_error_handler
13375 /* xgettext:c-format */
13378 input_bfd,
13379 input_section,
13384 }
13387 {
13389 {
13391 /* If the overflowing reloc was to an undefined symbol,
13392 we have already printed one error message and there
13393 is no point complaining again. */
13414 /* error_message should already be set. */
13419 /* Fall through. */
13421 common_error:
13426 }
13427 }
13428 }
13431 }
13433 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13434 adds the edit to the start of the list. (The list must be built in order of
13435 ascending TINDEX: the function's callers are primarily responsible for
13436 maintaining that condition). */
13438 static void
13441 arm_unwind_edit_type type,
13444 {
13453 {
13463 }
13464 else
13465 {
13472 }
13473 }
13477 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13479 static void
13481 {
13489 /* Adjust size of output section. */
13491 }
13493 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13495 static void
13497 {
13501 add_unwind_table_edit
13509 }
13511 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13512 made to those tables, such that:
13514 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13515 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13516 codes which have been inlined into the index).
13518 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13520 The edits are applied when the tables are written
13521 (in elf32_arm_write_section). */
13523 bool
13528 {
13535 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13536 text sections. */
13538 {
13542 {
13550 {
13551 Elf_Internal_Shdr *linked_hdr
13559 /* Link this .ARM.exidx section back from the text section it
13560 describes. */
13562 }
13563 }
13564 }
13566 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13567 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13568 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13571 {
13578 bfd_vma j;
13589 {
13590 /* Section has no unwind data. */
13594 /* Ignore zero sized sections. */
13601 }
13603 /* Skip /DISCARD/ sections. */
13620 /* An error? */
13624 {
13626 /* Add cantunwind if first unwind item does not match section
13627 start. */
13629 {
13632 }
13633 }
13636 {
13641 /* An EXIDX_CANTUNWIND entry. */
13643 {
13647 }
13648 /* Inlined unwinding data. Merge if equal to previous. */
13650 {
13656 }
13657 /* Normal table entry. In theory we could merge these too,
13658 but duplicate entries are likely to be much less common. */
13659 else
13663 {
13668 }
13671 }
13673 /* Free contents if we allocated it ourselves. */
13677 /* Record edits to be applied later (in elf32_arm_write_section). */
13686 }
13688 /* Add terminating CANTUNWIND entry. */
13694 }
13696 static bool
13699 {
13715 }
13717 static bool
13719 {
13726 /* Invoke the regular ELF backend linker to do all the work. */
13730 /* Process stub sections (eg BE8 encoding, ...). */
13734 {
13736 /* Only process it once, in its link_sec slot. */
13738 {
13744 }
13745 }
13747 /* Write out any glue sections now that we have created all the
13748 stubs. */
13750 {
13753 ARM2THUMB_GLUE_SECTION_NAME))
13758 THUMB2ARM_GLUE_SECTION_NAME))
13763 VFP11_ERRATUM_VENEER_SECTION_NAME))
13768 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13773 ARM_BX_GLUE_SECTION_NAME))
13775 }
13778 }
13780 /* Return a best guess for the machine number based on the attributes. */
13782 static unsigned int
13784 {
13788 {
13795 {
13802 {
13810 {
13816 {
13820 }
13821 }
13822 }
13825 }
13857 /* Force entry to be added for any new known Tag_CPU_arch value. */
13860 /* Unknown Tag_CPU_arch value. */
13862 }
13863 }
13865 /* Set the right machine number. */
13867 static bool
13869 {
13875 {
13878 else
13880 }
13884 }
13886 /* Function to keep ARM specific flags in the ELF header. */
13888 static bool
13890 {
13893 {
13895 {
13897 _bfd_error_handler
13898 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13899 abfd);
13900 else
13901 _bfd_error_handler
13903 abfd);
13904 }
13905 }
13906 else
13907 {
13910 }
13913 }
13915 /* Copy backend specific data from one object module to another. */
13917 static bool
13919 {
13920 flagword in_flags;
13921 flagword out_flags;
13932 {
13933 /* Cannot mix APCS26 and APCS32 code. */
13937 /* Cannot mix float APCS and non-float APCS code. */
13941 /* If the src and dest have different interworking flags
13942 then turn off the interworking bit. */
13944 {
13946 _bfd_error_handler
13947 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13951 }
13953 /* Likewise for PIC, though don't warn for this case. */
13956 }
13962 }
13964 /* Values for Tag_ABI_PCS_R9_use. */
13965 enum
13966 {
13967 AEABI_R9_V6,
13968 AEABI_R9_SB,
13969 AEABI_R9_TLS,
13970 AEABI_R9_unused
13971 };
13973 /* Values for Tag_ABI_PCS_RW_data. */
13974 enum
13975 {
13976 AEABI_PCS_RW_data_absolute,
13977 AEABI_PCS_RW_data_PCrel,
13978 AEABI_PCS_RW_data_SBrel,
13979 AEABI_PCS_RW_data_unused
13980 };
13982 /* Values for Tag_ABI_enum_size. */
13983 enum
13984 {
13985 AEABI_enum_unused,
13986 AEABI_enum_short,
13987 AEABI_enum_wide,
13988 AEABI_enum_forced_wide
13989 };
13991 /* Determine whether an object attribute tag takes an integer, a
13992 string or both. */
13994 static int
13996 {
14005 else
14007 }
14009 /* The ABI defines that Tag_conformance should be emitted first, and that
14010 Tag_nodefaults should be second (if either is defined). This sets those
14011 two positions, and bumps up the position of all the remaining tags to
14012 compensate. */
14013 static int
14015 {
14025 }
14027 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14028 static bool
14030 {
14032 {
14033 _bfd_error_handler
14038 }
14039 else
14040 {
14041 _bfd_error_handler
14045 }
14046 }
14048 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14049 Returns -1 if no architecture could be read. */
14051 static int
14053 {
14057 /* Note: the tag and its argument below are uleb128 values, though
14058 currently-defined values fit in one byte for each. */
14065 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14067 }
14069 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14070 The tag is removed if ARCH is -1. */
14072 static void
14074 {
14079 {
14082 }
14084 /* Note: the tag and its argument below are uleb128 values, though
14085 currently-defined values fit in one byte for each. */
14091 }
14093 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14094 into account. */
14096 static int
14099 {
14100 #define T(X) TAG_CPU_ARCH_##X
14103 {
14113 };
14115 {
14126 };
14128 {
14140 };
14142 {
14155 };
14157 {
14171 };
14173 {
14188 };
14190 {
14206 };
14208 {
14225 };
14227 {
14245 };
14247 {
14266 };
14268 {
14291 };
14293 {
14317 };
14319 {
14320 v6t2,
14321 v6k,
14322 v7,
14323 v6_m,
14324 v6s_m,
14325 v7e_m,
14326 v8,
14327 v8r,
14328 v8m_baseline,
14329 v8m_mainline,
14330 NULL,
14331 NULL,
14332 NULL,
14333 v8_1m_mainline,
14334 /* Pseudo-architecture. */
14335 v4t_plus_v6_m
14336 };
14338 /* Check we've not got a higher architecture than we know about. */
14341 {
14344 }
14346 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14352 /* And override the new tag if we have a Tag_also_compatible_with on the
14353 input. */
14362 /* Architectures before V6KZ add features monotonically. */
14368 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14369 as the canonical version. */
14371 {
14374 }
14375 else
14379 {
14383 }
14386 #undef T
14387 }
14389 /* Query attributes object to see if integer divide instructions may be
14390 present in an object. */
14391 static bool
14393 {
14398 {
14400 /* Integer divide allowed if instruction contained in archetecture. */
14405 else
14409 /* Integer divide explicitly prohibited. */
14413 /* Unrecognised case - treat as allowing divide everywhere. */
14415 /* Integer divide allowed in ARM state. */
14417 }
14418 }
14420 /* Query attributes object to see if integer divide instructions are
14421 forbidden to be in the object. This is not the inverse of
14422 elf32_arm_attributes_accept_div. */
14423 static bool
14425 {
14427 }
14429 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14430 are conflicting attributes. */
14432 static bool
14434 {
14438 /* Some tags have 0 = don't care, 1 = strong requirement,
14439 2 = weak requirement. */
14445 /* Skip the linker stubs file. This preserves previous behavior
14446 of accepting unknown attributes in the first input file - but
14447 is that a bug? */
14451 /* Skip any input that hasn't attribute section.
14452 This enables to link object files without attribute section with
14453 any others. */
14458 {
14459 /* This is the first object. Copy the attributes. */
14464 /* Use the Tag_null value to indicate the attributes have been
14465 initialized. */
14468 /* We do not output objects with Tag_MPextension_use_legacy - we move
14469 the attribute's value to Tag_MPextension_use. */
14471 {
14475 {
14476 _bfd_error_handler
14480 }
14486 }
14489 }
14493 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14495 {
14496 /* Ignore mismatches if the object doesn't use floating point or is
14497 floating point ABI independent. */
14504 {
14505 _bfd_error_handler
14510 }
14511 }
14514 {
14515 /* Merge this attribute with existing attributes. */
14517 {
14520 /* These are merged after Tag_CPU_arch. */
14525 /* Use the first value seen. */
14529 {
14534 {
14535 /* These aren't real CPU names, but we can't guess
14536 that from the architecture version alone. */
14554 };
14556 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14562 secondary_compat);
14564 /* Return with error if failed to merge. */
14572 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14576 {
14577 /* The output architecture has been changed to match the
14578 input architecture. Use the input names. */
14585 }
14586 else
14587 {
14590 }
14592 /* If we still don't have a value for Tag_CPU_name,
14593 make one up now. Tag_CPU_raw_name remains blank. */
14598 }
14605 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14619 /* Use the largest value specified. */
14626 /* Use the smallest value specified. */
14635 {
14636 /* This error message should be enabled once all non-conformant
14637 binaries in the toolchain have had the attributes set
14638 properly.
14639 _bfd_error_handler
14640 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14641 obfd, ibfd);
14642 result = false; */
14643 }
14644 /* Fall through. */
14647 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14648 value if greater than 2 (for future-proofing). */
14656 /* The virtualization tag effectively stores two bits of
14657 information: the intended use of TrustZone (in bit 0), and the
14658 intended use of Virtualization (in bit 1). */
14663 {
14666 else
14667 {
14668 _bfd_error_handler
14673 }
14674 }
14679 {
14680 /* 0 will merge with anything.
14681 'A' and 'S' merge to 'A'.
14682 'R' and 'S' merge to 'R'.
14683 'M' and 'A|R|S' is an error. */
14692 else
14693 {
14694 _bfd_error_handler
14696 ibfd,
14700 }
14701 }
14705 /* No need to change output value if any of:
14706 - pre (<=) ARMv5T input architecture (do not have DSP)
14707 - M input profile not ARMv7E-M and do not have DSP. */
14713 /* Output value should be 0 if DSP part of architecture, ie.
14714 - post (>=) ARMv5te architecture output
14715 - A, R or S profile output or ARMv7E-M output architecture. */
14722 /* Otherwise, DSP instructions are added and not part of output
14723 architecture. */
14724 else
14729 {
14730 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14731 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14732 when it's 0. It might mean absence of FP hardware if
14733 Tag_FP_arch is zero. */
14735 #define VFP_VERSION_COUNT 9
14736 static const struct
14737 {
14741 {
14751 };
14756 /* If the output has no requirement about FP hardware,
14757 follow the requirement of the input. */
14759 {
14760 /* This assert is still reasonable, we shouldn't
14761 produce the suspicious build attribute
14762 combination (See below for in_attr). */
14768 }
14769 /* If the input has no requirement about FP hardware, do
14770 nothing. */
14772 {
14773 /* We used to assert that Tag_ABI_HardFP_use was
14774 zero here, but we should never assert when
14775 consuming an object file that has suspicious
14776 build attributes. The single precision variant
14777 of 'no FP architecture' is still 'no FP
14778 architecture', so we just ignore the tag in this
14779 case. */
14781 }
14783 /* Both the input and the output have nonzero Tag_FP_arch.
14784 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14786 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14787 do nothing. */
14790 ;
14791 /* If the input and the output have different Tag_ABI_HardFP_use,
14792 the combination of them is 0 (implied by Tag_FP_arch). */
14797 /* Now we can handle Tag_FP_arch. */
14799 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14800 pick the biggest. */
14803 {
14806 }
14807 /* The output uses the superset of input features
14808 (ISA version) and registers. */
14815 /* This assumes all possible supersets are also a valid
14816 options. */
14818 {
14822 }
14824 }
14830 {
14831 /* It's sometimes ok to mix different configs, so this is only
14832 a warning. */
14833 _bfd_error_handler
14835 }
14841 {
14842 _bfd_error_handler
14845 }
14853 {
14854 _bfd_error_handler
14856 ibfd);
14858 }
14859 /* Use the smallest value specified. */
14866 {
14867 _bfd_error_handler
14868 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14870 }
14876 {
14879 {
14880 /* The existing object is compatible with anything.
14881 Use whatever requirements the new object has. */
14883 }
14887 {
14898 _bfd_error_handler
14899 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14901 }
14902 }
14905 /* Aready done. */
14909 {
14910 _bfd_error_handler
14914 }
14917 /* Merged in target-independent code. */
14920 /* This is handled along with Tag_FP_arch. */
14924 {
14926 {
14927 _bfd_error_handler
14931 }
14932 }
14938 /* A value of zero on input means that the divide instruction may
14939 be used if available in the base architecture as specified via
14940 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14941 the user did not want divide instructions. A value of 2
14942 explicitly means that divide instructions were allowed in ARM
14943 and Thumb state. */
14957 /* We don't output objects with Tag_MPextension_use_legacy - we
14958 move the value to Tag_MPextension_use. */
14960 {
14962 {
14963 _bfd_error_handler
14966 ibfd);
14968 }
14969 }
14977 /* This tag is set if it exists, but the value is unused (and is
14978 typically zero). We don't actually need to do anything here -
14979 the merge happens automatically when the type flags are merged
14980 below. */
14983 /* Already done in Tag_CPU_arch. */
14986 /* Keep the attribute if it matches. Throw it away otherwise.
14987 No attribute means no claim to conform. */
14994 result
14996 }
14998 /* If out_attr was copied from in_attr then it won't have a type yet. */
15001 }
15003 /* Merge Tag_compatibility attributes and any common GNU ones. */
15007 /* Check for any attributes not known on ARM. */
15011 }
15014 /* Return TRUE if the two EABI versions are incompatible. */
15016 static bool
15018 {
15019 /* v4 and v5 are the same spec before and after it was released,
15020 so allow mixing them. */
15026 }
15028 /* Merge backend specific data from an object file to the output
15029 object file when linking. */
15031 static bool
15034 /* Display the flags field. */
15036 static bool
15038 {
15044 /* Print normal ELF private data. */
15048 /* Ignore init flag - it may not be set, despite the flags field
15049 containing valid data. */
15054 {
15056 /* The following flag bits are GNU extensions and not part of the
15057 official ARM ELF extended ABI. Hence they are only decoded if
15058 the EABI version is not set. */
15064 else
15071 else
15100 else
15111 else
15143 eabi:
15156 }
15177 }
15179 static int
15181 {
15183 {
15188 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15189 This allows us to distinguish between data used by Thumb instructions
15190 and non-data (which is probably code) inside Thumb regions of an
15191 executable. */
15198 }
15201 }
15209 {
15212 {
15216 }
15219 }
15221 /* Look through the relocs for a section during the first phase. */
15223 static bool
15226 {
15250 /* Create dynamic sections for relocatable executables so that we can
15251 copy relocations. */
15254 {
15257 }
15272 {
15284 /* PR 9934: It is possible to have relocations that do not
15285 refer to symbols, thus it is also possible to have an
15286 object file containing relocations but no symbol table. */
15288 {
15290 r_symndx);
15292 }
15297 {
15299 {
15300 /* A local symbol. */
15305 }
15306 else
15307 {
15312 }
15313 }
15321 /* Could be done earlier, if h were already available. */
15324 {
15326 {
15328 {
15335 }
15336 else
15337 {
15339 }
15340 }
15344 {
15346 {
15347 /* Such a relocation is not supposed to be generated
15348 by gcc on a static function. */
15349 /* Anyway if needed it could be handled. */
15351 }
15352 else
15353 {
15355 }
15356 }
15360 {
15362 {
15369 }
15370 else
15371 {
15373 }
15374 }
15388 /* This symbol requires a global offset table entry. */
15389 {
15393 {
15406 }
15412 {
15415 }
15416 else
15417 {
15418 /* This is a global offset table entry for a local symbol. */
15422 {
15424 r_symndx);
15426 }
15430 }
15432 /* If a variable is accessed with both tls methods, two
15433 slots may be created. */
15438 /* We will already have issued an error message if there
15439 is a TLS/non-TLS mismatch, based on the symbol
15440 type. So just combine any TLS types needed. */
15445 /* If the symbol is accessed in both IE and GDESC
15446 method, we're able to relax. Turn off the GDESC flag,
15447 without messing up with any other kind of tls types
15448 that may be involved. */
15453 {
15456 else
15458 }
15459 }
15460 /* Fall through. */
15466 /* Fall through. */
15488 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15489 ldr __GOTT_INDEX__ offsets. */
15491 {
15494 }
15497 /* Fall through. */
15504 {
15505 _bfd_error_handler
15506 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15511 }
15513 /* Fall through. */
15516 jump_over:
15518 {
15520 }
15521 /* Fall through. */
15529 /* Should the interworking branches be listed here? */
15533 {
15536 {
15537 /* In shared libraries and relocatable executables,
15538 we treat local relative references as calls;
15539 see the related SYMBOL_CALLS_LOCAL code in
15540 allocate_dynrelocs. */
15543 }
15544 else
15545 /* We are creating a shared library or relocatable
15546 executable, and this is a reloc against a global symbol,
15547 or a non-PC-relative reloc against a local symbol.
15548 We may need to copy the reloc into the output. */
15550 }
15551 else
15555 /* This relocation describes the C++ object vtable hierarchy.
15556 Reconstruct it for later use during GC. */
15562 /* This relocation describes which C++ vtable entries are actually
15563 used. Record for later use during GC. */
15568 }
15571 {
15573 /* We may need a .plt entry if the function this reloc
15574 refers to is in a different object, regardless of the
15575 symbol's type. We can't tell for sure yet, because
15576 something later might force the symbol local. */
15579 /* If this reloc is in a read-only section, we might
15580 need a copy reloc. We can't check reliably at this
15581 stage whether the section is read-only, as input
15582 sections have not yet been mapped to output sections.
15583 Tentatively set the flag for now, and correct in
15584 adjust_dynamic_symbol. */
15586 }
15590 {
15596 {
15599 }
15600 else
15601 {
15607 }
15609 /* If the symbol is a function that doesn't bind locally,
15610 this relocation will need a PLT entry. */
15617 /* It's too early to use htab->use_blx here, so we have to
15618 record possible blx references separately from
15619 relocs that definitely need a thumb stub. */
15627 }
15630 {
15633 /* Create a reloc section in dynobj. */
15635 {
15636 sreloc = _bfd_elf_make_dynamic_reloc_section
15641 }
15643 /* If this is a global symbol, count the number of
15644 relocations we need for this symbol. */
15647 else
15648 {
15652 }
15656 {
15667 }
15674 {
15675 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15676 that will become rofixup. */
15677 /* This is due to the fact that we suppose all will become rofixup. */
15678 _bfd_error_handler
15683 }
15684 }
15685 }
15688 }
15690 static void
15693 {
15715 {
15718 }
15720 {
15723 }
15724 else
15736 {
15739 {
15742 irela++;
15743 count++;
15744 }
15746 {
15750 bfd_size_type j;
15751 bfd_vma offset;
15767 else
15771 {
15773 {
15775 bfd_vma bias;
15776 bfd_vma reloc_index;
15786 {
15787 bias++;
15789 }
15793 {
15795 irela++;
15796 count++;
15797 }
15800 }
15803 {
15804 /* New relocation entity. */
15813 irela++;
15814 count++;
15815 }
15816 }
15817 else
15818 {
15820 {
15823 irela++;
15824 }
15827 }
15828 }
15829 }
15837 {
15840 irela++;
15841 count--;
15842 }
15846 /* Hashes are no longer valid. */
15849 }
15851 /* Unwinding tables are not referenced directly. This pass marks them as
15852 required if the corresponding code section is marked. Similarly, ARMv8-M
15853 secure entry functions can only be referenced by SG veneers which are
15854 created after the GC process. They need to be marked in case they reside in
15855 their own section (as would be the case if code was compiled with
15856 -ffunction-sections). */
15858 static bool
15860 elf_gc_mark_hook_fn gc_mark_hook)
15861 {
15881 /* Marking EH data may cause additional code sections to be marked,
15882 requiring multiple passes. */
15885 {
15888 {
15896 {
15905 {
15909 }
15910 }
15912 /* Mark section holding ARMv8-M secure entry functions. We mark all
15913 of them so no need for a second browsing. */
15915 {
15922 /* Scan symbols. */
15924 {
15927 /* Assume it is a special symbol. If not, cmse_scan will
15928 warn about it and user can do something about it. */
15930 CMSE_PREFIX))
15931 {
15936 /* The debug sections related to these secure entry
15937 functions are marked on enabling below flag. */
15939 }
15940 }
15943 {
15944 /* Looping over all the sections of the object file containing
15945 Armv8-M secure entry functions and marking all the debug
15946 sections. */
15948 {
15949 /* If not a debug sections, skip it. */
15952 }
15954 }
15955 }
15956 }
15958 }
15961 }
15963 /* Treat mapping symbols as special target symbols. */
15965 static bool
15967 {
15969 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
15970 }
15972 /* If the ELF symbol SYM might be a function in SEC, return the
15973 function size and set *CODE_OFF to the function's entry point,
15974 otherwise return zero. */
15976 static bfd_size_type
15979 {
15980 bfd_size_type size;
15992 {
15994 /* Ignore symbols created by the annobin plugin for gcc and clang.
15995 These symbols are hidden, local, notype and have a size of 0. */
16000 /* Fall through. */
16003 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16007 }
16011 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16016 /* Do not return 0 for the function's size. */
16019 }
16021 static bool
16026 {
16032 }
16034 /* Adjust a symbol defined by a dynamic object and referenced by a
16035 regular object. The current definition is in some section of the
16036 dynamic object, but we're not including those sections. We have to
16037 change the definition to something the rest of the link can
16038 understand. */
16040 static bool
16043 {
16055 /* Make sure we know what is going on here. */
16066 /* If this is a function, put it in the procedure linkage table. We
16067 will fill in the contents of the procedure linkage table later,
16068 when we know the address of the .got section. */
16070 {
16071 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16072 symbol binds locally. */
16078 {
16079 /* This case can occur if we saw a PLT32 reloc in an input
16080 file, but the symbol was never referred to by a dynamic
16081 object, or if all references were garbage collected. In
16082 such a case, we don't actually need to build a procedure
16083 linkage table, and we can just do a PC24 reloc instead. */
16089 }
16092 }
16093 else
16094 {
16095 /* It's possible that we incorrectly decided a .plt reloc was
16096 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16097 in check_relocs. We can't decide accurately between function
16098 and non-function syms in check-relocs; Objects loaded later in
16099 the link may change h->type. So fix it now. */
16104 }
16106 /* If this is a weak symbol, and there is a real definition, the
16107 processor independent code will have arranged for us to see the
16108 real definition first, and we can just use the same value. */
16110 {
16116 }
16118 /* If there are no non-GOT references, we do not need a copy
16119 relocation. */
16123 /* This is a reference to a symbol defined by a dynamic object which
16124 is not a function. */
16126 /* If we are creating a shared library, we must presume that the
16127 only references to the symbol are via the global offset table.
16128 For such cases we need not do anything here; the relocations will
16129 be handled correctly by relocate_section. Relocatable executables
16130 can reference data in shared objects directly, so we don't need to
16131 do anything here. */
16135 /* We must allocate the symbol in our .dynbss section, which will
16136 become part of the .bss section of the executable. There will be
16137 an entry for this symbol in the .dynsym section. The dynamic
16138 object will contain position independent code, so all references
16139 from the dynamic object to this symbol will go through the global
16140 offset table. The dynamic linker will use the .dynsym entry to
16141 determine the address it must put in the global offset table, so
16142 both the dynamic object and the regular object will refer to the
16143 same memory location for the variable. */
16144 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16145 linker to copy the initial value out of the dynamic object and into
16146 the runtime process image. We need to remember the offset into the
16147 .rel(a).bss section we are going to use. */
16149 {
16152 }
16153 else
16154 {
16157 }
16161 {
16164 }
16167 }
16169 /* Allocate space in .plt, .got and associated reloc sections for
16170 dynamic relocs. */
16172 static bool
16174 {
16192 {
16193 /* Make sure this symbol is output as a dynamic symbol.
16194 Undefined weak syms won't yet be marked as dynamic. */
16197 {
16200 }
16202 /* If the call in the PLT entry binds locally, the associated
16203 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16204 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16205 than the .plt section. */
16207 {
16211 /* All non-call references can be resolved directly.
16212 This means that they can (and in some cases, must)
16213 resolve directly to the run-time target, rather than
16214 to the PLT. That in turns means that any .got entry
16215 would be equal to the .igot.plt entry, so there's
16216 no point having both. */
16218 }
16223 {
16226 /* If this symbol is not defined in a regular file, and we are
16227 not generating a shared library, then set the symbol to this
16228 location in the .plt. This is required to make function
16229 pointers compare as equal between the normal executable and
16230 the shared library. */
16233 {
16237 /* Make sure the function is not marked as Thumb, in case
16238 it is the target of an ABS32 relocation, which will
16239 point to the PLT entry. */
16241 }
16243 /* VxWorks executables have a second set of relocations for
16244 each PLT entry. They go in a separate relocation section,
16245 which is processed by the kernel loader. */
16247 {
16248 /* There is a relocation for the initial PLT entry:
16249 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16253 /* There are two extra relocations for each subsequent
16254 PLT entry: an R_ARM_32 relocation for the GOT entry,
16255 and an R_ARM_32 relocation for the PLT entry. */
16257 }
16258 }
16259 else
16260 {
16263 }
16264 }
16265 else
16266 {
16269 }
16275 {
16281 /* Make sure this symbol is output as a dynamic symbol.
16282 Undefined weak syms won't yet be marked as dynamic. */
16287 {
16290 }
16299 /* Non-TLS symbols need one GOT slot. */
16301 else
16302 {
16304 {
16305 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16306 eh->tlsdesc_got
16311 /* plt.got_offset needs to know there's a TLS_DESC
16312 reloc in the middle of .got.plt. */
16314 }
16317 {
16318 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16319 consecutive GOT slots. If the symbol is both GD
16320 and GDESC, got.offset may have been
16321 overwritten. */
16324 }
16327 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16328 slot. */
16330 }
16344 {
16352 {
16354 /* GDESC needs a trampoline to jump to. */
16356 }
16358 /* Only GD needs it. GDESC just emits one relocation per
16359 2 entries. */
16362 }
16365 {
16367 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16369 }
16372 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16373 they all resolve dynamically instead. Reserve room for the
16374 GOT entry's R_ARM_IRELATIVE relocation. */
16378 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16381 /* Reserve room for rofixup for FDPIC executable. */
16382 /* TLS relocs do not need space since they are completely
16383 resolved. */
16385 }
16386 else
16389 /* FDPIC support. */
16391 {
16392 /* Symbol musn't be exported. */
16396 /* We only allocate one function descriptor with its associated
16397 relocation. */
16399 {
16404 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16407 else
16409 }
16410 }
16413 {
16422 {
16423 /* We only allocate one function descriptor with its
16424 associated relocation. */
16426 {
16430 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16431 rofixups. */
16434 else
16436 }
16437 }
16439 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16440 R_ARM_RELATIVE/rofixup relocation on it. */
16445 else
16447 }
16450 {
16457 {
16458 /* We only allocate one function descriptor with its
16459 associated relocation. */
16461 {
16466 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16467 rofixups. */
16470 else
16472 }
16473 }
16475 {
16476 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16478 }
16479 else
16480 {
16481 /* Will need one dynamic reloc per reference. will be either
16482 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16485 }
16486 }
16488 /* Allocate stubs for exported Thumb functions on v4t. */
16493 {
16500 /* Create a new symbol to regist the real location of the function. */
16514 /* Point the symbol at the stub. */
16519 }
16524 /* In the shared -Bsymbolic case, discard space allocated for
16525 dynamic pc-relative relocs against symbols which turn out to be
16526 defined in regular objects. For the normal shared case, discard
16527 space for pc-relative relocs that have become local due to symbol
16528 visibility changes. */
16533 {
16534 /* Relocs that use pc_count are PC-relative forms, which will appear
16535 on something like ".long foo - ." or "movw REG, foo - .". We want
16536 calls to protected symbols to resolve directly to the function
16537 rather than going via the plt. If people want function pointer
16538 comparisons to work as expected then they should avoid writing
16539 assembly like ".long foo - .". */
16541 {
16545 {
16550 else
16552 }
16553 }
16556 {
16560 {
16563 else
16565 }
16566 }
16568 /* Also discard relocs on undefined weak syms with non-default
16569 visibility. */
16572 {
16577 /* Make sure undefined weak symbols are output as a dynamic
16578 symbol in PIEs. */
16581 {
16584 }
16585 }
16589 {
16590 /* Output absolute symbols so that we can create relocations
16591 against them. For normal symbols we output a relocation
16592 against the section that contains them. */
16595 }
16597 }
16598 else
16599 {
16600 /* For the non-shared case, discard space for relocs against
16601 symbols which turn out to need copy relocs or are not
16602 dynamic. */
16610 {
16611 /* Make sure this symbol is output as a dynamic symbol.
16612 Undefined weak syms won't yet be marked as dynamic. */
16615 {
16618 }
16620 /* If that succeeded, we know we'll be keeping all the
16621 relocs. */
16624 }
16628 keep: ;
16629 }
16631 /* Finally, allocate space. */
16633 {
16645 else
16647 }
16650 }
16652 void
16655 {
16663 }
16665 /* Set the sizes of the dynamic sections. */
16667 static bool
16670 {
16686 {
16687 /* Set the contents of the .interp section to the interpreter. */
16689 {
16694 }
16695 }
16697 /* Set up .got offsets for local syms, and space for local dynamic
16698 relocs. */
16700 {
16706 bfd_size_type locsymcount;
16716 {
16721 {
16724 {
16725 /* Input section has been discarded, either because
16726 it is a copy of a linkonce section or due to
16727 linker script /DISCARD/, so we'll be discarding
16728 the relocs too. */
16729 }
16733 {
16734 /* Relocations in vxworks .tls_vars sections are
16735 handled specially by the loader. */
16736 }
16738 {
16742 else
16746 }
16747 }
16748 }
16767 {
16774 /* FDPIC support. */
16776 {
16778 {
16782 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16785 else
16787 }
16788 }
16791 {
16793 {
16797 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16800 else
16802 }
16804 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16807 else
16809 }
16812 {
16816 {
16821 /* All references to the PLT are calls, so all
16822 non-call references can resolve directly to the
16823 run-time target. This means that the .got entry
16824 would be the same as the .igot.plt entry, so there's
16825 no point creating both. */
16827 }
16828 else
16829 {
16832 }
16835 {
16841 else
16843 }
16844 }
16846 {
16851 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16854 {
16859 /* plt.got_offset needs to know there's a TLS_DESC
16860 reloc in the middle of .got.plt. */
16862 }
16867 {
16868 /* If the symbol is both GD and GDESC, *local_got
16869 may have been overwritten. */
16872 }
16875 symndx);
16879 /* If all references to an STT_GNU_IFUNC PLT are calls,
16880 then all non-call references, including this GOT entry,
16881 resolve directly to the run-time target. */
16887 {
16895 {
16899 }
16900 }
16901 }
16902 else
16904 }
16905 }
16908 {
16909 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16910 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
16915 }
16916 else
16919 /* At the very end of the .rofixup section is a pointer to the GOT,
16920 reserve space for it. */
16924 /* Allocate global sym .plt and .got entries, and space for global
16925 sym dynamic relocs. */
16928 /* Here we rummage through the found bfds to collect glue information. */
16930 {
16934 /* Initialise mapping tables for code/data. */
16941 }
16943 /* Allocate space for the glue sections now that we've sized them. */
16946 /* For every jump slot reserved in the sgotplt, reloc_count is
16947 incremented. However, when we reserve space for TLS descriptors,
16948 it's not incremented, so in order to compute the space reserved
16949 for them, it suffices to multiply the reloc count by the jump
16950 slot size. */
16955 {
16962 /* If we're not using lazy TLS relocations, don't generate the
16963 PLT and GOT entries they require. */
16966 else
16967 {
16973 }
16974 }
16976 /* The check_relocs and adjust_dynamic_symbol entry points have
16977 determined the sizes of the various dynamic sections. Allocate
16978 memory for them. */
16981 {
16987 /* It's OK to base decisions on the section name, because none
16988 of the dynobj section names depend upon the input files. */
16992 {
16993 /* Remember whether there is a PLT. */
16994 ;
16995 }
16997 {
16999 {
17000 /* Remember whether there are any reloc sections other
17001 than .rel(a).plt and .rela.plt.unloaded. */
17005 /* We use the reloc_count field as a counter if we need
17006 to copy relocs into the output file. */
17008 }
17009 }
17017 {
17018 /* It's not one of our sections, so don't allocate space. */
17020 }
17023 {
17024 /* If we don't need this section, strip it from the
17025 output file. This is mostly to handle .rel(a).bss and
17026 .rel(a).plt. We must create both sections in
17027 create_dynamic_sections, because they must be created
17028 before the linker maps input sections to output
17029 sections. The linker does that before
17030 adjust_dynamic_symbol is called, and it is that
17031 function which decides whether anything needs to go
17032 into these sections. */
17035 }
17040 /* Allocate memory for the section contents. */
17044 }
17047 relocs);
17048 }
17050 /* Size sections even though they're not dynamic. We use it to setup
17051 _TLS_MODULE_BASE_, if needed. */
17053 static bool
17056 {
17068 {
17071 tlsbase = elf_link_hash_lookup
17075 {
17091 }
17092 }
17100 }
17102 /* Finish up dynamic symbol handling. We set the contents of various
17103 dynamic sections here. */
17105 static bool
17110 {
17121 {
17123 {
17128 }
17131 {
17132 /* Mark the symbol as undefined, rather than as defined in
17133 the .plt section. */
17135 /* If the symbol is weak we need to clear the value.
17136 Otherwise, the PLT entry would provide a definition for
17137 the symbol even if the symbol wasn't defined anywhere,
17138 and so the symbol would never be NULL. Leave the value if
17139 there were any relocations where pointer equality matters
17140 (this is a clue for the dynamic linker, to make function
17141 pointer comparisons work between an application and shared
17142 library). */
17145 }
17147 {
17148 /* At least one non-call relocation references this .iplt entry,
17149 so the .iplt entry is the function's canonical address. */
17157 }
17158 }
17161 {
17163 Elf_Internal_Rela rel;
17165 /* This symbol needs a copy reloc. Set it up. */
17177 else
17180 }
17182 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17183 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17184 it is relative to the ".got" section. */
17192 }
17194 static void
17198 {
17202 {
17205 /* Emit mov pc,rx if bx is not permitted. */
17209 }
17210 }
17212 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17213 other variants, NaCl needs this entry in a static executable's
17214 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17215 zero. For .iplt really only the last bundle is useful, and .iplt
17216 could have a shorter first entry, with each individual PLT entry's
17217 relative branch calculated differently so it targets the last
17218 bundle instead of the instruction before it (labelled .Lplt_tail
17219 above). But it's simpler to keep the size and layout of PLT0
17220 consistent with the dynamic case, at the cost of some dead code at
17221 the start of .iplt and the one dead store to the stack at the start
17222 of .Lplt_tail. */
17223 static void
17226 {
17242 }
17244 /* Finish up the dynamic sections. */
17246 static bool
17248 {
17261 /* A broken linker script might have discarded the dynamic sections.
17262 Catch this here so that we do not seg-fault later on. */
17268 {
17280 {
17281 Elf_Internal_Dyn dyn;
17288 {
17308 get_vma:
17311 {
17312 _bfd_error_handler
17316 }
17348 /* Set the bottom bit of DT_INIT/FINI if the
17349 corresponding function is Thumb. */
17355 get_sym:
17356 /* If it wasn't set by elf_bfd_final_link
17357 then there is nothing to adjust. */
17359 {
17367 {
17370 }
17371 }
17373 }
17374 }
17376 /* Fill in the first entry in the procedure linkage table. */
17378 {
17382 /* Calculate the addresses of the GOT and PLT. */
17387 {
17388 /* The VxWorks GOT is relocated by the dynamic linker.
17389 Therefore, we must emit relocations rather than simply
17390 computing the values now. */
17391 Elf_Internal_Rela rel;
17402 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17408 }
17413 {
17425 }
17426 else
17427 {
17440 #ifdef FOUR_WORD_PLT
17441 /* The displacement value goes in the otherwise-unused
17442 last word of the second entry. */
17444 #else
17446 #endif
17447 }
17448 }
17450 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17451 really seem like the right value. */
17456 {
17457 bfd_vma got_address
17461 bfd_vma plt_address
17477 }
17480 {
17484 #ifdef FOUR_WORD_PLT
17487 #endif
17488 }
17493 {
17494 /* Correct the .rel(a).plt.unloaded relocations. They will have
17495 incorrect symbol indexes. */
17504 {
17505 Elf_Internal_Rela rel;
17516 }
17517 }
17518 }
17523 /* NaCl uses a special first entry in .iplt too. */
17526 /* Fill in the first three entries in the global offset table. */
17528 {
17530 {
17533 else
17539 }
17542 }
17544 /* At the very end of the .rofixup section is a pointer to the GOT. */
17546 {
17555 /* Make sure we allocated and generated the same number of fixups. */
17557 }
17560 }
17562 static bool
17564 {
17579 {
17586 }
17590 {
17594 else
17596 }
17598 /* Scan segment to set p_flags attribute if it contains only sections with
17599 SHF_ARM_PURECODE flag. */
17601 {
17607 {
17610 }
17612 {
17615 }
17616 }
17618 }
17620 static enum elf_reloc_type_class
17624 {
17626 {
17637 }
17638 }
17640 static void
17642 {
17644 }
17646 static bool
17648 {
17651 }
17653 /* Return TRUE if this is an unwinding table entry. */
17655 static bool
17657 {
17660 }
17663 /* Set the type and flags for an ARM section. We do this by
17664 the section name, which is a hack, but ought to work. */
17666 static bool
17668 {
17674 {
17677 }
17683 }
17685 /* Handle an ARM specific section when reading an object file. This is
17686 called when bfd_section_from_shdr finds a section with an unknown
17687 type. */
17689 static bool
17694 {
17695 /* There ought to be a place to keep ELF backend specific flags, but
17696 at the moment there isn't one. We just keep track of the
17697 sections by their name, instead. Fortunately, the ABI gives
17698 names for all the ARM specific sections, so we will probably get
17699 away with this. */
17701 {
17709 }
17715 }
17719 {
17722 else
17724 }
17727 {
17736 enum map_symbol_type
17737 {
17738 ARM_MAP_ARM,
17739 ARM_MAP_THUMB,
17740 ARM_MAP_DATA
17741 };
17744 /* Output a single mapping symbol. */
17746 static bool
17749 bfd_vma offset)
17750 {
17752 Elf_Internal_Sym sym;
17764 }
17766 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17767 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17769 static bool
17774 {
17786 {
17789 }
17790 else
17791 {
17794 }
17800 {
17809 }
17811 {
17814 }
17816 {
17818 ? ARM_MAP_THUMB
17831 }
17833 {
17836 }
17837 else
17838 {
17843 {
17846 }
17847 #ifdef FOUR_WORD_PLT
17852 #else
17853 /* A three-word PLT with no Thumb thunk contains only Arm code,
17854 so only need to output a mapping symbol for the first PLT entry and
17855 entries with thumb thunks. */
17857 {
17860 }
17861 #endif
17862 }
17865 }
17867 /* Output mapping symbols for PLT entries associated with H. */
17869 static bool
17871 {
17879 /* When warning symbols are created, they **replace** the "real"
17880 entry in the hash table, thus we never get to see the real
17881 symbol in a hash traversal. So look at it now. */
17887 }
17889 /* Bind a veneered symbol to its veneer identified by its hash entry
17890 STUB_ENTRY. The veneered location thus loose its symbol. */
17892 static void
17894 {
17901 }
17903 /* Output a single local symbol for a generated stub. */
17905 static bool
17908 {
17909 Elf_Internal_Sym sym;
17920 }
17922 static bool
17925 {
17928 bfd_vma addr;
17937 /* Massage our args to the form they really have. */
17943 /* Ensure this stub is attached to the current section being
17944 processed. */
17953 else
17954 {
17957 {
17972 }
17973 }
17978 {
17980 {
17997 }
18000 {
18004 }
18007 {
18024 }
18025 }
18028 }
18030 /* Output mapping symbols for linker generated sections,
18031 and for those data-only sections that do not have a
18032 $d. */
18034 static bool
18039 Elf_Internal_Sym *,
18040 asection *,
18042 {
18043 output_arch_syminfo osi;
18045 bfd_vma offset;
18046 bfd_size_type size;
18059 /* Add a $d mapping symbol to data-only sections that
18060 don't have any mapping symbol. This may result in (harmless) redundant
18061 mapping symbols. */
18065 {
18070 {
18075 == SEC_HAS_CONTENTS
18080 {
18085 }
18086 }
18087 }
18089 /* ARM->Thumb glue. */
18091 {
18093 ARM2THUMB_GLUE_SECTION_NAME);
18102 else
18106 {
18109 }
18110 }
18112 /* Thumb->ARM glue. */
18114 {
18116 THUMB2ARM_GLUE_SECTION_NAME);
18123 {
18126 }
18127 }
18129 /* ARMv4 BX veneers. */
18131 {
18133 ARM_BX_GLUE_SECTION_NAME);
18139 }
18141 /* Long calls stubs. */
18143 {
18149 {
18150 /* Ignore non-stub sections. */
18160 }
18161 }
18163 /* Finally, output mapping symbols for the PLT. */
18165 {
18170 /* Output mapping symbols for the plt header. */
18172 {
18173 /* VxWorks shared libraries have no PLT header. */
18175 {
18180 }
18181 }
18183 {
18186 }
18188 {
18195 }
18197 {
18200 #ifndef FOUR_WORD_PLT
18203 #endif
18204 }
18205 }
18209 {
18210 /* NaCl uses a special first entry in .iplt too. */
18216 }
18219 {
18224 {
18230 {
18233 {
18236 input_bfd,
18238 num_syms);
18240 }
18247 }
18248 }
18249 }
18251 {
18252 /* Mapping symbols for the lazy tls trampoline. */
18260 }
18262 {
18263 /* Mapping symbols for the tls trampoline. */
18266 #ifdef FOUR_WORD_PLT
18270 #endif
18271 }
18274 }
18276 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18277 the import library. All SYMCOUNT symbols of ABFD can be examined
18278 from their pointers in SYMS. Pointers of symbols to keep should be
18279 stored continuously at the beginning of that array.
18281 Returns the number of symbols to keep. */
18283 static unsigned int
18287 {
18302 {
18305 flagword flags;
18320 {
18324 }
18336 }
18342 }
18344 /* Filter symbols of ABFD to include in the import library. All
18345 SYMCOUNT symbols of ABFD can be examined from their pointers in
18346 SYMS. Pointers of symbols to keep should be stored continuously at
18347 the beginning of that array.
18349 Returns the number of symbols to keep. */
18351 static unsigned int
18355 {
18358 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18359 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18360 library to be a relocatable object file. */
18364 else
18366 }
18368 /* Allocate target specific section data. */
18370 static bool
18372 {
18374 {
18382 }
18385 }
18388 /* Used to order a list of mapping symbols by address. */
18390 static int
18392 {
18401 /* Ensure results do not depend on the host qsort for objects with
18402 multiple mapping symbols at the same address by sorting on type
18403 after vma. */
18407 else
18409 }
18411 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18413 static unsigned long
18415 {
18417 }
18419 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18420 relocations. */
18422 static void
18424 {
18428 /* High bit of first word is supposed to be zero. */
18432 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18433 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18439 }
18441 /* Data for make_branch_to_a8_stub(). */
18443 struct a8_branch_to_stub_data
18444 {
18447 };
18450 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18451 places for a particular section. */
18453 static bool
18456 {
18462 bfd_signed_vma branch_offset;
18475 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18476 generated when both source and target are in the same section. */
18493 /* We attempt to avoid this condition by setting stubs_always_after_branch
18494 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18495 This check is just to be on the safe side... */
18497 {
18501 }
18504 {
18515 {
18520 jump24:
18522 {
18523 /* There's not much we can do apart from complain if this
18524 happens. */
18528 }
18530 /* i1 = not(j1 eor s), so:
18531 not i1 = j1 eor s
18532 j1 = (not i1) eor s. */
18544 }
18550 }
18556 }
18558 /* Beginning of stm32l4xx work-around. */
18560 /* Functions encoding instructions necessary for the emission of the
18561 fix-stm32l4xx-629360.
18562 Encoding is extracted from the
18563 ARM (C) Architecture Reference Manual
18564 ARMv7-A and ARMv7-R edition
18565 ARM DDI 0406C.b (ID072512). */
18569 {
18570 /* A8.8.18 B (A8-334)
18571 B target_address (Encoding T4). */
18572 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18573 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18574 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18591 }
18595 {
18596 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18597 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18604 }
18608 {
18609 /* A8.8.60 LDMDB/LDMEA (A8-402)
18610 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18617 }
18621 {
18622 /* A8.8.103 MOV (register) (A8-486)
18623 MOV Rd, Rm (Encoding T1). */
18630 }
18634 {
18635 /* A8.8.221 SUB (immediate) (A8-708)
18636 SUB Rd, Rn, #value (Encoding T3). */
18646 }
18651 {
18652 /* A8.8.332 VLDM (A8-922)
18653 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18662 }
18667 {
18668 /* A8.8.332 VLDM (A8-922)
18669 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18677 }
18681 {
18682 /* A8.8.247 UDF (A8-758)
18683 Undefined (Encoding T2). */
18689 }
18693 {
18694 /* A8.8.247 UDF (A8-758)
18695 Undefined (Encoding T1). */
18700 }
18702 /* Functions writing an instruction in memory, returning the next
18703 memory position to write to. */
18708 {
18711 }
18716 {
18719 }
18721 /* Function filling up a region in memory with T1 and T2 UDFs taking
18722 care of alignment. */
18730 {
18733 /* Fill the remaining of the stub with deterministic contents : UDF
18734 instructions.
18735 Check if realignment is needed on modulo 4 frontier using T1, to
18736 further use T2. */
18740 current_stub_contents =
18745 current_stub_contents =
18750 }
18752 /* Functions writing the stream of instructions equivalent to the
18753 derived sequence for ldmia, ldmdb, vldm respectively. */
18755 static void
18761 {
18774 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18775 smaller than 8 registers load sequences that do not cause the
18776 hardware issue. */
18778 {
18779 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18780 current_stub_contents =
18782 initial_insn);
18784 /* B initial_insn_addr+4. */
18786 current_stub_contents =
18788 create_instruction_branch_absolute
18791 /* Fill the remaining of the stub with deterministic contents. */
18792 current_stub_contents =
18795 base_stub_contents +
18796 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18799 }
18801 /* - reg_list[13] == 0. */
18804 /* - reg_list[14] & reg_list[15] != 1. */
18807 /* - if (wback==1) reg_list[rn] == 0. */
18810 /* - nb_registers > 8. */
18813 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18815 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18816 - One with the 7 lowest registers (register mask 0x007F)
18817 This LDM will finally contain between 2 and 7 registers
18818 - One with the 7 highest registers (register mask 0xDF80)
18819 This ldm will finally contain between 2 and 7 registers. */
18823 /* A spare register may be needed during this veneer to temporarily
18824 handle the base register. This register will be restored with the
18825 last LDM operation.
18826 The usable register may be any general purpose register (that
18827 excludes PC, SP, LR : register mask is 0x1FFF). */
18830 /* Generate the stub function. */
18832 {
18833 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18834 current_stub_contents =
18836 create_instruction_ldmia
18839 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18840 current_stub_contents =
18842 create_instruction_ldmia
18845 {
18846 /* B initial_insn_addr+4. */
18847 current_stub_contents =
18849 create_instruction_branch_absolute
18851 }
18852 }
18854 {
18857 /* If Rn is not part of the high-register-list, move it there. */
18859 {
18860 /* Choose a Ri in the high-register-list that will be restored. */
18863 /* MOV Ri, Rn. */
18864 current_stub_contents =
18867 }
18869 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18870 current_stub_contents =
18872 create_instruction_ldmia
18875 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18876 current_stub_contents =
18878 create_instruction_ldmia
18882 {
18883 /* B initial_insn_addr+4. */
18884 current_stub_contents =
18886 create_instruction_branch_absolute
18888 }
18889 }
18891 /* Fill the remaining of the stub with deterministic contents. */
18892 current_stub_contents =
18895 base_stub_contents +
18896 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18897 }
18899 static void
18905 {
18918 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18919 smaller than 8 registers load sequences that do not cause the
18920 hardware issue. */
18922 {
18923 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18924 current_stub_contents =
18926 initial_insn);
18928 /* B initial_insn_addr+4. */
18929 current_stub_contents =
18931 create_instruction_branch_absolute
18934 /* Fill the remaining of the stub with deterministic contents. */
18935 current_stub_contents =
18938 base_stub_contents +
18939 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18942 }
18944 /* - reg_list[13] == 0. */
18947 /* - reg_list[14] & reg_list[15] != 1. */
18950 /* - if (wback==1) reg_list[rn] == 0. */
18953 /* - nb_registers > 8. */
18956 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18958 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18959 - One with the 7 lowest registers (register mask 0x007F)
18960 This LDM will finally contain between 2 and 7 registers
18961 - One with the 7 highest registers (register mask 0xDF80)
18962 This ldm will finally contain between 2 and 7 registers. */
18966 /* A spare register may be needed during this veneer to temporarily
18967 handle the base register. This register will be restored with
18968 the last LDM operation.
18969 The usable register may be any general purpose register (that excludes
18970 PC, SP, LR : register mask is 0x1FFF). */
18973 /* Generate the stub function. */
18975 {
18976 /* Choose a Ri in the low-register-list that will be restored. */
18979 /* MOV Ri, Rn. */
18980 current_stub_contents =
18984 /* LDMDB Ri!, {R-high-register-list}. */
18985 current_stub_contents =
18987 create_instruction_ldmdb
18990 /* LDMDB Ri, {R-low-register-list}. */
18991 current_stub_contents =
18993 create_instruction_ldmdb
18996 /* B initial_insn_addr+4. */
18997 current_stub_contents =
18999 create_instruction_branch_absolute
19001 }
19003 {
19004 /* LDMDB Rn!, {R-high-register-list}. */
19005 current_stub_contents =
19007 create_instruction_ldmdb
19010 /* LDMDB Rn!, {R-low-register-list}. */
19011 current_stub_contents =
19013 create_instruction_ldmdb
19016 /* B initial_insn_addr+4. */
19017 current_stub_contents =
19019 create_instruction_branch_absolute
19021 }
19023 {
19024 /* Choose a Ri in the high-register-list that will be restored. */
19027 /* SUB Ri, Rn, #(4*nb_registers). */
19028 current_stub_contents =
19032 /* LDMIA Ri!, {R-low-register-list}. */
19033 current_stub_contents =
19035 create_instruction_ldmia
19038 /* LDMIA Ri, {R-high-register-list}. */
19039 current_stub_contents =
19041 create_instruction_ldmia
19043 }
19045 {
19046 /* Choose a Ri in the high-register-list that will be restored. */
19049 /* SUB Rn, Rn, #(4*nb_registers) */
19050 current_stub_contents =
19054 /* MOV Ri, Rn. */
19055 current_stub_contents =
19059 /* LDMIA Ri!, {R-low-register-list}. */
19060 current_stub_contents =
19062 create_instruction_ldmia
19065 /* LDMIA Ri, {R-high-register-list}. */
19066 current_stub_contents =
19068 create_instruction_ldmia
19070 }
19072 {
19075 {
19076 /* Choose a Ri in the low-register-list that will be restored. */
19079 /* MOV Ri, Rn. */
19080 current_stub_contents =
19083 }
19085 /* LDMDB Ri!, {R-high-register-list}. */
19086 current_stub_contents =
19088 create_instruction_ldmdb
19091 /* LDMDB Ri, {R-low-register-list}. */
19092 current_stub_contents =
19094 create_instruction_ldmdb
19097 /* B initial_insn_addr+4. */
19098 current_stub_contents =
19100 create_instruction_branch_absolute
19102 }
19104 {
19107 {
19108 /* Choose a Ri in the high-register-list that will be restored. */
19110 }
19112 /* SUB Ri, Rn, #(4*nb_registers). */
19113 current_stub_contents =
19117 /* LDMIA Ri!, {R-low-register-list}. */
19118 current_stub_contents =
19120 create_instruction_ldmia
19123 /* LDMIA Ri, {R-high-register-list}. */
19124 current_stub_contents =
19126 create_instruction_ldmia
19128 }
19130 {
19131 /* The assembler should not have accepted to encode this. */
19134 }
19136 /* Fill the remaining of the stub with deterministic contents. */
19137 current_stub_contents =
19140 base_stub_contents +
19141 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19143 }
19145 static void
19151 {
19157 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19158 smaller than 8 words load sequences that do not cause the
19159 hardware issue. */
19161 {
19162 /* Untouched instruction. */
19163 current_stub_contents =
19165 initial_insn);
19167 /* B initial_insn_addr+4. */
19168 current_stub_contents =
19170 create_instruction_branch_absolute
19172 }
19173 else
19174 {
19184 /* d = UInt (Vd:D);. */
19188 /* Compute the number of 8-words chunks needed to split. */
19192 /* The test coverage has been done assuming the following
19193 hypothesis that exactly one of the previous is_ predicates is
19194 true. */
19198 /* We treat the cutting of the words in one pass for all
19199 cases, then we emit the adjustments:
19201 vldm rx, {...}
19202 -> vldm rx!, {8_words_or_less} for each needed 8_word
19203 -> sub rx, rx, #size (list)
19205 vldm rx!, {...}
19206 -> vldm rx!, {8_words_or_less} for each needed 8_word
19207 This also handles vpop instruction (when rx is sp)
19209 vldmd rx!, {...}
19210 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19212 {
19216 {
19217 new_insn = create_instruction_vldmia
19219 is_dp,
19224 }
19226 {
19227 new_insn = create_instruction_vldmdb
19229 is_dp,
19233 }
19236 current_stub_contents =
19238 new_insn);
19239 }
19241 /* Only this case requires the base register compensation
19242 subtract. */
19244 {
19245 current_stub_contents =
19247 create_instruction_sub
19249 }
19251 /* B initial_insn_addr+4. */
19252 current_stub_contents =
19254 create_instruction_branch_absolute
19256 }
19258 /* Fill the remaining of the stub with deterministic contents. */
19259 current_stub_contents =
19262 base_stub_contents +
19263 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19264 }
19266 static void
19272 {
19276 stub_contents);
19280 stub_contents);
19284 stub_contents);
19285 }
19287 /* End of stm32l4xx work-around. */
19290 /* Do code byteswapping. Return FALSE afterwards so that the section is
19291 written out as normal. */
19293 static bool
19298 {
19305 bfd_vma ptr;
19306 bfd_vma end;
19308 bfd_byte tmp;
19314 /* If this section has not been allocated an _arm_elf_section_data
19315 structure then we cannot record anything. */
19325 {
19330 {
19334 {
19336 {
19337 bfd_vma branch_to_veneer;
19338 /* Original condition code of instruction, plus bit mask for
19339 ARM B instruction. */
19343 /* The instruction is before the label. */
19346 /* Above offset included in -4 below. */
19360 }
19364 {
19365 bfd_vma branch_from_veneer;
19368 /* Take size of veneer into account. */
19377 /* Original instruction. */
19384 /* Branch back to insn after original insn. */
19390 }
19395 }
19396 }
19397 }
19400 {
19404 {
19408 {
19410 {
19412 bfd_vma branch_to_veneer =
19417 {
19418 bfd_vma out_of_range =
19424 _bfd_error_handler
19426 "cannot create STM32L4XX veneer; "
19429 output_bfd,
19433 }
19435 insn = create_instruction_branch_absolute
19438 /* The instruction is before the label. */
19443 }
19447 {
19453 veneer_r = veneer
19458 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19459 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19460 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19463 {
19467 }
19469 /* Original instruction. */
19472 stm32l4xx_create_replacing_stub
19474 }
19479 }
19480 }
19481 }
19484 {
19485 arm_unwind_table_edit *edit_node
19487 /* Now, sec->size is the size of the section we will write. The original
19488 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19489 markers) was sec->rawsize. (This isn't the case if we perform no
19490 edits, then rawsize will be zero and we should use size). */
19499 {
19501 {
19505 {
19508 out_index++;
19509 in_index++;
19510 }
19514 {
19516 {
19518 in_index++;
19523 {
19531 /* Note: this is meant to be equivalent to an
19532 R_ARM_PREL31 relocation. These synthetic
19533 EXIDX_CANTUNWIND markers are not relocated by the
19534 usual BFD method. */
19538 {
19539 /* Here relocation for new EXIDX_CANTUNWIND is
19540 created, so there is no need to
19541 adjust offset by hand. */
19544 }
19546 /* First address we can't unwind. */
19550 /* Code for EXIDX_CANTUNWIND. */
19554 out_index++;
19556 }
19558 }
19561 }
19562 }
19563 else
19564 {
19565 /* No more edits, copy remaining entries verbatim. */
19568 out_index++;
19569 in_index++;
19570 }
19571 }
19575 edited_contents,
19579 }
19581 /* Fix code to point to Cortex-A8 erratum stubs. */
19583 {
19591 }
19597 {
19602 {
19605 else
19609 {
19611 /* Byte swap code words. */
19613 {
19621 }
19625 /* Byte swap code halfwords. */
19627 {
19632 }
19636 /* Leave data alone. */
19638 }
19640 }
19641 }
19649 }
19651 /* Mangle thumb function symbols as we read them in. */
19653 static bool
19658 {
19663 /* New EABI objects mark thumb function symbols by setting the low bit of
19664 the address. */
19667 {
19669 {
19672 ST_BRANCH_TO_THUMB);
19673 }
19674 else
19676 }
19678 {
19681 }
19684 else
19688 }
19691 /* Mangle thumb function symbols as we write them out. */
19693 static void
19698 {
19699 Elf_Internal_Sym newsym;
19701 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19702 of the address set, as per the new EABI. We do this unconditionally
19703 because objcopy does not set the elf header flags until after
19704 it writes out the symbol table. */
19706 {
19711 {
19712 /* Do this only for defined symbols. At link type, the static
19713 linker will simulate the work of dynamic linker of resolving
19714 symbols and will carry over the thumbness of found symbols to
19715 the output symbol table. It's not clear how it happens, but
19716 the thumbness of undefined symbols can well be different at
19717 runtime, and writing '1' for them will be confusing for users
19718 and possibly for dynamic linker itself.
19719 */
19721 }
19724 }
19726 }
19728 /* Add the PT_ARM_EXIDX program header. */
19730 static bool
19733 {
19739 {
19740 /* If there is already a PT_ARM_EXIDX header, then we do not
19741 want to add another one. This situation arises when running
19742 "strip"; the input binary already has the header. */
19747 {
19758 }
19759 }
19762 }
19764 /* We may add a PT_ARM_EXIDX program header. */
19766 static int
19769 {
19775 else
19777 }
19779 /* Hook called by the linker routine which adds symbols from an object
19780 file. */
19782 static bool
19786 {
19796 }
19798 /* We use this to override swap_symbol_in and swap_symbol_out. */
19800 {
19813 bfd_elf32_write_out_phdrs,
19814 bfd_elf32_write_shdrs_and_ehdr,
19815 bfd_elf32_checksum_contents,
19816 bfd_elf32_write_relocs,
19817 elf32_arm_swap_symbol_in,
19818 elf32_arm_swap_symbol_out,
19819 bfd_elf32_slurp_reloc_table,
19820 bfd_elf32_slurp_symbol_table,
19821 bfd_elf32_swap_dyn_in,
19822 bfd_elf32_swap_dyn_out,
19823 bfd_elf32_swap_reloc_in,
19824 bfd_elf32_swap_reloc_out,
19825 bfd_elf32_swap_reloca_in,
19826 bfd_elf32_swap_reloca_out
19827 };
19829 static bfd_vma
19831 {
19832 /* V7 BE8 code is always little endian. */
19837 }
19839 static bfd_vma
19841 {
19842 /* V7 BE8 code is always little endian. */
19847 }
19849 /* Return size of plt0 entry starting at ADDR
19850 or (bfd_vma) -1 if size can not be determined. */
19852 static bfd_vma
19854 {
19855 bfd_vma first_word;
19856 bfd_vma plt0_size;
19864 else
19865 /* We don't yet handle this PLT format. */
19869 }
19871 /* Return size of plt entry starting at offset OFFSET
19872 of plt section located at address START
19873 or (bfd_vma) -1 if size can not be determined. */
19875 static bfd_vma
19877 {
19878 bfd_vma first_insn;
19882 /* PLT entry size if fixed on Thumb-only platforms. */
19886 /* Respect Thumb stub if necessary. */
19888 {
19890 }
19892 /* Strip immediate from first add. */
19895 #ifdef FOUR_WORD_PLT
19898 #else
19903 #endif
19904 else
19905 /* We don't yet handle this PLT format. */
19909 }
19911 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19913 static long
19920 {
19929 bfd_vma offset;
19958 {
19962 }
19968 {
19972 }
19986 {
19994 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19995 we are defining a symbol, ensure one of them is set. */
20007 {
20014 ;
20018 }
20023 }
20026 }
20028 static bool
20030 {
20034 }
20036 static flagword
20038 {
20043 }
20045 static unsigned int
20047 {
20052 }
20054 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20055 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20056 FALSE otherwise. ISECTION is the best guess matching section from the
20057 input bfd IBFD, but it might be NULL. */
20059 static bool
20064 {
20066 {
20068 {
20076 /* The sh_link field must be set to the text section associated with
20077 this index section. Unfortunately the ARM EHABI does not specify
20078 exactly how to determine this association. Our caller does try
20079 to match up OSECTION with its corresponding input section however
20080 so that is a good first guess. */
20091 )
20092 {
20097 }
20100 {
20101 /* Failing that we have to find a matching section ourselves. If
20102 we had the output section name available we could compare that
20103 with input section names. Unfortunately we don't. So instead
20104 we use a simple heuristic and look for the nearest executable
20105 section before this one. */
20117 }
20120 {
20122 /* If the text section was part of a group
20123 then the index section should be too. */
20127 }
20128 }
20140 }
20143 }
20145 /* Returns TRUE if NAME is an ARM mapping symbol.
20146 Traditionally the symbols $a, $d and $t have been used.
20147 The ARM ELF standard also defines $x (for A64 code). It also allows a
20148 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20149 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20150 not support them here. $t.x indicates the start of ThumbEE instructions. */
20152 static bool
20154 {
20157 the mapping symbols could have acquired a prefix.
20158 We do not support this here, since such symbols no
20159 longer conform to the ARM ELF ABI. */
20162 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20163 any characters that follow the period are legal characters for the body
20164 of a symbol's name. For now we just assume that this is the case. */
20165 }
20167 /* Make sure that mapping symbols in object files are not removed via the
20168 "strip --strip-unneeded" tool. These symbols are needed in order to
20169 correctly generate interworking veneers, and for byte swapping code
20170 regions. Once an object file has been linked, it is safe to remove the
20171 symbols as they will no longer be needed. */
20173 static void
20175 {
20180 }
20182 #undef elf_backend_copy_special_section_fields
20183 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20185 #define ELF_ARCH bfd_arch_arm
20186 #define ELF_TARGET_ID ARM_ELF_DATA
20187 #define ELF_MACHINE_CODE EM_ARM
20188 #ifdef __QNXTARGET__
20189 #define ELF_MAXPAGESIZE 0x1000
20190 #else
20191 #define ELF_MAXPAGESIZE 0x10000
20192 #endif
20193 #define ELF_MINPAGESIZE 0x1000
20194 #define ELF_COMMONPAGESIZE 0x1000
20196 #define bfd_elf32_mkobject elf32_arm_mkobject
20198 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20199 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20200 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20201 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20202 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20203 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20204 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20205 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20206 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20207 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20208 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20209 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20211 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20212 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20213 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20214 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20215 #define elf_backend_check_relocs elf32_arm_check_relocs
20216 #define elf_backend_update_relocs elf32_arm_update_relocs
20217 #define elf_backend_relocate_section elf32_arm_relocate_section
20218 #define elf_backend_write_section elf32_arm_write_section
20219 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20220 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20221 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20222 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20223 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20224 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20225 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20226 #define elf_backend_init_file_header elf32_arm_init_file_header
20227 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20228 #define elf_backend_object_p elf32_arm_object_p
20229 #define elf_backend_fake_sections elf32_arm_fake_sections
20230 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20231 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20232 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20233 #define elf_backend_size_info elf32_arm_size_info
20234 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20235 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20236 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20237 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20238 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20239 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20240 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20241 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20243 #define elf_backend_can_refcount 1
20244 #define elf_backend_can_gc_sections 1
20245 #define elf_backend_plt_readonly 1
20246 #define elf_backend_want_got_plt 1
20247 #define elf_backend_want_plt_sym 0
20248 #define elf_backend_want_dynrelro 1
20249 #define elf_backend_may_use_rel_p 1
20250 #define elf_backend_may_use_rela_p 0
20251 #define elf_backend_default_use_rela_p 0
20252 #define elf_backend_dtrel_excludes_plt 1
20254 #define elf_backend_got_header_size 12
20255 #define elf_backend_extern_protected_data 1
20257 #undef elf_backend_obj_attrs_vendor
20259 #undef elf_backend_obj_attrs_section
20261 #undef elf_backend_obj_attrs_arg_type
20262 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20263 #undef elf_backend_obj_attrs_section_type
20264 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20265 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20266 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20268 #undef elf_backend_section_flags
20269 #define elf_backend_section_flags elf32_arm_section_flags
20270 #undef elf_backend_lookup_section_flags_hook
20271 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20273 #define elf_backend_linux_prpsinfo32_ugid16 true
20277 /* Native Client targets. */
20279 #undef TARGET_LITTLE_SYM
20280 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20281 #undef TARGET_LITTLE_NAME
20283 #undef TARGET_BIG_SYM
20284 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20285 #undef TARGET_BIG_NAME
20288 /* Like elf32_arm_link_hash_table_create -- but overrides
20289 appropriately for NaCl. */
20293 {
20298 {
20304 }
20306 }
20308 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20309 really need to use elf32_arm_modify_segment_map. But we do it
20310 anyway just to reduce gratuitous differences with the stock ARM backend. */
20312 static bool
20314 {
20317 }
20319 static bool
20321 {
20324 }
20326 static bfd_vma
20329 {
20333 }
20335 #undef elf32_bed
20336 #define elf32_bed elf32_arm_nacl_bed
20337 #undef bfd_elf32_bfd_link_hash_table_create
20338 #define bfd_elf32_bfd_link_hash_table_create \
20339 elf32_arm_nacl_link_hash_table_create
20340 #undef elf_backend_plt_alignment
20341 #define elf_backend_plt_alignment 4
20342 #undef elf_backend_modify_segment_map
20343 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20344 #undef elf_backend_modify_headers
20345 #define elf_backend_modify_headers nacl_modify_headers
20346 #undef elf_backend_final_write_processing
20347 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20348 #undef bfd_elf32_get_synthetic_symtab
20349 #undef elf_backend_plt_sym_val
20350 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20351 #undef elf_backend_copy_special_section_fields
20353 #undef ELF_MINPAGESIZE
20354 #undef ELF_COMMONPAGESIZE
20356 #undef ELF_TARGET_OS
20357 #define ELF_TARGET_OS is_nacl
20361 /* Reset to defaults. */
20362 #undef elf_backend_plt_alignment
20363 #undef elf_backend_modify_segment_map
20364 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20365 #undef elf_backend_modify_headers
20366 #undef elf_backend_final_write_processing
20367 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20368 #undef ELF_MINPAGESIZE
20369 #define ELF_MINPAGESIZE 0x1000
20370 #undef ELF_COMMONPAGESIZE
20371 #define ELF_COMMONPAGESIZE 0x1000
20374 /* FDPIC Targets. */
20376 #undef TARGET_LITTLE_SYM
20377 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20378 #undef TARGET_LITTLE_NAME
20380 #undef TARGET_BIG_SYM
20381 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20382 #undef TARGET_BIG_NAME
20384 #undef elf_match_priority
20385 #define elf_match_priority 128
20386 #undef ELF_OSABI
20387 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20389 /* Like elf32_arm_link_hash_table_create -- but overrides
20390 appropriately for FDPIC. */
20394 {
20399 {
20403 }
20405 }
20407 /* We need dynamic symbols for every section, since segments can
20408 relocate independently. */
20409 static bool
20412 ATTRIBUTE_UNUSED,
20414 {
20416 {
20419 /* If sh_type is yet undecided, assume it could be
20420 SHT_PROGBITS/SHT_NOBITS. */
20424 /* There shouldn't be section relative relocations
20425 against any other section. */
20428 }
20429 }
20431 #undef elf32_bed
20432 #define elf32_bed elf32_arm_fdpic_bed
20434 #undef bfd_elf32_bfd_link_hash_table_create
20435 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20437 #undef elf_backend_omit_section_dynsym
20438 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20440 #undef ELF_TARGET_OS
20444 #undef elf_match_priority
20445 #undef ELF_OSABI
20446 #undef elf_backend_omit_section_dynsym
20448 /* VxWorks Targets. */
20450 #undef TARGET_LITTLE_SYM
20451 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20452 #undef TARGET_LITTLE_NAME
20454 #undef TARGET_BIG_SYM
20455 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20456 #undef TARGET_BIG_NAME
20459 /* Like elf32_arm_link_hash_table_create -- but overrides
20460 appropriately for VxWorks. */
20464 {
20469 {
20473 }
20475 }
20477 static bool
20479 {
20482 }
20484 #undef elf32_bed
20485 #define elf32_bed elf32_arm_vxworks_bed
20487 #undef bfd_elf32_bfd_link_hash_table_create
20488 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20489 #undef elf_backend_final_write_processing
20490 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20491 #undef elf_backend_emit_relocs
20492 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20494 #undef elf_backend_may_use_rel_p
20495 #define elf_backend_may_use_rel_p 0
20496 #undef elf_backend_may_use_rela_p
20497 #define elf_backend_may_use_rela_p 1
20498 #undef elf_backend_default_use_rela_p
20499 #define elf_backend_default_use_rela_p 1
20500 #undef elf_backend_want_plt_sym
20501 #define elf_backend_want_plt_sym 1
20502 #undef ELF_MAXPAGESIZE
20503 #define ELF_MAXPAGESIZE 0x1000
20504 #undef ELF_TARGET_OS
20505 #define ELF_TARGET_OS is_vxworks
20510 /* Merge backend specific data from an object file to the output
20511 object file when linking. */
20513 static bool
20515 {
20517 flagword out_flags;
20518 flagword in_flags;
20522 /* Check if we have the same endianness. */
20532 /* The input BFD must have had its flags initialised. */
20533 /* The following seems bogus to me -- The flags are initialized in
20534 the assembler but I don't think an elf_flags_init field is
20535 written into the object. */
20536 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20541 /* In theory there is no reason why we couldn't handle this. However
20542 in practice it isn't even close to working and there is no real
20543 reason to want it. */
20547 {
20549 ibfd);
20551 }
20554 {
20555 /* If the input is the default architecture and had the default
20556 flags then do not bother setting the flags for the output
20557 architecture, instead allow future merges to do this. If no
20558 future merges ever set these flags then they will retain their
20559 uninitialised values, which surprise surprise, correspond
20560 to the default values. */
20573 }
20575 /* Determine what should happen if the input ARM architecture
20576 does not match the output ARM architecture. */
20580 /* Identical flags must be compatible. */
20584 /* Check to see if the input BFD actually contains any sections. If
20585 not, its flags may not have been initialised either, but it
20586 cannot actually cause any incompatiblity. Do not short-circuit
20587 dynamic objects; their section list may be emptied by
20588 elf_link_add_object_symbols.
20590 Also check to see if there are no code sections in the input.
20591 In this case there is no need to check for code specific flags.
20592 XXX - do we need to worry about floating-point format compatability
20593 in data sections ? */
20595 {
20600 {
20601 /* Ignore synthetic glue sections. */
20604 {
20612 }
20613 }
20617 }
20619 /* Complain about various flag mismatches. */
20622 {
20623 _bfd_error_handler
20628 }
20630 /* Not sure what needs to be checked for EABI versions >= 1. */
20631 /* VxWorks libraries do not use these flags. */
20635 {
20637 {
20638 _bfd_error_handler
20643 }
20646 {
20648 _bfd_error_handler
20649 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20651 else
20652 _bfd_error_handler
20653 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20657 }
20660 {
20662 _bfd_error_handler
20665 else
20666 _bfd_error_handler
20671 }
20674 {
20676 _bfd_error_handler
20679 else
20680 _bfd_error_handler
20685 }
20687 #ifdef EF_ARM_SOFT_FLOAT
20689 {
20690 /* We can allow interworking between code that is VFP format
20691 layout, and uses either soft float or integer regs for
20692 passing floating point arguments and results. We already
20693 know that the APCS_FLOAT flags match; similarly for VFP
20694 flags. */
20697 {
20699 _bfd_error_handler
20702 else
20703 _bfd_error_handler
20708 }
20709 }
20710 #endif
20712 /* Interworking mismatch is only a warning. */
20714 {
20716 {
20717 _bfd_error_handler
20720 }
20721 else
20722 {
20723 _bfd_error_handler
20726 }
20727 }
20728 }
20731 }