| blob | aba1814f8555933f8a98da214bd9708336da6000 |
1 /* 32-bit ELF support for ARM
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto 0
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1693 };
1695 /* 160 onwards: */
1697 {
1711 };
1713 /* 249-255 extended, currently unused, relocations: */
1715 {
1771 };
1775 {
1787 }
1789 static void
1792 {
1797 }
1799 struct elf32_arm_reloc_map
1800 {
1801 bfd_reloc_code_real_type bfd_reloc_val;
1803 };
1805 /* All entries in this list must also be present in elf32_arm_howto_table. */
1807 {
1894 };
1898 bfd_reloc_code_real_type code)
1899 {
1907 }
1912 {
1931 }
1933 /* Support for core dump NOTE sections. */
1935 static bfd_boolean
1937 {
1942 {
1947 /* pr_cursig */
1950 /* pr_pid */
1953 /* pr_reg */
1958 }
1960 /* Make a ".reg/999" section. */
1963 }
1965 static bfd_boolean
1967 {
1969 {
1980 }
1982 /* Note that for some reason, a spurious space is tacked
1983 onto the end of the args in some (at least one anyway)
1984 implementations, so strip it off if it exists. */
1985 {
1991 }
1994 }
1999 {
2001 {
2006 {
2018 }
2021 {
2040 }
2041 }
2042 }
2044 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
2046 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
2049 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2050 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2051 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2056 /* In lieu of proper flags, assume all EABIv4 or later objects are
2057 interworkable. */
2058 #define INTERWORK_FLAG(abfd) \
2059 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2060 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2061 || ((abfd)->flags & BFD_LINKER_CREATED))
2063 /* The linker script knows the section names for placement.
2064 The entry_names are used to do simple name mangling on the stubs.
2065 Given a function name, and its type, the stub can be found. The
2066 name can be changed. The only requirement is the %s be present. */
2081 /* The name of the dynamic interpreter. This is put in the .interp
2082 section. */
2086 {
2090 };
2093 {
2101 + dl_tlsdesc_lazy_resolver(GOT) */
2103 };
2105 #ifdef FOUR_WORD_PLT
2107 /* The first entry in a procedure linkage table looks like
2108 this. It is set up so that any shared library function that is
2109 called before the relocation has been set up calls the dynamic
2110 linker first. */
2112 {
2117 };
2119 /* Subsequent entries in a procedure linkage table look like
2120 this. */
2122 {
2127 };
2129 #else
2131 /* The first entry in a procedure linkage table looks like
2132 this. It is set up so that any shared library function that is
2133 called before the relocation has been set up calls the dynamic
2134 linker first. */
2136 {
2142 };
2144 /* Subsequent entries in a procedure linkage table look like
2145 this. */
2147 {
2151 };
2153 #endif
2155 /* The format of the first entry in the procedure linkage table
2156 for a VxWorks executable. */
2158 {
2163 };
2165 /* The format of subsequent entries in a VxWorks executable. */
2167 {
2174 };
2176 /* The format of entries in a VxWorks shared library. */
2178 {
2185 };
2187 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2188 #define PLT_THUMB_STUB_SIZE 4
2190 {
2193 };
2195 /* The entries in a PLT when using a DLL-based target with multiple
2196 address spaces. */
2198 {
2201 };
2203 /* The first entry in a procedure linkage table looks like
2204 this. It is set up so that any shared library function that is
2205 called before the relocation has been set up calls the dynamic
2206 linker first. */
2208 {
2209 /* First bundle: */
2214 /* Second bundle: */
2219 /* Third bundle: */
2223 /* .Lplt_tail: */
2225 /* Fourth bundle: */
2230 };
2231 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2233 /* Subsequent entries in a procedure linkage table look like this. */
2235 {
2240 };
2242 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2243 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2244 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2245 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2246 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2247 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2249 enum stub_insn_type
2250 {
2252 THUMB32_TYPE,
2253 ARM_TYPE,
2254 DATA_TYPE
2255 };
2257 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2258 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2259 is inserted in arm_build_one_stub(). */
2260 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2261 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2262 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2263 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2264 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2265 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2268 {
2269 bfd_vma data;
2275 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2276 to reach the stub if necessary. */
2278 {
2281 };
2283 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2284 available. */
2286 {
2290 };
2292 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2294 {
2302 };
2304 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2305 allowed. */
2307 {
2313 };
2315 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2316 available. */
2318 {
2323 };
2325 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2326 one, when the destination is close enough. */
2328 {
2332 };
2334 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2335 blx to reach the stub if necessary. */
2337 {
2341 };
2343 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2344 blx to reach the stub if necessary. We can not add into pc;
2345 it is not guaranteed to mode switch (different in ARMv6 and
2346 ARMv7). */
2348 {
2353 };
2355 /* V4T ARM -> ARM long branch stub, PIC. */
2357 {
2362 };
2364 /* V4T Thumb -> ARM long branch stub, PIC. */
2366 {
2372 };
2374 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2375 architectures. */
2377 {
2385 };
2387 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2388 allowed. */
2390 {
2397 };
2399 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2400 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2402 {
2406 };
2408 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2409 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2411 {
2417 };
2419 /* Cortex-A8 erratum-workaround stubs. */
2421 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2422 can't use a conditional branch to reach this stub). */
2425 {
2429 };
2431 /* Stub used for b.w and bl.w instructions. */
2434 {
2436 };
2439 {
2441 };
2443 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2444 instruction (which switches to ARM mode) to point to this stub. Jump to the
2445 real destination using an ARM-mode branch. */
2448 {
2450 };
2452 /* For each section group there can be a specially created linker section
2453 to hold the stubs for that group. The name of the stub section is based
2454 upon the name of another section within that group with the suffix below
2455 applied.
2457 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2458 create what appeared to be a linker stub section when it actually
2459 contained user code/data. For example, consider this fragment:
2461 const char * stubborn_problems[] = { "np" };
2463 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2464 section called:
2466 .data.rel.local.stubborn_problems
2468 This then causes problems in arm32_arm_build_stubs() as it triggers:
2470 // Ignore non-stub sections.
2471 if (!strstr (stub_sec->name, STUB_SUFFIX))
2472 continue;
2474 And so the section would be ignored instead of being processed. Hence
2475 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2476 C identifier. */
2479 /* One entry per long/short branch stub defined above. */
2480 #define DEF_STUBS \
2481 DEF_STUB(long_branch_any_any) \
2482 DEF_STUB(long_branch_v4t_arm_thumb) \
2483 DEF_STUB(long_branch_thumb_only) \
2484 DEF_STUB(long_branch_v4t_thumb_thumb) \
2485 DEF_STUB(long_branch_v4t_thumb_arm) \
2486 DEF_STUB(short_branch_v4t_thumb_arm) \
2487 DEF_STUB(long_branch_any_arm_pic) \
2488 DEF_STUB(long_branch_any_thumb_pic) \
2489 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2490 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2491 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2492 DEF_STUB(long_branch_thumb_only_pic) \
2493 DEF_STUB(long_branch_any_tls_pic) \
2494 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2495 DEF_STUB(a8_veneer_b_cond) \
2496 DEF_STUB(a8_veneer_b) \
2497 DEF_STUB(a8_veneer_bl) \
2498 DEF_STUB(a8_veneer_blx)
2500 #define DEF_STUB(x) arm_stub_##x,
2501 enum elf32_arm_stub_type
2502 {
2503 arm_stub_none,
2504 DEF_STUBS
2505 /* Note the first a8_veneer type */
2506 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2507 };
2508 #undef DEF_STUB
2511 {
2516 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2518 {
2520 DEF_STUBS
2521 };
2523 struct elf32_arm_stub_hash_entry
2524 {
2525 /* Base hash table entry structure. */
2528 /* The stub section. */
2531 /* Offset within stub_sec of the beginning of this stub. */
2532 bfd_vma stub_offset;
2534 /* Given the symbol's value and its section we can determine its final
2535 value when building the stubs (so the stub knows where to jump). */
2536 bfd_vma target_value;
2539 /* Offset to apply to relocation referencing target_value. */
2540 bfd_vma target_addend;
2542 /* The instruction which caused this stub to be generated (only valid for
2543 Cortex-A8 erratum workaround stubs at present). */
2546 /* The stub type. */
2548 /* Its encoding size in bytes. */
2550 /* Its template. */
2552 /* The size of the template (number of entries). */
2555 /* The symbol table entry, if any, that this was derived from. */
2558 /* Type of branch. */
2561 /* Where this stub is being called from, or, in the case of combined
2562 stub sections, the first input section in the group. */
2565 /* The name for the local symbol at the start of this stub. The
2566 stub name in the hash table has to be unique; this does not, so
2567 it can be friendlier. */
2569 };
2571 /* Used to build a map of a section. This is required for mixed-endian
2572 code/data. */
2575 {
2576 bfd_vma vma;
2578 }
2579 elf32_arm_section_map;
2581 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2584 {
2585 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2586 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2587 VFP11_ERRATUM_ARM_VENEER,
2588 VFP11_ERRATUM_THUMB_VENEER
2589 }
2590 elf32_vfp11_erratum_type;
2593 {
2595 bfd_vma vma;
2596 union
2597 {
2598 struct
2599 {
2603 struct
2604 {
2609 elf32_vfp11_erratum_type type;
2610 }
2611 elf32_vfp11_erratum_list;
2614 {
2615 DELETE_EXIDX_ENTRY,
2616 INSERT_EXIDX_CANTUNWIND_AT_END
2617 }
2618 arm_unwind_edit_type;
2620 /* A (sorted) list of edits to apply to an unwind table. */
2622 {
2623 arm_unwind_edit_type type;
2624 /* Note: we sometimes want to insert an unwind entry corresponding to a
2625 section different from the one we're currently writing out, so record the
2626 (text) section this edit relates to here. */
2630 }
2631 arm_unwind_table_edit;
2634 {
2635 /* Information about mapping symbols. */
2640 /* Information about CPU errata. */
2643 /* Information about unwind tables. */
2644 union
2645 {
2646 /* Unwind info attached to a text section. */
2647 struct
2648 {
2652 /* Unwind info attached to an .ARM.exidx section. */
2653 struct
2654 {
2659 }
2660 _arm_elf_section_data;
2662 #define elf32_arm_section_data(sec) \
2663 ((_arm_elf_section_data *) elf_section_data (sec))
2665 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2666 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2667 so may be created multiple times: we use an array of these entries whilst
2668 relaxing which we can refresh easily, then create stubs for each potentially
2669 erratum-triggering instruction once we've settled on a solution. */
2671 struct a8_erratum_fix
2672 {
2675 bfd_vma offset;
2676 bfd_vma addend;
2681 };
2683 /* A table of relocs applied to branches which might trigger Cortex-A8
2684 erratum. */
2686 struct a8_erratum_reloc
2687 {
2688 bfd_vma from;
2689 bfd_vma destination;
2694 bfd_boolean non_a8_stub;
2695 };
2697 /* The size of the thread control block. */
2698 #define TCB_SIZE 8
2700 /* ARM-specific information about a PLT entry, over and above the usual
2701 gotplt_union. */
2702 struct arm_plt_info
2703 {
2704 /* We reference count Thumb references to a PLT entry separately,
2705 so that we can emit the Thumb trampoline only if needed. */
2706 bfd_signed_vma thumb_refcount;
2708 /* Some references from Thumb code may be eliminated by BL->BLX
2709 conversion, so record them separately. */
2710 bfd_signed_vma maybe_thumb_refcount;
2712 /* How many of the recorded PLT accesses were from non-call relocations.
2713 This information is useful when deciding whether anything takes the
2714 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2715 non-call references to the function should resolve directly to the
2716 real runtime target. */
2719 /* Since PLT entries have variable size if the Thumb prologue is
2720 used, we need to record the index into .got.plt instead of
2721 recomputing it from the PLT offset. */
2722 bfd_signed_vma got_offset;
2723 };
2725 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2726 struct arm_local_iplt_info
2727 {
2728 /* The information that is usually found in the generic ELF part of
2729 the hash table entry. */
2732 /* The information that is usually found in the ARM-specific part of
2733 the hash table entry. */
2736 /* A list of all potential dynamic relocations against this symbol. */
2738 };
2740 struct elf_arm_obj_tdata
2741 {
2744 /* tls_type for each local got entry. */
2747 /* GOTPLT entries for TLS descriptors. */
2750 /* Information for local symbols that need entries in .iplt. */
2753 /* Zero to warn when linking objects with incompatible enum sizes. */
2756 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2758 };
2760 #define elf_arm_tdata(bfd) \
2761 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2763 #define elf32_arm_local_got_tls_type(bfd) \
2764 (elf_arm_tdata (bfd)->local_got_tls_type)
2766 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2767 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2769 #define elf32_arm_local_iplt(bfd) \
2770 (elf_arm_tdata (bfd)->local_iplt)
2772 #define is_arm_elf(bfd) \
2773 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2774 && elf_tdata (bfd) != NULL \
2775 && elf_object_id (bfd) == ARM_ELF_DATA)
2777 static bfd_boolean
2779 {
2781 ARM_ELF_DATA);
2782 }
2784 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2786 /* Arm ELF linker hash entry. */
2787 struct elf32_arm_link_hash_entry
2788 {
2791 /* Track dynamic relocs copied for this symbol. */
2794 /* ARM-specific PLT information. */
2797 #define GOT_UNKNOWN 0
2798 #define GOT_NORMAL 1
2799 #define GOT_TLS_GD 2
2800 #define GOT_TLS_IE 4
2801 #define GOT_TLS_GDESC 8
2802 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2805 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2810 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2811 starting at the end of the jump table. */
2812 bfd_vma tlsdesc_got;
2814 /* The symbol marking the real symbol location for exported thumb
2815 symbols with Arm stubs. */
2818 /* A pointer to the most recently used stub hash entry against this
2819 symbol. */
2821 };
2823 /* Traverse an arm ELF linker hash table. */
2824 #define elf32_arm_link_hash_traverse(table, func, info) \
2825 (elf_link_hash_traverse \
2826 (&(table)->root, \
2827 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2828 (info)))
2830 /* Get the ARM elf linker hash table from a link_info structure. */
2831 #define elf32_arm_hash_table(info) \
2832 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2833 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2835 #define arm_stub_hash_lookup(table, string, create, copy) \
2836 ((struct elf32_arm_stub_hash_entry *) \
2837 bfd_hash_lookup ((table), (string), (create), (copy)))
2839 /* Array to keep track of which stub sections have been created, and
2840 information on stub grouping. */
2841 struct map_stub
2842 {
2843 /* This is the section to which stubs in the group will be
2844 attached. */
2846 /* The stub section. */
2848 };
2850 #define elf32_arm_compute_jump_table_size(htab) \
2851 ((htab)->next_tls_desc_index * 4)
2853 /* ARM ELF linker hash table. */
2854 struct elf32_arm_link_hash_table
2855 {
2856 /* The main hash table. */
2859 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2860 bfd_size_type thumb_glue_size;
2862 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2863 bfd_size_type arm_glue_size;
2865 /* The size in bytes of section containing the ARMv4 BX veneers. */
2866 bfd_size_type bx_glue_size;
2868 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2869 veneer has been populated. */
2872 /* The size in bytes of the section containing glue for VFP11 erratum
2873 veneers. */
2874 bfd_size_type vfp11_erratum_glue_size;
2876 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2877 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2878 elf32_arm_write_section(). */
2882 /* An arbitrary input BFD chosen to hold the glue sections. */
2885 /* Nonzero to output a BE8 image. */
2888 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2889 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2892 /* The relocation to use for R_ARM_TARGET2 relocations. */
2895 /* 0 = Ignore R_ARM_V4BX.
2896 1 = Convert BX to MOV PC.
2897 2 = Generate v4 interworing stubs. */
2900 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2903 /* Whether we should fix the ARM1176 BLX immediate issue. */
2906 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2909 /* What sort of code sequences we should look for which may trigger the
2910 VFP11 denorm erratum. */
2911 bfd_arm_vfp11_fix vfp11_fix;
2913 /* Global counter for the number of fixes we have emitted. */
2916 /* Nonzero to force PIC branch veneers. */
2919 /* The number of bytes in the initial entry in the PLT. */
2920 bfd_size_type plt_header_size;
2922 /* The number of bytes in the subsequent PLT etries. */
2923 bfd_size_type plt_entry_size;
2925 /* True if the target system is VxWorks. */
2928 /* True if the target system is Symbian OS. */
2931 /* True if the target system is Native Client. */
2934 /* True if the target uses REL relocations. */
2937 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2938 bfd_vma next_tls_desc_index;
2940 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2941 bfd_vma num_tls_desc;
2943 /* Short-cuts to get to dynamic linker sections. */
2947 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2950 /* The offset into splt of the PLT entry for the TLS descriptor
2951 resolver. Special values are 0, if not necessary (or not found
2952 to be necessary yet), and -1 if needed but not determined
2953 yet. */
2954 bfd_vma dt_tlsdesc_plt;
2956 /* The offset into sgot of the GOT entry used by the PLT entry
2957 above. */
2958 bfd_vma dt_tlsdesc_got;
2960 /* Offset in .plt section of tls_arm_trampoline. */
2961 bfd_vma tls_trampoline;
2963 /* Data for R_ARM_TLS_LDM32 relocations. */
2964 union
2965 {
2966 bfd_signed_vma refcount;
2967 bfd_vma offset;
2970 /* Small local sym cache. */
2973 /* For convenience in allocate_dynrelocs. */
2976 /* The amount of space used by the reserved portion of the sgotplt
2977 section, plus whatever space is used by the jump slots. */
2978 bfd_vma sgotplt_jump_table_size;
2980 /* The stub hash table. */
2983 /* Linker stub bfd. */
2986 /* Linker call-backs. */
2990 /* Array to keep track of which stub sections have been created, and
2991 information on stub grouping. */
2994 /* Number of elements in stub_group. */
2997 /* Assorted information used by elf32_arm_size_stubs. */
3001 };
3003 /* Create an entry in an ARM ELF linker hash table. */
3009 {
3013 /* Allocate the structure if it has not already been allocated by a
3014 subclass. */
3021 /* Call the allocation method of the superclass. */
3026 {
3038 }
3041 }
3043 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3044 symbols. */
3046 static bfd_boolean
3048 {
3050 {
3051 bfd_size_type num_syms;
3052 bfd_size_type size;
3074 }
3076 }
3078 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3079 to input bfd ABFD. Create the information if it doesn't already exist.
3080 Return null if an allocation fails. */
3084 {
3095 }
3097 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3098 in ABFD's symbol table. If the symbol is global, H points to its
3099 hash table entry, otherwise H is null.
3101 Return true if the symbol does have PLT information. When returning
3102 true, point *ROOT_PLT at the target-independent reference count/offset
3103 union and *ARM_PLT at the ARM-specific information. */
3105 static bfd_boolean
3109 {
3113 {
3117 }
3129 }
3131 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3132 before it. */
3134 static bfd_boolean
3137 {
3143 }
3145 /* Return a pointer to the head of the dynamic reloc list that should
3146 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3147 ABFD's symbol table. Return null if an error occurs. */
3152 {
3154 {
3161 }
3162 else
3163 {
3164 /* Track dynamic relocs needed for local syms too.
3165 We really need local syms available to do this
3166 easily. Oh well. */
3176 }
3177 }
3179 /* Initialize an entry in the stub hash table. */
3185 {
3186 /* Allocate the structure if it has not already been allocated by a
3187 subclass. */
3189 {
3194 }
3196 /* Call the allocation method of the superclass. */
3199 {
3202 /* Initialize the local fields. */
3217 }
3220 }
3222 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3223 shortcuts to them in our hash table. */
3225 static bfd_boolean
3227 {
3234 /* BPABI objects never have a GOT, or associated sections. */
3242 }
3244 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3246 static bfd_boolean
3248 {
3253 flagword flags;
3261 {
3268 }
3271 {
3279 }
3282 {
3288 }
3290 }
3292 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3293 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3294 hash table. */
3296 static bfd_boolean
3298 {
3317 {
3322 {
3324 htab->plt_entry_size
3326 }
3327 else
3328 {
3329 htab->plt_header_size
3331 htab->plt_entry_size
3333 }
3334 }
3343 }
3345 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3347 static void
3351 {
3358 {
3360 {
3364 /* Add reloc counts against the indirect sym to the direct sym
3365 list. Merge any entries against the same section. */
3367 {
3372 {
3377 }
3380 }
3382 }
3386 }
3389 {
3390 /* Copy over PLT info. */
3398 /* We should only allocate a function to .iplt once the final
3399 symbol information is known. */
3403 {
3406 }
3407 }
3410 }
3412 /* Create an ARM elf linker hash table. */
3416 {
3425 elf32_arm_link_hash_newfunc,
3427 ARM_ELF_DATA))
3428 {
3431 }
3434 #ifdef FOUR_WORD_PLT
3437 #else
3440 #endif
3446 {
3449 }
3452 }
3454 /* Free the derived linker hash table. */
3456 static void
3458 {
3464 }
3466 /* Determine if we're dealing with a Thumb only architecture. */
3468 static bfd_boolean
3470 {
3472 Tag_CPU_arch);
3482 Tag_CPU_arch_profile);
3485 }
3487 /* Determine if we're dealing with a Thumb-2 object. */
3489 static bfd_boolean
3491 {
3493 Tag_CPU_arch);
3495 }
3497 /* Determine what kind of NOPs are available. */
3499 static bfd_boolean
3501 {
3503 Tag_CPU_arch);
3508 }
3510 static bfd_boolean
3512 {
3514 Tag_CPU_arch);
3517 }
3519 static bfd_boolean
3521 {
3523 {
3537 }
3538 }
3540 /* Determine the type of stub needed, if any, for a call. */
3542 static enum elf32_arm_stub_type
3549 bfd_vma destination,
3553 {
3554 bfd_vma location;
3555 bfd_signed_vma branch_offset;
3577 /* Determine where the call point is. */
3584 /* For TLS call relocs, it is the caller's responsibility to provide
3585 the address of the appropriate trampoline. */
3591 {
3596 else
3599 {
3602 /* Note when dealing with PLT entries: the main PLT stub is in
3603 ARM mode, so if the branch is in Thumb mode, another
3604 Thumb->ARM stub will be inserted later just before the ARM
3605 PLT stub. We don't take this extra distance into account
3606 here, because if a long branch stub is needed, we'll add a
3607 Thumb->Arm one and branch directly to the ARM PLT entry
3608 because it avoids spreading offset corrections in several
3609 places. */
3616 }
3617 }
3618 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3625 {
3626 /* Handle cases where:
3627 - this call goes too far (different Thumb/Thumb2 max
3628 distance)
3629 - it's a Thumb->Arm call and blx is not available, or it's a
3630 Thumb->Arm branch (not bl). A stub is needed in this case,
3631 but only if this call is not through a PLT entry. Indeed,
3632 PLT stubs handle mode switching already.
3633 */
3637 || (thumb2
3645 {
3647 {
3648 /* Thumb to thumb. */
3650 {
3652 /* PIC stubs. */
3655 /* V5T and above. Stub starts with ARM code, so
3656 we must be able to switch mode before
3657 reaching it, which is only possible for 'bl'
3658 (ie R_ARM_THM_CALL relocation). */
3659 ? arm_stub_long_branch_any_thumb_pic
3660 /* On V4T, use Thumb code only. */
3663 /* non-PIC stubs. */
3666 /* V5T and above. */
3667 ? arm_stub_long_branch_any_any
3668 /* V4T. */
3670 }
3671 else
3672 {
3674 /* PIC stub. */
3675 ? arm_stub_long_branch_thumb_only_pic
3676 /* non-PIC stub. */
3678 }
3679 }
3680 else
3681 {
3682 /* Thumb to arm. */
3686 {
3691 }
3693 stub_type =
3695 /* PIC stubs. */
3697 /* TLS PIC stubs */
3701 /* V5T PIC and above. */
3702 ? arm_stub_long_branch_any_arm_pic
3703 /* V4T PIC stub. */
3706 /* non-PIC stubs. */
3708 /* V5T and above. */
3709 ? arm_stub_long_branch_any_any
3710 /* V4T. */
3713 /* Handle v4t short branches. */
3718 }
3719 }
3720 }
3725 {
3727 {
3728 /* Arm to thumb. */
3733 {
3738 }
3740 /* We have an extra 2-bytes reach because of
3741 the mode change (bit 24 (H) of BLX encoding). */
3747 {
3749 /* PIC stubs. */
3751 /* V5T and above. */
3752 ? arm_stub_long_branch_any_thumb_pic
3753 /* V4T stub. */
3756 /* non-PIC stubs. */
3758 /* V5T and above. */
3759 ? arm_stub_long_branch_any_any
3760 /* V4T. */
3762 }
3763 }
3764 else
3765 {
3766 /* Arm to arm. */
3769 {
3770 stub_type =
3772 /* PIC stubs. */
3774 /* TLS PIC Stub */
3775 ? arm_stub_long_branch_any_tls_pic
3777 /* non-PIC stubs. */
3779 }
3780 }
3781 }
3783 /* If a stub is needed, record the actual destination type. */
3788 }
3790 /* Build a name for an entry in the stub hash table. */
3798 {
3800 bfd_size_type len;
3803 {
3812 }
3813 else
3814 {
3826 }
3829 }
3831 /* Look up an entry in the stub hash. Stub entries are cached because
3832 creating the stub name takes a bit of time. */
3841 {
3849 /* If this input section is part of a group of sections sharing one
3850 stub section, then use the id of the first section in the group.
3851 Stub names need to include a section id, as there may well be
3852 more than one stub used to reach say, printf, and we need to
3853 distinguish between them. */
3860 {
3862 }
3863 else
3864 {
3877 }
3880 }
3882 /* Find or create a stub section. Returns a pointer to the stub section, and
3883 the section to which the stub section will be attached (in *LINK_SEC_P).
3884 LINK_SEC_P may be NULL. */
3889 {
3898 {
3901 {
3903 bfd_size_type len;
3918 }
3920 }
3926 }
3928 /* Add a new stub entry to the stub hash. Not all fields of the new
3929 stub entry are initialised. */
3935 {
3944 /* Enter this entry into the linker stub hash table. */
3948 {
3951 stub_name);
3953 }
3960 }
3962 /* Store an Arm insn into an output section not processed by
3963 elf32_arm_write_section. */
3965 static void
3968 {
3971 else
3973 }
3975 /* Store a 16-bit Thumb insn into an output section not processed by
3976 elf32_arm_write_section. */
3978 static void
3981 {
3984 else
3986 }
3988 /* If it's possible to change R_TYPE to a more efficient access
3989 model, return the new reloc type. */
3991 static unsigned
3994 {
4000 /* We do not support relaxations for Old TLS models. */
4002 {
4009 }
4012 }
4014 static bfd_reloc_status_type elf32_arm_final_link_relocate
4020 static unsigned int
4022 {
4024 {
4049 }
4050 }
4052 static bfd_boolean
4055 {
4056 #define MAXRELOCS 2
4063 bfd_vma sym_value;
4072 /* Massage our args to the form they really have. */
4084 /* We have to do less-strictly-aligned fixes last. */
4087 /* Make a note of the offset within the stubs for this entry. */
4093 /* This is the address of the stub destination. */
4103 {
4105 {
4107 {
4110 {
4111 /* We've borrowed the reloc_addend field to mean we should
4112 insert a condition code into this (Thumb-1 branch)
4113 instruction. See THUMB16_BCOND_INSN. */
4116 }
4119 }
4129 {
4132 }
4139 /* Handle cases where the target is encoded within the
4140 instruction. */
4142 {
4145 }
4159 }
4160 }
4164 /* Stub size has already been computed in arm_size_one_stub. Check
4165 consistency. */
4168 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4172 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4173 in each stub. */
4181 {
4182 Elf_Internal_Rela rel;
4183 bfd_boolean unresolved_reloc;
4185 enum arm_st_branch_type branch_type
4196 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4197 template should refer back to the instruction after the original
4198 branch. */
4201 /* There may be unintended consequences if this is not true. */
4204 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4205 properly. We should probably use this function unconditionally,
4206 rather than only for certain relocations listed in the enclosing
4207 conditional, for the sake of consistency. */
4214 }
4215 else
4216 {
4217 Elf_Internal_Rela rel;
4218 bfd_boolean unresolved_reloc;
4235 }
4238 #undef MAXRELOCS
4239 }
4241 /* Calculate the template, template size and instruction size for a stub.
4242 Return value is the instruction size. */
4244 static unsigned int
4248 {
4263 {
4265 {
4279 }
4280 }
4283 }
4285 /* As above, but don't actually build the stub. Just bump offset so
4286 we know stub section sizes. */
4288 static bfd_boolean
4291 {
4296 /* Massage our args to the form they really have. */
4313 }
4315 /* External entry points for sizing and building linker stubs. */
4317 /* Set up various things so that we can make a list of input sections
4318 for each output section included in the link. Returns -1 on error,
4319 0 when no stubs will be needed, and 1 on success. */
4321 int
4324 {
4330 bfd_size_type amt;
4338 /* Count the number of input BFDs and find the top input section id. */
4342 {
4347 {
4350 }
4351 }
4360 /* We can't use output_bfd->section_count here to find the top output
4361 section index as some sections may have been removed, and
4362 _bfd_strip_section_from_output doesn't renumber the indices. */
4366 {
4369 }
4378 /* For sections we aren't interested in, mark their entries with a
4379 value we can check later. */
4381 do
4388 {
4391 }
4394 }
4396 /* The linker repeatedly calls this function for each input section,
4397 in the order that input sections are linked into output sections.
4398 Build lists of input sections to determine groupings between which
4399 we may insert linker stubs. */
4401 void
4404 {
4411 {
4415 {
4416 /* Steal the link_sec pointer for our list. */
4417 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4418 /* This happens to make the list in reverse order,
4419 which we reverse later. */
4422 }
4423 }
4424 }
4426 /* See whether we can group stub sections together. Grouping stub
4427 sections may result in fewer stubs. More importantly, we need to
4428 put all .init* and .fini* stubs at the end of the .init or
4429 .fini output sections respectively, because glibc splits the
4430 _init and _fini functions into multiple parts. Putting a stub in
4431 the middle of a function is not a good idea. */
4433 static void
4435 bfd_size_type stub_group_size,
4436 bfd_boolean stubs_always_after_branch)
4437 {
4440 do
4441 {
4448 /* Reverse the list: we must avoid placing stubs at the
4449 beginning of the section because the beginning of the text
4450 section may be required for an interrupt vector in bare metal
4451 code. */
4452 #define NEXT_SEC PREV_SEC
4455 {
4456 /* Pop from tail. */
4460 /* Push on head. */
4463 }
4466 {
4470 bfd_vma end_of_next;
4474 {
4478 /* End of NEXT is too far from start, so stop. */
4480 /* Add NEXT to the group. */
4482 }
4484 /* OK, the size from the start to the start of CURR is less
4485 than stub_group_size and thus can be handled by one stub
4486 section. (Or the head section is itself larger than
4487 stub_group_size, in which case we may be toast.)
4488 We should really be keeping track of the total size of
4489 stubs added here, as stubs contribute to the final output
4490 section size. */
4491 do
4492 {
4494 /* Set up this stub group. */
4496 }
4499 /* But wait, there's more! Input sections up to stub_group_size
4500 bytes after the stub section can be handled by it too. */
4502 {
4506 {
4509 /* End of NEXT is too far from stubs, so stop. */
4511 /* Add NEXT to the stub group. */
4515 }
4516 }
4518 }
4519 }
4523 #undef PREV_SEC
4524 #undef NEXT_SEC
4525 }
4527 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4528 erratum fix. */
4530 static int
4532 {
4540 else
4542 }
4547 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4548 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4549 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4550 otherwise. */
4552 static bfd_boolean
4562 {
4575 {
4579 bfd_vma base_vma;
4598 {
4609 /* Span is entirely within a single 4KB region: skip scanning. */
4614 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4616 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4617 * The branch target is in the same 4KB region as the
4618 first half of the branch.
4619 * The instruction before the branch is a 32-bit
4620 length non-branch instruction. */
4622 {
4631 {
4632 /* Load the rest of the insn (in manual-friendly order). */
4635 /* Encoding T4: B<c>.W. */
4637 /* Encoding T1: BL<c>.W. */
4639 /* Encoding T2: BLX<c>.W. */
4641 /* Encoding T3: B<c>.W (not permitted in IT block). */
4644 }
4649 && insn_32bit
4650 && is_32bit_branch
4651 && last_was_32bit
4653 {
4657 bfd_vma target;
4669 {
4673 /* We don't care about the error returned from this
4674 function, only if there is glue or not. */
4681 /* Keep a simpler condition, for the sake of clarity. */
4687 {
4691 else
4693 }
4694 }
4696 /* Check if we have an offending branch instruction. */
4699 /* We've already made a stub for this instruction, e.g.
4700 it's a long branch or a Thumb->ARM stub. Assume that
4701 stub will suffice to work around the A8 erratum (see
4702 setting of always_after_branch above). */
4703 ;
4705 {
4714 }
4716 {
4736 }
4739 {
4742 /* The original instruction is a BL, but the target is
4743 an ARM instruction. If we were not making a stub,
4744 the BL would have been converted to a BLX. Use the
4745 BLX stub instead in that case. */
4748 {
4752 }
4753 /* Conversely, if the original instruction was
4754 BLX but the target is Thumb mode, use the BL
4755 stub. */
4758 {
4762 }
4767 /* If we found a relocation, use the proper destination,
4768 not the offset in the (unrelocated) instruction.
4769 Note this is always done if we switched the stub type
4770 above. */
4772 offset =
4775 /* If the stub will use a Thumb-mode branch to a
4776 PLT target, redirect it to the preceding Thumb
4777 entry point. */
4783 /* The BLX stub is ARM-mode code. Adjust the offset to
4784 take the different PC value (+8 instead of +4) into
4785 account. */
4790 {
4794 {
4800 }
4803 {
4804 /* If we're doing a subsequent scan,
4805 check if we've found the same fix as
4806 before, and try and reuse the stub
4807 name. */
4811 {
4815 }
4816 }
4819 {
4823 }
4835 num_a8_fixes++;
4836 }
4837 }
4838 }
4843 }
4844 }
4848 }
4855 }
4857 /* Determine and set the size of the stub section for a final link.
4859 The basic idea here is to examine all the relocations looking for
4860 PC-relative calls to a target that is unreachable with a "bl"
4861 instruction. */
4863 bfd_boolean
4867 bfd_signed_vma group_size,
4870 {
4871 bfd_size_type stub_group_size;
4872 bfd_boolean stubs_always_after_branch;
4883 {
4888 }
4890 /* Propagate mach to stub bfd, because it may not have been
4891 finalized when we created stub_bfd. */
4895 /* Stash our params away. */
4901 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4902 as the first half of a 32-bit branch straddling two 4K pages. This is a
4903 crude way of enforcing that. */
4909 else
4913 {
4914 /* Default values. */
4915 /* Thumb branch range is +-4MB has to be used as the default
4916 maximum size (a given section can contain both ARM and Thumb
4917 code, so the worst case has to be taken into account).
4919 This value is 24K less than that, which allows for 2025
4920 12-byte stubs. If we exceed that, then we will fail to link.
4921 The user will have to relink with an explicit group size
4922 option. */
4924 }
4928 /* If we're applying the cortex A8 fix, we need to determine the
4929 program header size now, because we cannot change it later --
4930 that could alter section placements. Notice the A8 erratum fix
4931 ends up requiring the section addresses to remain unchanged
4932 modulo the page size. That's something we cannot represent
4933 inside BFD, and we don't want to force the section alignment to
4934 be the page size. */
4939 {
4950 {
4960 /* We'll need the symbol table in a second. */
4965 /* Walk over each section attached to the input bfd. */
4969 {
4972 /* If there aren't any relocs, then there's nothing more
4973 to do. */
4979 /* If this section is a link-once section that will be
4980 discarded, then don't create any stubs. */
4985 /* Get the relocs. */
4986 internal_relocs
4992 /* Now examine each relocation. */
4996 {
5001 bfd_vma sym_value;
5002 bfd_vma destination;
5015 {
5017 error_ret_free_internal:
5021 }
5025 hash = elf32_arm_hash_entry
5029 /* Only look for stubs on branch instructions, or
5030 non-relaxed TLSCALL */
5043 : (elf32_arm_local_got_tls_type
5048 /* Now determine the call target, its name, value,
5049 section. */
5057 {
5058 /* A non-relaxed TLS call. The target is the
5059 plt-resident trampoline and nothing to do
5060 with the symbol. */
5067 }
5069 {
5070 /* It's a local symbol. */
5074 {
5075 local_syms
5078 local_syms
5084 }
5093 else
5094 sym_sec =
5098 /* This is an undefined symbol. It can never
5099 be resolved. */
5109 sym_name
5113 }
5114 else
5115 {
5116 /* It's an external symbol. */
5124 {
5131 /* For a destination in a shared library,
5132 use the PLT stub as target address to
5133 decide whether a branch stub is
5134 needed. */
5139 {
5143 destination = (sym_value
5146 }
5151 }
5154 {
5155 /* For a shared library, use the PLT stub as
5156 target address to decide whether a long
5157 branch stub is needed.
5158 For absolute code, they cannot be handled. */
5166 {
5170 destination = (sym_value
5173 }
5174 else
5176 }
5177 else
5178 {
5181 }
5185 }
5187 do
5188 {
5189 /* Determine what (if any) linker stub is needed. */
5197 /* Support for grouping stub sections. */
5200 /* Get the name of this stub. */
5206 /* We've either created a stub for this reloc already,
5207 or we are about to. */
5210 stub_entry = arm_stub_hash_lookup
5214 {
5215 /* The proper stub has already been created. */
5219 }
5222 htab);
5224 {
5227 }
5242 {
5245 }
5247 /* For historical reasons, use the existing names for
5248 ARM-to-Thumb and Thumb-to-ARM stubs. */
5259 else
5261 sym_name);
5264 }
5267 /* Look for relocations which might trigger Cortex-A8
5268 erratum. */
5274 {
5280 {
5281 /* Found a candidate. Note we haven't checked the
5282 destination is within 4K here: if we do so (and
5283 don't create an entry in a8_relocs) we can't tell
5284 that a branch should have been relocated when
5285 scanning later. */
5287 {
5293 }
5303 num_a8_relocs++;
5304 }
5305 }
5306 }
5308 /* We're done with the internal relocs, free them. */
5311 }
5314 {
5315 /* Sort relocs which might apply to Cortex-A8 erratum. */
5320 /* Scan for branches which might trigger Cortex-A8 erratum. */
5327 }
5328 }
5336 /* OK, we've added some stubs. Find out the new size of the
5337 stub sections. */
5341 {
5342 /* Ignore non-stub sections. */
5347 }
5351 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5354 {
5361 stub_sec->size
5363 NULL);
5364 }
5367 /* Ask the linker to do its stuff. */
5369 }
5371 /* Add stubs for Cortex-A8 erratum fixes now. */
5373 {
5375 {
5388 {
5391 stub_name);
5393 }
5412 }
5414 /* Stash the Cortex-A8 erratum fix array for use later in
5415 elf32_arm_write_section(). */
5418 }
5419 else
5420 {
5423 }
5426 error_ret_free_local:
5428 }
5430 /* Build all the stubs associated with the current output file. The
5431 stubs are kept in a hash table attached to the main linker hash
5432 table. We also set up the .plt entries for statically linked PIC
5433 functions here. This function is called via arm_elf_finish in the
5434 linker. */
5436 bfd_boolean
5438 {
5450 {
5451 bfd_size_type size;
5453 /* Ignore non-stub sections. */
5457 /* Allocate memory to hold the linker stubs. */
5463 }
5465 /* Build the stubs as directed by the stub hash table. */
5469 {
5470 /* Place the cortex a8 stubs last. */
5473 }
5476 }
5478 /* Locate the Thumb encoded calling stub for NAME. */
5484 {
5489 /* We need a pointer to the armelf specific hash table. */
5501 hash = elf_link_hash_lookup
5512 }
5514 /* Locate the ARM encoded calling stub for NAME. */
5520 {
5525 /* We need a pointer to the elfarm specific hash table. */
5537 myh = elf_link_hash_lookup
5548 }
5550 /* ARM->Thumb glue (static images):
5552 .arm
5553 __func_from_arm:
5554 ldr r12, __func_addr
5555 bx r12
5556 __func_addr:
5557 .word func @ behave as if you saw a ARM_32 reloc.
5559 (v5t static images)
5560 .arm
5561 __func_from_arm:
5562 ldr pc, __func_addr
5563 __func_addr:
5564 .word func @ behave as if you saw a ARM_32 reloc.
5566 (relocatable images)
5567 .arm
5568 __func_from_arm:
5569 ldr r12, __func_offset
5570 add r12, r12, pc
5571 bx r12
5572 __func_offset:
5573 .word func - . */
5575 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5580 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5584 #define ARM2THUMB_PIC_GLUE_SIZE 16
5589 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5591 .thumb .thumb
5592 .align 2 .align 2
5593 __func_from_thumb: __func_from_thumb:
5594 bx pc push {r6, lr}
5595 nop ldr r6, __func_addr
5596 .arm mov lr, pc
5597 b func bx r6
5598 .arm
5599 ;; back_to_thumb
5600 ldmia r13! {r6, lr}
5601 bx lr
5602 __func_addr:
5603 .word func */
5605 #define THUMB2ARM_GLUE_SIZE 8
5610 #define VFP11_ERRATUM_VENEER_SIZE 8
5612 #define ARM_BX_VENEER_SIZE 12
5617 #ifndef ELFARM_NABI_C_INCLUDED
5618 static void
5620 {
5625 {
5626 /* Do not include empty glue sections in the output. */
5628 {
5632 }
5634 }
5645 }
5647 bfd_boolean
5649 {
5657 ARM2THUMB_GLUE_SECTION_NAME);
5661 THUMB2ARM_GLUE_SECTION_NAME);
5665 VFP11_ERRATUM_VENEER_SECTION_NAME);
5669 ARM_BX_GLUE_SECTION_NAME);
5672 }
5674 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5675 returns the symbol identifying the stub. */
5680 {
5687 bfd_vma val;
5688 bfd_size_type size;
5694 s = bfd_get_linker_section
5706 myh = elf_link_hash_lookup
5710 {
5711 /* We've already seen this guy. */
5714 }
5716 /* The only trick here is using hash_table->arm_glue_size as the value.
5717 Even though the section isn't allocated yet, this is where we will be
5718 putting it. The +1 on the value marks that the stub has not been
5719 output yet - not that it is a Thumb function. */
5737 else
5744 }
5746 /* Allocate space for ARMv4 BX veneers. */
5748 static void
5750 {
5756 bfd_vma val;
5758 /* BX PC does not need a veneer. */
5766 /* Check if this veneer has already been allocated. */
5770 s = bfd_get_linker_section
5775 /* Add symbol for veneer. */
5783 myh = elf_link_hash_lookup
5801 }
5804 /* Add an entry to the code/data map for section SEC. */
5806 static void
5808 {
5813 {
5818 }
5823 {
5828 }
5831 {
5834 }
5835 }
5838 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5839 veneers are handled for now. */
5841 static bfd_vma
5847 {
5853 bfd_vma val;
5861 s = bfd_get_linker_section
5876 myh = elf_link_hash_lookup
5891 /* Link veneer back to calling location. */
5905 /* A symbol for the return from the veneer. */
5909 myh = elf_link_hash_lookup
5926 /* Generate a mapping symbol for the veneer section, and explicitly add an
5927 entry for that symbol to the code/data map for the section. */
5929 {
5931 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5932 ever requires this erratum fix. */
5942 /* The elf32_arm_init_maps function only cares about symbols from input
5943 BFDs. We must make a note of this generated mapping symbol
5944 ourselves so that code byteswapping works properly in
5945 elf32_arm_write_section. */
5947 }
5953 /* The offset of the veneer. */
5955 }
5957 #define ARM_GLUE_SECTION_FLAGS \
5958 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
5959 | SEC_READONLY | SEC_LINKER_CREATED)
5961 /* Create a fake section for use by the ARM backend of the linker. */
5963 static bfd_boolean
5965 {
5970 /* Already made. */
5979 /* Set the gc mark to prevent the section from being removed by garbage
5980 collection, despite the fact that no relocs refer to this section. */
5984 }
5986 /* Add the glue sections to ABFD. This function is called from the
5987 linker scripts in ld/emultempl/{armelf}.em. */
5989 bfd_boolean
5992 {
5993 /* If we are only performing a partial
5994 link do not bother adding the glue. */
6002 }
6004 /* Select a BFD to be used to hold the sections used by the glue code.
6005 This function is called from the linker scripts in ld/emultempl/
6006 {armelf/pe}.em. */
6008 bfd_boolean
6010 {
6013 /* If we are only performing a partial link
6014 do not bother getting a bfd to hold the glue. */
6018 /* Make sure we don't attach the glue sections to a dynamic object. */
6027 /* Save the bfd for later use. */
6031 }
6033 static void
6035 {
6039 Tag_CPU_arch);
6042 {
6045 }
6046 else
6047 {
6050 }
6051 }
6053 bfd_boolean
6056 {
6065 /* If we are only performing a partial link do not bother
6066 to construct any glue. */
6070 /* Here we have a bfd that is to be included on the link. We have a
6071 hook to do reloc rummaging, before section sizes are nailed down. */
6078 {
6080 abfd);
6082 }
6084 /* PR 5398: If we have not decided to include any loadable sections in
6085 the output then we will not have a glue owner bfd. This is OK, it
6086 just means that there is nothing else for us to do here. */
6090 /* Rummage around all the relocs and map the glue vectors. */
6097 {
6106 /* Load the relocs. */
6107 internal_relocs
6115 {
6124 /* These are the only relocation types we care about. */
6129 /* Get the section contents if we haven't done so already. */
6131 {
6132 /* Get cached copy if it exists. */
6135 else
6136 {
6137 /* Go get them off disk. */
6140 }
6141 }
6144 {
6150 }
6152 /* If the relocation is not against a symbol it cannot concern us. */
6155 /* We don't care about local symbols. */
6159 /* This is an external symbol. */
6164 /* If the relocation is against a static symbol it must be within
6165 the current section and so cannot be a cross ARM/Thumb relocation. */
6169 /* If the call will go through a PLT entry then we do not need
6170 glue. */
6175 {
6177 /* This one is a call from arm code. We need to look up
6178 the target of the call. If it is a thumb target, we
6179 insert glue. */
6186 }
6187 }
6198 }
6202 error_return:
6211 }
6212 #endif
6215 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6217 void
6219 {
6224 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6234 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6235 should contain the number of local symbols, which should come before any
6236 global symbols. Mapping symbols are always local. */
6238 NULL);
6240 /* No internal symbols read? Skip this BFD. */
6245 {
6252 {
6257 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6259 }
6260 }
6261 }
6264 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6265 say what they wanted. */
6267 void
6269 {
6277 {
6278 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6283 else
6285 }
6286 }
6289 void
6291 {
6297 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6299 {
6301 {
6308 /* Give a warning, but do as the user requests anyway. */
6311 }
6312 }
6314 /* For earlier architectures, we might need the workaround, but do not
6315 enable it by default. If users is running with broken hardware, they
6316 must enable the erratum fix explicitly. */
6318 }
6321 enum bfd_arm_vfp11_pipe
6322 {
6323 VFP11_FMAC,
6324 VFP11_LS,
6325 VFP11_DS,
6326 VFP11_BAD
6327 };
6329 /* Return a VFP register number. This is encoded as RX:X for single-precision
6330 registers, or X:RX for double-precision registers, where RX is the group of
6331 four bits in the instruction encoding and X is the single extension bit.
6332 RX and X fields are specified using their lowest (starting) bit. The return
6333 value is:
6335 0...31: single-precision registers s0...s31
6336 32...63: double-precision registers d0...d31.
6338 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6339 encounter VFP3 instructions, so we allow the full range for DP registers. */
6341 static unsigned int
6344 {
6347 else
6349 }
6351 /* Set bits in *WMASK according to a register number REG as encoded by
6352 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6354 static void
6356 {
6361 }
6363 /* Return TRUE if WMASK overwrites anything in REGS. */
6365 static bfd_boolean
6367 {
6371 {
6384 }
6387 }
6389 /* In this function, we're interested in two things: finding input registers
6390 for VFP data-processing instructions, and finding the set of registers which
6391 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6392 hold the written set, so FLDM etc. are easy to deal with (we're only
6393 interested in 32 SP registers or 16 dp registers, due to the VFP version
6394 implemented by the chip in question). DP registers are marked by setting
6395 both SP registers in the write mask). */
6397 static enum bfd_arm_vfp11_pipe
6400 {
6405 {
6415 {
6437 vfp_binop:
6445 {
6450 {
6464 /* These instructions will not bounce due to underflow. */
6470 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6471 registers to cause the erratum in previous instructions. */
6477 {
6482 /* Only FCVTSD can underflow. */
6489 }
6494 }
6495 }
6500 }
6501 }
6502 /* Two-register transfer. */
6504 {
6508 {
6511 else
6512 {
6515 }
6516 }
6519 }
6521 {
6526 {
6533 {
6541 }
6551 }
6554 }
6555 /* Single-register transfer. Note L==0. */
6557 {
6562 {
6565 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6566 destination register. I don't know if this is exactly right,
6567 but it is the conservative choice. */
6573 }
6576 }
6579 }
6585 /* Look for potentially-troublesome code sequences which might trigger the
6586 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6587 (available from ARM) for details of the erratum. A short version is
6588 described in ld.texinfo. */
6590 bfd_boolean
6592 {
6603 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6604 The states transition as follows:
6606 0 -> 1 (vector) or 0 -> 2 (scalar)
6607 A VFP FMAC-pipeline instruction has been seen. Fill
6608 regs[0]..regs[numregs-1] with its input operands. Remember this
6609 instruction in 'first_fmac'.
6611 1 -> 2
6612 Any instruction, except for a VFP instruction which overwrites
6613 regs[*].
6615 1 -> 3 [ -> 0 ] or
6616 2 -> 3 [ -> 0 ]
6617 A VFP instruction has been seen which overwrites any of regs[*].
6618 We must make a veneer! Reset state to 0 before examining next
6619 instruction.
6621 2 -> 0
6622 If we fail to match anything in state 2, reset to state 0 and reset
6623 the instruction pointer to the instruction after 'first_fmac'.
6625 If the VFP11 vector mode is in use, there must be at least two unrelated
6626 instructions between anti-dependent VFP11 instructions to properly avoid
6627 triggering the erratum, hence the use of the extra state 1. */
6629 /* If we are only performing a partial link do not bother
6630 to construct any glue. */
6634 /* Skip if this bfd does not correspond to an ELF image. */
6638 /* We should have chosen a fix type by the time we get here. */
6644 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6649 {
6653 /* If we don't have executable progbits, we're not interested in this
6654 section. Also skip if section is to be excluded. */
6674 elf32_arm_compare_mapping);
6677 {
6683 /* FIXME: Only ARM mode is supported at present. We may need to
6684 support Thumb-2 mode also at some point. */
6689 {
6704 {
6708 /* I'm assuming the VFP11 erratum can trigger with denorm
6709 operands on either the FMAC or the DS pipeline. This might
6710 lead to slightly overenthusiastic veneer insertion. */
6712 {
6716 }
6720 {
6723 other_regs,
6727 numregs))
6729 else
6731 }
6735 {
6738 other_regs,
6742 numregs))
6744 else
6745 {
6748 }
6749 }
6754 }
6757 {
6766 {
6773 }
6776 first_fmac);
6784 }
6787 }
6788 }
6794 }
6798 error_return:
6804 }
6806 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6807 after sections have been laid out, using specially-named symbols. */
6809 void
6812 {
6820 /* Skip if this bfd does not correspond to an ELF image. */
6832 {
6837 {
6839 bfd_vma vma;
6842 {
6845 /* Find veneer symbol. */
6849 myh = elf_link_hash_lookup
6865 /* Find return location. */
6869 myh = elf_link_hash_lookup
6885 }
6886 }
6887 }
6890 }
6893 /* Set target relocation values needed during linking. */
6895 void
6902 bfd_arm_vfp11_fix vfp11_fix,
6906 {
6920 else
6921 {
6923 target2_type);
6924 }
6935 }
6937 /* Replace the target offset of a Thumb bl or b.w instruction. */
6939 static void
6941 {
6942 bfd_vma upper;
6943 bfd_vma lower;
6960 }
6962 /* Thumb code calling an ARM function. */
6964 static int
6972 bfd_vma offset,
6973 bfd_signed_vma addend,
6974 bfd_vma val,
6976 {
6978 bfd_vma my_offset;
6994 THUMB2ARM_GLUE_SECTION_NAME);
7001 {
7005 {
7012 }
7023 ret_offset =
7024 /* Address of destination of the stub. */
7027 /* Offset from the start of the current section
7028 to the start of the stubs. */
7030 /* Offset of the start of this stub from the start of the stubs. */
7031 + my_offset
7032 /* Address of the start of the current section. */
7034 /* The branch instruction is 4 bytes into the stub. */
7036 /* ARM branches work from the pc of the instruction + 8. */
7042 }
7046 /* Now go back and fix up the original BL insn to point to here. */
7047 ret_offset =
7048 /* Address of where the stub is located. */
7050 /* Address of where the BL is located. */
7053 /* Addend in the relocation. */
7054 - addend
7055 /* Biassing for PC-relative addressing. */
7061 }
7063 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
7071 bfd_vma val,
7074 {
7075 bfd_vma my_offset;
7091 {
7095 {
7100 }
7107 {
7108 /* For relocatable objects we can't use absolute addresses,
7109 so construct the address from a relative offset. */
7110 /* TODO: If the offset is small it's probably worth
7111 constructing the address with adds. */
7118 /* Adjust the offset by 4 for the position of the add,
7119 and 8 for the pipeline offset. */
7126 }
7128 {
7132 /* It's a thumb address. Add the low order bit. */
7135 }
7136 else
7137 {
7144 /* It's a thumb address. Add the low order bit. */
7149 }
7150 }
7155 }
7157 /* Arm code calling a Thumb function. */
7159 static int
7167 bfd_vma offset,
7168 bfd_signed_vma addend,
7169 bfd_vma val,
7171 {
7173 bfd_vma my_offset;
7184 ARM2THUMB_GLUE_SECTION_NAME);
7198 /* Somehow these are both 4 too far, so subtract 8. */
7200 + my_offset
7212 }
7214 /* Populate Arm stub for an exported Thumb function. */
7216 static bfd_boolean
7218 {
7225 bfd_vma val;
7229 /* Allocate stubs for exported Thumb functions on v4t. */
7238 ARM2THUMB_GLUE_SECTION_NAME);
7256 }
7258 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7260 static bfd_vma
7262 {
7264 bfd_vma glue_addr;
7273 ARM_BX_GLUE_SECTION_NAME);
7283 {
7289 }
7292 }
7294 /* Generate Arm stubs for exported Thumb symbols. */
7295 static void
7298 {
7302 /* Ignore this if we are not called by the ELF backend linker. */
7309 /* If blx is available then exported Thumb symbols are OK and there is
7310 nothing to do. */
7315 link_info);
7316 }
7318 /* Reserve space for COUNT dynamic relocations in relocation selection
7319 SRELOC. */
7321 static void
7323 bfd_size_type count)
7324 {
7332 }
7334 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7335 dynamic, the relocations should go in SRELOC, otherwise they should
7336 go in the special .rel.iplt section. */
7338 static void
7340 bfd_size_type count)
7341 {
7347 else
7348 {
7351 }
7352 }
7354 /* Add relocation REL to the end of relocation section SRELOC. */
7356 static void
7359 {
7374 }
7376 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7377 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7378 to .plt. */
7380 static void
7382 bfd_boolean is_iplt_entry,
7385 {
7393 {
7397 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7399 }
7400 else
7401 {
7405 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7408 /* If this is the first .plt entry, make room for the special
7409 first entry. */
7412 }
7414 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7421 {
7422 /* We also need to make an entry in the .got.plt section, which
7423 will be placed in the .got section by the linker script. */
7426 }
7427 }
7429 static bfd_vma
7431 {
7433 }
7435 static bfd_vma
7437 {
7439 }
7441 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7442 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7443 Otherwise, DYNINDX is the index of the symbol in the dynamic
7444 symbol table and SYM_VALUE is undefined.
7446 ROOT_PLT points to the offset of the PLT entry from the start of its
7447 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7448 bookkeeping information. */
7450 static void
7455 {
7461 bfd_vma plt_index;
7462 Elf_Internal_Rela rel;
7463 bfd_vma plt_header_size;
7464 bfd_vma got_header_size;
7468 /* Pick the appropriate sections and sizes. */
7470 {
7475 /* There are no reserved entries in .igot.plt, and no special
7476 first entry in .iplt. */
7479 }
7480 else
7481 {
7488 }
7491 /* Fill in the entry in the procedure linkage table. */
7493 {
7502 /* Fill in the entry in the .rel.plt section. */
7508 /* Get the index in the procedure linkage table which
7509 corresponds to this symbol. This is the index of this symbol
7510 in all the symbols for which we are making plt entries. The
7511 first entry in the procedure linkage table is reserved. */
7514 }
7515 else
7516 {
7523 /* Get the offset into the .(i)got.plt table of the entry that
7524 corresponds to this function. */
7527 /* Get the index in the procedure linkage table which
7528 corresponds to this symbol. This is the index of this symbol
7529 in all the symbols for which we are making plt entries.
7530 After the reserved .got.plt entries, all symbols appear in
7531 the same order as in .plt. */
7534 /* Calculate the address of the GOT entry. */
7539 /* ...and the address of the PLT entry. */
7546 {
7548 bfd_vma val;
7551 {
7559 else
7561 }
7562 }
7564 {
7566 bfd_vma val;
7569 {
7579 else
7581 }
7586 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7587 referencing the GOT for this PLT entry. */
7594 /* Create the R_ARM_ABS32 relocation referencing the
7595 beginning of the PLT for this GOT entry. */
7600 }
7602 {
7603 /* Calculate the displacement between the PLT slot and the
7604 common tail that's part of the special initial PLT slot. */
7605 int32_t tail_displacement
7615 /* Calculate the displacement between the PLT slot and the entry
7616 in the GOT. The offset accounts for the value produced by
7617 adding to pc in the penultimate instruction of the PLT stub. */
7618 got_displacement = (got_address
7621 /* NaCl does not support interworking at all. */
7639 }
7640 else
7641 {
7642 /* Calculate the displacement between the PLT slot and the
7643 entry in the GOT. The eight-byte offset accounts for the
7644 value produced by adding to pc in the first instruction
7645 of the PLT stub. */
7651 {
7656 }
7670 #ifdef FOUR_WORD_PLT
7672 #endif
7673 }
7675 /* Fill in the entry in the .rel(a).(i)plt section. */
7679 {
7680 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7681 The dynamic linker or static executable then calls SYM_VALUE
7682 to determine the correct run-time value of the .igot.plt entry. */
7685 }
7686 else
7687 {
7691 }
7693 /* Fill in the entry in the global offset table. */
7696 }
7700 }
7702 /* Some relocations map to different relocations depending on the
7703 target. Return the real relocation. */
7705 static int
7708 {
7710 {
7714 else
7722 }
7723 }
7725 /* Return the base VMA address which should be subtracted from real addresses
7726 when resolving @dtpoff relocation.
7727 This is PT_TLS segment p_vaddr. */
7729 static bfd_vma
7731 {
7732 /* If tls_sec is NULL, we should have signalled an error already. */
7736 }
7738 /* Return the relocation value for @tpoff relocation
7739 if STT_TLS virtual address is ADDRESS. */
7741 static bfd_vma
7743 {
7745 bfd_vma base;
7747 /* If tls_sec is NULL, we should have signalled an error already. */
7752 }
7754 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7755 VALUE is the relocation value. */
7757 static bfd_reloc_status_type
7759 {
7766 }
7768 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7769 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7770 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7772 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7773 is to then call final_link_relocate. Return other values in the
7774 case of error.
7776 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7777 the pre-relaxed code. It would be nice if the relocs were updated
7778 to match the optimization. */
7780 static bfd_reloc_status_type
7784 {
7788 {
7795 else
7796 {
7800 else
7802 }
7807 /* Thumb insn. */
7810 {
7812 /* nop */
7814 }
7816 {
7818 /* nop */
7820 else
7821 /* ldr rx,[ry] */
7823 }
7825 {
7827 /* nop */
7829 else
7830 /* mov r0, rx */
7833 }
7834 else
7835 {
7837 /* It's a 32 bit instruction, fetch the rest of it for
7838 error generation. */
7845 }
7849 /* arm insn. */
7852 {
7854 /* mov rx, ry */
7857 }
7859 {
7861 /* nop */
7863 else
7864 /* ldr rx,[ry] */
7867 }
7869 {
7871 /* nop */
7873 else
7874 /* mov r0, rx */
7877 }
7878 else
7879 {
7884 }
7888 /* GD->IE relaxation, turn the instruction into 'nop' or
7889 'ldr r0, [pc,r0]' */
7895 /* GD->IE relaxation */
7897 /* add r0,pc; ldr r0, [r0] */
7900 /* nop.w */
7902 else
7903 /* nop; nop */
7909 }
7911 }
7913 /* For a given value of n, calculate the value of G_n as required to
7914 deal with group relocations. We return it in the form of an
7915 encoded constant-and-rotation, together with the final residual. If n is
7916 specified as less than zero, then final_residual is filled with the
7917 input value and no further action is performed. */
7919 static bfd_vma
7921 {
7923 bfd_vma g_n;
7928 {
7931 /* Calculate which part of the value to mask. */
7934 else
7935 {
7938 /* Determine the most significant bit in the residual and
7939 align the resulting value to a 2-bit boundary. */
7944 /* The desired shift is now (msb - 6), or zero, whichever
7945 is the greater. */
7949 }
7951 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
7956 /* Calculate the residual for the next time around. */
7958 }
7963 }
7965 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
7966 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
7968 static int
7970 {
7980 }
7982 /* Perform a relocation as part of a final link. */
7984 static bfd_reloc_status_type
7991 bfd_vma value,
8000 {
8010 bfd_vma addend;
8011 bfd_signed_vma signed_addend;
8013 bfd_vma dynreloc_value;
8018 bfd_vma plt_offset;
8019 bfd_vma gotplt_offset;
8020 bfd_boolean has_iplt_entry;
8028 /* Some relocation types map to different relocations depending on the
8029 target. We pick the right one here. */
8032 /* It is possible to have linker relaxations on some TLS access
8033 models. Update our information here. */
8039 /* If the start address has been set, then set the EF_ARM_HASENTRY
8040 flag. Setting this more than once is redundant, but the cost is
8041 not too high, and it keeps the code simple.
8043 The test is done here, rather than somewhere else, because the
8044 start address is only set just before the final link commences.
8046 Note - if the user deliberately sets a start address of 0, the
8047 flag will not be set. */
8058 else
8064 {
8068 {
8072 }
8073 else
8075 }
8076 else
8079 /* Record the symbol information that should be used in dynamic
8080 relocations. */
8086 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8087 VALUE appropriately for relocations that we resolve at link time. */
8091 {
8096 {
8100 /* Populate .iplt entries here, because not all of them will
8101 be seen by finish_dynamic_symbol. The lower bit is set if
8102 we have already populated the entry. */
8104 plt_offset--;
8105 else
8106 {
8110 }
8112 /* Static relocations always resolve to the .iplt entry. */
8119 /* If there are non-call relocations that resolve to the .iplt
8120 entry, then all dynamic ones must too. */
8122 {
8125 }
8126 }
8127 else
8128 /* We populate the .plt entry in finish_dynamic_symbol. */
8130 }
8131 else
8132 {
8136 }
8139 {
8141 /* We don't need to find a value for this symbol. It's just a
8142 marker. */
8160 /* Handle relocations which should use the PLT entry. ABS32/REL32
8161 will use the symbol's value, which may point to a PLT entry, but we
8162 don't need to handle that here. If we created a PLT entry, all
8163 branches in this object should go to it, except if the PLT is too
8164 far away, in which case a long branch stub should be inserted. */
8171 {
8172 /* If we've created a .plt section, and assigned a PLT entry
8173 to this function, it must either be a STT_GNU_IFUNC reference
8174 or not be known to bind locally. In other cases, we should
8175 have cleared the PLT entry by now. */
8185 }
8187 /* When generating a shared object or relocatable executable, these
8188 relocations are copied into the output file to be resolved at
8189 run time. */
8207 {
8208 Elf_Internal_Rela outrel;
8214 {
8220 }
8244 else
8245 {
8248 /* This symbol is local, or marked to become local. */
8251 {
8254 /* On Symbian OS, the data segment and text segement
8255 can be relocated independently. Therefore, we
8256 must indicate the segment to which this
8257 relocation is relative. The BPABI allows us to
8258 use any symbol in the right segment; we just use
8259 the section symbol as it is convenient. (We
8260 cannot use the symbol given by "h" directly as it
8261 will not appear in the dynamic symbol table.)
8263 Note that the dynamic linker ignores the section
8264 symbol value, so we don't subtract osec->vma
8265 from the emitted reloc addend. */
8268 else
8272 {
8278 else
8281 }
8283 }
8284 else
8285 /* On SVR4-ish systems, the dynamic loader cannot
8286 relocate the text and data segments independently,
8287 so the symbol does not matter. */
8290 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8291 to the .iplt entry. Instead, every non-call reference
8292 must use an R_ARM_IRELATIVE relocation to obtain the
8293 correct run-time address. */
8295 else
8299 else
8301 }
8305 /* If this reloc is against an external symbol, we do not want to
8306 fiddle with the addend. Otherwise, we need to include the symbol
8307 value so that it becomes an addend for the dynamic reloc. */
8314 }
8316 {
8325 {
8329 {
8330 /* Check for Arm calling Arm function. */
8331 /* FIXME: Should we translate the instruction into a BL
8332 instruction instead ? */
8336 input_bfd,
8338 }
8340 {
8341 /* Check for Arm calling Thumb function. */
8343 {
8348 error_message))
8350 else
8352 }
8353 }
8355 /* Check if a stub has to be inserted because the
8356 destination is too far or we are changing mode. */
8360 {
8371 {
8372 /* The target is out of reach, so redirect the
8373 branch to the local stub for this function. */
8377 stub_type);
8378 {
8386 }
8387 }
8388 else
8389 {
8390 /* If the call goes through a PLT entry, make sure to
8391 check distance to the right destination address. */
8393 {
8398 /* The PLT entry is in ARM mode, regardless of the
8399 target function. */
8401 }
8402 }
8403 }
8405 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8406 where:
8407 S is the address of the symbol in the relocation.
8408 P is address of the instruction being relocated.
8409 A is the addend (extracted from the instruction) in bytes.
8411 S is held in 'value'.
8412 P is the base address of the section containing the
8413 instruction plus the offset of the reloc into that
8414 section, ie:
8415 (input_section->output_section->vma +
8416 input_section->output_offset +
8417 rel->r_offset).
8418 A is the addend, converted into bytes, ie:
8419 (signed_addend * 4)
8421 Note: None of these operations have knowledge of the pipeline
8422 size of the processor, thus it is up to the assembler to
8423 encode this information into the addend. */
8429 else
8430 /* RELA addends do not have to be adjusted by howto->size. */
8436 /* A branch to an undefined weak symbol is turned into a jump to
8437 the next instruction unless a PLT entry will be created.
8438 Do the same for local undefined symbols (but not for STN_UNDEF).
8439 The jump to the next instruction is optimized as a NOP depending
8440 on the architecture. */
8444 {
8449 else
8451 }
8452 else
8453 {
8454 /* Perform a signed range check. */
8465 {
8466 /* Set the H bit in the BLX instruction. */
8468 {
8471 else
8473 }
8475 /* Select the correct instruction (BL or BLX). */
8476 /* Only if we are not handling a BL to a stub. In this
8477 case, mode switching is performed by the stub. */
8481 {
8484 }
8485 }
8486 }
8487 }
8519 {
8520 /* Check for overflow. */
8523 }
8529 }
8537 /* There is no way to tell whether the user intended to use a signed or
8538 unsigned addend. When checking for overflow we accept either,
8539 as specified by the AAELF. */
8549 /* See comment for R_ARM_ABS8. */
8557 /* Support ldr and str instructions for the thumb. */
8559 {
8560 /* Need to refetch addend. */
8562 /* ??? Need to determine shift amount from operand size. */
8564 }
8567 /* ??? Isn't value unsigned? */
8571 /* ??? Value needs to be properly shifted into place first. */
8577 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8578 {
8579 bfd_vma insn;
8580 bfd_signed_vma relocation;
8586 {
8591 }
8613 }
8616 /* PR 10073: This reloc is not generated by the GNU toolchain,
8617 but it is supported for compatibility with third party libraries
8618 generated by other compilers, specifically the ARM/IAR. */
8619 {
8620 bfd_vma insn;
8621 bfd_signed_vma relocation;
8635 /* We do not check for overflow of this reloc. Although strictly
8636 speaking this is incorrect, it appears to be necessary in order
8637 to work with IAR generated relocs. Since GCC and GAS do not
8638 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8639 a problem for them. */
8647 }
8650 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8651 {
8652 bfd_vma insn;
8653 bfd_signed_vma relocation;
8659 {
8663 }
8683 }
8688 /* Thumb BL (branch long instruction). */
8689 {
8690 bfd_vma relocation;
8691 bfd_vma reloc_sign;
8695 bfd_signed_vma reloc_signed_max;
8696 bfd_signed_vma reloc_signed_min;
8697 bfd_vma check;
8698 bfd_signed_vma signed_check;
8702 /* A branch to an undefined weak symbol is turned into a jump to
8703 the next instruction unless a PLT entry will be created.
8704 The jump to the next instruction is optimized as a NOP.W for
8705 Thumb-2 enabled architectures. */
8708 {
8710 {
8713 }
8714 else
8715 {
8718 }
8720 }
8722 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8723 with Thumb-1) involving the J1 and J2 bits. */
8725 {
8735 /* Sign extend. */
8739 }
8742 {
8743 /* Check for Thumb to Thumb call. */
8744 /* FIXME: Should we translate the instruction into a BL
8745 instruction instead ? */
8749 input_bfd,
8751 }
8752 else
8753 {
8754 /* If it is not a call to Thumb, assume call to Arm.
8755 If it is a call relative to a section name, then it is not a
8756 function call at all, but rather a long jump. Calls through
8757 the PLT do not require stubs. */
8759 {
8761 {
8762 /* Convert BL to BLX. */
8764 }
8767 {
8771 error_message))
8773 else
8775 }
8776 }
8780 {
8781 /* Make sure this is a BL. */
8783 }
8784 }
8788 {
8789 /* Check if a stub has to be inserted because the destination
8790 is too far. */
8802 {
8803 /* The target is out of reach or we are changing modes, so
8804 redirect the branch to the local stub for this
8805 function. */
8809 stub_type);
8811 {
8818 }
8820 /* If this call becomes a call to Arm, force BLX. */
8822 {
8827 }
8828 }
8829 }
8831 /* Handle calls via the PLT. */
8833 {
8839 {
8840 /* If the Thumb BLX instruction is available, convert
8841 the BL to a BLX instruction to call the ARM-mode
8842 PLT entry. */
8845 }
8846 else
8847 {
8848 /* Target the Thumb stub before the ARM PLT entry. */
8851 }
8853 }
8863 /* If this is a signed value, the rightshift just dropped
8864 leading 1 bits (assuming twos complement). */
8867 else
8870 /* Calculate the permissable maximum and minimum values for
8871 this relocation according to whether we're relocating for
8872 Thumb-2 or not. */
8879 /* Assumes two's complement. */
8884 /* For a BLX instruction, make sure that the relocation is rounded up
8885 to a word boundary. This follows the semantics of the instruction
8886 which specifies that bit 1 of the target address will come from bit
8887 1 of the base address. */
8890 /* Put RELOCATION back into the insn. Assumes two's complement.
8891 We use the Thumb-2 encoding, which is safe even if dealing with
8892 a Thumb-1 instruction by virtue of our overflow check above. */
8902 /* Put the relocated value back in the object file: */
8907 }
8911 /* Thumb32 conditional branch instruction. */
8912 {
8913 bfd_vma relocation;
8919 bfd_signed_vma signed_check;
8921 /* Need to refetch the addend, reconstruct the top three bits,
8922 and squish the two 11 bit pieces together. */
8924 {
8938 }
8940 /* Handle calls via the PLT. */
8942 {
8946 /* Target the Thumb stub before the ARM PLT entry. */
8949 }
8951 /* ??? Should handle interworking? GCC might someday try to
8952 use this for tail calls. */
8963 /* Put RELOCATION back into the insn. */
8964 {
8973 }
8975 /* Put the relocated value back in the object file: */
8980 }
8985 /* Thumb B (branch) instruction). */
8986 {
8987 bfd_signed_vma relocation;
8990 bfd_signed_vma signed_check;
8992 /* CZB cannot jump backward. */
8997 {
8998 /* Need to refetch addend. */
9001 {
9005 }
9006 else
9008 /* The value in the insn has been right shifted. We need to
9009 undo this, so that we can perform the address calculation
9010 in terms of bytes. */
9012 }
9024 else
9030 /* Assumes two's complement. */
9035 }
9040 {
9041 bfd_vma insn;
9042 bfd_vma relocation;
9046 {
9047 /* Extract the addend. */
9050 }
9060 }
9068 /* Relocation is relative to the start of the
9069 global offset table. */
9075 /* If we are addressing a Thumb function, we need to adjust the
9076 address by one, so that attempts to call the function pointer will
9077 correctly interpret it as Thumb code. */
9081 /* Note that sgot->output_offset is not involved in this
9082 calculation. We always want the start of .got. If we
9083 define _GLOBAL_OFFSET_TABLE in a different way, as is
9084 permitted by the ABI, we might have to change this
9085 calculation. */
9092 /* Use global offset table as symbol value. */
9106 /* Relocation is to the entry for this symbol in the
9107 global offset table. */
9114 {
9115 /* We have a relocation against a locally-binding STT_GNU_IFUNC
9116 symbol, and the relocation resolves directly to the runtime
9117 target rather than to the .iplt entry. This means that any
9118 .got entry would be the same value as the .igot.plt entry,
9119 so there's no point creating both. */
9122 }
9124 {
9125 bfd_vma off;
9130 {
9131 /* We have already processsed one GOT relocation against
9132 this symbol. */
9137 }
9138 else
9139 {
9140 Elf_Internal_Rela outrel;
9143 {
9144 /* If the symbol doesn't resolve locally in a static
9145 object, we have an undefined reference. If the
9146 symbol doesn't resolve locally in a dynamic object,
9147 it should be resolved by the dynamic linker. */
9149 {
9152 }
9153 else
9156 }
9157 else
9158 {
9163 else
9166 }
9168 /* The GOT entry is initialized to zero by default.
9169 See if we should install a different value. */
9172 {
9176 }
9179 {
9184 }
9186 }
9188 }
9189 else
9190 {
9191 bfd_vma off;
9198 /* The offset must always be a multiple of 4. We use the
9199 least significant bit to record whether we have already
9200 generated the necessary reloc. */
9203 else
9204 {
9209 {
9210 Elf_Internal_Rela outrel;
9218 else
9221 }
9224 }
9227 }
9243 {
9244 bfd_vma off;
9253 else
9254 {
9255 /* If we don't know the module number, create a relocation
9256 for it. */
9258 {
9259 Elf_Internal_Rela outrel;
9274 }
9275 else
9279 }
9287 }
9296 {
9304 {
9305 bfd_boolean dyn;
9310 {
9313 }
9317 }
9318 else
9319 {
9324 }
9326 /* Linker relaxations happens from one of the
9327 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9335 else
9336 {
9338 Elf_Internal_Rela outrel;
9341 /* The GOT entries have not been initialized yet. Do it
9342 now, and emit any relocations. If both an IE GOT and a
9343 GD GOT are necessary, we emit the GD first. */
9349 {
9352 }
9355 {
9358 /* We should have relaxed, unless this is an undefined
9359 weak symbol. */
9368 + offplt
9380 /* For globals, the first word in the relocation gets
9381 the relocation index and the top bit set, or zero,
9382 if we're binding now. For locals, it gets the
9383 symbol's offset in the tls section. */
9391 /* Second word in the relocation is always zero. */
9395 }
9397 {
9399 {
9415 else
9416 {
9419 R_ARM_TLS_DTPOFF32);
9428 }
9429 }
9430 else
9431 {
9432 /* If we are not emitting relocations for a
9433 general dynamic reference, then we must be in a
9434 static link or an executable link with the
9435 symbol binding locally. Mark it as belonging
9436 to module 1, the executable. */
9441 }
9444 }
9447 {
9449 {
9452 else
9464 }
9465 else
9469 }
9473 else
9475 }
9484 {
9485 bfd_signed_vma offset;
9486 /* TLS stubs are arm mode. The original symbol is a
9487 data object, so branch_type is bogus. */
9489 enum elf32_arm_stub_type stub_type
9497 {
9499 = elf32_arm_get_stub_entry
9505 }
9506 else
9512 {
9522 }
9523 else
9524 {
9525 /* Thumb blx encodes the offset in a complicated
9526 fashion. */
9536 {
9538 }
9539 else
9540 {
9542 /* Round up the offset to a word boundary */
9544 }
9556 }
9557 }
9558 /* These relocations needs special care, as besides the fact
9559 they point somewhere in .gotplt, the addend must be
9560 adjusted accordingly depending on the type of instruction
9561 we refer to */
9563 {
9572 {
9579 /* bl/blx */
9582 /* add */
9584 else
9585 {
9591 }
9592 }
9593 else
9594 {
9598 {
9614 }
9615 }
9623 }
9624 else
9633 }
9637 {
9643 }
9644 else
9653 {
9656 /* Ensure that we have a BX instruction. */
9660 {
9661 /* Branch to veneer. */
9662 bfd_vma glue_addr;
9669 }
9670 else
9671 {
9672 /* Preserve Rm (lowest four bits) and the condition code
9673 (highest four bits). Other bits encode MOV PC,Rm. */
9675 }
9678 }
9685 /* Until we properly support segment-base-relative addressing then
9686 we assume the segment base to be zero, as for the group relocations.
9687 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9688 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9692 {
9696 {
9699 }
9721 }
9728 /* Until we properly support segment-base-relative addressing then
9729 we assume the segment base to be zero, as for the above relocations.
9730 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9731 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9732 as R_ARM_THM_MOVT_ABS. */
9736 {
9737 bfd_vma insn;
9743 {
9749 }
9775 }
9788 {
9792 /* sb should be the origin of the *segment* containing the symbol.
9793 It is not clear how to obtain this OS-dependent value, so we
9794 make an arbitrary choice of zero. */
9796 bfd_vma residual;
9797 bfd_vma g_n;
9798 bfd_signed_vma signed_value;
9801 /* Determine which group of bits to select. */
9803 {
9825 }
9827 /* If REL, extract the addend from the insn. If RELA, it will
9828 have already been fetched for us. */
9830 {
9837 else
9838 {
9839 /* Compensate for the fact that in the instruction, the
9840 rotation is stored in multiples of 2 bits. */
9843 /* Rotate "constant" right by "rotation" bits. */
9846 }
9848 /* Determine if the instruction is an ADD or a SUB.
9849 (For REL, this determines the sign of the addend.) */
9852 {
9858 }
9861 }
9863 /* Compute the value (X) to go in the place. */
9869 /* PC relative. */
9871 else
9872 /* Section base relative. */
9875 /* If the target symbol is a Thumb function, then set the
9876 Thumb bit in the address. */
9880 /* Calculate the value of the relevant G_n, in encoded
9881 constant-with-rotation format. */
9885 /* Check for overflow if required. */
9892 {
9898 }
9900 /* Mask out the value and the ADD/SUB part of the opcode; take care
9901 not to destroy the S bit. */
9904 /* Set the opcode according to whether the value to go in the
9905 place is negative. */
9908 else
9911 /* Encode the offset. */
9915 }
9924 {
9929 bfd_vma residual;
9930 bfd_signed_vma signed_value;
9933 /* Determine which groups of bits to calculate. */
9935 {
9953 }
9955 /* If REL, extract the addend from the insn. If RELA, it will
9956 have already been fetched for us. */
9958 {
9961 }
9963 /* Compute the value (X) to go in the place. */
9967 /* PC relative. */
9969 else
9970 /* Section base relative. */
9973 /* Calculate the value of the relevant G_{n-1} to obtain
9974 the residual at that stage. */
9977 /* Check for overflow. */
9979 {
9985 }
9987 /* Mask out the value and U bit. */
9990 /* Set the U bit if the value to go in the place is non-negative. */
9994 /* Encode the offset. */
9998 }
10007 {
10012 bfd_vma residual;
10013 bfd_signed_vma signed_value;
10016 /* Determine which groups of bits to calculate. */
10018 {
10036 }
10038 /* If REL, extract the addend from the insn. If RELA, it will
10039 have already been fetched for us. */
10041 {
10044 }
10046 /* Compute the value (X) to go in the place. */
10050 /* PC relative. */
10052 else
10053 /* Section base relative. */
10056 /* Calculate the value of the relevant G_{n-1} to obtain
10057 the residual at that stage. */
10060 /* Check for overflow. */
10062 {
10068 }
10070 /* Mask out the value and U bit. */
10073 /* Set the U bit if the value to go in the place is non-negative. */
10077 /* Encode the offset. */
10081 }
10090 {
10095 bfd_vma residual;
10096 bfd_signed_vma signed_value;
10099 /* Determine which groups of bits to calculate. */
10101 {
10119 }
10121 /* If REL, extract the addend from the insn. If RELA, it will
10122 have already been fetched for us. */
10124 {
10127 }
10129 /* Compute the value (X) to go in the place. */
10133 /* PC relative. */
10135 else
10136 /* Section base relative. */
10139 /* Calculate the value of the relevant G_{n-1} to obtain
10140 the residual at that stage. */
10143 /* Check for overflow. (The absolute value to go in the place must be
10144 divisible by four and, after having been divided by four, must
10145 fit in eight bits.) */
10147 {
10153 }
10155 /* Mask out the value and U bit. */
10158 /* Set the U bit if the value to go in the place is non-negative. */
10162 /* Encode the offset. */
10166 }
10171 }
10172 }
10174 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
10175 static void
10179 bfd_signed_vma increment)
10180 {
10181 bfd_signed_vma addend;
10185 {
10203 }
10204 else
10205 {
10206 bfd_vma contents;
10210 /* Get the (signed) value from the instruction. */
10213 {
10214 bfd_signed_vma mask;
10219 }
10221 /* Add in the increment, (which is a byte value). */
10223 {
10235 /* Should we check for overflow here ? */
10237 /* Drop any undesired bits. */
10240 }
10245 }
10246 }
10248 #define IS_ARM_TLS_RELOC(R_TYPE) \
10249 ((R_TYPE) == R_ARM_TLS_GD32 \
10250 || (R_TYPE) == R_ARM_TLS_LDO32 \
10251 || (R_TYPE) == R_ARM_TLS_LDM32 \
10252 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10253 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10254 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10255 || (R_TYPE) == R_ARM_TLS_LE32 \
10256 || (R_TYPE) == R_ARM_TLS_IE32 \
10257 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10259 /* Specific set of relocations for the gnu tls dialect. */
10260 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10261 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10262 || (R_TYPE) == R_ARM_TLS_CALL \
10263 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10264 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10265 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10267 /* Relocate an ARM ELF section. */
10269 static bfd_boolean
10278 {
10296 {
10303 bfd_vma relocation;
10304 bfd_reloc_status_type r;
10305 arelent bfd_reloc;
10326 {
10331 /* An object file might have a reference to a local
10332 undefined symbol. This is a daft object file, but we
10333 should at least do something about it. V4BX & NONE
10334 relocations do not use the symbol and are explicitly
10335 allowed to use the undefined symbol, so allow those.
10336 Likewise for relocations against STN_UNDEF. */
10342 {
10349 }
10352 {
10359 {
10364 {
10386 {
10392 }
10396 /* Get the (signed) value from the instruction. */
10399 {
10400 bfd_signed_vma mask;
10405 }
10407 }
10410 addend =
10415 /* Cases here must match those in the preceding
10416 switch statement. */
10418 {
10441 }
10442 }
10443 }
10444 else
10446 }
10447 else
10448 {
10449 bfd_boolean warned;
10457 }
10464 {
10465 /* This is a relocatable link. We don't have to change
10466 anything, unless the reloc is against a section symbol,
10467 in which case we have to adjust according to where the
10468 section symbol winds up in the output section. */
10470 {
10474 else
10476 }
10478 }
10482 else
10483 {
10484 name = (bfd_elf_string_from_elf_section
10488 }
10496 {
10501 input_bfd,
10502 input_section,
10505 name);
10506 }
10508 /* We call elf32_arm_final_link_relocate unless we're completely
10509 done, i.e., the relaxation produced the final output we want,
10510 and we won't let anybody mess with it. Also, we have to do
10511 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10512 both in relaxed and non-relaxed cases */
10518 {
10521 /* This may have been marked unresolved because it came from
10522 a shared library. But we've just dealt with that. */
10524 }
10525 else
10536 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10537 because such sections are not SEC_ALLOC and thus ld.so will
10538 not process them. */
10544 {
10547 input_bfd,
10548 input_section,
10553 }
10556 {
10558 {
10560 /* If the overflowing reloc was to an undefined symbol,
10561 we have already printed one error message and there
10562 is no point complaining again. */
10588 /* error_message should already be set. */
10593 /* Fall through. */
10595 common_error:
10602 }
10603 }
10604 }
10607 }
10609 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10610 adds the edit to the start of the list. (The list must be built in order of
10611 ascending TINDEX: the function's callers are primarily responsible for
10612 maintaining that condition). */
10614 static void
10617 arm_unwind_edit_type type,
10620 {
10629 {
10639 }
10640 else
10641 {
10648 }
10649 }
10653 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10654 static void
10656 {
10664 /* Adjust size of output section. */
10666 }
10668 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10669 static void
10671 {
10681 }
10683 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10684 made to those tables, such that:
10686 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10687 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10688 codes which have been inlined into the index).
10690 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10692 The edits are applied when the tables are written
10693 (in elf32_arm_write_section). */
10695 bfd_boolean
10699 bfd_boolean merge_exidx_entries)
10700 {
10707 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10708 text sections. */
10710 {
10714 {
10722 {
10723 Elf_Internal_Shdr *linked_hdr
10731 /* Link this .ARM.exidx section back from the text section it
10732 describes. */
10734 }
10735 }
10736 }
10738 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10739 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10740 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10743 {
10750 bfd_vma j;
10761 {
10762 /* Section has no unwind data. */
10766 /* Ignore zero sized sections. */
10773 }
10775 /* Skip /DISCARD/ sections. */
10792 /* An error? */
10796 {
10801 /* An EXIDX_CANTUNWIND entry. */
10803 {
10807 }
10808 /* Inlined unwinding data. Merge if equal to previous. */
10810 {
10816 }
10817 /* Normal table entry. In theory we could merge these too,
10818 but duplicate entries are likely to be much less common. */
10819 else
10823 {
10828 }
10831 }
10833 /* Free contents if we allocated it ourselves. */
10837 /* Record edits to be applied later (in elf32_arm_write_section). */
10846 }
10848 /* Add terminating CANTUNWIND entry. */
10853 }
10855 static bfd_boolean
10858 {
10874 }
10876 static bfd_boolean
10878 {
10885 /* Invoke the regular ELF backend linker to do all the work. */
10889 /* Process stub sections (eg BE8 encoding, ...). */
10893 {
10895 /* Only process it once, in its link_sec slot. */
10897 {
10903 }
10904 }
10906 /* Write out any glue sections now that we have created all the
10907 stubs. */
10909 {
10912 ARM2THUMB_GLUE_SECTION_NAME))
10917 THUMB2ARM_GLUE_SECTION_NAME))
10922 VFP11_ERRATUM_VENEER_SECTION_NAME))
10927 ARM_BX_GLUE_SECTION_NAME))
10929 }
10932 }
10934 /* Return a best guess for the machine number based on the attributes. */
10936 static unsigned int
10938 {
10942 {
10948 {
10955 {
10961 }
10964 }
10968 }
10969 }
10971 /* Set the right machine number. */
10973 static bfd_boolean
10975 {
10981 {
10984 else
10986 }
10990 }
10992 /* Function to keep ARM specific flags in the ELF header. */
10994 static bfd_boolean
10996 {
10999 {
11001 {
11004 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11005 abfd);
11006 else
11007 _bfd_error_handler
11009 abfd);
11010 }
11011 }
11012 else
11013 {
11016 }
11019 }
11021 /* Copy backend specific data from one object module to another. */
11023 static bfd_boolean
11025 {
11026 flagword in_flags;
11027 flagword out_flags;
11038 {
11039 /* Cannot mix APCS26 and APCS32 code. */
11043 /* Cannot mix float APCS and non-float APCS code. */
11047 /* If the src and dest have different interworking flags
11048 then turn off the interworking bit. */
11050 {
11052 _bfd_error_handler
11053 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
11057 }
11059 /* Likewise for PIC, though don't warn for this case. */
11062 }
11067 /* Also copy the EI_OSABI field. */
11071 /* Copy object attributes. */
11075 }
11077 /* Values for Tag_ABI_PCS_R9_use. */
11078 enum
11079 {
11080 AEABI_R9_V6,
11081 AEABI_R9_SB,
11082 AEABI_R9_TLS,
11083 AEABI_R9_unused
11084 };
11086 /* Values for Tag_ABI_PCS_RW_data. */
11087 enum
11088 {
11089 AEABI_PCS_RW_data_absolute,
11090 AEABI_PCS_RW_data_PCrel,
11091 AEABI_PCS_RW_data_SBrel,
11092 AEABI_PCS_RW_data_unused
11093 };
11095 /* Values for Tag_ABI_enum_size. */
11096 enum
11097 {
11098 AEABI_enum_unused,
11099 AEABI_enum_short,
11100 AEABI_enum_wide,
11101 AEABI_enum_forced_wide
11102 };
11104 /* Determine whether an object attribute tag takes an integer, a
11105 string or both. */
11107 static int
11109 {
11118 else
11120 }
11122 /* The ABI defines that Tag_conformance should be emitted first, and that
11123 Tag_nodefaults should be second (if either is defined). This sets those
11124 two positions, and bumps up the position of all the remaining tags to
11125 compensate. */
11126 static int
11128 {
11138 }
11140 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
11141 static bfd_boolean
11143 {
11145 {
11146 _bfd_error_handler
11151 }
11152 else
11153 {
11154 _bfd_error_handler
11158 }
11159 }
11161 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
11162 Returns -1 if no architecture could be read. */
11164 static int
11166 {
11170 /* Note: the tag and its argument below are uleb128 values, though
11171 currently-defined values fit in one byte for each. */
11178 /* This tag is "safely ignorable", so don't complain if it looks funny. */
11180 }
11182 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
11183 The tag is removed if ARCH is -1. */
11185 static void
11187 {
11192 {
11195 }
11197 /* Note: the tag and its argument below are uleb128 values, though
11198 currently-defined values fit in one byte for each. */
11204 }
11206 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
11207 into account. */
11209 static int
11212 {
11213 #define T(X) TAG_CPU_ARCH_##X
11216 {
11226 };
11228 {
11239 };
11241 {
11253 };
11255 {
11268 };
11270 {
11284 };
11286 {
11301 };
11303 {
11319 };
11321 {
11338 };
11340 {
11341 v6t2,
11342 v6k,
11343 v7,
11344 v6_m,
11345 v6s_m,
11346 v7e_m,
11347 v8,
11348 /* Pseudo-architecture. */
11349 v4t_plus_v6_m
11350 };
11352 /* Check we've not got a higher architecture than we know about. */
11355 {
11358 }
11360 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11366 /* And override the new tag if we have a Tag_also_compatible_with on the
11367 input. */
11376 /* Architectures before V6KZ add features monotonically. */
11382 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11383 as the canonical version. */
11385 {
11388 }
11389 else
11393 {
11397 }
11400 #undef T
11401 }
11403 /* Query attributes object to see if integer divide instructions may be
11404 present in an object. */
11405 static bfd_boolean
11407 {
11412 {
11414 /* Integer divide allowed if instruction contained in archetecture. */
11419 else
11423 /* Integer divide explicitly prohibited. */
11427 /* Unrecognised case - treat as allowing divide everywhere. */
11429 /* Integer divide allowed in ARM state. */
11431 }
11432 }
11434 /* Query attributes object to see if integer divide instructions are
11435 forbidden to be in the object. This is not the inverse of
11436 elf32_arm_attributes_accept_div. */
11437 static bfd_boolean
11439 {
11441 }
11443 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11444 are conflicting attributes. */
11446 static bfd_boolean
11448 {
11451 /* Some tags have 0 = don't care, 1 = strong requirement,
11452 2 = weak requirement. */
11457 /* Skip the linker stubs file. This preserves previous behavior
11458 of accepting unknown attributes in the first input file - but
11459 is that a bug? */
11464 {
11465 /* This is the first object. Copy the attributes. */
11470 /* Use the Tag_null value to indicate the attributes have been
11471 initialized. */
11474 /* We do not output objects with Tag_MPextension_use_legacy - we move
11475 the attribute's value to Tag_MPextension_use. */
11477 {
11481 {
11482 _bfd_error_handler
11486 }
11492 }
11495 }
11499 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11501 {
11502 /* Ignore mismatches if the object doesn't use floating point. */
11506 {
11507 _bfd_error_handler
11512 }
11513 }
11516 {
11517 /* Merge this attribute with existing attributes. */
11519 {
11522 /* These are merged after Tag_CPU_arch. */
11527 /* Use the first value seen. */
11531 {
11535 /* These aren't real CPU names, but we can't guess
11536 that from the architecture version alone. */
11550 "ARM v8"
11551 };
11553 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11559 secondary_compat);
11562 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11566 {
11567 /* The output architecture has been changed to match the
11568 input architecture. Use the input names. */
11575 }
11576 else
11577 {
11580 }
11582 /* If we still don't have a value for Tag_CPU_name,
11583 make one up now. Tag_CPU_raw_name remains blank. */
11588 }
11595 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11604 /* Use the largest value specified. */
11611 /* Use the smallest value specified. */
11620 {
11621 /* This error message should be enabled once all non-conformant
11622 binaries in the toolchain have had the attributes set
11623 properly.
11624 _bfd_error_handler
11625 (_("error: %B: 8-byte data alignment conflicts with %B"),
11626 obfd, ibfd);
11627 result = FALSE; */
11628 }
11629 /* Fall through. */
11632 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11633 value if greater than 2 (for future-proofing). */
11641 /* The virtualization tag effectively stores two bits of
11642 information: the intended use of TrustZone (in bit 0), and the
11643 intended use of Virtualization (in bit 1). */
11648 {
11651 else
11652 {
11653 _bfd_error_handler
11658 }
11659 }
11664 {
11665 /* 0 will merge with anything.
11666 'A' and 'S' merge to 'A'.
11667 'R' and 'S' merge to 'R'.
11668 'M' and 'A|R|S' is an error. */
11677 else
11678 {
11679 _bfd_error_handler
11681 ibfd,
11685 }
11686 }
11689 {
11690 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11691 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11692 when it's 0. It might mean absence of FP hardware if
11693 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11695 #define VFP_VERSION_COUNT 8
11696 static const struct
11697 {
11701 {
11710 };
11715 /* If the output has no requirement about FP hardware,
11716 follow the requirement of the input. */
11718 {
11724 }
11725 /* If the input has no requirement about FP hardware, do
11726 nothing. */
11728 {
11731 }
11733 /* Both the input and the output have nonzero Tag_FP_arch.
11734 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11736 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11737 do nothing. */
11740 ;
11741 /* If the input and the output have different Tag_ABI_HardFP_use,
11742 the combination of them is 3 (SP & DP). */
11747 /* Now we can handle Tag_FP_arch. */
11749 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
11750 pick the biggest. */
11753 {
11756 }
11757 /* The output uses the superset of input features
11758 (ISA version) and registers. */
11765 /* This assumes all possible supersets are also a valid
11766 options. */
11768 {
11772 }
11774 }
11780 {
11781 /* It's sometimes ok to mix different configs, so this is only
11782 a warning. */
11783 _bfd_error_handler
11785 }
11791 {
11792 _bfd_error_handler
11795 }
11803 {
11804 _bfd_error_handler
11806 ibfd);
11808 }
11809 /* Use the smallest value specified. */
11816 {
11817 _bfd_error_handler
11818 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
11820 }
11826 {
11829 {
11830 /* The existing object is compatible with anything.
11831 Use whatever requirements the new object has. */
11833 }
11837 {
11848 _bfd_error_handler
11849 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
11851 }
11852 }
11855 /* Aready done. */
11859 {
11860 _bfd_error_handler
11864 }
11867 /* Merged in target-independent code. */
11870 /* This is handled along with Tag_FP_arch. */
11874 {
11876 {
11877 _bfd_error_handler
11881 }
11882 }
11888 /* A value of zero on input means that the divide instruction may
11889 be used if available in the base architecture as specified via
11890 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
11891 the user did not want divide instructions. A value of 2
11892 explicitly means that divide instructions were allowed in ARM
11893 and Thumb state. */
11907 /* We don't output objects with Tag_MPextension_use_legacy - we
11908 move the value to Tag_MPextension_use. */
11910 {
11912 {
11913 _bfd_error_handler
11916 ibfd);
11918 }
11919 }
11927 /* This tag is set if it exists, but the value is unused (and is
11928 typically zero). We don't actually need to do anything here -
11929 the merge happens automatically when the type flags are merged
11930 below. */
11933 /* Already done in Tag_CPU_arch. */
11936 /* Keep the attribute if it matches. Throw it away otherwise.
11937 No attribute means no claim to conform. */
11944 result
11946 }
11948 /* If out_attr was copied from in_attr then it won't have a type yet. */
11951 }
11953 /* Merge Tag_compatibility attributes and any common GNU ones. */
11957 /* Check for any attributes not known on ARM. */
11961 }
11964 /* Return TRUE if the two EABI versions are incompatible. */
11966 static bfd_boolean
11968 {
11969 /* v4 and v5 are the same spec before and after it was released,
11970 so allow mixing them. */
11976 }
11978 /* Merge backend specific data from an object file to the output
11979 object file when linking. */
11981 static bfd_boolean
11984 /* Display the flags field. */
11986 static bfd_boolean
11988 {
11994 /* Print normal ELF private data. */
11998 /* Ignore init flag - it may not be set, despite the flags field
11999 containing valid data. */
12001 /* xgettext:c-format */
12005 {
12007 /* The following flag bits are GNU extensions and not part of the
12008 official ARM ELF extended ABI. Hence they are only decoded if
12009 the EABI version is not set. */
12015 else
12022 else
12051 else
12062 else
12094 eabi:
12107 }
12125 }
12127 static int
12129 {
12131 {
12136 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
12137 This allows us to distinguish between data used by Thumb instructions
12138 and non-data (which is probably code) inside Thumb regions of an
12139 executable. */
12146 }
12149 }
12157 {
12160 {
12164 }
12167 }
12169 /* Update the got entry reference counts for the section being removed. */
12171 static bfd_boolean
12176 {
12200 {
12205 bfd_boolean call_reloc_p;
12206 bfd_boolean may_become_dynamic_p;
12207 bfd_boolean may_need_local_target_p;
12213 {
12218 }
12228 {
12234 {
12237 }
12239 {
12242 }
12263 {
12266 }
12267 /* Fall through. */
12280 /* Should the interworking branches be here also? */
12283 {
12286 {
12289 }
12290 else
12292 }
12293 else
12299 }
12303 {
12304 /* If PLT refcount book-keeping is wrong and too low, we'll
12305 see a zero value (going to -1) for the root PLT reference
12306 count. */
12308 {
12311 }
12312 else
12313 /* A value of -1 means the symbol has become local, forced
12314 or seeing a hidden definition. Any other negative value
12315 is an error. */
12327 }
12330 {
12336 else
12337 {
12347 }
12350 {
12351 /* Everything must go for SEC. */
12354 }
12355 }
12356 }
12359 }
12361 /* Look through the relocs for a section during the first phase. */
12363 static bfd_boolean
12366 {
12374 bfd_boolean call_reloc_p;
12375 bfd_boolean may_become_dynamic_p;
12376 bfd_boolean may_need_local_target_p;
12390 /* Create dynamic sections for relocatable executables so that we can
12391 copy relocations. */
12394 {
12397 }
12412 {
12424 /* PR 9934: It is possible to have relocations that do not
12425 refer to symbols, thus it is also possible to have an
12426 object file containing relocations but no symbol table. */
12428 {
12430 r_symndx);
12432 }
12437 {
12439 {
12440 /* A local symbol. */
12445 }
12446 else
12447 {
12452 }
12453 }
12461 /* Could be done earlier, if h were already available. */
12464 {
12474 /* This symbol requires a global offset table entry. */
12475 {
12479 {
12490 }
12493 {
12496 }
12497 else
12498 {
12499 /* This is a global offset table entry for a local symbol. */
12504 }
12506 /* If a variable is accessed with both tls methods, two
12507 slots may be created. */
12512 /* We will already have issued an error message if there
12513 is a TLS/non-TLS mismatch, based on the symbol
12514 type. So just combine any TLS types needed. */
12519 /* If the symbol is accessed in both IE and GDESC
12520 method, we're able to relax. Turn off the GDESC flag,
12521 without messing up with any other kind of tls types
12522 that may be involved */
12527 {
12530 else
12532 }
12533 }
12534 /* Fall through. */
12539 /* Fall through. */
12561 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12562 ldr __GOTT_INDEX__ offsets. */
12564 {
12567 }
12568 /* Fall through. */
12575 {
12577 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12582 }
12584 /* Fall through. */
12594 /* Should the interworking branches be listed here? */
12597 {
12600 {
12601 /* In shared libraries and relocatable executables,
12602 we treat local relative references as calls;
12603 see the related SYMBOL_CALLS_LOCAL code in
12604 allocate_dynrelocs. */
12607 }
12608 else
12609 /* We are creating a shared library or relocatable
12610 executable, and this is a reloc against a global symbol,
12611 or a non-PC-relative reloc against a local symbol.
12612 We may need to copy the reloc into the output. */
12614 }
12615 else
12619 /* This relocation describes the C++ object vtable hierarchy.
12620 Reconstruct it for later use during GC. */
12626 /* This relocation describes which C++ vtable entries are actually
12627 used. Record for later use during GC. */
12634 }
12637 {
12639 /* We may need a .plt entry if the function this reloc
12640 refers to is in a different object, regardless of the
12641 symbol's type. We can't tell for sure yet, because
12642 something later might force the symbol local. */
12645 /* If this reloc is in a read-only section, we might
12646 need a copy reloc. We can't check reliably at this
12647 stage whether the section is read-only, as input
12648 sections have not yet been mapped to output sections.
12649 Tentatively set the flag for now, and correct in
12650 adjust_dynamic_symbol. */
12652 }
12656 {
12662 {
12665 }
12666 else
12667 {
12673 }
12675 /* If the symbol is a function that doesn't bind locally,
12676 this relocation will need a PLT entry. */
12683 /* It's too early to use htab->use_blx here, so we have to
12684 record possible blx references separately from
12685 relocs that definitely need a thumb stub. */
12693 }
12696 {
12699 /* Create a reloc section in dynobj. */
12701 {
12702 sreloc = _bfd_elf_make_dynamic_reloc_section
12708 /* BPABI objects never have dynamic relocations mapped. */
12710 {
12711 flagword flags;
12716 }
12717 }
12719 /* If this is a global symbol, count the number of
12720 relocations we need for this symbol. */
12723 else
12724 {
12728 }
12732 {
12743 }
12748 }
12749 }
12752 }
12754 /* Unwinding tables are not referenced directly. This pass marks them as
12755 required if the corresponding code section is marked. */
12757 static bfd_boolean
12759 elf_gc_mark_hook_fn gc_mark_hook)
12760 {
12763 bfd_boolean again;
12767 /* Marking EH data may cause additional code sections to be marked,
12768 requiring multiple passes. */
12771 {
12774 {
12782 {
12791 {
12795 }
12796 }
12797 }
12798 }
12801 }
12803 /* Treat mapping symbols as special target symbols. */
12805 static bfd_boolean
12807 {
12809 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
12810 }
12812 /* This is a copy of elf_find_function() from elf.c except that
12813 ARM mapping symbols are ignored when looking for function names
12814 and STT_ARM_TFUNC is considered to a function type. */
12816 static bfd_boolean
12820 bfd_vma offset,
12823 {
12830 {
12836 {
12845 /* Skip mapping symbols. */
12848 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
12850 /* Fall through. */
12854 {
12857 }
12859 }
12860 }
12871 }
12874 /* Find the nearest line to a particular section and offset, for error
12875 reporting. This code is a duplicate of the code in elf.c, except
12876 that it uses arm_elf_find_function. */
12878 static bfd_boolean
12882 bfd_vma offset,
12886 {
12889 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
12896 {
12900 functionname_ptr);
12903 }
12923 }
12925 static bfd_boolean
12930 {
12931 bfd_boolean found;
12936 }
12938 /* Adjust a symbol defined by a dynamic object and referenced by a
12939 regular object. The current definition is in some section of the
12940 dynamic object, but we're not including those sections. We have to
12941 change the definition to something the rest of the link can
12942 understand. */
12944 static bfd_boolean
12947 {
12959 /* Make sure we know what is going on here. */
12970 /* If this is a function, put it in the procedure linkage table. We
12971 will fill in the contents of the procedure linkage table later,
12972 when we know the address of the .got section. */
12974 {
12975 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
12976 symbol binds locally. */
12982 {
12983 /* This case can occur if we saw a PLT32 reloc in an input
12984 file, but the symbol was never referred to by a dynamic
12985 object, or if all references were garbage collected. In
12986 such a case, we don't actually need to build a procedure
12987 linkage table, and we can just do a PC24 reloc instead. */
12993 }
12996 }
12997 else
12998 {
12999 /* It's possible that we incorrectly decided a .plt reloc was
13000 needed for an R_ARM_PC24 or similar reloc to a non-function sym
13001 in check_relocs. We can't decide accurately between function
13002 and non-function syms in check-relocs; Objects loaded later in
13003 the link may change h->type. So fix it now. */
13008 }
13010 /* If this is a weak symbol, and there is a real definition, the
13011 processor independent code will have arranged for us to see the
13012 real definition first, and we can just use the same value. */
13014 {
13020 }
13022 /* If there are no non-GOT references, we do not need a copy
13023 relocation. */
13027 /* This is a reference to a symbol defined by a dynamic object which
13028 is not a function. */
13030 /* If we are creating a shared library, we must presume that the
13031 only references to the symbol are via the global offset table.
13032 For such cases we need not do anything here; the relocations will
13033 be handled correctly by relocate_section. Relocatable executables
13034 can reference data in shared objects directly, so we don't need to
13035 do anything here. */
13039 /* We must allocate the symbol in our .dynbss section, which will
13040 become part of the .bss section of the executable. There will be
13041 an entry for this symbol in the .dynsym section. The dynamic
13042 object will contain position independent code, so all references
13043 from the dynamic object to this symbol will go through the global
13044 offset table. The dynamic linker will use the .dynsym entry to
13045 determine the address it must put in the global offset table, so
13046 both the dynamic object and the regular object will refer to the
13047 same memory location for the variable. */
13051 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
13052 copy the initial value out of the dynamic object and into the
13053 runtime process image. We need to remember the offset into the
13054 .rel(a).bss section we are going to use. */
13056 {
13062 }
13065 }
13067 /* Allocate space in .plt, .got and associated reloc sections for
13068 dynamic relocs. */
13070 static bfd_boolean
13072 {
13090 {
13091 /* Make sure this symbol is output as a dynamic symbol.
13092 Undefined weak syms won't yet be marked as dynamic. */
13095 {
13098 }
13100 /* If the call in the PLT entry binds locally, the associated
13101 GOT entry should use an R_ARM_IRELATIVE relocation instead of
13102 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
13103 than the .plt section. */
13105 {
13109 /* All non-call references can be resolved directly.
13110 This means that they can (and in some cases, must)
13111 resolve directly to the run-time target, rather than
13112 to the PLT. That in turns means that any .got entry
13113 would be equal to the .igot.plt entry, so there's
13114 no point having both. */
13116 }
13121 {
13124 /* If this symbol is not defined in a regular file, and we are
13125 not generating a shared library, then set the symbol to this
13126 location in the .plt. This is required to make function
13127 pointers compare as equal between the normal executable and
13128 the shared library. */
13131 {
13135 /* Make sure the function is not marked as Thumb, in case
13136 it is the target of an ABS32 relocation, which will
13137 point to the PLT entry. */
13139 }
13143 /* VxWorks executables have a second set of relocations for
13144 each PLT entry. They go in a separate relocation section,
13145 which is processed by the kernel loader. */
13147 {
13148 /* There is a relocation for the initial PLT entry:
13149 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
13153 /* There are two extra relocations for each subsequent
13154 PLT entry: an R_ARM_32 relocation for the GOT entry,
13155 and an R_ARM_32 relocation for the PLT entry. */
13157 }
13158 }
13159 else
13160 {
13163 }
13164 }
13165 else
13166 {
13169 }
13175 {
13177 bfd_boolean dyn;
13181 /* Make sure this symbol is output as a dynamic symbol.
13182 Undefined weak syms won't yet be marked as dynamic. */
13185 {
13188 }
13191 {
13199 /* Non-TLS symbols need one GOT slot. */
13201 else
13202 {
13204 {
13205 /* R_ARM_TLS_DESC needs 2 GOT slots. */
13206 eh->tlsdesc_got
13211 /* plt.got_offset needs to know there's a TLS_DESC
13212 reloc in the middle of .got.plt. */
13214 }
13217 {
13218 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
13219 the symbol is both GD and GDESC, got.offset may
13220 have been overwritten. */
13223 }
13226 /* R_ARM_TLS_IE32 needs one GOT slot. */
13228 }
13242 {
13250 {
13252 /* GDESC needs a trampoline to jump to. */
13254 }
13256 /* Only GD needs it. GDESC just emits one relocation per
13257 2 entries. */
13260 }
13262 {
13264 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
13266 }
13269 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
13270 they all resolve dynamically instead. Reserve room for the
13271 GOT entry's R_ARM_IRELATIVE relocation. */
13274 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
13276 }
13277 }
13278 else
13281 /* Allocate stubs for exported Thumb functions on v4t. */
13286 {
13293 /* Create a new symbol to regist the real location of the function. */
13307 /* Point the symbol at the stub. */
13312 }
13317 /* In the shared -Bsymbolic case, discard space allocated for
13318 dynamic pc-relative relocs against symbols which turn out to be
13319 defined in regular objects. For the normal shared case, discard
13320 space for pc-relative relocs that have become local due to symbol
13321 visibility changes. */
13324 {
13325 /* The only relocs that use pc_count are R_ARM_REL32 and
13326 R_ARM_REL32_NOI, which will appear on something like
13327 ".long foo - .". We want calls to protected symbols to resolve
13328 directly to the function rather than going via the plt. If people
13329 want function pointer comparisons to work as expected then they
13330 should avoid writing assembly like ".long foo - .". */
13332 {
13336 {
13341 else
13343 }
13344 }
13347 {
13351 {
13354 else
13356 }
13357 }
13359 /* Also discard relocs on undefined weak syms with non-default
13360 visibility. */
13363 {
13367 /* Make sure undefined weak symbols are output as a dynamic
13368 symbol in PIEs. */
13371 {
13374 }
13375 }
13379 {
13380 /* Output absolute symbols so that we can create relocations
13381 against them. For normal symbols we output a relocation
13382 against the section that contains them. */
13385 }
13387 }
13388 else
13389 {
13390 /* For the non-shared case, discard space for relocs against
13391 symbols which turn out to need copy relocs or are not
13392 dynamic. */
13400 {
13401 /* Make sure this symbol is output as a dynamic symbol.
13402 Undefined weak syms won't yet be marked as dynamic. */
13405 {
13408 }
13410 /* If that succeeded, we know we'll be keeping all the
13411 relocs. */
13414 }
13418 keep: ;
13419 }
13421 /* Finally, allocate space. */
13423 {
13429 else
13431 }
13434 }
13436 /* Find any dynamic relocs that apply to read-only sections. */
13438 static bfd_boolean
13440 {
13446 {
13450 {
13455 /* Not an error, just cut short the traversal. */
13457 }
13458 }
13460 }
13462 void
13465 {
13473 }
13475 /* Set the sizes of the dynamic sections. */
13477 static bfd_boolean
13480 {
13483 bfd_boolean plt;
13484 bfd_boolean relocs;
13497 {
13498 /* Set the contents of the .interp section to the interpreter. */
13500 {
13505 }
13506 }
13508 /* Set up .got offsets for local syms, and space for local dynamic
13509 relocs. */
13511 {
13517 bfd_size_type locsymcount;
13527 {
13532 {
13535 {
13536 /* Input section has been discarded, either because
13537 it is a copy of a linkonce section or due to
13538 linker script /DISCARD/, so we'll be discarding
13539 the relocs too. */
13540 }
13544 {
13545 /* Relocations in vxworks .tls_vars sections are
13546 handled specially by the loader. */
13547 }
13549 {
13554 }
13555 }
13556 }
13574 {
13578 {
13582 {
13587 /* All references to the PLT are calls, so all
13588 non-call references can resolve directly to the
13589 run-time target. This means that the .got entry
13590 would be the same as the .igot.plt entry, so there's
13591 no point creating both. */
13593 }
13594 else
13595 {
13598 }
13601 {
13607 else
13609 }
13610 }
13612 {
13617 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13620 {
13625 /* plt.got_offset needs to know there's a TLS_DESC
13626 reloc in the middle of .got.plt. */
13628 }
13633 {
13634 /* If the symbol is both GD and GDESC, *local_got
13635 may have been overwritten. */
13638 }
13644 /* If all references to an STT_GNU_IFUNC PLT are calls,
13645 then all non-call references, including this GOT entry,
13646 resolve directly to the run-time target. */
13652 {
13658 {
13662 }
13663 }
13664 }
13665 else
13667 }
13668 }
13671 {
13672 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13673 for R_ARM_TLS_LDM32 relocations. */
13678 }
13679 else
13682 /* Allocate global sym .plt and .got entries, and space for global
13683 sym dynamic relocs. */
13686 /* Here we rummage through the found bfds to collect glue information. */
13688 {
13692 /* Initialise mapping tables for code/data. */
13697 /* xgettext:c-format */
13700 }
13702 /* Allocate space for the glue sections now that we've sized them. */
13705 /* For every jump slot reserved in the sgotplt, reloc_count is
13706 incremented. However, when we reserve space for TLS descriptors,
13707 it's not incremented, so in order to compute the space reserved
13708 for them, it suffices to multiply the reloc count by the jump
13709 slot size. */
13714 {
13721 /* If we're not using lazy TLS relocations, don't generate the
13722 PLT and GOT entries they require. */
13724 {
13730 }
13731 }
13733 /* The check_relocs and adjust_dynamic_symbol entry points have
13734 determined the sizes of the various dynamic sections. Allocate
13735 memory for them. */
13739 {
13745 /* It's OK to base decisions on the section name, because none
13746 of the dynobj section names depend upon the input files. */
13750 {
13751 /* Remember whether there is a PLT. */
13753 }
13755 {
13757 {
13758 /* Remember whether there are any reloc sections other
13759 than .rel(a).plt and .rela.plt.unloaded. */
13763 /* We use the reloc_count field as a counter if we need
13764 to copy relocs into the output file. */
13766 }
13767 }
13773 {
13774 /* It's not one of our sections, so don't allocate space. */
13776 }
13779 {
13780 /* If we don't need this section, strip it from the
13781 output file. This is mostly to handle .rel(a).bss and
13782 .rel(a).plt. We must create both sections in
13783 create_dynamic_sections, because they must be created
13784 before the linker maps input sections to output
13785 sections. The linker does that before
13786 adjust_dynamic_symbol is called, and it is that
13787 function which decides whether anything needs to go
13788 into these sections. */
13791 }
13796 /* Allocate memory for the section contents. */
13800 }
13803 {
13804 /* Add some entries to the .dynamic section. We fill in the
13805 values later, in elf32_arm_finish_dynamic_sections, but we
13806 must add the entries now so that we get the correct size for
13807 the .dynamic section. The DT_DEBUG entry is filled in by the
13808 dynamic linker and used by the debugger. */
13809 #define add_dynamic_entry(TAG, VAL) \
13810 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
13813 {
13816 }
13819 {
13831 }
13834 {
13836 {
13841 }
13842 else
13843 {
13848 }
13849 }
13851 /* If any dynamic relocs apply to a read-only section,
13852 then we need a DT_TEXTREL entry. */
13855 info);
13858 {
13861 }
13865 }
13866 #undef add_dynamic_entry
13869 }
13871 /* Size sections even though they're not dynamic. We use it to setup
13872 _TLS_MODULE_BASE_, if needed. */
13874 static bfd_boolean
13877 {
13886 {
13889 tlsbase = elf_link_hash_lookup
13893 {
13909 }
13910 }
13912 }
13914 /* Finish up dynamic symbol handling. We set the contents of various
13915 dynamic sections here. */
13917 static bfd_boolean
13922 {
13933 {
13935 {
13939 }
13942 {
13943 /* Mark the symbol as undefined, rather than as defined in
13944 the .plt section. Leave the value alone. */
13946 /* If the symbol is weak, we do need to clear the value.
13947 Otherwise, the PLT entry would provide a definition for
13948 the symbol even if the symbol wasn't defined anywhere,
13949 and so the symbol would never be NULL. */
13952 }
13954 {
13955 /* At least one non-call relocation references this .iplt entry,
13956 so the .iplt entry is the function's canonical address. */
13964 }
13965 }
13968 {
13970 Elf_Internal_Rela rel;
13972 /* This symbol needs a copy reloc. Set it up. */
13986 }
13988 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
13989 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
13990 to the ".got" section. */
13996 }
13998 static void
14002 {
14006 {
14009 /* Emit mov pc,rx if bx is not permitted. */
14013 }
14014 }
14016 /* Finish up the dynamic sections. */
14018 static bfd_boolean
14020 {
14033 /* A broken linker script might have discarded the dynamic sections.
14034 Catch this here so that we do not seg-fault later on. */
14040 {
14052 {
14053 Elf_Internal_Dyn dyn;
14060 {
14093 get_vma:
14096 {
14097 /* PR ld/14397: Issue an error message if a required section is missing. */
14102 }
14105 else
14106 /* In the BPABI, tags in the PT_DYNAMIC section point
14107 at the file offset, not the memory address, for the
14108 convenience of the post linker. */
14113 get_vma_if_bpabi:
14128 {
14129 /* My reading of the SVR4 ABI indicates that the
14130 procedure linkage table relocs (DT_JMPREL) should be
14131 included in the overall relocs (DT_REL). This is
14132 what Solaris does. However, UnixWare can not handle
14133 that case. Therefore, we override the DT_RELSZ entry
14134 here to make it not include the JMPREL relocs. Since
14135 the linker script arranges for .rel(a).plt to follow all
14136 other relocation sections, we don't have to worry
14137 about changing the DT_REL entry. */
14143 }
14144 /* Fall through. */
14148 /* In the BPABI, the DT_REL tag must point at the file
14149 offset, not the VMA, of the first relocation
14150 section. So, we use code similar to that in
14151 elflink.c, but do not check for SHF_ALLOC on the
14152 relcoation section, since relocations sections are
14153 never allocated under the BPABI. The comments above
14154 about Unixware notwithstanding, we include all of the
14155 relocations here. */
14157 {
14163 {
14164 Elf_Internal_Shdr *hdr
14167 {
14174 }
14175 }
14177 }
14194 /* Set the bottom bit of DT_INIT/FINI if the
14195 corresponding function is Thumb. */
14201 get_sym:
14202 /* If it wasn't set by elf_bfd_final_link
14203 then there is nothing to adjust. */
14205 {
14211 {
14214 }
14215 }
14217 }
14218 }
14220 /* Fill in the first entry in the procedure linkage table. */
14222 {
14226 /* Calculate the addresses of the GOT and PLT. */
14231 {
14232 /* The VxWorks GOT is relocated by the dynamic linker.
14233 Therefore, we must emit relocations rather than simply
14234 computing the values now. */
14235 Elf_Internal_Rela rel;
14246 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
14252 }
14254 {
14271 }
14272 else
14273 {
14286 #ifdef FOUR_WORD_PLT
14287 /* The displacement value goes in the otherwise-unused
14288 last word of the second entry. */
14290 #else
14292 #endif
14293 }
14294 }
14296 /* UnixWare sets the entsize of .plt to 4, although that doesn't
14297 really seem like the right value. */
14302 {
14303 bfd_vma got_address
14307 bfd_vma plt_address
14323 }
14326 {
14330 #ifdef FOUR_WORD_PLT
14333 #endif
14334 }
14337 {
14338 /* Correct the .rel(a).plt.unloaded relocations. They will have
14339 incorrect symbol indexes. */
14348 {
14349 Elf_Internal_Rela rel;
14360 }
14361 }
14362 }
14364 /* Fill in the first three entries in the global offset table. */
14366 {
14368 {
14371 else
14377 }
14380 }
14383 }
14385 static void
14386 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14387 {
14395 else
14400 {
14404 }
14408 {
14412 else
14414 }
14415 }
14417 static enum elf_reloc_type_class
14419 {
14421 {
14430 }
14431 }
14433 static void
14435 {
14437 }
14439 /* Return TRUE if this is an unwinding table entry. */
14441 static bfd_boolean
14443 {
14446 }
14449 /* Set the type and flags for an ARM section. We do this by
14450 the section name, which is a hack, but ought to work. */
14452 static bfd_boolean
14454 {
14460 {
14463 }
14465 }
14467 /* Handle an ARM specific section when reading an object file. This is
14468 called when bfd_section_from_shdr finds a section with an unknown
14469 type. */
14471 static bfd_boolean
14476 {
14477 /* There ought to be a place to keep ELF backend specific flags, but
14478 at the moment there isn't one. We just keep track of the
14479 sections by their name, instead. Fortunately, the ABI gives
14480 names for all the ARM specific sections, so we will probably get
14481 away with this. */
14483 {
14491 }
14497 }
14501 {
14504 else
14506 }
14509 {
14518 enum map_symbol_type
14519 {
14520 ARM_MAP_ARM,
14521 ARM_MAP_THUMB,
14522 ARM_MAP_DATA
14523 };
14526 /* Output a single mapping symbol. */
14528 static bfd_boolean
14531 bfd_vma offset)
14532 {
14534 Elf_Internal_Sym sym;
14546 }
14548 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14549 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14551 static bfd_boolean
14553 bfd_boolean is_iplt_entry_p,
14556 {
14568 {
14571 }
14572 else
14573 {
14576 }
14582 {
14587 }
14589 {
14598 }
14600 {
14603 }
14604 else
14605 {
14606 bfd_boolean thumb_stub_p;
14610 {
14613 }
14614 #ifdef FOUR_WORD_PLT
14619 #else
14620 /* A three-word PLT with no Thumb thunk contains only Arm code,
14621 so only need to output a mapping symbol for the first PLT entry and
14622 entries with thumb thunks. */
14624 {
14627 }
14628 #endif
14629 }
14632 }
14634 /* Output mapping symbols for PLT entries associated with H. */
14636 static bfd_boolean
14638 {
14646 /* When warning symbols are created, they **replace** the "real"
14647 entry in the hash table, thus we never get to see the real
14648 symbol in a hash traversal. So look at it now. */
14654 }
14656 /* Output a single local symbol for a generated stub. */
14658 static bfd_boolean
14661 {
14662 Elf_Internal_Sym sym;
14673 }
14675 static bfd_boolean
14678 {
14681 bfd_vma addr;
14690 /* Massage our args to the form they really have. */
14696 /* Ensure this stub is attached to the current section being
14697 processed. */
14706 {
14720 }
14725 {
14727 {
14744 }
14747 {
14751 }
14754 {
14771 }
14772 }
14775 }
14777 /* Output mapping symbols for linker generated sections,
14778 and for those data-only sections that do not have a
14779 $d. */
14781 static bfd_boolean
14786 Elf_Internal_Sym *,
14787 asection *,
14789 {
14790 output_arch_syminfo osi;
14792 bfd_vma offset;
14793 bfd_size_type size;
14806 /* Add a $d mapping symbol to data-only sections that
14807 don't have any mapping symbol. This may result in (harmless) redundant
14808 mapping symbols. */
14812 {
14817 {
14822 == SEC_HAS_CONTENTS
14827 {
14832 }
14833 }
14834 }
14836 /* ARM->Thumb glue. */
14838 {
14840 ARM2THUMB_GLUE_SECTION_NAME);
14849 else
14853 {
14856 }
14857 }
14859 /* Thumb->ARM glue. */
14861 {
14863 THUMB2ARM_GLUE_SECTION_NAME);
14870 {
14873 }
14874 }
14876 /* ARMv4 BX veneers. */
14878 {
14880 ARM_BX_GLUE_SECTION_NAME);
14886 }
14888 /* Long calls stubs. */
14890 {
14896 {
14897 /* Ignore non-stub sections. */
14907 }
14908 }
14910 /* Finally, output mapping symbols for the PLT. */
14912 {
14917 /* Output mapping symbols for the plt header. SymbianOS does not have a
14918 plt header. */
14920 {
14921 /* VxWorks shared libraries have no PLT header. */
14923 {
14928 }
14929 }
14931 {
14934 }
14936 {
14939 #ifndef FOUR_WORD_PLT
14942 #endif
14943 }
14944 }
14947 {
14952 {
14958 {
14966 }
14967 }
14968 }
14970 {
14971 /* Mapping symbols for the lazy tls trampoline. */
14978 }
14980 {
14981 /* Mapping symbols for the tls trampoline. */
14984 #ifdef FOUR_WORD_PLT
14988 #endif
14989 }
14992 }
14994 /* Allocate target specific section data. */
14996 static bfd_boolean
14998 {
15000 {
15008 }
15011 }
15014 /* Used to order a list of mapping symbols by address. */
15016 static int
15018 {
15027 /* Ensure results do not depend on the host qsort for objects with
15028 multiple mapping symbols at the same address by sorting on type
15029 after vma. */
15033 else
15035 }
15037 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
15039 static unsigned long
15041 {
15043 }
15045 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
15046 relocations. */
15048 static void
15050 {
15054 /* High bit of first word is supposed to be zero. */
15058 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
15059 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
15065 }
15067 /* Data for make_branch_to_a8_stub(). */
15069 struct a8_branch_to_stub_data
15070 {
15073 };
15076 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
15077 places for a particular section. */
15079 static bfd_boolean
15082 {
15088 bfd_signed_vma branch_offset;
15117 /* We attempt to avoid this condition by setting stubs_always_after_branch
15118 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
15119 This check is just to be on the safe side... */
15121 {
15125 }
15128 {
15139 {
15144 jump24:
15146 {
15147 /* There's not much we can do apart from complain if this
15148 happens. */
15152 }
15154 /* i1 = not(j1 eor s), so:
15155 not i1 = j1 eor s
15156 j1 = (not i1) eor s. */
15168 }
15174 }
15180 }
15182 /* Do code byteswapping. Return FALSE afterwards so that the section is
15183 written out as normal. */
15185 static bfd_boolean
15190 {
15196 bfd_vma ptr;
15197 bfd_vma end;
15199 bfd_byte tmp;
15205 /* If this section has not been allocated an _arm_elf_section_data
15206 structure then we cannot record anything. */
15216 {
15221 {
15225 {
15227 {
15228 bfd_vma branch_to_veneer;
15229 /* Original condition code of instruction, plus bit mask for
15230 ARM B instruction. */
15234 /* The instruction is before the label. */
15237 /* Above offset included in -4 below. */
15251 }
15255 {
15256 bfd_vma branch_from_veneer;
15259 /* Take size of veneer into account. */
15268 /* Original instruction. */
15275 /* Branch back to insn after original insn. */
15281 }
15286 }
15287 }
15288 }
15291 {
15292 arm_unwind_table_edit *edit_node
15294 /* Now, sec->size is the size of the section we will write. The original
15295 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
15296 markers) was sec->rawsize. (This isn't the case if we perform no
15297 edits, then rawsize will be zero and we should use size). */
15304 {
15306 {
15310 {
15313 out_index++;
15314 in_index++;
15315 }
15319 {
15321 {
15323 in_index++;
15328 {
15336 /* Note: this is meant to be equivalent to an
15337 R_ARM_PREL31 relocation. These synthetic
15338 EXIDX_CANTUNWIND markers are not relocated by the
15339 usual BFD method. */
15343 /* First address we can't unwind. */
15347 /* Code for EXIDX_CANTUNWIND. */
15351 out_index++;
15353 }
15355 }
15358 }
15359 }
15360 else
15361 {
15362 /* No more edits, copy remaining entries verbatim. */
15365 out_index++;
15366 in_index++;
15367 }
15368 }
15372 edited_contents,
15376 }
15378 /* Fix code to point to Cortex-A8 erratum stubs. */
15380 {
15388 }
15394 {
15399 {
15402 else
15406 {
15408 /* Byte swap code words. */
15410 {
15418 }
15422 /* Byte swap code halfwords. */
15424 {
15429 }
15433 /* Leave data alone. */
15435 }
15437 }
15438 }
15446 }
15448 /* Mangle thumb function symbols as we read them in. */
15450 static bfd_boolean
15455 {
15459 /* New EABI objects mark thumb function symbols by setting the low bit of
15460 the address. */
15463 {
15465 {
15468 }
15469 else
15471 }
15473 {
15476 }
15479 else
15483 }
15486 /* Mangle thumb function symbols as we write them out. */
15488 static void
15493 {
15494 Elf_Internal_Sym newsym;
15496 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15497 of the address set, as per the new EABI. We do this unconditionally
15498 because objcopy does not set the elf header flags until after
15499 it writes out the symbol table. */
15501 {
15506 {
15507 /* Do this only for defined symbols. At link type, the static
15508 linker will simulate the work of dynamic linker of resolving
15509 symbols and will carry over the thumbness of found symbols to
15510 the output symbol table. It's not clear how it happens, but
15511 the thumbness of undefined symbols can well be different at
15512 runtime, and writing '1' for them will be confusing for users
15513 and possibly for dynamic linker itself.
15514 */
15516 }
15519 }
15521 }
15523 /* Add the PT_ARM_EXIDX program header. */
15525 static bfd_boolean
15528 {
15534 {
15535 /* If there is already a PT_ARM_EXIDX header, then we do not
15536 want to add another one. This situation arises when running
15537 "strip"; the input binary already has the header. */
15542 {
15553 }
15554 }
15557 }
15559 /* We may add a PT_ARM_EXIDX program header. */
15561 static int
15564 {
15570 else
15572 }
15574 /* Hook called by the linker routine which adds symbols from an object
15575 file. */
15577 static bfd_boolean
15581 {
15593 }
15595 /* We use this to override swap_symbol_in and swap_symbol_out. */
15597 {
15610 bfd_elf32_write_out_phdrs,
15611 bfd_elf32_write_shdrs_and_ehdr,
15612 bfd_elf32_checksum_contents,
15613 bfd_elf32_write_relocs,
15614 elf32_arm_swap_symbol_in,
15615 elf32_arm_swap_symbol_out,
15616 bfd_elf32_slurp_reloc_table,
15617 bfd_elf32_slurp_symbol_table,
15618 bfd_elf32_swap_dyn_in,
15619 bfd_elf32_swap_dyn_out,
15620 bfd_elf32_swap_reloc_in,
15621 bfd_elf32_swap_reloc_out,
15622 bfd_elf32_swap_reloca_in,
15623 bfd_elf32_swap_reloca_out
15624 };
15626 #define ELF_ARCH bfd_arch_arm
15627 #define ELF_TARGET_ID ARM_ELF_DATA
15628 #define ELF_MACHINE_CODE EM_ARM
15629 #ifdef __QNXTARGET__
15630 #define ELF_MAXPAGESIZE 0x1000
15631 #else
15632 #define ELF_MAXPAGESIZE 0x8000
15633 #endif
15634 #define ELF_MINPAGESIZE 0x1000
15635 #define ELF_COMMONPAGESIZE 0x1000
15637 #define bfd_elf32_mkobject elf32_arm_mkobject
15639 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
15640 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
15641 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
15642 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
15643 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
15644 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
15645 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
15646 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
15647 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
15648 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
15649 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
15650 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
15651 #define bfd_elf32_bfd_final_link elf32_arm_final_link
15653 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
15654 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
15655 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
15656 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
15657 #define elf_backend_check_relocs elf32_arm_check_relocs
15658 #define elf_backend_relocate_section elf32_arm_relocate_section
15659 #define elf_backend_write_section elf32_arm_write_section
15660 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
15661 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
15662 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
15663 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
15664 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
15665 #define elf_backend_always_size_sections elf32_arm_always_size_sections
15666 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
15667 #define elf_backend_post_process_headers elf32_arm_post_process_headers
15668 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
15669 #define elf_backend_object_p elf32_arm_object_p
15670 #define elf_backend_fake_sections elf32_arm_fake_sections
15671 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
15672 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15673 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
15674 #define elf_backend_size_info elf32_arm_size_info
15675 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15676 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
15677 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
15678 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
15679 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
15681 #define elf_backend_can_refcount 1
15682 #define elf_backend_can_gc_sections 1
15683 #define elf_backend_plt_readonly 1
15684 #define elf_backend_want_got_plt 1
15685 #define elf_backend_want_plt_sym 0
15686 #define elf_backend_may_use_rel_p 1
15687 #define elf_backend_may_use_rela_p 0
15688 #define elf_backend_default_use_rela_p 0
15690 #define elf_backend_got_header_size 12
15692 #undef elf_backend_obj_attrs_vendor
15694 #undef elf_backend_obj_attrs_section
15696 #undef elf_backend_obj_attrs_arg_type
15697 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
15698 #undef elf_backend_obj_attrs_section_type
15699 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
15700 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
15701 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
15705 /* Native Client targets. */
15707 #undef TARGET_LITTLE_SYM
15708 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_nacl_vec
15709 #undef TARGET_LITTLE_NAME
15711 #undef TARGET_BIG_SYM
15712 #define TARGET_BIG_SYM bfd_elf32_bigarm_nacl_vec
15713 #undef TARGET_BIG_NAME
15716 /* Like elf32_arm_link_hash_table_create -- but overrides
15717 appropriately for NaCl. */
15721 {
15726 {
15734 }
15736 }
15738 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
15739 really need to use elf32_arm_modify_segment_map. But we do it
15740 anyway just to reduce gratuitous differences with the stock ARM backend. */
15742 static bfd_boolean
15744 {
15747 }
15749 #undef elf32_bed
15750 #define elf32_bed elf32_arm_nacl_bed
15751 #undef bfd_elf32_bfd_link_hash_table_create
15752 #define bfd_elf32_bfd_link_hash_table_create \
15753 elf32_arm_nacl_link_hash_table_create
15754 #undef elf_backend_plt_alignment
15755 #define elf_backend_plt_alignment 4
15756 #undef elf_backend_modify_segment_map
15757 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
15758 #undef elf_backend_modify_program_headers
15759 #define elf_backend_modify_program_headers nacl_modify_program_headers
15761 #undef ELF_MAXPAGESIZE
15762 #define ELF_MAXPAGESIZE 0x10000
15766 /* Reset to defaults. */
15767 #undef elf_backend_plt_alignment
15768 #undef elf_backend_modify_segment_map
15769 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15770 #undef elf_backend_modify_program_headers
15772 /* VxWorks Targets. */
15774 #undef TARGET_LITTLE_SYM
15775 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
15776 #undef TARGET_LITTLE_NAME
15778 #undef TARGET_BIG_SYM
15779 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
15780 #undef TARGET_BIG_NAME
15783 /* Like elf32_arm_link_hash_table_create -- but overrides
15784 appropriately for VxWorks. */
15788 {
15793 {
15798 }
15800 }
15802 static void
15804 {
15807 }
15809 #undef elf32_bed
15810 #define elf32_bed elf32_arm_vxworks_bed
15812 #undef bfd_elf32_bfd_link_hash_table_create
15813 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
15814 #undef elf_backend_final_write_processing
15815 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
15816 #undef elf_backend_emit_relocs
15817 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
15819 #undef elf_backend_may_use_rel_p
15820 #define elf_backend_may_use_rel_p 0
15821 #undef elf_backend_may_use_rela_p
15822 #define elf_backend_may_use_rela_p 1
15823 #undef elf_backend_default_use_rela_p
15824 #define elf_backend_default_use_rela_p 1
15825 #undef elf_backend_want_plt_sym
15826 #define elf_backend_want_plt_sym 1
15827 #undef ELF_MAXPAGESIZE
15828 #define ELF_MAXPAGESIZE 0x1000
15833 /* Merge backend specific data from an object file to the output
15834 object file when linking. */
15836 static bfd_boolean
15838 {
15839 flagword out_flags;
15840 flagword in_flags;
15844 /* Check if we have the same endianness. */
15854 /* The input BFD must have had its flags initialised. */
15855 /* The following seems bogus to me -- The flags are initialized in
15856 the assembler but I don't think an elf_flags_init field is
15857 written into the object. */
15858 /* BFD_ASSERT (elf_flags_init (ibfd)); */
15863 /* In theory there is no reason why we couldn't handle this. However
15864 in practice it isn't even close to working and there is no real
15865 reason to want it. */
15869 {
15871 ibfd);
15873 }
15876 {
15877 /* If the input is the default architecture and had the default
15878 flags then do not bother setting the flags for the output
15879 architecture, instead allow future merges to do this. If no
15880 future merges ever set these flags then they will retain their
15881 uninitialised values, which surprise surprise, correspond
15882 to the default values. */
15895 }
15897 /* Determine what should happen if the input ARM architecture
15898 does not match the output ARM architecture. */
15902 /* Identical flags must be compatible. */
15906 /* Check to see if the input BFD actually contains any sections. If
15907 not, its flags may not have been initialised either, but it
15908 cannot actually cause any incompatiblity. Do not short-circuit
15909 dynamic objects; their section list may be emptied by
15910 elf_link_add_object_symbols.
15912 Also check to see if there are no code sections in the input.
15913 In this case there is no need to check for code specific flags.
15914 XXX - do we need to worry about floating-point format compatability
15915 in data sections ? */
15917 {
15922 {
15923 /* Ignore synthetic glue sections. */
15926 {
15934 }
15935 }
15939 }
15941 /* Complain about various flag mismatches. */
15944 {
15945 _bfd_error_handler
15951 }
15953 /* Not sure what needs to be checked for EABI versions >= 1. */
15954 /* VxWorks libraries do not use these flags. */
15958 {
15960 {
15961 _bfd_error_handler
15967 }
15970 {
15972 _bfd_error_handler
15973 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
15975 else
15976 _bfd_error_handler
15977 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
15981 }
15984 {
15986 _bfd_error_handler
15989 else
15990 _bfd_error_handler
15995 }
15998 {
16000 _bfd_error_handler
16003 else
16004 _bfd_error_handler
16009 }
16011 #ifdef EF_ARM_SOFT_FLOAT
16013 {
16014 /* We can allow interworking between code that is VFP format
16015 layout, and uses either soft float or integer regs for
16016 passing floating point arguments and results. We already
16017 know that the APCS_FLOAT flags match; similarly for VFP
16018 flags. */
16021 {
16023 _bfd_error_handler
16026 else
16027 _bfd_error_handler
16032 }
16033 }
16034 #endif
16036 /* Interworking mismatch is only a warning. */
16038 {
16040 {
16041 _bfd_error_handler
16044 }
16045 else
16046 {
16047 _bfd_error_handler
16050 }
16051 }
16052 }
16055 }
16058 /* Symbian OS Targets. */
16060 #undef TARGET_LITTLE_SYM
16061 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
16062 #undef TARGET_LITTLE_NAME
16064 #undef TARGET_BIG_SYM
16065 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
16066 #undef TARGET_BIG_NAME
16069 /* Like elf32_arm_link_hash_table_create -- but overrides
16070 appropriately for Symbian OS. */
16074 {
16079 {
16082 /* There is no PLT header for Symbian OS. */
16084 /* The PLT entries are each one instruction and one word. */
16087 /* Symbian uses armv5t or above, so use_blx is always true. */
16090 }
16092 }
16094 static const struct bfd_elf_special_section
16095 elf32_arm_symbian_special_sections[] =
16096 {
16097 /* In a BPABI executable, the dynamic linking sections do not go in
16098 the loadable read-only segment. The post-linker may wish to
16099 refer to these sections, but they are not part of the final
16100 program image. */
16106 /* These sections do not need to be writable as the SymbianOS
16107 postlinker will arrange things so that no dynamic relocation is
16108 required. */
16113 };
16115 static void
16118 {
16119 /* BPABI objects are never loaded directly by an OS kernel; they are
16120 processed by a postlinker first, into an OS-specific format. If
16121 the D_PAGED bit is set on the file, BFD will align segments on
16122 page boundaries, so that an OS can directly map the file. With
16123 BPABI objects, that just results in wasted space. In addition,
16124 because we clear the D_PAGED bit, map_sections_to_segments will
16125 recognize that the program headers should not be mapped into any
16126 loadable segment. */
16129 }
16131 static bfd_boolean
16134 {
16138 /* BPABI shared libraries and executables should have a PT_DYNAMIC
16139 segment. However, because the .dynamic section is not marked
16140 with SEC_LOAD, the generic ELF code will not create such a
16141 segment. */
16144 {
16150 {
16154 }
16155 }
16157 /* Also call the generic arm routine. */
16159 }
16161 /* Return address for Ith PLT stub in section PLT, for relocation REL
16162 or (bfd_vma) -1 if it should not be included. */
16164 static bfd_vma
16167 {
16169 }
16172 #undef elf32_bed
16173 #define elf32_bed elf32_arm_symbian_bed
16175 /* The dynamic sections are not allocated on SymbianOS; the postlinker
16176 will process them and then discard them. */
16177 #undef ELF_DYNAMIC_SEC_FLAGS
16178 #define ELF_DYNAMIC_SEC_FLAGS \
16179 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
16181 #undef elf_backend_emit_relocs
16183 #undef bfd_elf32_bfd_link_hash_table_create
16184 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
16185 #undef elf_backend_special_sections
16186 #define elf_backend_special_sections elf32_arm_symbian_special_sections
16187 #undef elf_backend_begin_write_processing
16188 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
16189 #undef elf_backend_final_write_processing
16190 #define elf_backend_final_write_processing elf32_arm_final_write_processing
16192 #undef elf_backend_modify_segment_map
16193 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
16195 /* There is no .got section for BPABI objects, and hence no header. */
16196 #undef elf_backend_got_header_size
16197 #define elf_backend_got_header_size 0
16199 /* Similarly, there is no .got.plt section. */
16200 #undef elf_backend_want_got_plt
16201 #define elf_backend_want_got_plt 0
16203 #undef elf_backend_plt_sym_val
16204 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
16206 #undef elf_backend_may_use_rel_p
16207 #define elf_backend_may_use_rel_p 1
16208 #undef elf_backend_may_use_rela_p
16209 #define elf_backend_may_use_rela_p 0
16210 #undef elf_backend_default_use_rela_p
16211 #define elf_backend_default_use_rela_p 0
16212 #undef elf_backend_want_plt_sym
16213 #define elf_backend_want_plt_sym 0
16214 #undef ELF_MAXPAGESIZE
16215 #define ELF_MAXPAGESIZE 0x8000